MPC99J93ACR2 [NXP]
99J SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LQFP-32;
| 型号： | MPC99J93ACR2 |
| 厂家： | 
NXP |
| 描述： | 99J SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LQFP-32 驱动 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC99J93
Rev 3, 05/2005
Freescale Semiconductor
Technical Data
Intelligent Dynamic Clock Switch
(IDCS) PLL Clock Driver
MPC99J93
The MPC99J93 is a PLL clock driver designed specifically for redundant clock
tree designs. The device receives two differential LVPECL clock signals from
which it generates 5 new differential LVPECL clock outputs. Two of the output
pairs regenerate the input signals frequency and phase while the other three
pairs generate 2x, phase aligned clock outputs.
INTELLIGENT DYNAMIC
CLOCK SWITCH
PLL CLOCK DRIVER
Features
•
•
•
•
•
•
•
Fully Integrated PLL
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control I/O
3.3 V Operation
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
32-Lead LQFP Packaging
32-Lead Pb-Free Package Available
Functional Description
The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously
monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or
LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that
CLK is the primary clock, the IDCS will switch to the good secondary clock and
phase/frequency alignment will occur with minimal output phase disturbance.
The typical phase bump caused by a failed clock is eliminated. (See Application
Information section).
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
PLL_En
Clk_Selected
Inp1bad
DYNAMIC
SWITCH
Inp0bad
Man_Override
Alarm_Reset
LOGIC
Qb0
Qb0
OR
Sel_Clk
Qb1
Qb1
CLK0
CLK0
CLK1
CLK1
Qb2
Qb2
÷2
÷4
PLL
Qa0
Qa0
Ext_FB
Ext_FB
200 – 360 MHz
Qa1
Qa1
MR
Figure 1. Block Diagram
© Freescale Semiconductor, Inc., 2005. All rights reserved.
24 23 22
21 20 19
18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
V
CC
Qa1
Qa1
Qa0
Qa0
Inp0bad
Inp1bad
Clk_Selected
MPC99J93
V
CC
GND
Ext_FB
V
CC_PLL
Man_Override
PLL_EN
Ext_FB
GND
1
2
3
4
5
6
7
8
Figure 2. 32-Lead Pinout (Top View)
Table 1. Pin Descriptions
Pin Name
I/O
Pin Definition
CLK0, CLK0
CLK1, CLK1
LVPECL Input
LVPECL Input
Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)
Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)
Ext_FB, Ext_FB
Qa0:1, Qa0:1
Qb0:2, Qb0:2
Inp0bad
LVPECL Input
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)
LVPECL Output Differential 1x output pairs. Connect one QAx pair to Ext_FB.
LVPECL Output Differential 2x output pairs
LVCMOS Output Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is
active HIGH and will remain HIGH until the alarm reset is asserted
Inp1bad
LVCMOS Output Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is
active HIGH and will remain HIGH until the alarm reset is asserted
Clk_Selected
Alarm_Reset
LVCMOS Output ‘0' if clock 0 is selected, ‘1' if clock 1 is selected
LVCMOS Input ‘0' will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one-shotted”
(50kΩ pullup)
Sel_Clk
LVCMOS Input ‘0' selects CLK0, ‘1' selects CLK1 (50kΩ pulldown)
Manual_Override
PLL_En
LVCMOS Input ‘1' disables internal clock switch circuitry (50kΩ pulldown)
LVCMOS Input ‘0' bypasses selected input reference around the phase-locked loop (50kΩ pullup)
LVCMOS Input ‘0' resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50kΩ pullup)
MR
V
V
Power Supply
Power Supply
Power Supply
Power Supply
PLL power supply
Digital power supply
PLL ground
CCA
CC
GNDA
GND
Digital ground
MPC99J93
Advanced Clock Drivers Devices
Freescale Semiconductor
2
Table 2. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min
–0.3
–0.3
–0.3
Max
Unit
V
Condition
V
Supply Voltage
3.9
CC
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
V
V
+0.3
V
IN
CC
CC
V
+0.3
V
OUT
I
±20
mA
mA
°C
IN
I
±50
OUT
T
Storage Temperature
–65
125
S
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 3. General Specifications
Symbol
Characteristics
Output Termination Voltage
Min
Typ
– 2
Max
Unit
V
Condition
V
V
TT
CC
MM
HBM
CDM
LU
ESD Protection (Machine model)
ESD Protection (Human body model)
ESD Protection (Charged device model)
Latch-Up Immunity
175
1500
1000
100
V
V
V
mA
pF
C
Input Capacitance
4.0
Inputs
IN
θ
Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
JA
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
JESD 51-6, 2S2P multilayer test board
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
θ
Thermal Resistance Junction to Case
23.0
26.3
°C/W MIL-SPEC 883E
JC
Method 1012.1
(1)
T
Operating Junction Temperature
110
°C
J
(continuous operation)
MTBF = 9.1 years
1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110°C junction temperature allowing the MPC99J93 to be used in applications requiring industrial temperature range. It is
recommended that users of the MPC99J93 employ thermal modeling analysis to assist in applying the junction temperature specifications
to their particular application.
MPC99J93
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 4. DC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (MR, PLL_En, Sel_Clk, Man_Override, Alarm_Reset)
V
Input High Voltage
Input Low Voltage
2.0
V
+ 0.3
CC
V
V
IH
V
I
0.8
IL
(1)
Input Current
±100
µA
V
= V or GND
IN
IN
CC
LVCMOS Control Outputs (Clk_selected, Inp0bad, Inp1bad)
V
Output High Voltage
Output Low Voltage
2.0
0.1
V
V
I
I
= -24 mA
= 24 mA
OH
OH
OL
V
0.55
1.3
OL
(2)
(4)
LVPECL Clock Inputs (CLK0, CLK1, Ext_FB)
(3)
V
DC Differential Input Voltage
Differential Cross Point Voltage
V
V
Differential operation
Differential operation
PP
V
V
–1.8
V
–0.3
CMR
CC
CC
(1)
I
Input Current
±100
µA
V
= V or GND
IN
IN CC
LVPECL Clock Outputs (QA[1:0], QB[2:0])
V
Output High Voltage
Output Low Voltage
V
–1.20
–1.90
V
V
–0.95
–1.75
V
V
–0.70
V
V
Termination 50 Ω to V
Termination 50 Ω to V
OH
CC
CC
CC
CC
CC
CC
TT
V
V
–1.45
OL
TT
Supply Current
Maximum Power Supply Current
Maximum PLL Supply Current
I
180
15
mA GND pins
mA pin
GND
I
V
CC_PLL
CC_PLL
1. Inputs have internal pull-up/pull-down resistors affecting the input current.
2. Clock inputs driven by differential LVPECL compatible signals.
3. V is the minimum differential input voltage swing required to maintain AC characteristics.
PP
4. V
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
(DC)
CMR
CMR
range and the input swing lies within the V (DC) specification.
PP
MPC99J93
Advanced Clock Drivers Devices
Freescale Semiconductor
4
Table 5. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40°C to +85°C)(1)
Symbol
Characteristics
Input Reference Frequency
Min
50
Typ
Max
90
Unit
Condition
f
÷4 feedback
÷4 feedback
MHz PLL locked
MHz
ref
(2)
f
VCO Frequency Range
Output Frequency
200
360
VCO
f
QA[1:0]
QB[2:0]
50
100
90
180
MHz PLL locked
MHz
MAX
f
Reference Input Duty Cycle
Propagation Delay
25
75
%
refDC
(3)
t
SPO, static phase offset
–0.15
0.9
+0.17
1.8
ns
ns
PLL_EN = 1
PLL_EN = 0
(∅)
CLK0, CLK1 to any Q
(4)
V
Differential Input Voltage
(peak-to-peak)
0.25
1.3
V
V
PP
CMR
sk(O)
(5)
V
Differential Input Crosspoint Voltage
V
–1.7
V
–0.3
CC
CC
t
Output-to-Output Skew
within QA[2:0] or QB[1:0]
50
80
ps
ps
within device
(6)
∆
Rate of Change of Period
QA[1:0]
QB[2:0]
QA[1:0]
QB[2:0]
20
10
200
100
50
25
400
200
ps
ps
ps
ps
per/cycle
(6)
(7)
(7)
DC
Output Duty Cycle
45
50
25
55
%
ps
ms
ns
t
Cycle-to-Cycle Jitter
Maximum PLL Lock Time
Output Rise/Fall Time
RMS (1 σ)
JIT(CC)
t
10
LOCK
t , t
0.05
0.70
20% to 80%
r
f
1. AC characteristics apply for parallel output termination of 50 Ω to V – 2 V.
CC
2. The input reference frequency must match the VCO lock range divided by the feedback divider ratio (FB): f = f
÷ FB.
VCO
ref
3. CLK0, CLK1 to Ext_FB.
4. V is the minimum differential input voltage swing required to maintain AC characteristics including SPO and device-to-device skew.
PP
Applicable to CLK0, CLK1 and Ext_FB.
5. V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
(AC)
CMR
CMR
range and the input swing lies within the V (AC) specification. Violation of V
(AC) or V (AC) impacts the SPO, device and part-to-part
PP
CMR
PP
skew. Applicable to CLK0, CLK1 and Ext_FB.
6. Specification holds for a clock switch between two input signals (CLK0, CLK1) no greater than 400 ps out of phase. Delta period change per
cycle is averaged over the clock switch excursion.
7. Specification holds for a clock switch between two input signals (CLK0, CLK1) at any phase difference (±180°). Delta period change per
cycle is averaged over the clock switch excursion.
MPC99J93
Advanced Clock Drivers Devices
Freescale Semiconductor
5
APPLICATIONS INFORMATION
The MPC99J93 is a dual clock PLL with on-chip Intelligent
both INP_BADs will be latched (H) after one Ext_FB period
and Clk_Selected will be latched (L) indicating CLK0 is the
PLL reference signal. While neither INP_BAD is latched (H),
the Clk_Selected can be freely changed with Sel_Clk.
Whenever a CLK switch occurs, (manually or by IDCS),
following the next negative edge of the newly selected PLL
reference signal, the next positive edge pair of Ext_FB and
the newly selected PLL reference signal will slew to
alignment.
To calculate the overall uncertainty between the input
CLKs and the outputs from multiple MPC99J93's, the
following procedure should be used. Assuming that the input
CLKs to all MPC9993's are exactly in phase, the total
uncertainty will be the sum of the static phase offset, max I/O
jitter, and output to output skew.
Dynamic Clock Switch (IDCS) circuitry.
Definitions
primary clock: The input CLK selected by Sel_Clk.
secondary clock: The input CLK NOT selected by
Sel_Clk.
PLL reference signal: The CLK selected as the PLL
reference signal by Sel_Clk or IDCS. (IDCS can override
Sel_Clk).
Status Functions
Clk_Selected: Clk_Selected (L) indicates CLK0 is
selected as the PLL reference signal. Clk_Selected (H)
indicates CLK1 is selected as the PLL reference signal.
During a dynamic switch, the output phase between two
devices may be increased for a short period of time. If the two
input CLKs are 400ps out of phase, a dynamic switch of an
MPC99J93 will result in an instantaneous phase change of
400ps to the PLL reference signal without a corresponding
change in the output phase (due to the limited response of
the PLL). As a result, the I/O phase of a device, undergoing
this switch, will initially be 400ps and diminish as the PLL
slews to its new phase alignment. This transient timing issue
should be considered when analyzing the overall skew
budget of a system.
INP_BAD: Latched (H) when it's CLK is stuck (H) or (L) for
at least one Ext_FB period (Pos to Pos or Neg to Neg).
Cleared (L) on assertion of Alarm_Reset.
Control Functions
Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock.
Sel_Clk (H) selects CLK1 as the primary clock.
Alarm_Reset: Asserted by a negative edge. Generates a
one-shot reset pulse that clears INPUT_BAD latches and
Clk_Selected latch.
PLL_En: While (L), the PLL reference signal is substituted
Hot insertion and withdrawal
for the VCO output.
In PECL applications, a powered up driver will experience
a low impedance path through an MPC99J93 input to its
powered down VCC pins. In this case, a 100 ohm series
resistance should be used in front of the input pins to limit the
driver current. The resistor will have minimal impact on the
rise and fall times of the input signals.
MR: While (L), internal dividers are held in reset which
holds all Q outputs LOW.
Man Override (H)
(IDCS is disabled, PLL functions normally). PLL reference
signal (as indicated by Clk_Selected) will always be the CLK
selected by Sel_Clk. The status function INP_BAD is active
in Man Override (H) and (L).
Acquiring Frequency Lock
1. While the MPC99J93 is receiving a valid CLK signal,
assert Man_Override HIGH.
Man Override (L)
(IDCS is enabled, PLL functions enhanced). The first CLK
to fail will latch it's INP_BAD (H) status flag and select the
other input as the Clk_Selected for the PLL reference clock.
Once latched, the Clk_Selected and INP_BAD remain
latched until assertion of Alarm_Reset which clears all
latches (INP_BADs are cleared and Clk_Selected = Sel_Clk).
NOTE: If both CLKs are bad when Alarm_Reset is asserted,
2. The PLL will phase and frequency lock within the
specified lock time.
3. Apply a HIGH to LOW transition to Alarm_Reset to reset
Input Bad flags.
4. De-assert Man_Override LOW to enable Intelligent
Dynamic Clock Switch mode.
MPC99J93
Advanced Clock Drivers Devices
Freescale Semiconductor
6
PACKAGE DIMENSIONS
4X
0.20
H
A-B D
6
D1
3
A, B, D
e/2
D1/2
32
PIN 1 INDEX
1
25
F
F
A
B
E1/2
6
E1
E
4
DETAIL G
E/2
DETAIL G
8
17
NOTES:
9
7
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
D
4
D/2
4X
D
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
0.20
C
A-B D
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
H
28X e
32X
0.1 C
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
SEATING
PLANE
C
DETAIL AD
BASE
METAL
PLATING
b1
c
c1
MILLIMETERS
DIM
A
A1
A2
b
b1
c
c1
D
MIN
1.40
0.05
1.35
0.30
0.30
0.09
0.09
MAX
1.60
0.15
1.45
0.45
0.40
0.20
0.16
b
5
8
8X (θ1˚)
M
0.20
C
A-B
D
R R2
SECTION F-F
R R1
9.00 BSC
D1
e
E
E1
L
L1
q
q1
R1
R2
S
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
A2
A
0.25
GAUGE PLANE
0.50
1.00 REF
0˚ 7˚
12 REF
0.70
(S)
A1
L
θ˚
0.08
0.08
0.20
---
(L1)
0.20 REF
DETAIL AD
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
MPC99J93
Advanced Clock Drivers Device Data
Freescale Semiconductor
7
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MPC99J93
Rev. 3
05/2005
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