MRFE6VP6300HR3 [NXP]
RF Power Field Effect Transistors;
| 型号： | MRFE6VP6300HR3 |
| 厂家： | 
NXP |
| 描述： | RF Power Field Effect Transistors 局域网 放大器 CD 晶体管 |
| 文件： | 总15页 (文件大小：1051K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MRFE6VP6300H
Rev. 1, 7/2011
Freescale Semiconductor
Technical Data
RF Power Field Effect Transistors
High Ruggedness N--Channel
MRFE6VP6300HR3
MRFE6VP6300HSR3
Enhancement--Mode Lateral MOSFETs
These high ruggedness devices are designed for use in high VSWR industrial
(including laser and plasma exciters), broadcast (analog and digital), aerospace
and radio/land mobile applications. They are unmatched input and output
designs allowing wide frequency range utilization, between 1.8 and 600 MHz.
1.8--600 MHz, 300 W, 50 V
LATERAL N--CHANNEL
BROADBAND
•
Typical Performance: VDD = 50 Volts, IDQ = 100 mA
P
(W)
f
G
(dB)
η
(%)
IRL
(dB)
out
ps
D
Signal Type
(MHz)
RF POWER MOSFETs
Pulsed (100 μsec,
300 Peak
230
26.5
74.0
-- 1 6
20% Duty Cycle)
CW
300 Avg.
130
25.0
80.0
-- 1 5
•
•
Capable of Handling a Load Mismatch of 65:1 VSWR, @ 50 Vdc, 230 MHz,
at all Phase Angles
•
300 Watts CW Output Power
•
300 Watts Pulsed Peak Power, 20% Duty Cycle, 100 μsec
CASE 465M--01, STYLE 1
N I -- 7 8 0 -- 4
Capable of 300 Watts CW Operation
MRFE6VP6300HR3
Features
•
•
•
•
•
•
•
•
•
•
Unmatched Input and Output Allowing Wide Frequency Range Utilization
Device can be used Single--Ended or in a Push--Pull Configuration
Qualified Up to a Maximum of 50 VDD Operation
Characterized from 30 V to 50 V for Extended Power Range
Suitable for Linear Application with Appropriate Biasing
Integrated ESD Protection
Greater Negative Gate--Source Voltage Range for Improved Class C Operation
Characterized with Series Equivalent Large--Signal Impedance Parameters
RoHS Compliant
CASE 465H--02, STYLE 1
NI--780S--4
MRFE6VP6300HSR3
NI--780--4 in Tape and Reel. R3 Suffix = 250 Units, 56 mm Tape Width,
13 inch Reel. For R5 Tape and Reel options, see p. 14.
•
NI--780S--4 in Tape and Reel. R3 Suffix = 250 Units, 32 mm Tape Width,
RF /V
RF /V
out DS
3
4
1
2
in GS
13 inch Reel. For R5 Tape and Reel options, see p. 14.
Table 1. Maximum Ratings
Rating
Drain--Source Voltage
Symbol
Value
--0.5, +130
--6.0, +10
--65 to +150
150
Unit
Vdc
Vdc
°C
RF /V
out DS
RF /V
in GS
V
DSS
Gate--Source Voltage
V
GS
Storage Temperature Range
Case Operating Temperature
T
stg
(Top View)
T
°C
C
D
Figure 1. Pin Connections
Total Device Dissipation @ T = 25°C
P
1050
5.26
W
C
Derate above 25°C
W/°C
(1,2)
Operating Junction Temperature
T
J
225
°C
Table 2. Thermal Characteristics
(2,3)
Characteristic
Symbol
Value
Unit
(4)
Thermal Resistance, Junction to Case
°C/W
Pulsed: Case Temperature 75°C, 300 W Pulsed, 100 μsec Pulse Width, 20% Duty Cycle,
50 Vdc, I = 100 mA, 230 MHz
CW: Case Temperature 87°C, 300 W CW, 50 Vdc, I
Z
R
θ
JC
0.05
0.19
θ
DQ
JC
= 1100 mA, 230 MHz
DQ
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access
MTTF calculators by product.
3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf.
Select Documentation/Application Notes -- AN1955.
4. Same test circuit is used for both pulsed and CW.
© Freescale Semiconductor, Inc., 2010--2011. All rights reserved.
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
Machine Model (per EIA/JESD22--A115)
Charge Device Model (per JESD22--C101)
2 (Minimum)
B (Minimum)
IV (Minimum)
Table 4. Electrical Characteristics (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(1)
Off Characteristics
Gate--Source Leakage Current
I
—
130
—
—
—
—
—
1
—
5
μAdc
Vdc
GSS
(V = 5 Vdc, V = 0 Vdc)
GS
DS
Drain--Source Breakdown Voltage
(V = 0 Vdc, I = 50 mA)
V
(BR)DSS
GS
D
Zero Gate Voltage Drain Leakage Current
(V = 50 Vdc, V = 0 Vdc)
I
μAdc
μAdc
DSS
DSS
DS
GS
Zero Gate Voltage Drain Leakage Current
I
—
10
(V = 100 Vdc, V = 0 Vdc)
DS
GS
On Characteristics
(1)
Gate Threshold Voltage
(V = 10 Vdc, I = 480 μAdc)
V
V
1.7
2.0
—
2.2
2.5
2.7
3.0
—
Vdc
Vdc
Vdc
GS(th)
GS(Q)
DS(on)
DS
D
Gate Quiescent Voltage
(V = 50 Vdc, I = 100 mAdc, Measured in Functional Test)
DD
D
(1)
Drain--Source On--Voltage
(V = 10 Vdc, I = 1 Adc)
V
0.25
GS
D
(1)
Dynamic Characteristics
Reverse Transfer Capacitance
(V = 50 Vdc ± 30 mV(rms)ac @ 1 MHz, V = 0 Vdc)
DS
C
—
—
—
0.8
76
—
—
—
pF
pF
pF
rss
GS
Output Capacitance
(V = 50 Vdc ± 30 mV(rms)ac @ 1 MHz, V = 0 Vdc)
DS
C
oss
GS
Input Capacitance
C
188
iss
(V = 50 Vdc, V = 0 Vdc ± 30 mV(rms)ac @ 1 MHz)
DS
GS
Functional Tests (In Freescale Test Fixture, 50 ohm system) V = 50 Vdc, I = 100 mA, P = 300 W Peak (60 W Avg.), f = 230 MHz,
DD
DQ
out
Pulsed, 100 μsec Pulse Width, 20% Duty Cycle
Power Gain
G
25.0
72.0
—
26.5
74.0
-- 1 6
28.0
—
dB
%
ps
D
Drain Efficiency
η
Input Return Loss
IRL
-- 9
dB
Load Mismatch (In Freescale Application Test Fixture, 50 ohm system) V = 50 Vdc, I = 100 mA
DD
DQ
VSWR 65:1 at all Phase Angles
Ψ
No Degradation in Output Power
Pulsed: P = 300 W Peak (60 W Avg.), f = 230 MHz, Pulsed,
out
100 μsec Pulse Width, 20% Duty Cycle
CW: P = 300 W Avg., f = 130 MHz
out
1. Each side of device measured separately.
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
2
V
V
SUPPLY
BIAS
+
+
+
+
L1
C9
C14
C15
C10 C11 C12
C13
C16
C8
L2
RF
OUTPUT
R1
C4
C5
C6 C7
Z8
Z9
Z10
Z11
Z12
Z13
RF
INPUT
C20
Z1
Z2
Z3
Z4
Z5
Z6
Z7
C17
C18 C19
C1
DUT
C2
C3
Z1
0.352″ x 0.080″ Microstrip
1.780″ x 0.080″ Microstrip
0.576″ x 0.080″ Microstrip
0.220″ x 0.220″ Microstrip
0.322″ x 0.220″ Microstrip
0.168″ x 0.220″ Microstrip
0.282″ x 0.630″ Microstrip
Z9
0.192″ x 0.170″ Microstrip
0.366″ x 0.170″ Microstrip
2.195″ x 0.170″ Microstrip
0.614″ x 0.170″ Microstrip
0.243″ x 0.080″ Microstrip
Z2*
Z3*
Z4
Z5
Z6
Z10*
Z11*
Z12*
Z13
* Line length includes microstrip bends
Z7, Z8
Note: Same test circuit is used for both pulsed and CW.
Figure 2. MRFE6VP6300HR3(HSR3) Test Circuit Schematic
Table 5. MRFE6VP6300HR3(HSR3) Test Circuit Component Designations and Values
Part
Description
Part Number
ATC100B150JT500XT
ATC100B820JT500XT
ATC100B910JT500XT
ATC100B102JT50XT
ATC200B103KT50XT
CDR33BX104AKWS
HMK432B7225KM--T
T491D106K035AT
Manufacturer
ATC
C1, C20
15 pF Chip Capacitors
C2
82 pF Chip Capacitor
ATC
C3, C17
C4, C10
C5, C11
C6
91 pF Chip Capacitors
ATC
1000 pF Chip Capacitors
10K pF Chip Capacitors
0.1 μF, 50 V Chip Capacitor
2.2 μF, 100 V Chip Capacitor
10 μF, 35 V Tantalum Capacitor
2.2 μF, 100 V Chip Capacitor
0.1 μF, 100 V Chip Capacitor
0.01 μF, 100 V Chip Capacitor
220 μF, 100 V Electolytic Capacitors
18 pF Chip Capacitors
ATC
ATC
AVX
C7
Taiyo Yuden
Kemet
ATC
C8
C9
G2225X7R225KT3AB
C1812F104K1RAC
C1825C103K1GAC
MCGPR100V227M16X26--RH
ATC100B180JT500XT
1812SMS--R12JLC
GA3095--ALC
C12
Kemet
Kemet
Multicomp
ATC
C13
C14, C15, C16
C18, C19
L1
120 nH Inductor
Coilcraft
Coilcraft
Vishay
Arlon
L2
17.5 nH Inductor
R1
1000 Ω, 1/2 W Chip Resistor
CRCW20101K00FKEF
AD255A
PCB
0.030″, ε = 2.55
r
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
3
C8
C14
C15
C13
L1
C16
C12
C11
C6
C5
C7
C9
L2
C10
C1
C4
C18
C20
C19
C3
R1
C17
C2
MRFE6VP6300H/HS
Rev. 2
Figure 3. MRFE6VP6300HR3(HSR3) Test Circuit Component Layout
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
4
TYPICAL CHARACTERISTICS — PULSED
1000
100
10
60
P3dB = 56.0 dBm (398 W)
C
iss
59
58
57
56
55
54
53
Ideal
P2dB = 55.8 dBm (380 W)
C
oss
P1dB = 55.4 dBm
(344 W)
Actual
C
rss
1
V
= 50 Vdc, I = 100 mA, f = 230 MHz
DQ
DD
Measured with ±30 mV(rms)ac @ 1 MHz
Pulse Width = 100 μsec, 20% Duty Cycle
V
= 0 Vdc
GS
0.1
0
10
20
30
40
50
26
27
28
29
30
31
32
33
34
V
, DRAIN--SOURCE VOLTAGE (VOLTS)
P , INPUT POWER (dBm) PULSED
in
DS
Note: Each side of device measured separately.
Figure 5. Pulsed Output Power versus
Input Power
Figure 4. Capacitance versus Drain--Source Voltage
29
28
27
26
29
28
27
26
25
90
V
= 50 Vdc, I = 100 mA, f = 230 MHz
DQ
DD
V
= 50 Vdc, I = 100 mA, f = 230 MHz
DQ
DD
Pulse Width = 100 μsec, 20% Duty Cycle
80
70
60
50
40
30
20
Pulse Width = 100 μsec, 20% Duty Cycle
50 V
24
23
22
21
25
24
23
22
G
45 V
ps
40 V
35 V
20
19
η
V
= 30 V
150
D
DD
20
100
600
0
50
100
200
250
300
350
400
P
, OUTPUT POWER (WATTS) PULSED
P
, OUTPUT POWER (WATTS) PULSED
out
out
Figure 7. Pulsed Power Gain versus
Output Power
Figure 6. Pulsed Power Gain and Drain Efficiency
versus Output Power
29
28
27
90
80
70
60
50
40
30
20
90
80
70
V
= 50 Vdc, I = 100 mA, f = 230 MHz
DQ
25_C
DD
85_C
45 V
50 V
40 V
35 V
Pulse Width = 100 μsec, 20% Duty Cycle
V
= 30 V
DD
-- 3 0 _C
G
ps
26
25
24
23
22
60
50
40
30
20
10
25_C
T
= --30_C
C
85_C
V
= 50 Vdc, I = 100 mA, f = 230 MHz
DQ
Pulse Width = 100 μsec, 20% Duty Cycle
DD
η
D
21
10
0
50
100
150
200
250
300
350
400
100
P , OUTPUT POWER (WATTS) PULSED
out
600
P
, OUTPUT POWER (WATTS) PULSED
out
Figure 9. Pulsed Power Gain and Drain Efficiency
versus Output Power
Figure 8. Pulsed Drain Efficiency versus
Output Power
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
5
TYPICAL CHARACTERISTICS — TWO--TONE (1)
-- 10
-- 20
-- 30
-- 10
V
= 50 Vdc, P = 250 W (PEP)/62.5 W Avg. per Tone
out
= 1600 mA, Two--Tone Measurements
DD
V
= 50 Vdc, I = 1600 mA, f1 = 230 MHz
DQ
DD
I
DQ
f2 = 230.1 MHz, Two--Tone Measurements
-- 20
3rd Order
-- 30
-- 40
-- 50
-- 60
-- 70
-- 40
-- 50
3rd Order
5th Order
5th Order
7th Order
-- 60
-- 70
7th Order
-- 8 0
10
100
, OUTPUT POWER (WATTS) PEP
400
0.1
1
10
40
P
TWO--TONE SPACING (MHz)
out
Figure 10. Intermodulation Distortion
Products versus Output Power
Figure 11. Intermodulation Distortion
Products versus Two--Tone Spacing
30
-- 15
-- 20
-- 25
-- 30
-- 35
-- 40
V
= 50 Vdc, f1 = 230 MHz, f2 = 230.1 MHz
DD
I
= 1600 mA
DQ
Two--Tone Measurements
29
28
27
1400 mA
1100 mA
I
= 650 mA
900 mA
DQ
900 mA
1100 mA
1400 mA
26
25
-- 45
-- 50
V
= 50 Vdc, f1 = 230 MHz, f2 = 230.1 MHz
650 mA
DD
Two--Tone Measurements
1600 mA
100
5
10
100
, OUTPUT POWER (WATTS) PEP
500
10
400
P
, OUTPUT POWER (WATTS) PEP
P
out
out
Figure 13. Third Order Intermodulation
Distortion versus Output Power
Figure 12. Two--Tone Power Gain versus
Output Power
1. The distortion products are referenced to one of the two tones and the peak envelope power (PEP) is 6 dB above the power in a single tone.
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
6
TYPICAL CHARACTERISTICS
9
8
10
V
P
η
= 50 Vdc
= 300 W Avg.
= 80%
DD
out
10
D
7
6
5
10
10
10
4
10
90
110
130
150
170
190
210
230
250
T , JUNCTION TEMPERATURE (°C)
J
MTTF calculator available at http://www.freescale.com/rf. Select
Software & Tools/Development Tools/Calculators to access MTTF
calculators by product.
Figure 14. MTTF versus Junction Temperature — CW
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
7
Z
source
f = 230 MHz
f = 230 MHz
Z
load
Z = 5 Ω
o
V
= 50 Vdc, I = 100 mA, P = 300 W Peak
DQ out
DD
f
Z
Z
load
source
MHz
Ω
Ω
230
0.65 + j2.79
1.64 + j2.85
Z
Z
=
=
Test circuit impedance as measured from
gate to ground.
source
Test circuit impedance as measured from
drain to ground.
load
Output
Matching
Network
Device
Under
Test
Input
Matching
Network
Z
Z
source
load
Figure 15. Series Equivalent Source and Load Impedance
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
8
V
= 50 Vdc, I = 100 mA
DD
DQ
f
Z
Z
load
source
MHz
Ω
Ω
10
25
36.0 + j128
20.0 + j64.0
16.0 + j41.6
8.00 + j24.8
3.00 + j12.8
1.52 + j7.92
1.08 + j5.04
1.04 + j3.16
0.88 + j1.76
12.0 + j8.80
12.4 + j6.40
11.6 + j14.4
9.00 + j9.80
7.20 + j6.40
6.00 + j5.00
4.20 + j4.00
3.32 + j2.72
2.72 + j1.68
50
100
200
300
400
500
600
1. Simulated performance at 1 dB gain compression.
Z
Z
=
=
Source impedance presented from gate to gate.
Load impedance presented from drain to drain.
source
load
Device
Under
Test
Load
Source
+
--
--
+
Z
Z
source
load
Figure 16. Simulated Source and Load Impedances Optimized for IRL,
Output Power and Drain Efficiency — Push--Pull
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
9
PACKAGE DIMENSIONS
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
10
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
11
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
12
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
13
PRODUCT DOCUMENTATION AND SOFTWARE
Refer to the following documents to aid your design process.
Application Notes
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
•
•
•
•
•
Electromigration MTTF Calculator
RF High Power Model
.s2p File
For Software, do a Part Number search at http://www.freescale.com, and select the “Part Number” link. Go to the Software &
Tools tab on the part’s Product Summary page to download the respective tool.
R5 TAPE AND REEL OPTION
NI--780--4 = R5 Suffix = 50 Units, 56 mm Tape Width, 13 inch Reel.
NI--780S--4 = R5 Suffix = 50 Units, 32 mm Tape Width, 13 inch Reel.
The R5 tape and reel option for MRFE6VP6300H and MRFE6VP6300HS parts will be available for 2 years after release of
MRFE6VP6300H and MRFE6VP6300HS. Freescale Semiconductor, Inc. reserves the right to limit the quantities that will be
delivered in the R5 tape and reel option. At the end of the 2 year period customers who have purchased these devices in the R5
tape and reel option will be offered MRFE6VP6300H and MRFE6VP6300HS in the R3 tape and reel option.
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
Description
0
1
Oct. 2010
July 2011
•
Initial Release of Data Sheet
Corrected pin 4 label from RF /V to RF /V , Fig. 1, Pin Connections, p. 1
•
•
•
out GS
in GS
Changed Drain--Source voltage from --0.5, +125 to --0.5, +130 in Maximum Ratings table, p. 1
Added Total Device Dissipation to Maximum Ratings table, p. 1
•
Changed V
Min value from 125 to 130 Vdc, Table 4, Off Characteristics, p. 2
(BR)DSS
•
Tightened V
Min limit from 1.5 to 1.7 Vdc and Max limit from 3.0 to 2.7 Vdc as a result of process
GS(th)
improvement, Table 4, On Characteristics, p. 2
•
Tightened V Min limit from 1.7 to 2.0 Vdc and Max limit from 3.2 to 3.0 Vdc as a result of process
GS(Q)
improvement, Table 4, On Characteristics, p. 2
•
Added Load Mismatch table to Table 4. Electrical Characteristics, p. 2
•
MTTF end temperature on graph changed to match maximum operating junction temperature, Fig. 14,
MTTF versus Junction Temperature, p. 7
•
Added Fig. 16, Simulated Source and Load Impedances Optimized for IRL, Output Power and Drain
Efficiency — Push--Pull table, p. 9
MRFE6VP6300HR3 MRFE6VP6300HSR3
RF Device Data
Freescale Semiconductor
14
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Document Number: MRFE6VP6300H
Rev. 1,7/2011
相关型号：
MRFE6VP8600H
RF Power LDMOS Transistors High Ruggedness N--Channel Enhancement--Mode Lateral MOSFETs
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