N74F173D [NXP]
Quad D-type flip-flop 3-State; 四D型触发器三态
| 型号： | N74F173D |
| 厂家： | 
NXP |
| 描述： | Quad D-type flip-flop 3-State |
| 文件： | 总10页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F173
Quad D-type flip-flop (3-State)
Product specification
IC15 Data Handbook
1990 Aug 31
Philips
Semiconductors
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
Data inputs and clock enable inputs are fully edge–triggered
and must be stable only one setup time before the
low–to–high clock transition.
FEATURES
• Edge–triggered D–type register
• Gated clock enable for hold ”do nothing” mode
• 3–state output buffers
The master reset (MR) is an active–high asynchronous
input. When the MR is high, all four flip–flops are reset
(cleared) independently of any other input condition.
• Gated output enable control
• Speed upgrade of N8T10 and current sink upgrade
• Controlled output edges to minimize ground bounces
• 48mA sinking capability
The 3–state output buffers are controlled by a 2–input NOR
gate. When both output enable (OE0 and OE1) inputs are
low, the data in the register is presented at the Q output.
When one or both OE inputs are high, the outputs are forced
to a high impedance ”off” state.
DESCRIPTION
The 3–state output buffers are completely independent of
the register operation; the OE transition does not affect the
clock and reset operations.
The 74F173 is a high speed 4–bit parallel load register with
clock enable control, 3–state buffered outputs, and master
reset (MR). When the two clock enable (E0 and E1) inputs
are low, the data on the D inputs is loaded into the register
simultaneously with low–to–high clock (CP) transition. When
one or both enable inputs are high one setup time before the
low–to–high clock transition, the register retains the previous
data.
TYPE
TYPICAL f
TYPICAL SUPPLY CURRENT (TOTAL)
max
74F173
125MHz
23mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
= 5V ±10%, T = 0°C to +70°C
DESCRIPTION
PKG DWG #
V
CC
amb
16–pin plastic DIP
16–pin plastic SO
N74F173N
N74F173D
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE
HIGH/LOW
D0 – D3
CP
Data inputs
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
750/80
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
15mA/48mA
Clock input
E0, E1
MR
Clock enable inputs
Master reset input
Output enable inputs
Data outputs
OE0, OE1
Q0 – Q3
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2
August 31, 1990
853–1160 00286
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
PIN CONFIGURATION
IEC/IEEE SYMBOL
9
&
1
2
3
4
5
16
15
14
13
12
OE0
OE1
Q0
V
CC
10
7
C1
EN
MR
D0
D3
D2
Q2
E1
E0
1
&
2
Q1
15
R
Q2
14
13
12
11
3
4
5
6
6
7
8
11
10
9
Q3
1D
CP
GND
SF00290
SF00292
LOGIC SYMBOL
14 13 12 11
D0 D1 D2 D3
9
10
7
E0
E1
CP
15
1
MR
OE0
OE1
2
Q0 Q1 Q2 Q3
3
4
5
6
V
= Pin 16
CC
GND = Pin 8
SF00291
FUNCTION TABLE
INPUTS
OUTPUTS
OUTPUTS
MR
H
L
CP
X
↑
E0
X
l
E1
X
l
Dn
X
l
Qn (register)
L
L
Reset (clear)
Parallel load
L
↑
l
l
h
H
L
X
X
h
X
X
h
X
X
qn
qn
Hold (do nothing)
L
Notes to function table
H = High–voltage level
h
L
l
=
=
=
High state one setup time before the low–to–high clock transition
Low–voltage level
Low state one setup time before the low–to–high clock transition
qn = Lower case letters indicate the state of the referenced input (or output) on setup time prior to the low–to–high clock transition
X
↑
=
=
Don’t care
Low–to–high clock transition
3
August 31, 1990
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
FUNCTION TABLE
INPUTS
OUTPUTS
OUTPUTS
Qn (register)
OE0
L
OE1
L
Qn
L
L
H
X
Read
L
L
H
Z
H
X
Disabled
X
X
H
Z
Notes to function table
H = High–voltage level
L
X
Z
=
=
=
Low–voltage level
Don’t care
High impedance ”off” state
LOGIC DIAGRAM
D1
13
D3
11
D0
14
D2
12
9
E0
E1
10
7
CP
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
CP
RD
CP
RD
CP
RD
CP
RD
15
1
MR
OE0
2
OE1
4
6
3
5
Q1
Q3
SF00293
Q0
Q2
V
= Pin 16
CC
GND = Pin 8
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
–0.5 to V
V
OUT
CC
96
mA
°C
°C
OUT
T
amb
Operating free air temperature range
Storage temperature range
0 to +70
T
stg
–65 to +150
4
August 31, 1990
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
NOM
5.0
UNIT
MAX
MIN
4.5
V
Supply voltage
5.5
V
V
CC
IH
IL
V
V
High–level input voltage
Low–level input voltage
Input clamp current
2.0
0.8
–18
–15
48
V
I
I
I
mA
mA
mA
Ik
High–level output current
Low–level output current
OH
OL
T
amb
Operating free air temperature range
0
+70
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN TYP
MAX
±10%V
±5%V
V
V
V
V
= MIN, V = MAX,
2.4
V
V
V
V
CC
CC
IL
V
OH
High-level output voltage
= MIN, I = MAX
2.7
2.0
2.0
3.4
CC
IH
OH
±10%V
= MIN, V = MAX,
CC
CC
CC
IL
±5%V
= MIN, I = –15mA
3.1
IH
OH
V
V
Low-level output voltage
V
V
V
V
V
V
= MIN, V = MAX,
±10%V
0.35
0.35
0.50
0.50
V
V
OL
CC
IL
CC
= MIN, I = MAX
±5%V
IH
OL
CC
Input clamp voltage
= MIN, I = I
IK
–0.73 -1.2
V
IK
CC
CC
CC
CC
I
I
I
I
Input current at maximum input voltage
High–level input current
= MAX, V = 7.0V
100
20
µA
µA
mA
µA
I
I
= MAX, V = 2.7V
IH
IL
I
Low–level input current
= MAX, V = 0.5V
–0.6
I
I
I
I
Off–state output current, high–level voltage applied
Off–state output current, low–level voltage applied
Short–circuit output current3
V
CC
V
CC
V
CC
= MAX, V = 2.7V
50
OZH
OZL
OS
O
µA
= MAX, V = 0.5V
–50
-150
O
= MAX
-60
mA
I
19
27
23
26
37
32
mA
mA
mA
CCH
I
Supply current (total)
I
V
CC
= MAX
CC
CCL
I
CCZ
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
amb
CC
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
5
August 31, 1990
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
T
amb
= +25°C
= 0°C to +70°C
amb
V
CC
= +5.0V ± 10%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
100
125
90
MHz
ns
max
t
t
Propagation delay
CP to Qn
4.5
6.0
6.5
8.0
9.0
10.5
4.0
5.5
10.0
11.5
PLH
PHL
Propagation delay
MR to Qn
t
Waveform 2
6.5
8.5
11.5
6.0
12.5
ns
ns
ns
ns
PHL
t
t
Output enable time
to high or low level
Waveform 4
Waveform 5
3.5
5.5
5.0
7.0
8.0
10.0
2.5
4.5
8.5
11.0
PZH
PZL
t
t
Output disable time
from high or low level
Waveform 4
Waveform 5
1.5
3.0
3.5
5.0
7.0
8.5
1.0
2.5
8.0
9.0
PHZ
PLZ
t
t
Transition time
10% to 90%, 90% to 10%
Waveform 5
Waveform 4
2.0
4.0
5.0
7.5
8.0
10.0
2.0
4.0
8.5
11.0
THL
TLH
AC SETUP REQUIREMENTS
LIMITS
T
T
= +25°C
= +5.0V
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low level
Dn to CP
2.5
2.5
3.0
4.0
su
su
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 1
ns
ns
ns
ns
ns
t (H)
Hold time, high or low level
Dn to CP
0
0
0
0
h
t
h
(L)
t
su
t
su
(H)
(L)
Setup time, high or low level
E to CP
4.5
7.5
5.0
8.5
t (H)
Hold time, high or low level
E to CP
0
0
0
0
h
t
h
(L)
t
w
t
w
(H)
(L)
CP Pulse width,
high or low
3.0
6.0
3.0
6.0
t
t
(H)
MR Pulse width, high
Waveform 2
Waveform 2
3.5
4.5
3.5
5.5
ns
ns
w
Recovery time, MR to CP
rec
AC WAVEFORMS
1/f
max
CP
V
V
V
M
M
M
t
w
(H)
t
t
w
(L)
t
PLH
PHL
V
V
M
M
Qn
SF00294
Waveform 1. Propagation delay for clock input to output, clock
pulse widths, and maximum clock frequency
6
August 31, 1990
Philips Semiconductors
Product specification
Quad D-type flip–flop (3-State)
74F173
MR
V
OE
Qn
M
V
V
M
V
t
M
M
V
-0.3V
0V
OH
t
t
PHZ
PZH
10%
t
(H)
rec
V
w
90%
CP
Qn
M
V
M
t
PHL
SF00297
V
V
M
M
Waveform 4. 3-state output enable time to high level, output
disable time from high level and transition time to high level
SF00295
OE
V
t
V
M
Waveform 2. Master reset pulse width, master reset to output
delay and master reset to clock recovery time
M
t
PZL
90%
PLZ
3.5V
V
M
Qn
10%
En, Dn
V
V
V
V
M
M
M
M
V +0.3V
OL
t
(L)
t
(L)
t
(H)
t (H)
h
su
h
su
SF00298
CP
V
M
V
M
Waveform 5. 3-state output enable time to low level, output
disable time from low level and transition time to low level
SF00296
Waveform 3. Data and enable setup time and hold times
Notes to AC waveforms
1. For all waveforms, V = 1.5V.
M
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORMS
V
CC
t
AMP (V)
0V
w
7.0V
90%
90%
NEGATIVE
PULSE
V
V
M
R
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Open Collector Outputs
10%
10%
t
SWITCH POSITION
TEST
w
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
INPUT PULSE REQUIREMENTS
family
V
M
rep. rate
t
w
t
t
THL
amplitude
TLH
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00128
7
August 31, 1990
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
8
1990 Aug 31
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
9
1990 Aug 31
Philips Semiconductors
Product specification
Quad D-type flip-flop (3-State)
74F173
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05088
Document order number:
Philips
Semiconductors
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