NTS0104BQ-Q100X [NXP]
NTS0104-Q100 - Dual supply translating transceiver; open drain; auto direction sensing QFN 14-Pin;
| 型号： | NTS0104BQ-Q100X |
| 厂家： | 
NXP |
| 描述： | NTS0104-Q100 - Dual supply translating transceiver; open drain; auto direction sensing QFN 14-Pin 逻辑集成电路 |
| 文件： | 总24页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTS0104-Q100
Dual supply translating transceiver; open drain; auto
direction sensing
Rev. 2 — 23 May 2013
Product data sheet
1. General description
The NTS0104-Q100 is a 4-bit, dual supply translating transceiver with auto direction
sensing, that enables bidirectional voltage level translation. It features two 4-bit
input-output ports (An and Bn), one output enable input (OE) and two supply pins (VCC(A)
and VCC(B)). VCC(A) can be supplied with any voltage between 1.65 V and 3.6 V. VCC(B) can
be supplied with any voltage between 2.3 V and 5.5 V. The range in supply voltages
makes the device suitable for translating between any of the voltage nodes (1.8 V, 2.5 V,
3.3 V and 5.0 V). Pins An and OE are referenced to VCC(A) and pins Bn are referenced to
V
CC(B). A LOW level at pin OE causes the outputs to assume a high-impedance
OFF-state. This device is fully specified for partial power-down applications using IOFF
.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range:
VCC(A): 1.65 V to 3.6 V and VCC(B): 2.3 V to 5.5 V
Maximum data rates:
Push-pull: 50 Mbps
IOFF circuitry provides partial Power-down mode operation
Inputs accept voltages up to 5.5 V
ESD protection:
MIL-STD-883, method 3015 Class 2 exceeds 2500 V for A port
MIL-STD-883, method 3015 Class 3B exceeds 15000 V for B port
HBM JESD22-A114E Class 2 exceeds 2500 V for A port
HBM JESD22-A114E Class 3B exceeds 15000 V for B port
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Latch-up performance exceeds 100 mA per JESD 78B Class II
Multiple package options
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
3. Applications
I2C/SMBus
UART
GPIO
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
NTS0104PW-Q100 40 C to +125 C TSSOP14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT402-1
SOT762-1
NTS0104BQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal
enhanced very thin quad flat package;
no leads; 14 terminals; body 2.5 3 0.85 mm
NTS0104UK-Q100 40 C to +125 C WLCSP12 wafer level chip-size package, 12 bumps; body NTS0104UK-Q100
1.20 1.60 0.56 mm
(Backside Coating included)
5. Marking
Table 2.
Marking
Type number
Marking code
NTS0104
S0104
NTS0104PW-Q100
NTS0104BQ-Q100
NTS0104UK-Q100
s04
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
2 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
6. Functional diagram
GATE BIAS
OE
A1
B1
A2
A3
A4
B2
GATE BIAS
B3
GATE BIAS
B4
V
V
CC(B)
CC(A)
GATE BIAS
001aan110
Fig 1. Logic symbol
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
3 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
7. Pinning information
7.1 Pinning
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(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered the solder land should remain
floating or connected to GND.
Fig 2. Pin configuration TSSOP14 (SOT402-1)
Fig 3. Pin configuration DHVQFN14 (SOT762-1)
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Fig 4. Pin configuration WLCSP12 package
Fig 5. Ball mapping for WLCSP12
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
4 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Ball
Description
SOT402-1 and SOT762-1
WLCSP12
B2
VCC(A)
1
supply voltage A
A1, A2, A3, A4
n.c.
2, 3, 4, 5
A3, B3, C3, D3 data input or output (referenced to VCC(A))
6, 9
-
not connected
ground (0 V)
GND
7
D2
C2
OE
8
output enable input (active HIGH; referenced to VCC(A))
B4, B3, B2, B1
VCC(B)
10, 11, 12, 13
14
D1, C1, B1, A1 data input or output (referenced to VCC(B))
A2
supply voltage B
8. Functional description
Table 4.
Function table[1]
Supply voltage
VCC(A)
Input
OE
L
Input/output
VCC(B)
An
Bn
1.65 V to VCC(B)
1.65 V to VCC(B)
GND[2]
2.3 V to 5.5 V
2.3 V to 5.5 V
GND[2]
Z
Z
H
input or output
Z
output or input
Z
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] When either VCC(A) or VCC(B) is at GND level, the device goes into power-down mode.
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
5 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
VI
Parameter
Conditions
Min
Max
+6.5
+6.5
+6.5
+6.5
Unit
V
supply voltage A
supply voltage B
input voltage
0.5
0.5
0.5
0.5
V
[1][2]
[1][2]
[1][2]
A port and OE input
B port
V
V
VO
output voltage
Active mode
A or B port
0.5
VCCO + 0.5
V
[1]
Power-down or 3-state mode
A port
0.5
0.5
50
50
-
+4.6
+6.5
-
V
B port
V
IIK
input clamping current
output clamping current
output current
VI < 0 V
mA
mA
mA
mA
mA
C
IOK
IO
VO < 0 V
-
[2]
[3]
VO = 0 V to VCCO
ICC(A) or ICC(B)
50
100
-
ICC
IGND
Tstg
Ptot
supply current
-
ground current
100
65
-
storage temperature
total power dissipation
+150
250
Tamb = 40 C to +125 C
mW
[1] The minimum input and minimum output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] CCO is the supply voltage associated with the output.
V
[3] For TSSOP14 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN14 packages: above 60 C the value of Ptot derates linearly at 4.5 mW/K.
10. Recommended operating conditions
Table 6.
Symbol
VCC(A)
VCC(B)
Tamb
Recommended operating conditions[1][2]
Parameter
Conditions
Min
1.65
2.3
Max
3.6
Unit
V
supply voltage A
supply voltage B
5.5
V
ambient temperature
40
+125
C
t/V
input transition rise and fall rate A or B port; push-pull driving
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
-
-
10
10
ns/V
ns/V
OE input
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
[1] Hold the A and B sides of an unused I/O pair in the same state, either both at VCCI or both at GND.
[2]
V
CC(A) must be less than or equal to VCC(B)
.
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
6 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
11. Static characteristics
Table 7.
Typical static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
II
input leakage
current
OE input; VI = 0 V to 3.6 V; VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
-
-
1
A
[1]
IOZ
IOFF
OFF-stateoutput A or B port; VO = 0 V or VCCO; VCC(A) = 1.65 V to 3.6 V;
-
-
-
-
-
1
1
1
-
A
A
A
pF
current
VCC(B) = 2.3 V to 5.5 V
power-off
A port; VI or VO = 0 V to 3.6 V;
-
leakage current
VCC(A) = 0 V; VCC(B) = 0 V to 5.5 V
B port; VI or VO = 0 V to 5.5 V;
VCC(B) = 0 V; VCC(A) = 0 V to 3.6 V
-
CI
input
OE input; VCC(A) = 3.3 V; VCC(B) = 3.3 V
2
capacitance
CI/O
input/output
capacitance
A port
-
-
-
4
7
9
-
-
-
pF
pF
pF
B port
A or B port; VCC(A) = 3.3 V; VCC(B) = 3.3 V
[1] VCCO is the supply voltage associated with the output.
Table 8.
Typical supply current
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
VCC(A)
VCC(B)
2.5 V
ICC(A)
0.1
Unit
3.3 V
ICC(A)
0.1
5.0 V
ICC(A)
0.1
ICC(B)
0.5
ICC(B)
1.5
ICC(B)
4.6
1.8 V
2.5 V
3.3 V
A
A
A
0.1
0.1
0.1
0.8
0.1
3.8
-
-
0.1
0.1
0.1
2.8
Table 9.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
VIH
HIGH-level
A port
input voltage
[1]
[1]
VCC(A) = 1.65 V to 1.95 V;
VCC(B) = 2.3 V to 5.5 V
VCCI 0.2
VCCI 0.4
-
-
VCCI 0.2
VCCI 0.4
-
-
V
V
VCC(A) = 2.3 V to 3.6 V;
V
CC(B) = 2.3 V to 5.5 V
B port
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
OE input
[1]
VCCI 0.4
-
-
VCCI 0.4
-
-
V
V
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
0.65VCC(A)
0.65VCC(A)
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
7 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 9.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
VIL
LOW-level
A or B port
input voltage
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
-
0.15
-
0.15
V
V
V
OE input
VCC(A) = 1.65 V to 3.6 V;
-
0.35VCC(A)
-
0.35VCC(A)
VCC(B) = 2.3 V to 5.5 V
VOH
HIGH-level
output voltage
A or B port; IO = 20 A
[2]
[2]
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
0.67VCCO
-
0.67VCCO
-
VOL
LOW-level
A or B port; IO = 1 mA
output voltage
VI 0.15 V;
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
-
-
-
0.4
2
2
-
-
-
0.4
12
12
V
II
input leakage OE input; VI = 0 V to 3.6 V;
current
A
A
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
[2]
IOZ
OFF-state
A or B port; VO = 0 V or VCCO;
output current VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0 V to 5.5 V
-
-
2
2
-
-
12
12
A
A
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0 V to 3.6 V
[1]
ICC
supply current VI = 0 V or VCCI; IO = 0 A
ICC(A)
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
-
2.4
-
15
A
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 5.5 V
ICC(B)
-
-
2.2
-
-
15
A
A
1
8
VCC(A) = 1.65 V to 3.6 V;
-
12
-
30
A
VCC(B) = 2.3 V to 5.5 V
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 5.5 V
ICC(A) + ICC(B)
-
-
1
-
-
5
A
A
1
6
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
-
14.4
-
45
A
[1] VCCI is the supply voltage associated with the input.
[2] VCCO is the supply voltage associated with the output.
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
8 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
12. Dynamic characteristics
Table 10. Dynamic characteristics for temperature range 40 C to +85 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
2.5 V 0.2 V
3.3 V 0.3 V
5.0 V 0.5 V
Min
Max
Min
Max
Min
Max
VCC(A) = 1.8 V 0.15 V
tPHL
tPLH
tPHL
tPLH
HIGH to LOW
propagation delay
A to B
A to B
B to A
B to A
-
-
-
-
4.6
6.8
4.4
5.3
-
-
-
-
4.7
6.8
4.5
4.5
-
-
-
-
5.8
7.0
4.7
0.5
ns
ns
ns
ns
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
ten
enable time
disable time
OE to A; B
-
200
35
-
200
35
-
200
35
ns
ns
ns
ns
ns
ns
ns
[2]
[2]
tdis
OE to A; no external load
OE to B; no external load
OE to A
-
-
-
-
-
-
35
35
35
-
230
200
9.5
-
230
200
9.3
9.1
-
230
200
7.6
7.6
OE to B
-
-
-
tTLH
LOW to HIGH
output transition
time
A port
3.2
3.3
2.3
2.7
1.8
2.7
B port
10.8
tTHL
HIGH to LOW
output transition
time
A port
B port
2.0
2.9
5.9
7.6
1.9
2.8
6.0
7.5
1.7
2.8
13.3 ns
10.0 ns
[3]
tsk(o)
tW
output skew time
pulse width
data rate
between channels
data inputs
-
20
-
0.7
-
-
20
-
0.7
-
-
20
-
0.7
-
ns
ns
fdata
50
50
50
Mbps
VCC(A) = 2.5 V 0.2 V
tPHL
tPLH
tPHL
tPLH
HIGH to LOW
propagation delay
A to B
A to B
B to A
B to A
-
-
-
-
3.2
3.5
3.0
2.5
-
-
-
-
3.3
4.1
3.6
1.6
-
-
-
-
3.4
4.4
4.3
0.7
ns
ns
ns
ns
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
ten
enable time
disable time
OE to A; B
-
200
35
-
200
35
-
200
35
ns
ns
ns
ns
ns
ns
ns
[2]
[2]
tdis
OE to A; no external load
OE to B; no external load
OE to A
-
-
-
-
-
-
35
35
35
-
200
200
7.4
8.3
-
200
200
6.6
7.9
-
200
200
6.2
6.8
OE to B
-
-
-
tTLH
LOW to HIGH
output transition
time
A port
2.8
3.2
2.6
2.9
1.8
2.4
B port
NTS0104_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
9 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 10. Dynamic characteristics for temperature range 40 C to +85 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
2.5 V 0.2 V
3.3 V 0.3 V
5.0 V 0.5 V
Min
1.9
2.2
Max
5.7
Min
1.9
2.4
Max
5.5
Min
1.8
2.6
Max
5.3
tTHL
HIGH to LOW
output transition
time
A port
B port
ns
ns
7.8
6.7
6.6
[3]
tsk(o)
tW
output skew time
pulse width
data rate
between channels
data inputs
-
20
-
0.7
-
-
20
-
0.7
-
-
20
-
0.7
-
ns
ns
fdata
50
50
50
Mbps
VCC(A) = 3.3 V 0.3 V
tPHL
tPLH
tPHL
tPLH
HIGH to LOW
propagation delay
A to B
A to B
B to A
B to A
-
-
-
-
-
-
-
-
-
-
-
-
2.4
4.2
2.5
2.5
-
-
-
-
3.1
4.4
3.3
2.6
ns
ns
ns
ns
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
ten
enable time
disable time
OE to A; B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200
35
-
200
35
ns
ns
ns
ns
ns
ns
ns
[2]
[2]
tdis
OE to A; no external load
OE to B; no external load
OE to A
-
-
-
-
35
35
-
260
200
5.6
6.4
-
260
200
5.9
7.4
OE to B
-
-
tTLH
LOW to HIGH
output transition
time
A port
2.3
2.5
1.9
2.1
B port
tTHL
HIGH to LOW
output transition
time
A port
B port
-
-
-
-
2.0
2.3
5.4
7.4
1.9
2.4
5.0
7.6
ns
ns
[3]
tsk(o)
tW
output skew time
pulse width
data rate
between channels
data inputs
-
-
-
-
-
-
-
20
-
0.7
-
-
20
-
0.7
-
ns
ns
fdata
50
50
Mbps
[1] ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
[2] Delay between OE going LOW and when the outputs are disabled.
[3] Skew between any two outputs of the same package switching in the same direction.
.
.
NTS0104_Q100
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Product data sheet
Rev. 2 — 23 May 2013
10 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 11. Dynamic characteristics for temperature range 40 C to +125 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
2.5 V 0.2 V
3.3 V 0.3 V
5.0 V 0.5 V
Min
Max
Min
Max
Min
Max
VCC(A) = 1.8 V 0.15 V
tPHL
tPLH
tPHL
tPLH
HIGH to LOW
propagation delay
A to B
A to B
B to A
B to A
-
-
-
-
5.8
8.5
5.5
6.7
-
-
-
-
5.9
8.5
5.7
5.7
-
-
-
-
7.3
8.8
5.9
0.7
ns
ns
ns
ns
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
ten
enable time
disable time
OE to A; B
-
200
45
-
200
45
-
200
45
ns
ns
ns
ns
ns
ns
ns
[2]
[2]
tdis
OE to A; no external load
OE to B; no external load
OE to A
-
-
-
-
-
-
45
45
45
-
250
220
11.9
13.5
-
250
220
11.7
11.4
-
250
220
9.5
9.5
OE to B
-
-
-
tTLH
LOW to HIGH
output transition
time
A port
3.2
3.3
2.3
2.7
1.8
2.7
B port
tTHL
HIGH to LOW
output transition
time
A port
B port
2.0
2.9
7.4
9.5
1.9
2.8
7.5
9.4
1.7
2.8
16.7 ns
12.5 ns
[3]
tsk(o)
tW
output skew time
pulse width
data rate
between channels
data inputs
-
20
-
0.8
-
-
20
-
0.8
-
-
20
-
0.8
-
ns
ns
fdata
50
50
50
Mbps
VCC(A) = 2.5 V 0.2 V
tPHL
tPLH
tPHL
tPLH
HIGH to LOW
propagation delay
A to B
A to B
B to A
B to A
-
-
-
-
4.0
4.4
3.8
3.2
-
-
-
-
4.2
5.2
4.5
2.0
-
-
-
-
4.3
5.5
5.4
0.9
ns
ns
ns
ns
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
ten
enable time
disable time
OE to A; B
-
200
45
-
200
45
-
200
45
ns
ns
ns
ns
ns
ns
ns
[2]
[2]
tdis
OE to A; no external load
OE to B; no external load
OE to A
-
-
-
-
-
-
45
45
45
-
220
220
9.3
-
220
220
8.3
9.7
-
220
220
7.8
8.3
OE to B
-
-
-
tTLH
LOW to HIGH
output transition
time
A port
2.8
3.2
2.6
2.9
1.8
2.4
B port
10.4
NTS0104_Q100
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Product data sheet
Rev. 2 — 23 May 2013
11 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
Table 11. Dynamic characteristics for temperature range 40 C to +125 C[1] …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8; for wave forms see Figure 6 and Figure 7.
Symbol Parameter
Conditions
VCC(B)
Unit
2.5 V 0.2 V
3.3 V 0.3 V
5.0 V 0.5 V
Min
1.9
2.2
Max
7.2
Min
1.9
2.4
Max
6.9
Min
1.8
2.6
Max
6.7
tTHL
HIGH to LOW
output transition
time
A port
B port
ns
ns
9.8
8.4
8.3
[3]
tsk(o)
tW
output skew time
pulse width
data rate
between channels
data inputs
-
20
-
0.8
-
-
20
-
0.8
-
-
20
-
0.8
-
ns
ns
fdata
50
50
50
Mbps
VCC(A) = 3.3 V 0.3 V
tPHL
tPLH
tPHL
tPLH
HIGH to LOW
propagation delay
A to B
A to B
B to A
B to A
-
-
-
-
-
-
-
-
-
-
-
-
3.0
5.3
3.2
3.2
-
-
-
-
3.9
5.5
4.2
3.3
ns
ns
ns
ns
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
ten
enable time
disable time
OE to A; B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200
45
-
200
45
ns
ns
ns
ns
ns
ns
ns
[2]
[2]
tdis
OE to A; no external load
OE to B; no external load
OE to A
-
-
-
-
45
45
-
280
220
7.0
8.0
-
280
220
7.4
9.3
OE to B
-
-
tTLH
LOW to HIGH
output transition
time
A port
2.3
2.5
1.9
2.1
B port
tTHL
HIGH to LOW
output transition
time
A port
B port
-
-
-
-
2.0
2.3
6.8
9.3
1.9
2.4
6.3
9.5
ns
ns
[3]
tsk(o)
tW
output skew time
pulse width
data rate
between channels
data inputs
-
-
-
-
-
-
-
20
-
0.8
-
-
20
-
0.8
-
ns
ns
fdata
50
50
Mbps
[1] ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
[2] Delay between OE going LOW and when the outputs are disabled.
[3] Skew between any two outputs of the same package switching in the same direction.
.
.
NTS0104_Q100
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Product data sheet
Rev. 2 — 23 May 2013
12 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
13. Waveforms
V
I
An, Bn
input
V
M
GND
t
t
PHL
PLH
V
OH
90 %
Bn, An
output
V
M
10 %
V
OL
t
t
THL
TLH
001aal918
Measurement points are given in Table 12.
OL and VOH are typical output voltage levels that occur with the output load.
V
Fig 6. The data input (An, Bn) to data output (Bn, An) propagation delay times
V
I
OE input
V
M
GND
t
t
PLZ
PZL
V
CCO
output
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aal919
Measurement points are given in Table 12.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Enable and disable times
Table 12. Measurement points[1][2]
Supply voltage
VCCO
Input
Output
VM
VM
VX
VY
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5.0 V 0.5 V
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
0.5VCCO
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOH 0.15 V
VOH 0.15 V
VOH 0.3 V
VOH 0.3 V
[1] VCCI is the supply voltage associated with the input.
[2] CCO is the supply voltage associated with the output.
V
NTS0104_Q100
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Product data sheet
Rev. 2 — 23 May 2013
13 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
C
L
R
L
001aal920
Test data is given in Table 13.
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; ZO = 50 ; dV/dt 1.0 V/ns.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
V
EXT = External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
Table 13. Test data
Supply voltage
VCC(A)
Input
VI[1]
Load
CL
VEXT
[2]
[3]
VCC(B)
t/V
RL
tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
1.65 V to 3.6 V 2.3 V to 5.5 V VCCI
1.0 ns/V
15 pF
50 k, 1 M open
open
2VCCO
[1] VCCI is the supply voltage associated with the input.
[2] For measuring data rate, pulse width, propagation delay and output rise and fall measurements, RL = 1 M. For measuring enable and
disable times, RL = 50 k.
[3] VCCO is the supply voltage associated with the output.
NTS0104_Q100
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Product data sheet
Rev. 2 — 23 May 2013
14 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
14. Application information
14.1 Applications
Voltage level-translation applications. The NTS0104-Q100 can be used in point-to-point
applications to interface between devices or systems operating at different supply
voltages. The device is primarily targeted at I2C or 1-wire which use open-drain drivers.
Although it may also be used in applications where push-pull drivers are connected to the
ports, the NTB0104-Q100 may be more suitable.
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Fig 9. Typical operating circuit
14.2 Architecture
The architecture of the NTS0104-Q100 is shown in Figure 10. The device does not
require an extra input signal to control the direction of data flow from A to B or B to A.
V
CC(A)
V
CC(B)
T1
T2
ONE
ONE
SHOT
SHOT
10 kΩ
10 kΩ
GATE BIAS
T3
A
B
001aal965
Fig 10. Architecture of NTS0104-Q100 I/O cell (one channel)
The NTS0104-Q100 is a "switch" type voltage translator, it employs two key circuits to
enable voltage translation:
1. A pass-gate transistor (N-channel) that ties the ports together.
2. An output edge-rate accelerator that detects and accelerates rising edges on the I/O
pins.
NTS0104_Q100
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Product data sheet
Rev. 2 — 23 May 2013
15 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
The gate bias voltage of the pass gate transistor (T3) is set at approximately one
threshold voltage above the VCC level of the low-voltage side. During a LOW-to-HIGH
transition, the output one-shot accelerates the output transition. This acceleration is
achieved by switching on the PMOS transistors (T1, T2) bypassing the 10 k pull-up
resistors and increasing current drive capability. The one-shot is activated once the input
transition reaches approximately VCCI/2; it is de-activated approximately 50 ns after the
output reaches VCCO/2. During the acceleration time, the driver output resistance is
between approximately 50 and 70 . To avoid signal contention and minimize dynamic
ICC, wait for the one-shot circuit to turn-off before applying a signal in the opposite
direction. Pull-up resistors are included in the device for DC current sourcing capability.
14.3 Input driver requirements
As the NTS0104-Q100 is a switch type translator, properties of the input driver directly
affect the output signal. The external open-drain or push-pull driver applied to an I/O,
determines the static current sinking capability of the system. The maximum data rate,
HIGH-to-LOW output transition time (tTHL) and propagation delay (tPHL), are dependent
upon the output impedance and edge-rate of the external driver. The limits provided for
these parameters in the data sheet assume a driver with output impedance below 50 is
used.
14.4 Output load considerations
The maximum lumped capacitive load that can be driven is dependant upon the one-shot
pulse duration. In cases with very heavy capacitive loading, there is a risk that the output
does not reach the positive rail within the one-shot pulse duration.
To avoid excessive capacitive loading and to ensure correct triggering of the one-shot,
use short trace lengths and low capacitance connectors on NTS0104-Q100 PCB layouts.
To ensure low impedance termination and avoid output signal oscillations and one-shot
retriggering, control the length of the PCB trace. The PCB trace must limit the round-trip
delay of any reflection to within the one-shot pulse duration (approximately 50 ns).
14.5 Power-up
During operation VCC(A) must never be higher than VCC(B). However, during power-up
VCC(A) VCC(B) does not damage the device. This means that either power supply can be
ramped up first. There is no special power-up sequencing required. The NTS0104-Q100
includes circuitry that disables all output ports when either VCC(A) or VCC(B) is switched off.
14.6 Enable and disable
An output enable input (OE) is used to disable the device. Setting OE = LOW causes all
I/Os to assume the high-impedance OFF-state. The disable time (tdis with no external
load) indicates the delay between when OE goes LOW and when outputs actually
become disabled. The enable time (ten) indicates the amount of time required for one
one-shot circuit to become operational after OE is taken HIGH. To ensure the
high-impedance OFF-state during power-up or power-down, tie pin OE to GND through a
pull-down resistor. The current-sourcing capability of the driver determines the minimum
value of the resistor.
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
16 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
14.7 Pull-up or pull-down resistors on I/Os lines
Each A port I/O has an internal 10 k pull-up resistor to VCC(A). Each B port I/O has an
internal 10 k pull-up resistor to VCC(B). If a smaller value of pull-up resistor is required,
add an external resistor in parallel to the internal 10 k. The smaller value, affects the VOL
level. When OE goes LOW, the internal pull-ups of the NTS0104-Q100 are disabled.
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
17 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
15. Package outline
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 11. Package outline SOT402-1 (TSSOP14)
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
18 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
6
L
1
7
8
E
h
e
14
13
9
D
h
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
1
y
D
D
E
L
v
w
y
h
h
1
max.
0.05 0.30
0.00 0.18
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT762-1
- - -
MO-241
- - -
Fig 12. Package outline SOT762-1 (DHVQFN14)
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
19 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
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Fig 13. Package outline WLCSP12 package
NTS0104_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
20 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
16. Abbreviations
Table 14. Abbreviations
Acronym
CDM
CMOS
DUT
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
General Purpose Input Output
Military
GPIO
MIL
HBM
I2C
Human Body Model
Inter-Integrated Circuit
MM
Machine Model
SMBus
UART
System Management Bus
Universal Asynchronous Receiver Transmitter
17. Revision history
Table 15. Revision history
Document ID
Release date
20130523
Data sheet status
Change notice
Supersedes
NTS0104_Q100 v.2
Modifications:
Product data sheet
-
NTS0104_Q100 v.1
• added type numbers NTS0104PW-Q100 and NTS0104BQ-Q100.
20120807 Product data sheet
NTS0104_Q100 v.1
-
-
NTS0104_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
21 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
18.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
NTS0104_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
22 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NTS0104_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 23 May 2013
23 of 24
NTS0104-Q100
NXP Semiconductors
Dual supply translating transceiver; open drain; auto direction sensing
20. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9
10
11
12
13
14
Application information. . . . . . . . . . . . . . . . . . 15
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input driver requirements . . . . . . . . . . . . . . . . 16
Output load considerations. . . . . . . . . . . . . . . 16
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Enable and disable. . . . . . . . . . . . . . . . . . . . . 16
Pull-up or pull-down resistors on I/Os lines . . 17
14.1
14.2
14.3
14.4
14.5
14.6
14.7
15
16
17
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 May 2013
Document identifier: NTS0104_Q100
相关型号：
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