NX3DV42GU10 [NXP]
NX3DV42 - Dual high-speed USB 2.0 double-pole double-throw analog switch QFN 10-Pin;
| 型号： | NX3DV42GU10 |
| 厂家： | 
NXP |
| 描述： | NX3DV42 - Dual high-speed USB 2.0 double-pole double-throw analog switch QFN 10-Pin |
| 文件： | 总19页 (文件大小：806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NX3DV42
Dual high-speed USB 2.0 double-pole double-throw analog
switch
Rev. 3 — 13 February 2013
Product data sheet
1. General description
The NX3DV42 is a double-pole double-throw analog switch suitable for use as an analog
or digital multiplexer/demultiplexer. Its wide bandwidth and low bit-to-bit skew allows the
NX3DV42 to pass high-speed differential signals with good signal integrity. Its high
channel to channel crosstalk rejection results in minimal noise interference. The
bandwidth is wide enough to pass high-speed USB 2.0 differential signals (480 Mb/s). It
consist of two switches, each with two independent input/outputs (HSDn+ and HSDn)
and a common input/output (D+ or D). One digital input (S) is used to select the switch
position. When pin OE is HIGH, the switches are turned off. Schmitt trigger action at the
select input (S) and output enable input (OE) makes the circuit tolerant to slower input rise
and fall times across the entire VCC range from 3.0 V to 4.3 V.
2. Features and benefits
Supply voltage range from 3.0 V to 4.3 V
4 typical ON resistance
7.3 pF typical ON capacitance
950 MHz typical bandwidth or data frequency
Low crosstalk of 30 dB at 240 MHz
Break-before-make switching
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
CDM AEC-Q100-011 revision B exceeds 1000 V
HBM exceeds 12000 V for power to GND protection
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Specified from 40 C to +125 C
3. Applications
Cell phone, PDA, digital camera and notebook
LCD monitor, TV and set-top box
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
NX3DV42GM
NX3DV42GU
NX3DV42GU10
40 C to +125 C
40 C to +125 C
40 C to +125 C
XQFN10
plastic, extremely thin quad flat package; no leads;
10 terminals; body 1.55 2.00 0.5 mm
SOT1049-3
XQFN10
XQFN10
plastic, extremely thin quad flat package; no leads;
10 terminals; body 1.40 x 1.80 x 0.50 mm
SOT1160-1
plastic extremely thin small outline package; no leads; SOT1337-1
10 terminals; body 1.3 x 1.6 x 0.5 mm
5. Marking
Table 2.
Marking
Type number
NX3DV42GM
NX3DV42GU
NX3DV42GU10
Marking code
x4
x4
x4
6. Functional diagram
HSD1-
D-
HSD2-
HSD1+
D+
S
HSD2+
OE
aaa-001356
Fig 1. Logic symbol
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
2 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
7. Pinning information
7.1 Pinning
NX3DV42
IY"9W#!
terminal 1
index area
ꢔ
ꢍ
ꢏ
ꢒ
ꢗ
ꢙ
ꢐꢑ
D+
D-
1
2
7
6
HSD2+
HSD2-
ꢕꢖ
ꢕꢘ
ꢎ
ꢚ
ꢛ
ꢓꢔꢕꢎꢖ
ꢓꢔꢕꢎꢘ
ꢓꢔꢕꢍꢖ
ꢜꢝꢕ
aaa-001357
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢆ
Transparent top view
ꢀꢁꢂꢃꢄꢅꢂꢁꢆꢃꢇꢈꢇꢉꢅꢈꢊꢋꢆꢌ
Fig 2. Pin configuration SOT1049-3 (XQFN10)
Fig 3. Pin configuration SOT1160-1 and SOT1337-1
(XQFN10)
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT1049-3 SOT1160-1, SOT1337-1
HSD1, HSD2
5, 7
4, 6
5, 7
1, 2
3
independent input or output
independent input or output
common output or input
ground (0 V)
HSD1+, HSD2+
6, 8
2, 3
4
D+, D
GND
OE
9
8
output enable input (active LOW)
select input
S
1
10
9
VCC
10
supply voltage
8. Functional description
Table 4.
Function table[1]
Input
Channel on
S
L
OE
L
HSD1+ and HSD1
HSD2+ and HSD2
switch off
H
X
L
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
3 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
pins S and OE
VI < 0.5 V
Min
0.5
0.5
0.5
50
50
-
Max
+5.5
+5.5
+5.5
-
Unit
V
supply voltage
input voltage
[1]
V
VSW
IIK
switch voltage
input clamping current
V
mA
mA
mA
mA
C
ISK
switch clamping current VI < 0.5 V
switch current
-
ISW
ICC
100
+50
+150
250
supply current
-
Tstg
Ptot
storage temperature
65
-
[2]
total power dissipation
Tamb = 40 C to +125 C
mW
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] For XQFN10 packages: above 100 C derate linearly with 4 mW/K.
10. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol Parameter
Conditions
Min
3.0
0
Max
4.3
Unit
V
VCC
VI
supply voltage
input voltage
pins S and OE
4.5
V
[1]
VSW
Tamb
switch voltage
ambient temperature
0
VCC
V
40
+125
C
[1] To avoid sinking GND current from terminals D+ and D when switch current flows in terminals HSDn+ and HSDn, the voltage drop
across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminals D+ and D, no GND current will flow from
terminals HSDn+ and HSDn. In this case, there is no limit for the voltage drop across the switch.
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
1.3
1.7
-
Typ[1]
Max
-
Min
1.3
1.7
-
Max
-
VIH
VIL
HIGH-level
input voltage
VCC = 3.0 V to 3.6 V
VCC = 4.3 V
-
-
-
-
-
V
V
V
V
V
-
-
LOW-level
input voltage
VCC = 3.0 V to 3.6 V
VCC = 4.3 V
0.5
0.7
1.2
0.5
0.7
1.2
-
-
VIK
II
inputclamping VCC = 3.0 V; II = 18 mA
voltage
-
-
input leakage pins S and OE;
-
-
1
-
10
A
current
VI = GND to 4.3 V; VCC = 4.3 V;
see Figure 5
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
4 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
IS(OFF)
OFF-state
leakage
current
V
CC = 4.3 V; see Figure 4 and
-
-
1
-
2
A
A
A
Figure 7
IOFF
power-off
leakage
current
VI or VO = 0 V to 4.3 V;
VCC = 0 V; see Figure 8
-
-
-
-
1
-
-
10
ICC
supply current VI = VCC or GND; VCC = 4.3 V;
SW = GND or VCC; see
1
10
V
Figure 6
ICC
additional
supply current VSW = GND or VCC
VI = 2.6 V; VCC = 4.3 V;
-
-
-
-
-
-
10
15
-
-
-
-
-
-
10
15
-
A
A
pF
pF
pF
VI = 1.8 V; VCC = 4.3 V;
-
VSW = GND or VCC
CI
input
capacitance
pins S and OE
1.0
2.8
7.3
CS(OFF) OFF-state
capacitance
pins HSDn+ and HSDn
VCC = 3.3 V; VI = 0 V to 3.3 V
-
-
CS(ON)
ON-state
pins D+ and DVCC = 3.3 V;
-
-
capacitance
VI = 0 V to 3.3 V
[1] Typical values are measured at Tamb = 25 C and VCC = 3.3 V.
11.1 Test circuit and graphs
V
CC
switch
S
V
1
2
IL
S
HSD1-
HSD2-
1
2
V
or V
V
IL
IH
V
IH
D-
switch
I
S
OE
GND
IH
V
V
O
I
aaa-001365
VI = VCC or GND and VO = GND or VCC
.
Test circuit also applies for D+, HSD1+ and HSD2+.
Fig 4. Test circuit for measuring OFF-state leakage current
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
5 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
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ꢀꢀꢀꢁꢂꢂꢇꢃꢂꢅ
ꢎꢐꢋ
ꢎ)!
ꢑ
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*
##
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ꢎꢋꢋ
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!)
!
ꢋ
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ꢌꢍꢋ
ꢄꢅꢆꢇꢈ
ꢘꢛ!
!
ꢛ!
ꢒ!
ꢍꢎ!
ꢍꢙ!
ꢈ&ꢞ#(
ꢀ
ꢀ
ꢂ$%
ꢁꢂꢃ
VCC = 4.3 V.
VCC = 4.3 V.
Fig 5. Waveform showing the typical input leakage
current versus temperature
Fig 6. Waveform showing the typical supply current
versus temperature
ꢀꢀꢀꢁꢂꢂꢇꢃꢂꢃ
ꢀꢀꢀꢁꢂꢂꢇꢃꢂꢄ
ꢍ !
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ꢚ!!
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ꢍꢎ
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ꢍ!!
!
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!
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!
!
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!
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ꢒ!
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!
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VCC = 4.3 V.
VCC = 4.3 V.
Fig 7. Waveform showing the typical OFF-state
leakage current versus temperature
Fig 8. Waveform showing the typical power-off
leakage current versus temperature
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
6 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
11.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Tamb = 40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
RON
ON resistance
VI = 0.4 V; ISW = 8 mA;
see Figure 9
VCC = 3.0 V
-
-
3.9
6.5
-
-
-
10
-
[2]
RON
ON resistance
mismatch between
channels
VI = 0.4 V; ISW = 8 mA
VCC = 3.0 V
0.65
[1] Typical values are measured at Tamb = 25 C.
[2] Measured at identical VCC, temperature and input voltage.
11.3 ON resistance test circuit
V
V
switch
S
CC
V
SW
V
1
2
IL
S
V
IH
HSD1-
HSD2-
1
2
V
IL
or V
IH
D-
switch
OE
GND
V
IL
V
I
SW
I
aaa-001366
RON = VSW / ISW
.
Test circuit also applies for D+, HSD1+ and HSD2+.
Fig 9. Test circuit for measuring ON resistance
12. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2][3]
tpd
propagation delay HSDn+ to D+ or
HSDn to Dor
D+ to HSDn+ or
D to HSDn;
see Figure 10
VCC = 3.3 V
-
-
0.25
11.2
-
-
-
-
ns
ns
[4]
ten
enable time
S or OE to D+ or D;
see Figure 11
VCC = 3.0 V to 3.6 V
30
40
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
7 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
Table 9.
Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[5]
[3]
tdis
disable time
S or OE to D+ or D;
see Figure 11
VCC = 3.0 V to 3.6 V
-
3.9
5.9
25
-
-
30
-
ns
ns
tb-m
tsk(p)
tjit
break-before-make see Figure 12
time
VCC = 3.0 V to 3.6 V
2.0
2.0
pulse skew time
see Figure 10
[3]
[3]
VCC = 3.0 V to 3.6 V
-
-
20
-
-
-
-
-
-
ps
ps
jitter time
RL = 50 ; CL = 5 pF; tr, tf
= 500 ps (10 % to 90 %) at
480 Mbs (PRBS = 215 1)
200
[1] Typical values are measured at Tamb = 25 C, CL = 5 pF and VCC = 3.3 V.
[2] tpd is the same as tPLH and tPHL
[3] Guaranteed by design.
.
[4]
ten is the same as tPZH.
[5] tdis is the same as tPHZ
.
12.1 Waveforms and test circuits
400 mV
input
GND
50%
t
t
PLH
PHL
V
OH
output
50%
V
OL
aaa-001359
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
sk(p) = |tPHL tPLH|.
t
Fig 10. The data input to output propagation delay times and pulse skew time
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
8 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
V
I
S, OE input
V
M
GND
t
t
PHZ
PZH
V
OH
V
X
V
X
output
HIGH to OFF
OFF to HIGH
GND
switch
enabled
switch
disabled
switch
enabled
aaa-001361
Measurement points are given in Table 10.
Logic level: VOH is the typical output voltage level that occurs with the output load.
Fig 11. Enable and disable times
Table 10. Measurement points
Supply voltage
VCC
Input
VM
Output
VI
VX
3.0 V to 3.6 V
0.5VCC
VCC
0.9VOH
V
CC
S
HSD1-
HSD2-
D-
OE
V
IL
G
V
V
I
V
R
C
V
= 0.8 V
EXT
O
L
L
GND
aaa-001364
a. Test circuit.
V
I
0.5V
I
0.9V
O
0.9V
O
V
O
t
b-m
001aag572
b. Input and output measurement points.
Test circuit also applies for D+, HSD1+ and HSD2+.
Fig 12. Test circuit for measuring break-before-make timing
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
9 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
V
CC
S
HSD1-
HSD2-
D-
OE
V
IL
G
V
I
C
R
V
= 0.8 V
EXT
L
L
GND
aaa-001363
Test circuit also applies for D+, HSD1+ and HSD2+.
Test data is given in Table 11.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
EXT = External voltage for measuring switching times.
V
VI may be connected to S or OE.
Fig 13. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
tr, tf
RL
3.0 V to 3.6 V
VCC
2.5 ns
5 pF
50
12.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf < 2.5 ns.
Symbol Parameter
Conditions
Tamb = 25 C
Unit
Min Typ[2] Max
[1]
f(3dB)
3 dB frequency
RL = 50 ; see Figure 14
response
CL = 0 pF; VCC = 3.0 V to 3.6 V
CL = 5 pF; VCC = 3.0 V to 3.6 V
fi = 240 MHz; RL = 50 ; see Figure 15
VCC = 3.0 V to 3.6 V
-
-
950
450
-
-
MHz
MHz
[1]
[1]
iso
isolation (OFF-state)
crosstalk
-
-
30
30
-
-
dB
dB
Xtalk
between switches;
fi = 240 MHz; RL = 50 ; see Figure 16
VCC = 3.0 V to 3.6 V
[1] fi is biased at 0.5VCC
.
[2] Typical values are measured at Tamb = 25 C and VCC = 3.3 V.
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
10 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
12.3 Test circuits
0.5V
CC
V
CC
switch
S
V
1
2
IL
R
L
S
HSD1-
HSD2-
1
2
V
or V
IH
IL
V
IH
switch
D-
OE
V
IL
f
C
L
dB
i
GND
aaa-001360
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB.
Test circuit also applies for D+, HSD1+ and HSD2+.
Fig 14. Test circuit for measuring the frequency response when channel is in ON-state
0.5V
0.5V
CC
CC
V
switch
S
CC
R
R
L
L
V
1
2
IH
S
V
IL
HSD1-
HSD2-
1
2
V
IL
or V
IH
D-
switch
OE
GND
V
IH
f
dB
i
aaa-001367
Adjust fi voltage to obtain 0 dBm level at input.
Test circuit also applies for D+, HSD1+ and HSD2+.
Fig 15. Test circuit for measuring isolation (OFF-state)
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
11 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
0.5V
CC
R
L
CHANNEL
ON
HSD1+ or
HSD2+
D+
S
f
50 Ω
V
O1
V
i
V
IL
0.5V
CC
R
L
HSD1 or
HSD2
D
CHANNEL
OFF
R
i
V
V
O2
50 Ω
aaa-001362
20 log10 (VO2/VO1) or 20 log10 (VO1/VO2).
Fig 16. Test circuit for measuring crosstalk between switches
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
12 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
13. Package outline
XQFN10: plastic, extremely thin quad flat package; no leads;
10 terminals; body 1.55 x 2.00 x 0.50 mm
SOT1049-3
X
D
B
A
E
terminal 1
index area
A
A
1
c
detail X
C
Æ v
Æ w
C
C
A
B
b
5
y
1
y
C
4
1
6
e
1
e
9
b
1
10
terminal 1
index area
L
L
1
0
1
2 mm
w
scale
Dimensions
(1)
Unit
A
A
1
b
b
c
D
E
e
e
1
L
L
v
y
y
1
1
1
max 0.5 0.05 0.25 0.33
1.65 2.1
0.20 0.28 0.127 1.55 2.0 0.5 1.5 0.43 0.35 0.1 0.05 0.05 0.05
0.00 0.15 0.23 1.45 1.9 0.38 0.30
0.48 0.40
mm nom
min
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot1049-3_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
MO255
JEITA
- - -
10-12-06
11-03-30
SOT1049-3
Fig 17. Package outline SOT1049-3 (XQFN10)
NX3DV42
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
13 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
XQFN10: plastic, extremely thin quad flat package; no leads;
10 terminals; body 1.40 x 1.80 x 0.50 mm
SOT1160-1
X
D
B
A
E
terminal 1
index area
A
A
1
A
3
detail X
e
1
e
C
v
C A
B
b
y
C
1
y
w
C
3
5
L
2
1
6
7
e
2
terminal 1
index area
10
8
L
1
0
1
2 mm
w
scale
Dimensions
(1)
Unit
A
A
A
b
D
E
e
e
e
2
L
L
1
v
y
y
1
1
3
1
max 0.5 0.05
mm nom
min
0.25 1.5 1.9
0.127 0.20 1.4 1.8 0.4 0.8 0.4 0.40 0.50 0.1 0.05 0.05 0.05
0.15 1.3 1.7 0.35 0.45
0.45 0.55
0.00
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot1160-1_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
09-12-28
09-12-29
SOT1160-1
Fig 18. Package outline SOT1160-1 (XQFN10)
NX3DV42
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
14 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
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Fig 19. Package outline SOT1337-1 (XQFN10)
NX3DV42
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
15 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
14. Abbreviations
Table 13. Abbreviations
Acronym
CDM
CMOS
ESD
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
HBM
LCD
Liquid Crystal Display
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 14. Revision history
Document ID
NX3DV42 v.3
Modifications:
Release date
20130213
Data sheet status
Change notice
Supersedes
Product data sheet
-
NX3DV42 v.2
• Values added for Tamb = +125 C throughout the data sheet.
• Type number NX3DV42GU10 added (Table 1).
• Marking code for type number NX3DV42GU10 added (Table 2).
• Package outline drawing SOT1337-1 added (Figure 19).
NX3DV42 v.2
Modifications:
NX3DV42 v.1
20120618
Product data sheet
-
NX3DV42 v.1
• Package outline drawing SOT1049-2 changed to SOT1049-3 (Figure 17).
20120103 Product data sheet
-
-
NX3DV42
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
16 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
NX3DV42
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
17 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NX3DV42
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 13 February 2013
18 of 19
NX3DV42
NXP Semiconductors
Dual high-speed USB 2.0 double-pole double-throw analog switch
18. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
9
10
11
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Test circuit and graphs . . . . . . . . . . . . . . . . . . . 5
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance test circuit . . . . . . . . . . . . . . . . . 7
11.1
11.2
11.3
12
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms and test circuits . . . . . . . . . . . . . . . 8
Additional dynamic characteristics . . . . . . . . . 10
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12.1
12.2
12.3
13
14
15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 February 2013
Document identifier: NX3DV42
相关型号：
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