NX3L1G53GM,125 [NXP]
NX3L1G53 - Low-ohmic single-pole double-throw analog switch QFN 8-Pin;
| 型号： | NX3L1G53GM,125 |
| 厂家： | 
NXP |
| 描述： | NX3L1G53 - Low-ohmic single-pole double-throw analog switch QFN 8-Pin 光电二极管 |
| 文件： | 总24页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NX3L1G53
Low-ohmic single-pole double-throw analog switch
Rev. 7.1 — 15 November 2016
Product data sheet
1. General description
The NX3L1G53 is a low-ohmic single-pole double-throw analog switch suitable for use as
an analog or digital 2:1 multiplexer/demultiplexer. It has a digital select input (S), two
independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an active LOW
enable input (E). When pin E is HIGH, the switch is turned off. Schmitt trigger action at the
digital inputs makes the circuit tolerant to slower input rise and fall times.
The NX3L1G53 allows signals with amplitude up to VCC to be transmitted from Z to Y0 or
Y1; or from Y0 or Y1 to Z. Its low ON resistance (0.5 ) and flatness (0.13 ) ensures
minimal attenuation and distortion of transmitted signals.
2. Features and benefits
Wide supply voltage range from 1.4 V to 4.3 V
Very low ON resistance (peak):
1.6 (typical) at VCC = 1.4 V
1.0 (typical) at VCC = 1.65 V
0.55 (typical) at VCC = 2.3 V
0.50 (typical) at VCC = 2.7 V
0.50 (typical) at VCC = 4.3 V
Break-before-make switching
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 7500 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
IEC61000-4-2 contact discharge exceeds 8000 V for switch ports
CMOS low-power consumption
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Direct interface with TTL levels at 3.0 V
Control input accepts voltages above supply voltage
High current handling capability (350 mA continuous current under 3.3 V supply)
Specified from 40 C to +85 C and from 40 C to +125 C
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
3. Applications
Cell phone
PDA
Portable media player
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
NX3L1G53GT
NX3L1G53GD
NX3L1G53GM
40 C to +125 C
40 C to +125 C
40 C to +125 C
XSON8 plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 1.95 0.5 mm
XSON8 plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm
XQFN8
plastic, extremely thin quad flat package; no leads;
SOT902-2
8 terminals; body 1.6 1.6 0.5 mm
5. Marking
Table 2.
Marking codes[1]
Type number
NX3L1G53GT
NX3L1G53GD
NX3L1G53GM
Marking code
D53
D53
D53
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
6
7
Y1
Y0
S
Z
5
1
E
2
001aad386
Fig 1. Logic symbol
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
2 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
Y0
S
Z
Y1
E
001aad387
Fig 2. Logic diagram
7. Pinning information
7.1 Pinning
NX3L1G53
Z
E
1
2
3
4
8
7
6
5
V
CC
NX3L1G53
Z
E
1
2
3
4
8
7
6
5
V
CC
Y0
Y1
S
Y0
Y1
S
GND
GND
GND
GND
001aah454
001aaj534
Transparent top view
Transparent top view
Fig 3. Pin configuration SOT833-1 (XSON8)
Fig 4. Pin configuration SOT996-2 (XSON8)
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
3 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
NX3L1G53
terminal 1
index area
Y0
1
7
6
5
Z
Y1
S
2
3
E
GND
001aah455
Transparent top view
Fig 5. Pin configuration SOT902-2 (XQFN8)
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT833-1 and SOT996-2
SOT902-2
Z
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
8
common output or input
enable input (active LOW)
ground (0 V)
E
GND
GND
S
ground (0 V)
select input
Y1
Y0
VCC
independent input or output
independent input or output
supply voltage
8. Functional description
Table 4.
Function table[1]
Input
Channel
S
L
E
L
Y0 to Z or Z to Y0
Y1 to Z or Z to Y1
switch off
H
X
L
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
4 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
Min
0.5
0.5
0.5
50
-
Max
+4.6
+4.6
Unit
V
supply voltage
input voltage
[1]
[2]
select input S and enable input E
VI < 0.5 V
V
VSW
IIK
switch voltage
input clamping current
VCC + 0.5 V
-
mA
ISK
switch clamping current VI < 0.5 V or VI > VCC + 0.5 V
50
350
mA
mA
ISW
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V;
-
source or sink current
VSW > 0.5 V or VSW < VCC + 0.5 V;
-
500
mA
pulsed at 1 ms duration, < 10 % duty cycle;
peak current
Tstg
Ptot
storage temperature
total power dissipation
65
+150
250
C
[3]
Tamb = 40 C to +125 C
-
mW
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not
exceed 4.6 V.
[3] For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
10. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol Parameter
Conditions
Min
1.4
0
Max
4.3
Unit
V
VCC
VI
supply voltage
input voltage
select input S and enable input E
4.3
V
[1]
[2]
VSW
Tamb
t/V
switch voltage
0
VCC
+125
200
V
ambient temperature
input transition rise and fall rate
40
-
C
ns/V
VCC = 1.4 V to 4.3 V
[1] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit
for the voltage drop across the switch.
[2] Applies to control signals.
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
5 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min
Typ
Max
Min
Max
Max
(85 C) (125 C)
VIH
HIGH-level
input voltage
VCC = 1.4 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
VCC = 1.4 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
0.65VCC
-
-
-
-
-
-
-
-
-
-
0.65VCC
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
A
1.7
-
1.7
2.0
-
2.0
0.7VCC
-
0.35VCC
0.7
0.7VCC
VIL
LOW-level
input voltage
-
-
-
-
-
-
-
-
-
-
0.35VCC 0.35VCC
0.7
0.8
0.7
0.8
0.8
0.3VCC
-
0.3VCC 0.3VCC
II
input leakage select input S and enable
0.5
1
current
input E; VI = GND to 4.3 V;
VCC = 1.4 V to 4.3 V
IS(OFF)
OFF-state
leakage
current
Y0 and Y1 port;
see Figure 6
VCC = 1.4 V to 3.6 V
VCC = 3.6 V to 4.3 V
Z port; see Figure 7
VCC = 1.4 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
-
-
5
-
-
50
50
500 nA
500 nA
10
IS(ON)
ON-state
leakage
current
-
-
-
-
5
-
-
50
50
500 nA
500 nA
10
ICC
supply current VI = VCC or GND;
VSW = GND or VCC
VCC = 3.6 V
VCC = 4.3 V
-
-
-
-
-
100
150
-
-
-
-
690
800
-
6000 nA
7000 nA
CI
input
1.0
-
-
-
pF
pF
pF
capacitance
CS(OFF) OFF-state
capacitance
-
-
35
-
-
-
-
-
-
CS(ON)
ON-state
130
capacitance
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
6 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
11.1 Test circuits
V
CC
switch
S
E
1
2
V
V
IL
IH
IH
V
V
IH
S
Z
Y0
Y1
1
2
V
or V
V
IL
IH
switch
I
S
E
GND
IH
V
V
O
I
001aad390
VI = 0.3 V or VCC 0.3 V; VO = VCC 0.3 V or 0.3 V.
Fig 6. Test circuit for measuring OFF-state leakage current
V
CC
switch
S
E
1
2
V
V
IL
IL
IL
V
IH
V
S
Z
Y0
Y1
1
2
V
or V
IH
IL
switch
I
S
E
GND
V
IL
V
V
O
I
001aad391
VI = 0.3 V or VCC 0.3 V; VO = open circuit.
Fig 7. Test circuit for measuring ON-state leakage current
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
7 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
11.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min Typ[1] Max
Min
Max
RON(peak) ON resistance (peak)
VI = GND to VCC
;
I
SW = 100 mA;
see Figure 8
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 4.3 V
-
-
-
-
-
1.6
1.0
3.7
1.6
-
-
-
-
-
4.1
1.7
0.9
0.9
0.9
0.55
0.5
0.8
0.75
0.75
0.5
[2]
RON
ON resistance mismatch VI = GND to VCC;
between channels
ISW = 100 mA
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 4.3 V
-
-
-
-
-
0.04
0.04
0.02
0.02
0.02
0.3
0.2
-
-
-
-
-
0.3
0.3
0.1
0.1
0.1
0.08
0.075
0.075
[3]
RON(flat)
ON resistance (flatness) VI = GND to VCC
ISW = 100 mA
;
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 4.3 V
-
-
-
-
-
1.0
0.5
3.3
1.2
0.3
0.3
0.4
-
-
-
-
-
3.6
1.3
0.15
0.13
0.2
0.35
0.35
0.45
[1] Typical values are measured at Tamb = 25 C.
[2] Measured at identical VCC, temperature and input voltage.
[3] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
8 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
11.3 ON resistance test circuit and waveforms
V
V
switch
S
E
CC
V
SW
1
2
V
V
IL
IL
IL
V
V
IH
S
Z
Y0
Y1
1
V
or V
IH
IL
switch
2
E
GND
V
IL
V
I
SW
I
001aah456
RON = VSW / ISW
.
Fig 8. Test circuit for measuring ON resistance
001aag564
1.6
R
ON
(Ω)
1.2
(1)
0.8
0.4
0
(2)
(3)
(4)
(5)
(6)
0
1
2
3
4
5
V (V)
I
(1) VCC = 1.5 V.
(2) CC = 1.8 V.
V
(3) VCC = 2.5 V.
(4) VCC = 2.7 V.
(5) VCC = 3.3 V.
(6)
V
CC = 4.3 V.
Measured at Tamb = 25 C.
Fig 9. ON resistance as a function of input voltage
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
9 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
001aag565
001aag566
1.6
1.0
R
(Ω)
ON
R
(Ω)
ON
0.8
1.2
(1)
(2)
(3)
(4)
0.6
0.4
0.2
0
(1)
(2)
(3)
(4)
0.8
0.4
0
0
1
2
3
0
1
2
3
V (V)
I
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 10. ON resistance as a function of input voltage;
VCC = 1.5 V
Fig 11. ON resistance as a function of input voltage;
VCC = 1.8 V
001aag567
001aaj896
1.0
1.0
R
ON
R
ON
(Ω)
(Ω)
0.8
0.8
(1)
(2)
(3)
(4)
0.6
0.4
0.2
0
0.6
0.4
0.2
0
(1)
(2)
(3)
(4)
0
1
2
3
0
1
2
3
4
5
V (V)
V (V)
I
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 12. ON resistance as a function of input voltage;
VCC = 2.5 V
Fig 13. ON resistance as a function of input voltage;
VCC = 2.7 V
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
10 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
001aag569
001aaj896
1.0
1.0
R
ON
R
ON
(Ω)
(Ω)
0.8
0.8
(1)
(2)
(3)
(4)
0.6
0.4
0.2
0
0.6
0.4
0.2
0
(1)
(2)
(3)
(4)
0
1
2
3
4
0
1
2
3
4
5
V (V)
I
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 14. ON resistance as a function of input voltage;
VCC = 3.3 V
Fig 15. ON resistance as a function of input voltage;
VCC = 4.3 V
12. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max
Min
Max
Max
(85 C) (125 C)
ten
enable time
S or E to Z or Yn;
see Figure 16
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
-
-
-
28
23
17
15
15
42
34
27
24
24
-
-
-
-
-
45
37
29
26
26
50
41
31
28
28
ns
ns
ns
ns
ns
tdis
disable time
S or E to Z or Yn;
see Figure 16
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.7 V to 4.3 V
-
-
-
-
-
10
7
19
14
9
-
-
-
-
-
21
16
10
9
23
17
11
9
ns
ns
ns
ns
ns
5
4
8
4
8
9
9
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
11 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
Table 9.
Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol Parameter
Conditions
25 C
40 C to +125 C
Unit
Min Typ[1] Max
Min
Max
Max
(85 C) (125 C)
[2]
tb-m
break-before-make see Figure 17
time
VCC = 1.4 V to 1.6 V
-
-
-
-
-
19
17
13
10
10
-
-
-
-
-
9
7
5
3
2
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.7 V to 4.3 V
[1] Typical values are measured at Tamb = 25 C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively.
[2] Break-before-make guaranteed by design.
12.1 Waveform and test circuits
V
I
V
V
S, E input
M
M
GND
t
t
dis
en
V
OH
output
OFF to HIGH
HIGH to OFF
V
V
X
X
GND
t
t
en
dis
V
OH
V
V
X
X
output
HIGH to OFF
OFF to HIGH
001aah457
GND
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Enable and disable times
Table 10. Measurement points
Supply voltage
VCC
Input
VM
Output
VX
1.4 V to 4.3 V
0.5VCC
0.9VOH
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
12 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
V
CC
S
Z
Y0
Y1
E
V
IL
G
V
V
R
L
C
L
V
= 1.5 V
EXT
V
I
O
GND
001aah458
a. Test circuit
V
I
0.5V
I
0.9V
O
0.9V
O
V
O
t
b-m
001aag572
b. Input and output measurement points
Fig 17. Test circuit for measuring break-before-make timing
V
CC
S
Z
Y0
Y1
1
switch
2
E
V
IL
G
V
V
R
L
C
L
V
= 1.5 V
EXT
V
I
O
GND
001aah459
Test data is given in Table 11.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
EXT = External voltage for measuring switching times.
V
VI may be connected to S or E.
Fig 18. Test circuit for measuring switching times
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
13 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
tr, tf
CL
RL
1.4 V to 4.3 V
VCC
2.5 ns
35 pF
50
12.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf 2.5 ns; Tamb = 25 C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[1]
THD
total harmonic
distortion
fi = 20 Hz to 20 kHz; RL = 32 ; see Figure 19
VCC = 1.4 V; VI = 1 V (p-p)
VCC = 1.65 V; VI = 1.2 V (p-p)
VCC = 2.3 V; VI = 1.5 V (p-p)
VCC = 2.7 V; VI = 2 V (p-p)
VCC = 4.3 V; VI = 2 V (p-p)
RL = 50 ; see Figure 20
VCC = 1.4 V to 4.3 V
-
-
-
-
-
0.15
-
-
-
-
-
%
%
%
%
%
0.10
0.02
0.02
0.02
[1]
[1]
f(3dB)
3 dB frequency
response
-
-
60
-
-
MHz
dB
iso
isolation (OFF-state)
crosstalk voltage
fi = 100 kHz; RL = 50 ; see Figure 21
VCC = 1.4 V to 4.3 V
90
Vct
between digital inputs and switch;
fi = 1 MHz; CL = 50 pF; RL = 50 ; see Figure 22
VCC = 1.4 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
0.2
0.3
-
-
V
V
[1]
Xtalk
Qinj
crosstalk
between switches;
fi = 100 kHz; RL = 50 ; see Figure 23
VCC = 1.4 V to 4.3 V
-
90
-
dB
charge injection
fi = 1 MHz; CL = 0.1 nF; RL = 1 M; Vgen = 0 V;
Rgen = 0 ; see Figure 24
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.3 V
-
-
-
-
-
3
4
-
-
-
-
-
pC
pC
pC
pC
pC
6
9
15
[1] fi is biased at 0.5VCC
.
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
14 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
12.3 Test circuits
V
CC
0.5V
CC
switch
S
E
1
2
V
V
IL
IL
IL
R
L
S
Z
Y0
Y1
1
2
V
IH
V
V
IL
or V
IH
switch
E
V
IL
f
D
i
GND
001aah460
Fig 19. Test circuit for measuring total harmonic distortion
V
CC
0.5V
CC
switch
S
E
1
2
V
V
V
IL
IL
IL
R
L
S
Z
Y0
Y1
1
2
V
IH
V
IL
or V
IH
switch
E
V
IL
f
dB
i
GND
001aah461
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
0.5V
V
0.5V
CC
CC
CC
switch
S
E
1
2
V
V
IH
IH
IH
R
L
R
L
S
Z
Y0
Y1
1
2
V
V
IL
V
or V
V
IL
IH
switch
E
IH
f
dB
i
GND
001aah462
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring isolation (OFF-state)
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
15 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
V
CC
E
S
Z
Y0
Y1
V
or V
IH
IL
logic
input
G
V
R
L
R
L
C
L
V
O
V
I
0.5V
0.5V
CC
CC
001aah452
a. Test circuit
logic input
(S, E)
off
on
off
V
ct
V
O
001aah453
b. Input and output pulse definitions
VI may be connected to S or E.
Fig 22. Test circuit for measuring crosstalk voltage between digital inputs and switch
V
0.5V
0.5V
CC
CC
CC
R
L
R
L
S
Z
Y0
Y1
1
V
or V
V
IL
IH
2
E
IH
f
dB
i
GND
001aah463
Fig 23. Test circuit for measuring crosstalk
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
16 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
V
CC
S
Z
Y0
Y1
1
2
switch
E
R
gen
V
IL
G
V
V
R
L
C
L
I
O
V
gen
GND
001aad398
a. Test circuit
logic input
(S, E)
off
on
off
V
O
ΔV
O
001aah451
b. Input and output pulse definitions
Qinj = VO CL.
VO = output voltage variation.
Rgen = generator resistance.
V
gen = generator voltage.
VI may be connected to S or E.
Fig 24. Test circuit for measuring charge injection
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
17 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
13. Package outline
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
b
1
2
3
4
4×
(2)
L
L
1
e
8
7
6
5
e
1
e
1
e
1
8×
A
(2)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
1
L
L
1
max max
0.25
0.17
2.0
1.9
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-11-14
07-12-07
SOT833-1
- - -
MO-252
Fig 25. Package outline SOT833-1 (XSON8)
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
18 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
XSON8: plastic extremely thin small outline package; no leads;
8 terminals; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
v
C
C
A
B
b
e
L
1
y
1
y
w
C
1
4
L
2
L
8
5
X
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
1
b
D
E
e
e
L
L
1
L
2
v
w
y
y
1
1
max
mm nom 0.5
min
0.05 0.35 2.1 3.1
0.00 0.15 1.9 2.9
0.5 0.15 0.6
0.3 0.05 0.4
0.5 1.5
0.1 0.05 0.05 0.1
sot996-2_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
07-12-21
12-11-20
SOT996-2
Fig 26. Package outline SOT996-2 (XSON8)
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
19 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm
SOT902-2
X
D
B
A
E
terminal 1
index area
A
A
1
detail X
e
C
v
C
C
A
B
b
y
y
w
C
1
4
3
2
5
e
1
terminal 1
index area
6
7
k
L
1
8
metal area
not for soldering
L
2
L
k
L
3
L
1
0
1
2 mm
v
scale
Dimensions
(1)
Unit
A
A
1
b
D
E
e
e
k
L
L
L
2
L
3
w
y
y
1
1
1
max 0.5 0.05 0.25 1.65 1.65
0.35 0.15 0.25 0.35
0.30 0.10 0.20 0.30 0.1 0.05 0.05 0.05
0.2 0.25 0.05 0.15 0.25
mm nom
min
0.20 1.60 1.60 0.55 0.5
0.00 0.15 1.55 1.55
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot902-2_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
16-07-14
16-11-08
SOT902-2
MO-255
Fig 27. Package outline SOT902-2 (XQFN8)
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
20 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
14. Abbreviations
Table 13. Abbreviations
Acronym
CDM
CMOS
ESD
Description
Charged Device Model
Complementary Metal Oxide Semiconductor
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 14. Revision history
Document ID
NX3L1G53 v.7.1
Modifications:
NX3L1G53 v.7
Modifications:
NX3L1G53 v.6
NX3L1G53 v.5
NX3L1G53 v.4
NX3L1G53 v.3
NX3L1G53 v.2
NX3L1G53 v.1
Release date
20161115
Data sheet status
Change notice
Supersedes
Product data sheet
-
NX3L1G53 v.7
• Updated Figure 27 “Package outline SOT902-2 (XQFN8)”
20130208 Product data sheet
• For type number NX3L1G53GD XSON8U has changed to XSON8
20120613
20111109
20100127
20090417
20080718
20080408
-
NX3L1G53 v.6
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
-
-
-
-
-
-
NX3L1G53 v.5
NX3L1G53 v.4
NX3L1G53 v.3
NX3L1G53 v.2
NX3L1G53 v.1
-
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
21 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
22 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NX3L1G53
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2016. All rights reserved.
Product data sheet
Rev. 7.1 — 15 November 2016
23 of 24
NX3L1G53
NXP Semiconductors
Low-ohmic single-pole double-throw analog switch
18. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
9
10
11
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 8
ON resistance test circuit and waveforms . . . . 9
11.1
11.2
11.3
12
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Waveform and test circuits . . . . . . . . . . . . . . . 12
Additional dynamic characteristics . . . . . . . . . 14
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
12.1
12.2
12.3
13
14
15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 22
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 November 2016
Document identifier: NX3L1G53
相关型号：
©2020 ICPDF网 联系我们和版权申明