OQ2535HP [NXP]
SDH/SONET STM16/OC48 multiplexer; SDH / SONET STM16 / OC48多路复用器
| 型号： | OQ2535HP |
| 厂家： | 
NXP |
| 描述： | SDH/SONET STM16/OC48 multiplexer |
| 文件： | 总19页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
OQ2535HP
SDH/SONET STM16/OC48
multiplexer
Product specification
1999 Oct 04
Supersedes data of 1997 Nov 27
File under Integrated Circuits, IC19
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
FEATURES
GENERAL DESCRIPTION
• Normal and loop (test) modes
The OQ2535HP is a 32-channel multiplexer intended for
use in STM16/OC48 applications. It combines data from a
total of 32 × 78 Mbits/s input channels onto a single
2.5 Gbits/s output channel. It features 3.3 V TTL data
inputs and a 5 V TTL clock output at the low speed
interface, and CML compatible inputs and outputs at the
high speed interface.
• 3.3 V TTL compatible data inputs
• Differential Current-Mode Logic (CML) clock and data
outputs
• 5 V TTL clock output (low speed interface)
• High input sensitivity (100 mV for the high speed clock
input)
• Boundary Scan Test (BST) at low speed interface, in
accordance with “IEEE Std 1149.1-1990”
• Low power dissipation (typically 1.65 W).
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
OQ2535HP
HLQFP100 plastic heat-dissipating low profile quad flat package; 100 leads;
body 14 × 14 × 1.4 mm
SOT470-1
BLOCK DIAGRAM
90
91
DOUT
2.5 Gbits/s
622 Mbits/s
78
Mbits/s
(1)
DOUTQ
D0
to
D31
4 ×
8 : 1 MUX
4
4 : 1 MUX
82
83
32
COUT
COUTQ
62
ENL
load
pulse
clock
65
66
59
58
OQ2535HP
DLOOP
SYNSEL1
SYNSEL2
SYNCHRONIZATION
DLOOPQ
2
5
3
7
6
TRST
TMS
TCK
TDI
68
69
CLOOP
CLOOPQ
622 MHz
DIVIDE BY 8
TDO
2.5 GHz
71
72
CIN
78 MHz
13
CDIV
DIVIDE BY 4
CINQ
74
75
DIOA
DIOC
BAND GAP
REFERENCE 1
BAND GAP
REFERENCE 2
(2)
14, 37,
63, 85, 86
12, 39,
87, 88
61
38
10
78
16
60
5
4
31
GND
REFC2
REFC1
BGCAP1
BGCAP2 V
V
V
V
CC
MGK351
CC(T) DD
EE
(1) See Chapter “Pinning” for D0 to D31 pin numbers.
(2) Pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100.
Fig.1 Block diagram.
1999 Oct 04
2
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
PINNING
SYMBOL
GND
PIN
TYPE(1)
DESCRIPTION
1
S
I
ground
TRS
TCK
GND
TMS
TDO
TDI
2
test reset input for BST mode (active LOW)
test clock input for BST mode
ground
3
I
4
S
I
5
test mode select input for BST mode
serial test data output for BST mode
serial test data input for BST mode
ground
6
O
I
7
GND
GND
BGCAP1
GND
VEE
8
S
S
A
S
S
O
S
S
S
S
I
9
ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
pin for connecting external band gap decoupling capacitor (4 × 8 : 1 MUX)
ground
supply voltage (−4.5 V)
CDIV
VDD
78 MHz clock output
supply voltage (+3.3 V)
GND
VCC(T)
GND
D31
D27
D23
GND
D19
D15
D11
GND
D7
ground
supply voltage for TTL buffer (+5.0 V); not connected internally to VCC
ground
78 Mbits/s data input channel for D31
78 Mbits/s data input channel for D27
78 Mbits/s data input channel for D23
ground
I
I
S
I
78 Mbits/s data input channel for D19
78 Mbits/s data input channel for D15
78 Mbits/s data input channel for D11
ground
I
I
S
I
78 Mbits/s data input channel for D7
78 Mbits/s data input channel for D3
78 Mbits/s data input channel for D30
78 Mbits/s data input channel for D26
78 Mbits/s data input channel for D22
78 Mbits/s data input channel for D18
78 Mbits/s data input channel for D14
78 Mbits/s data input channel for D10
78 Mbits/s data input channel for D6
78 Mbits/s data input channel for D2
ground
D3
I
D30
D26
D22
D18
D14
D10
D6
I
I
I
I
I
I
I
D2
I
GND
VDD
S
S
A
supply voltage (+3.3 V)
REFC2
pin for connecting external reference decoupling capacitor (3.3 V CMOS
reference)
VEE
39
S
supply voltage (−4.5 V)
1999 Oct 04
3
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
SYMBOL
GND
PIN
TYPE(1)
DESCRIPTION
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
S
I
ground
D29
D25
D21
D17
D13
D9
78 Mbits/s data input channel for D29
78 Mbits/s data input channel for D25
78 Mbits/s data input channel for D21
78 Mbits/s data input channel for D17
78 Mbits/s data input channel for D13
78 Mbits/s data input channel for D9
78 Mbits/s data input channel for D5
78 Mbits/s data input channel for D1
78 Mbits/s data input channel for D28
78 Mbits/s data input channel for D24
78 Mbits/s data input channel for D20
78 Mbits/s data input channel for D16
78 Mbits/s data input channel for D12
78 Mbits/s data input channel for D8
78 Mbits/s data input channel for D4
ground
I
I
I
I
I
D5
I
D1
I
D28
D24
D20
D16
D12
D8
I
I
I
I
I
I
D4
I
GND
D0
S
I
78 Mbits/s data input channel for D0
selection input 2 for synchronization pulse timing
selection input 1 for synchronization pulse timing
supply voltage (+5.0 V)
SYNSEL2
SYNSEL1
VCC
I
I
S
A
REFC1
pin for connecting external reference decoupling capacitor (for standard
TTL reference)
ENL
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
I
loop mode enable (active LOW)
VDD
S
S
O
O
S
O
O
S
I
supply voltage (+3.3 V)
GND
ground
DLOOP
DLOOPQ
GND
data output to demultiplexer IC OQ2536 (loop mode)
inverted data output to demultiplexer IC OQ2536 (loop mode)
ground
CLOOP
CLOOPQ
GND
clock output to demultiplexer IC OQ2536 (loop mode)
inverted clock output to demultiplexer IC OQ2536 (loop mode)
ground
CIN
clock input from VCO IC
CINQ
GND
I
inverted clock input from VCO IC
S
A
A
S
S
A
S
ground
DIOA
DIOC
GND
anode of temperature diode array
cathode of temperature diode array
ground
GND
ground
BGCAP2
GND
pin for connecting external band gap decoupling capacitor (4 : 1 MUX)
ground
1999 Oct 04
4
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
SYMBOL
GND
PIN
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TYPE(1)
DESCRIPTION
S
S
O
O
S
S
S
S
S
S
O
O
S
S
S
S
S
S
S
−
ground
GND
COUT
COUTQ
GND
VDD
ground
clock output to laser driver IC
inverted clock output to laser driver IC
ground
supply voltage (+3.3 V)
VDD
supply voltage (+3.3 V)
VEE
supply voltage (−4.5 V)
VEE
supply voltage (−4.5 V)
GND
DOUT
DOUTQ
GND
GND
GND
GND
GND
GND
GND
i.c.
ground
data output to laser driver IC
inverted data output to laser driver IC
ground
ground
ground
ground
ground
ground
ground
internally connected, to be left open-circuit
ground
GND
S
Note
1. Pin type abbreviations: O = Output, I = Input, S = power Supply, A = Analog function.
1999 Oct 04
5
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
GND
TRST
TCK
1
2
75 DIOC
DIOA
GND
74
73
3
GND
4
72 CINQ
71 CIN
TMS
5
TDO
6
GND
70
69
TDI
7
CLOOPQ
GND
8
68 CLOOP
67 GND
GND
9
BGCAP1
GND
10
11
12
13
14
15
16
DLOOPQ
DLOOP
66
65
V
64 GND
EE
OQ2535HP
CDIV
63
62
61
60
V
DD
V
ENL
DD
GND
REFC1
V
V
CC(T)
CC
GND 17
59 SYNSEL1
D31
D27
D23
18
19
20
SYNSEL2
D0
58
57
56 GND
55 D4
GND 21
D19 22
D15 23
D11 24
GND 25
D8
54
53
D12
52 D16
51 D20
MGK350
Fig.2 Pin configuration.
6
1999 Oct 04
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
FUNCTIONAL DESCRIPTION
The outputs CLOOP, CLOOPQ, DLOOP and DLOOPQ
are terminated internally with 100 Ω resistors to GND and
are specifically designed to drive 50 Ω printed-circuit
board transmission lines.
The OQ2535HP is a 32-channel multiplexer intended for
use in STM16/OC48 applications. It multiplexes
32 × 78 Mbits/s input channels onto a single 2.5 Gbits/s
output channel.
The 2.5 GHz clock connected to CIN and CINQ is
terminated internally with 50 Ω to GND.
The multiplexing is performed in two stages. The 32 input
channels are fed into four 8 : 1 multiplexers to generate
four 622 Mbits/s channels. These four channels are then
combined into a single 2.5 Gbits/s data stream.
Power supply connections
The power supply pins need to be individually decoupled
using chip capacitors mounted as close as possible to the
IC. If multiple decoupling capacitors are used for a single
supply node, they must be placed close to each other to
avoid RF resonance.
The ENL control input is used for switching between
normal and loop modes. When loop mode is enabled,
(ENL = LOW), the output signal is switched to DLOOP and
DLOOPQ (these outputs could be connected to the
DLOOP and DLOOPQ inputs on the OQ2536HP
demultiplexer to form part of a test loop).
To minimize low frequency switching noise in the vicinity of
the OQ2535HP, all power supply lines should be filtered
once by an LC-circuit with a low cut-off frequency (as
shown in the application diagram, Fig.6). VCC(T) needs to
be filtered separately via an LC-circuit because of the high
switching currents present at the CDIV TTL output. As this
current contains only 78 MHz harmonics, filtering can be
achieved with relatively small values of L and C.
The 2.5 GHz clock at CIN and CINQ is used as the system
reference. It is divided down to 78 MHz and made
available on the CDIV TTL output for timing the input data
(D0 to D31).
Low bit rate stage: 4 × 8 : 1 MUX
This part of the circuit consists of four 8-bit shift registers,
each acting as an 8 : 1 multiplexer, together with a
synchronization block.
Ground connection
The ground connection on the printed-circuit board needs
to be a large copper area fill connected to a common
ground plane with low inductance.
The 32 data input signals are loaded into the shift registers
before being shifted out on a 622 MHz clock.
RF connections
The load pulse for the shift registers is generated in the
synchronization block. The inputs SYNSEL1 and
SYNSEL2 can be used to adjust the phase of the load
pulse with respect to the input data (see Table 3) to
synchronize the data and clock signals.
A coupled stripline or microstrip with an odd mode
characteristic impedance of 50 Ω (nominal value) should
be used for the RF connections on the printed-circuit
board. The connections should be kept as short as
possible. This applies to the CML differential line pairs CIN
and CINQ, DOUT and DOUTQ, COUT and COUTQ,
DLOOP and DLOOPQ, and CLOOP and CLOOPQ. In
addition, the following lines should not vary in length by
more than 5 mm:
High bit rate stage: 4 : 1 MUX
The four 622 Mbits/s data outputs from the low bit rate
stage are combined into a single 2.5 Gbits/s data stream
in two stages: two 2 : 1 multiplexers are used to generate
two 1244 Mbits/s data streams; these signals are then fed
into a third 2 : 1 multiplexer to generate the 2.5 Gbits/s
data stream.
• CIN and CINQ
• DOUT, DOUTQ, COUT and COUTQ
• DLOOP, DLOOPQ, CLOOP and CLOOPQ.
The 2.5 Gbits/s serial data stream is passed either to the
DOUT and DOUTQ outputs (normal mode), or to the
DLOOP and DLOOPQ outputs (loop mode). The output
sequence is D31 (MSB) to D0 (LSB). Data and clock
output buffers are terminated internally with 100 Ω
resistors to GND and are capable of driving 50 Ω loads.
The unused output buffers are switched off to help
minimize power dissipation.
Interface to transmit logic
The 78 Mbits/s interface lines, CDIV and D0 to D31,
should not vary in length by more than 20 mm.
The parasitic capacitance of these lines should be as
small as possible.
1999 Oct 04
7
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
ESD protection
1
1
Rth h-a
≤
–
–1 – Rth j-c – Rth c-h
(4)
-------- -------------
Rth R th j-a
All pads are protected by ESD protection diodes with the
exception of the high frequency outputs DOUT, DOUTQ,
DLOOP, DLOOPQ, COUT, COUTQ, CLOOP and
CLOOPQ and clock inputs CIN and CINQ.
where:
Rth h-a = thermal resistance from heatsink to ambient
Rth c-h = thermal resistance from case to heatsink
Cooling
Rth j-c = thermal resistance from junction to case,
see Chapter “Thermal characteristics”.
In many cases it is necessary to mount a special cooling
device on the package. The thermal resistance from
junction to case, Rth j-c and from junction to ambient, Rth j-a
are given in Chapter “Thermal characteristics”. Since the
heat-slug in the package is connected to the die, the
cooling device should be electrically isolated.
If for instance Rth c-h = 0.5 K/W and Rth j-a = 33 K/W then:
,
–1
1
1
Rth h-a
≤
–
– 3.1
(5)
----------- ------
12.5 33
≤ 17.0 K/W
To calculate if a heatsink is necessary, the maximum
allowed total thermal resistance Rth is calculated as:
Built in temperature sensor
Tj – Tamb
Three series-connected diodes have been integrated for
measuring junction temperature. The diode array,
accessed by means of the DIOA (anode) and DIOC
(cathode) pins, has a temperature dependency of
approximately −6 mV/°C. With a diode current of 1 mA, the
voltage will be somewhere in the range of 1.7 to 2.5 V,
depending on temperature.
Rth
=
(1)
-----------------------
Ptot
where:
Rth = total thermal resistance from junction to ambient in
the application
Tj = junction temperature
Tamb = ambient temperature.
Boundary Scan Test (BST) interface
As long as Rth is greater than Rth j-a of the OQ2536HP
including environmental conditions such as air flow and
board layout, no heatsink is necessary.
For example if Tj = 120 °C, Tamb = 55 °C and
Ptot = 1.65 W, then:
Boundary scan test logic has been implemented for all
digital inputs and outputs on the low frequency interface, in
accordance with “IEEE Std 1149.1-1990”. All scan tests
other than SAMPLE mode are available. The boundary
scan test logic consists of a TAP controller, a BYPASS
register, a 2-bit instruction register, a 32-bit identification
register and a 36-bit boundary scan register (the last two
are combined). The architecture of the TAP controller and
the BYPASS register is in accordance with IEEE
recommendations. The four command modes, selected by
means of the instruction register, are: EXTEST (00),
PRELOAD (01), IDCODE (10) and BYPASS (11). All
boundary scan test inputs, TDI, TMS, TCK and TRST,
have internal pull-up resistors. The maximum test clock
frequency at TCK is 12 MHz.
(120 – 55)
R th
=
= 39.4 K/W
(2)
--------------------------
1.65
which is more than the worst case Rth j-a = 33 K/W, so no
heatsink is necessary.
Another example; if for safety reasons Tj should stay as
low as 110 °C, while Tamb = 85 °C and Ptot = 2 W, then:
(110 – 85)
Rth
=
= 12.5 K/W
(3)
--------------------------
2.0
In this case extra cooling is needed. The thermal
resistance of the heatsink is calculated as follows:
Table 1 BST identifier code
VERSION
OQ
2535 (BINARY)
PHILIPS SEMICONDUCTORS
LSB(1)
0001
01
00 1001 1110 0111
0000 0010 101
1
Note
1. LSB is shifted out first on the TDO pin.
1999 Oct 04
8
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
Table 2 BST bit order
BIT NUMBER
SYMBOL
CDIV
PIN
35 (MSB)
13
62
58
59
18
28
41
49
19
29
42
50
20
30
43
51
22
31
44
52
23
32
45
53
24
33
46
54
26
34
47
55
27
35
48
57
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
ENL
SYNSEL2
SYNSEL1
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
8
D8
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0 (LSB)(1)
D0
Note
1. LSB is shifted out first on the TDO pin.
1999 Oct 04
9
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
−0.5
MAX.
+6.0
UNIT
VCC, VCC(T) supply voltage
V
V
V
VEE
VDD
Vn
supply voltage
supply voltage
DC voltage
−6.0
−0.5
+0.5
+5.0
pins 18 to 20, 22 to 24, 26 to 35, 41 to 55 and 57
pins 2, 3, 5, 7, 38, 61 and 62
pins 65, 66, 68, 69, 71, 72, 82, 83, 90 and 91
pins 10 and 78
−0.5
−0.5
−1.0
V
DD + 0.5
V
V
V
V
V
VCC + 0.5
+0.5
VEE − 0.5 0.5
pins 74 and 75
VEE − 0.5 VCC + 0.5
In
DC current
pins 6 and 13
−
−
−
−
50
mA
mA
W
pins 74 and 75
10
Ptot
Tj
total power dissipation
junction temperature
2.35
120
°C
Tstg
storage temperature
−65
+150
°C
THERMAL CHARACTERISTICS
SYMBOL
Rth j-c
PARAMETER
CONDITIONS
VALUE
UNIT
thermal resistance from junction to
case
2.6
K/W
Rth j-a
thermal resistance from junction to
ambient
see note 1
airflow = 0 ft/min
33
28
25
22
20
K/W
K/W
K/W
K/W
K/W
airflow = 100 ft/min
airflow = 200 ft/min
airflow = 400 ft/min
airflow = 600 ft/min
Note
1. The thermal resistance from junction to ambient is strongly depending on the board design and airflow. The values
given in the table are typical values and are measured on a single sided test board with dimensions of
76 × 114 × 1.6 mm. Better values can be obtained when mounted on multilayer boards with large ground planes.
1999 Oct 04
10
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
DC CHARACTERISTICS
All typical values are at Tamb = 25 °C and at typical supply voltages; minimum and maximum values are valid over the
entire ambient temperature range and supply voltage range.
SYMBOL
General
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CC, VCC(T) supply voltage
note 1
4.75
5.0
5.25
V
V
V
VEE
VDD
ICC
supply voltage
−4.75
−4.5
3.3
2.3
20
−4.25
3.47
4
supply voltage
3.14
−
supply current
mA
mA
mA
mA
W
ICC(T)
IEE
supply current
−
40
supply current
−
265
20
400
28
IDD
supply current
−
Ptot
Tj
total power dissipation
junction temperature
ambient temperature
−
1.65
−
2.35
120
+85
−
°C
Tamb
−40
−
°C
TTL 3.3 V inputs: D0 to D31; note 2
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
−
−
−
−
−
0.8
−
V
2.0
−65
0
V
0
µA
µA
IIH
110
TTL inputs: ENL, SYNSEL1, SYNSEL2, TDI, TCK, TMS and TRST
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
−
−
−
−
−
0.8
−
V
2.0
−100
0
V
note 3
note 3
0
µA
µA
IIH
210
CML clock inputs: CIN and CINQ; note 4
Vi(p-p)
VIO
input voltage (peak-to-peak value)
permitted input offset voltage
input voltages
50 Ω
measurement
system
100
−25
−600
−
250
−
500
+25
+250
−
mV
mV
mV
Ω
VI, VIQ
Zi
−
single ended input impedance
for DC signal
50
TTL outputs: CDIV and TDO; note 5
VOL
VOH
IOZ
LOW-level output voltage
IOL = 4 mA
−
0.3
4.0
−
0.5
−
V
HIGH-level output voltage
IOH = −400 µA 2.4
V
output current in high-impedance state
−
1
µA
CML outputs in normal mode: COUT, COUTQ, DOUT and DOUTQ; note 4
Vo(p-p)
VOO
output voltage (peak-to-peak value)
output offset voltage
outputs
230
300
0
500
+25
0
mV
mV
mV
terminated
externally with
50 Ω resistors
−25
VO, VOQ
output voltages
−600
−
Zo
output impedance
for DC signal
−
100
−
Ω
1999 Oct 04
11
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CML outputs in loop mode: CLOOP, CLOOPQ, DLOOP and DLOOPQ; note 4
Vo(p-p)
VOO
output voltage (peak-to-peak value)
output offset voltage
outputs
230
300
500
mV
terminated
externally with
50 Ω
−25
0
+25
0
mV
mV
VO, VOQ
output voltages
−600
−
Zo
output impedance
for DC signal
−
100
−
Ω
Temperature diode array
∆VDIOA-DIOC diode voltage range; note 6
II(d) = 1 mA
−
2.1
−
V
Notes
1. VCC and VCC(T) require the same power supply voltage. However, a filter is needed to isolate VCC(T) because of the
high peak currents that occur at 78 MHz.
2. The output sequence is D31 (MSB) to D0 (LSB).
3. Only for inputs ENL, SYNSEL1 and SYNSEL2. TDI, TMS, TCK and TRST are connected to VCC through 90 kΩ
resistors.
4. See Fig.3 for symbol definitions.
5. TDO is switched to high impedance state if BST is inactive.
6. The temperature diode array can be used to measure the temperature of the die. The temperature dependency of
this voltage is approximately −6 mV/K.
CML INPUT
CML OUTPUT
V
I(max)
GND
GND
V
O(max)
V
V
IQH
OQH
V
V
OH
IH
V
V
i(p-p)
o(p-p)
V
V
V
IQL
V
OQL
OO
IO
V
V
OL
IL
V
V
O(min)
I(min)
MGK144
Fig.3 Logic level symbol definitions for CML.
1999 Oct 04
12
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
TIMING
Typical values at Tamb = 25 °C and at typical supply voltages; minimum and maximum values are valid over the entire
ambient temperature range and supply voltage range.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
TTL input timing
fclk(CDIV)
low speed output clock frequency
fclk(CIN) = 2.488 GHz
capacitive load of 15 pF
note 1
−
−
77.76
−
MHz
tr(CDIV), tf(CDIV) CDIV rise/fall time
−
−
−
2600
ps
ps
ps
tsu
th
input data set-up time
input data hold time
1200
2600
−
−
note 1
CML output timing; note 2
fclk(COUT) output clock frequency
tCDV
fclk(CIN) = 2.488 GHz
−
2.488
−
GHz
ps
clock edge to data valid time
data invalid time
−
−
250
120
150
55
tDI
−
−
ps
tr(CML), tf(CML) CML output rise/fall time
−
−
ps
δCOUT
output clock duty factor
45
50
%
Notes
1. The set-up and hold times given are valid for SYNSEL1 = SYNSEL2 = HIGH. Different SYNSEL1, SYNSEL2
combinations will produce different set-up and hold times (see Table 3).
2. All CML outputs must be terminated externally with 50 Ω to GND. The specified timing characteristics are applicable
in both normal and loop modes.
Table 3 Timing relationship between the clock edge and the data valid region (minimum values)
SYNSEL2
SYNSEL1
tsu
th
UNIT
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
1200
2800
1700
3300
2600
1000
2100
500
ps
ps
ps
ps
1999 Oct 04
13
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
T
cy(CDIV)
t
t
f
r
2.0 V
1.5 V
0.8 V
CDIV
1.5 V
D0 to D31
t
h
valid data
MGK352
t
su
Fig.4 TTL input timing.
T
t
t
r
cy(COUT)
f
+100 mV
0 V
COUT − COUTQ,
CLOOP − CLOOPQ
−100 mV
+100 mV
DOUT − DOUTQ,
DLOOP − DLOOPQ
−100 mV
MGK353
t
CDV
t
DI
Fig.5 CML output timing.
14
1999 Oct 04
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
APPLICATION INFORMATION
system reference
DATA
INTERFACE
PHASE
DETECTOR
D0 to D31
D0 to D31
CDIV
13
V
EE
10 nF
BGCAP1
10
V
EE
10 nF
BGCAP2
REFC1
78
61
PLL
LOOP
FILTER
ENL
68 nF
68 nF
62
micro-
controller
REFC2
38
SYNSEL1
SYNSEL2
GND
or
TDI
7
59
58
V
TCK
3
CC
CIN
TMS
71
72
BOUNDARY SCAN
TEST EQUIPMENT
5
2
6
VCO
2.488 GHz
CINQ
TRST
TDO
ferrite
bead
OQ2535
V
CC
60
16
100
nF
1 µF
1 µF
ferrite
bead
V
CC(T)
100
nF
DLOOP
DLOOPQ
CLOOP
ferrite
bead
65
66
68
69
DLOOP
V
DD
(1)
(2)
(3)
DLOOPQ
100
nF
OQ2536
DMUX
1 µF
1 µF
CLOOP
ferrite
bead
CLOOPQ
CLOOPQ
V
EE
100
nF
GND
90
91
82
83
COUTQ
DOUT DOUTQ
COUT
D
DQ
CLQ
CL
(1) VDD pins 14, 37, 63, 85 and 86 should be
OQ2545
LASER DRIVER
connected together, and to the filter network.
(2) VEE pins 12, 39, 87 and 88 should be connected
together, and to the filter network.
LA
LAQ
(3) All GND pins (pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36,
40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89,
92 to 98 and 100) must be connected directly to
the printed-circuit board ground plane.
LASER DIODE
MGK354
Fig.6 Application diagram.
15
1999 Oct 04
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
PACKAGE OUTLINE
HLQFP100: plastic heat-dissipating low profile quad flat package;
100 leads; body 14 x 14 x 1.4 mm
SOT470-1
y
X
A
51
75
50
76
Z
E
e
H
E
J
E
A
2
A
(A )
3
w M
p
A
1
b
θ
L
p
pin 1 index
L
detail X
100
26
1
25
Z
D
v
M
A
e
w M
b
p
D
B
H
v M
B
D
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
E
(2)
UNIT
A
A
A
b
c
D
E
e
H
D
H
J
L
L
v
w
y
Z
D
Z
θ
1
2
3
p
E
p
max.
7o
0o
0.20 1.5
0.05 1.3
0.28 0.18 14.1 14.1
0.16 0.12 13.9 13.9
16.25 16.25 10.15
15.75 15.75 9.15
0.75
0.45
1.15 1.15
0.85 0.85
mm
1.6
0.25
0.5
1.0
0.2 0.12 0.1
Notes
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
2. Heatsink intrusion 0.0127 maximum.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-01-13
SOT470-1
1999 Oct 04
16
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
SOLDERING
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Oct 04
17
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 multiplexer
OQ2535HP
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Oct 04
18
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68
SCA
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465012/50/02/pp20
Date of release: 1999 Oct 04
Document order number: 9397 750 03901
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