P1021NSE2DFB [NXP]
QorIQ, Power Arch 32-Bit SoC, 2 X 533MHz, GbE, DDR2/3, ECC, QE, PCIe, USB, TDM, SEC, 0 to 125C, R1.1;
| 型号： | P1021NSE2DFB |
| 厂家： | 
NXP |
| 描述： | QorIQ, Power Arch 32-Bit SoC, 2 X 533MHz, GbE, DDR2/3, ECC, QE, PCIe, USB, TDM, SEC, 0 to 125C, R1.1 时钟 PC 双倍数据速率 外围集成电路 |
| 文件： | 总2页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QorIQ Communications Platforms
P Series
QorIQ P1012 and P1021
communications processors
performance general-purpose control processor
earlier PowerQUICC processors. This enables
customers to create a product with multiple
performance points from a single board design.
The QorIQ P1021 dual-core processor supports
both symmetric and asymmetric processing,
enabling customers to further optimize their
design with the same applications running on
each core or serialize your application using the
cores for different processing tasks.
Overview
applications with tight thermal constraints.
Freescale QorIQ communications platforms are
the next-generation evolution of our leading
PowerQUICC communications processors. Built
using high-performance Power Architecture®
cores, QorIQ platforms enable a new era of
networking innovation where the reliability,
security and quality of service for every
connection matters.
The P1012 and P1021 processors are pin-
compatible with the QorIQ P1011, P1020 and
P2 platform products, offering a six-chip range
of cost-effective solutions. Scaling from a single
core at 533 MHz (P1012) to a dual core at 1.2
GHz per core (P2020), the combined QorIQ
platforms deliver an impressive 4.5x aggregate
frequency range.
The P1012 and P1021 processors have an
advanced set of features for ease of use. The
256 KB L2 cache offers incremental configuration
to partition the cache between the two cores or
to configure it as SRAM or stashing memory.
QorIQ P1012 and P1021
Communications Processors
The P1012 and P1021 platforms are fully
software compatible, both featuring the e500
Power Architecture core and peripherals, as
well as being fully software compatible with the
The QorIQ P1 family, which includes the P1012
and P1021 communications processors, offers
the value of smart integration and efficient power
intelligence for a wide variety of applications in
the networking, telecom, defense and industrial
markets. Based on 45 nm technology for low
power, the P1012 and P1021 processors provide
single- and dual-core options, from 533 MHz–
800 MHz, along with advanced security and a
rich set of interfaces.
QorIQ P1012 and P1021 Block Diagram
Not on P1012
Security
Acceleration
DDR2/DDR3
SDRAM Controller
Power Architecture®
e500 Core
Power Architecture
e500 Core
256 KB
L2 Cache
XOR
32 KB
32 KB
32 KB
32 KB
DUART, 2x I2C, Timers,
Interrupt Control,
SD/MMC, SPI,
L1 I Cache L1 D Cache
L1 I Cache L1 D Cache
2x USB 2.0/ULPI
The P1012 and P1021 processors are ideally
suited for multiservice gateways, Ethernet switch
controllers, wireless LAN access points and high-
Coherency Module
System Bus
Enhanced Local Bus
Controller (eLBC)
3x
Gigabit
Ethernet
On-Chip Network
2x PCI 4-ch. DMA
QUICC Engine
Express®
Controller
4-lane SerDes
Basic Peripherals and Interconnect
UTOPIA-L2 TDM Ethernet
Core Complex (CPU, L2 and Frontside CoreNet Platform Cache)
Accelerators and Memory Control Networking Elements
The integrated security engine supports the
cryptographic algorithms commonly used
in IPsec, SSL, 3GPP and other networking
and wireless security protocols. The memory
controller offers future proofing against memory
technology migration with support for both DDR2
and DDR3. It also supports error correction
codes, a baseline requirement for any high-
reliability system.
and outdoor environments less protected from
the environment. The devices primarily target
applications such as networking and
telecom linecards.
• High-speed interfaces (not all available
simultaneously)
Four SerDes to 3.125 GHz multiplexed
across controllers
Two PCI Express controllers
Two SGMII interfaces
A multiservice router or business gateway
requires a combination of high performance
and a rich set of peripherals to support the
datapath throughputs and required system
functionality. The P1012 and P1021 devices
offer a scalable platform to develop a range of
products that can support the same feature
set. The QUICC Engine module, as well as
integrated 10/100/1000 Ethernet controllers
with classification and QoS capabilities, are
ideal for managing the datapath traffic between
the LAN and WAN interface. PCI Express ports
can provide connectivity to IEEE 802.11n radio
cards for wireless support, TDM for legacy
phone interfaces to support voice and the USB
or SD/MMC interfaces can be used to support
local storage. The integrated security engine
can provide encrypted secure communications
for remote users with VPN support.
• QUICC Engine module
UTOPIA-L2
Up to two 10/100 Ethernet interfaces
Up to four T1/E1/J1/E3 or DS-3 serial
interfaces
The P1012 and P1021 processors integrate a
rich set of interfaces, including a multiprotocol
SerDes, Gigabit Ethernet, QUICC Engine module,
PCI Express® and USB. The three 10/100/1000
Ethernet ports support advanced packet parsing,
flow control and quality of service features, as
well as IEEE® 1588 time stamping—all ideal
for managing the datapath traffic between the
LAN and WAN interface. The QUICC Engine
module provides UTOPIA-L2, TDM and 10/100
Ethernet interfaces as well as a programmable
RISC engine to offload protocol termination from
the main CPU cores. Four SerDes lanes can be
portioned across two PCI Express ports and
two SGMII ports. The PCI Express ports can
provide connectivity to IEEE 802.11n radio cards
for wireless support. USB or SD/MMC interfaces
can be used to support local storage. Multiple
memory connection ports are available, including
the 16-bit local bus, a USB 2.0 controller,
Up to four HDLC interfaces with 128
channels of HDLC
Up to four BISYNC interfaces
Up to four UART interfaces
SPI interfaces
GPIO
• Two High-Speed USB controllers (USB 2.0)
Host and device support
Enhanced host controller interface (EHCI)
ULPI interface to PHY
• Enhanced secure digital host controller
• Serial peripheral interface
• Integrated security engine (SEC 3.3)
Crypto algorithm support includes
3DES, AES, RSA/ECC, MD5/
SHA, ARC4, Snow 3G and FIPS
deterministic RNG
Technical Specifications
• Single (P1012) and dual (P1021) high-
performance Power Architecture e500 cores
36-bit physical addressing
Single pass encryption/message
authentication for common security
protocols (e.g., IPsec, SSL, SRTP,
WiMAX)
Double-precision floating-point support
32 KB L1 instruction cache and 32 KB
L1 data cache for each core
533 MHz–800 MHz core clock
frequency
enhanced secure digital host controller (eSDHC)
and serial peripheral interface (SPI).
XOR acceleration
• 32-bit DDR2/DDR3 SDRAM memory
controller with ECC support
• Programmable interrupt controller (PIC)
compliant with OpenPIC standard
• Four-channel DMA controller
• Two I2C controllers, DUART, timers
• Enhanced local bus controller (eLBC)
• 16 general-purpose I/O signals
• Package: 689-pin wirebond power-BGA
(TEPBGA2)
Target Applications
• 256 KB L2 cache with ECC, also configurable
as SRAM and stashing memory
• Three 10/100/1000 Mb/s enhanced three-
speed Ethernet controllers (eTSECs)
TCP/IP acceleration and classification
capabilities
The P1012 and P1021 processors serve
a wide variety of applications and are well
suited for various combinations of data plane
and control plane workloads in networking
and telecom applications. With an available
junction temperature range of –40 ºC to
+125 ºC, the devices can be used in power-
sensitive defense and industrial applications,
IEEE 1588 support
Lossless flow control
RGMII, SGMII
QorIQ P1021 Features
QorIQ
Device Cores
Top Core
L2 Size DDR 2/3 Support GE Ports
QUICC
Engine
SerDes
PCI Express Serial RapidIO
TDM
Platform
Frequency
P1
P1
P1
P1
P2
P2
P1011
P1020
P1012
P1021
P2010
P2020
1
2
1
2
1
2
800 MHz
800 MHz
800 MHz
800 MHz
1200 MHz
1200 MHz
256 KB 32-bit with ECC
256 KB 32-bit with ECC
256 KB 32-bit with ECC
256 KB 32-bit with ECC
512 KB 64-bit with ECC
512 KB 64-bit with ECC
3
3
3
3
3
3
N/A
N/A
Yes
Yes
N/A
N/A
4
4
4
4
4
4
2
2
2
2
3
3
N/A
N/A
N/A
N/A
2
Yes
Yes
In QUICC Engine
In QUICC Engine
N/A
2
N/A
For more information, please visit freescale.com/QorIQ
Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
QUICC Engine and CoreNet are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of
their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks
are trademarks and service marks licensed by Power.org. © 2009, 2011, 2013 Freescale Semiconductor, Inc.
Document Number: QORIQP1021FS REV 2
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