P89LPC9408FBD [NXP]

8-bit microcontroller with two-clock 80C51 core 8 kB 3 V byte-erasable flash, 32 segment x 4 LCD driver, 10-bit ADC; 8位微控制器两个小时80C51核心8 KB的3伏字节可擦除闪存， 32段×4的LCD驱动器， 10位ADC


型号：	P89LPC9408FBD
厂家：	NXP
描述：	8-bit microcontroller with two-clock 80C51 core 8 kB 3 V byte-erasable flash, 32 segment x 4 LCD driver, 10-bit ADC 8位微控制器两个小时80C51核心8 KB的3伏字节可擦除闪存， 32段×4的LCD驱动器， 10位ADC 驱动器闪存微控制器 CD
文件：	总69页 (文件大小：328K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P89LPC9408

8-bit microcontroller with two-clock 80C51 core 8 kB 3 V

byte-erasable ﬂash, 32 segment × 4 LCD driver, 10-bit ADC

Rev. 01 — 16 December 2005

Product data sheet

1. General description

The P89LPC9408 is a multi-chip module consisting of a P89LPC938 single-chip

microcontroller combined with a PCF8576D universal LCD controller in a low-cost 64-pin

package. The LCD controller provides 32 segments and supports from 1 to 4 backplanes.

Display overhead is minimized by an on-chip display RAM with auto-increment

addressing.

2. Features

2.1 Principal features

■ 8 kB byte-erasable ﬂash code memory organized into 1 kB sectors and 64-byte pages.

Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

■ 256-byte RAM data memory.

■ 512-byte customer Data EEPROM on chip allows serialization of devices, storage of

set-up parameters, etc.

■ 32 segment × 4 backplane LCD controller supports from 1 to 4 backplanes.

■ 8-input multiplexed 10-bit ADC. Two analog comparators with selectable inputs and

reference source.

■ Two 16-bit counter/timers (each may be conﬁgured to toggle a port output upon timer

overﬂow or to become a PWM output) and a 23-bit system timer that can also be used

as a Real-Time Clock (RTC).

■ Enhanced UART with fractional baud rate generator, break detect, framing error

detection, and automatic address detection; 400 kHz byte-wide I²C-bus

communication port and SPI communication port.

■ CCU provides PWM, input capture, and output compare functions.

■ High-accuracy internal RC oscillator option allows operation without external oscillator

components. The RC oscillator option is selectable and ﬁne tunable.

■ 64-pin LQFP package with 20 microcontroller I/O pins minimum and up to 23

microcontroller I/O pins while using on-chip oscillator and reset options.

2.2 Additional features

■ 2.4 V to 3.6 V V_DDoperating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

■ Serial ﬂash In-Circuit Programming (ICP) allows simple production coding with

commercial EPROM programmers. Flash security bits prevent reading of sensitive

application programs.

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns

for all instructions except multiply and divide when executing at 18 MHz. This is six

times the performance of the standard 80C51 running at the same clock frequency. A

lower clock frequency for the same performance results in power savings and reduced

EMI.

■ Serial ﬂash In-System Programming (ISP) allows coding while the device is mounted

in the end application.

■ In-Application Programming (IAP) of the ﬂash code memory. This allows changing the

code in a running application.

■ Watchdog timer with separate on-chip oscillator, requiring no external components.

The watchdog prescaler is selectable from eight values.

■ Low voltage detect (brownout) allows a graceful system shutdown when power fails.

May optionally be conﬁgured as an interrupt.

■ Idle and two different power-down reduced power modes. Improved wake-up from

Power-down mode (a LOW interrupt input starts execution). Typical power-down

current is 9 µA typical (total power-down with voltage comparators disabled).

■ Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A reset counter and reset glitch suppression circuitry prevent spurious

and incomplete resets. A software reset function is also available.

■ Conﬁgurable on-chip oscillator with frequency range options selected by user

programmed ﬂash conﬁguration bits. Oscillator options support frequencies from

20 kHz to the maximum operating frequency of 18 MHz.

■ Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator

allowing it to perform an oscillator fail detect function.

■ Programmable port output conﬁguration options: quasi-bidirectional, open drain,

push-pull, input-only.

■ Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of

the pins match or do not match a programmable pattern.

■ LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the

entire chip.

■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns

minimum ramp times.

■ Only power and ground connections are required to operate the P89LPC9408 when

internal reset option is selected.

■ Four interrupt priority levels.

■ Eight keypad interrupt inputs, plus two additional external interrupt inputs.

■ Schmitt trigger port inputs.

■ Second data pointer.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

2 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

P89LPC9408FBD

LQFP64

plastic low proﬁle quad ﬂat package; 64 leads;

SOT791-1

body 14 × 14 × 1.4 mm

3.1 Ordering options

Table 2:

Part options

Type number

Flash memory

8 kB

Temperature range

Frequency

P89LPC9408FBD

−40 °C to +85 °C

0 MHz to 18 MHz

4. Block diagram

P3[1:0]

P2.5, P2[3:0]

P1[7:0]

S[31:0]

BP[3:0]

PCF8576D

LCD

CONTROLLER

P89LPC938

MCU

LCD

P0[7:0]

A[2:0] SA0 OSC

002aab775

SCL, SDA

SCL_LCD, SDA_LCD

Fig 1. Block diagram

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

3 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

P89LPC938

ACCELERATED 2-CLOCK 80C51 CPU

TXD

RXD

8 kB

CODE FLASH

UART

internal

bus

SCL

SDA

256-BYTE

DATA RAM

I C-BUS

SPI

SPICLK

MOSI

MISO

512-BYTE

AUXILIARY RAM

REAL-TIME CLOCK/

SYSTEM TIMER

512-BYTE

DATA EEPROM

TIMER 0

TIMER 1

PORT 3

CONFIGURABLE I/Os

P3[1:0]

P2[7:0]

CMP2

CIN2A

CIN1A

CIN2B

CMP1

CIN1B

ANALOG

COMPARATORS

PORT 2

CONFIGURABLE I/Os

OCA

OCC

ICA

PORT 1

CONFIGURABLE I/Os

OCB

OCD

ICB

P1[7:0]

P0[7:0]

CCU (CAPTURE/

COMPARE UNIT)

PORT 0

CONFIGURABLE I/Os

AD00

AD02

AD01

AD03

KEYPAD

INTERRUPT

ADC0

AD04

AD06

AD05

AD07

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

clock

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

CRYSTAL

RESONATOR

ON-CHIP

OSCILLATOR

CONFIGURABLE

OSCILLATOR

002aab106

Fig 2. Microcontroller section block diagram

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

4 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

BP0 BP1 BP2 BP3

S0 TO S39

BACKPLANE

OUTPUTS

DISPLAY SEGMENT OUTPUTS

LCD

VOLTAGE

SELECTOR

DISPLAY LATCH

SHIFT REGISTER

LCD BIAS

GENERATOR

LCD

CLK

TIMING

BLINKER

INPUT

BANK

SELECTOR

DISPLAY

RAM

40 × 4 BITS

OUTPUT

BANK

SELECTOR

SYNC

DISPLAY

CONTROLLER

POWER-

RESET

OSCILLATOR

OSC

DATA

POINTER

COMMAND

DECODER

SCL

SDA

SUB-

ADDRESS

COUNTER

INPUT

FILTERS

I C-BUS

CONTROLLER

SA0

A0 A1 A2

002aab470

Fig 3. LCD display controller block diagram

5. Functional diagram

TXD

RXD

INT0

INT1

RST

OCB

OCC

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

AD05

AD00

AD01

AD02

AD03

SCL

SDA

PORT 0

PORT 3

PORT 1

AD04

P89LPC9408

ICB

AD07

AD06

CLKOUT

XTAL2

XTAL1

OCD

MOSI

MISO

PORT 2

SPICLK

OCA

ICA

002aab776

Fig 4. P89LPC9408 functional diagram

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

5 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

6. Pinning information

6.1 Pinning

P0.5/CMPREF/KBI5

S17

S16

S15

S14

S13

S12

S11

S10

P0.4/CIN1A/KBI4/AD03

P0.3/CIN1B/KBI3/AD02

P0.2/CIN2A/KBI2/AD01

P0.1/CIN2B/KBI1/AD00

P2.0/ICB/AD07

P2.1/OCD/AD06

P0.0/CMP2/KBI0/AD05

P1.7/OCC/AD04

P89LPC9408

P1.6/OCB

P1.5/RST

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

002aab777

Fig 5. Pin conﬁguration

6.2 Pin description

Table 3:

Pin description

Symbol

Type Description

I/O

P0.0 to P0.7

Port 0: Port 0 is an 8-bit I/O port with a user-conﬁgurable output type. During reset

Port 0 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 7.13.1 “Port

conﬁgurations” and Table 12 “Static electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt trigger inputs.

Port 0 also provides various special functions as described below:

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

6 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

Table 3:

Symbol

Pin description …continued

Type Description

P0.0/CMP2/

KBI0/AD05

I/O

P0.0 — Port 0 bit 0.

CMP2 — Comparator 2 output.

KBI0 — Keyboard input 0.

AD05 — ADC0 channel 5 analog input.

P0.1 — Port 0 bit 1.

P0.1/CIN2B/

KBI1/AD00

I/O

CIN2B — Comparator 2 positive input B.

KBI1 — Keyboard input 1.

AD00 — ADC0 channel 0 analog input.

P0.2 — Port 0 bit 2.

P0.2/CIN2A/

KBI2/AD01

I/O

CIN2A — Comparator 2 positive input A.

KBI2 — Keyboard input 2.

AD01 — ADC0 channel 1 analog input.

P0.3 — Port 0 bit 3.

P0.3/CIN1B/

KBI3/AD02

I/O

CIN1B — Comparator 1 positive input B.

KBI3 — Keyboard input 3.

AD02 — ADC0 channel 2 analog input.

P0.4 — Port 0 bit 4.

P0.4/CIN1A/

KBI4/AD03

I/O

CIN1A — Comparator 1 positive input A.

KBI4 — Keyboard input 4.

AD03 — ADC0 channel 3 analog input.

P0.5 — Port 0 bit 5.

P0.5/

I/O

CMPREF/

KBI5

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

P0.6/CMP1/

KBI6

I/O

P0.6 — Port 0 bit 6.

CMP1 — Comparator 1 output.

KBI6 — Keyboard input 6.

P0.7/T1/KBI7 23

P1.0 to P1.7

I/O

P0.7 — Port 0 bit 7.

T1 — Timer/counter 1 external count input or overﬂow output.

KBI7 — Keyboard input 7.

I/O, I Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable output type, except for three

[1]

pins as noted below. During reset Port 1 latches are conﬁgured in the input only mode

with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as

inputs and outputs depends upon the port conﬁguration selected. Each of the

conﬁgurable port pins are programmed independently. Refer to Section 7.13.1 “Port

conﬁgurations” and Table 12 “Static electrical characteristics” for details. P1.2 and P1.3

are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt trigger inputs.

Port 1 also provides various special functions as described below:

P1.0/TXD

P1.1/RXD

I/O

P1.0 — Port 1 bit 0.

TXD — Transmitter output for the serial port.

P1.1 — Port 1 bit 1.

I/O

RXD — Receiver input for the serial port.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

7 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

Table 3:

Pin description …continued

Symbol

Type Description

P1.2/T0/SCL

I/O

P1.2 — Port 1 bit 2 (open-drain when used as output).

T0 — Timer/counter 0 external count input or overﬂow output (open-drain when used

as output).

I/O

SCL — I²C-bus serial clock input/output.

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

SDA — I²C-bus serial data input/output.

P1.4 — Port 1 bit 4.

P1.3/INT0/

SDA

I/O

P1.4/INT1

P1.5/RST

INT1 — External interrupt 1 input.

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during power-on or if selected via UCFG1. When

functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O

ports and peripherals to take on their default states, and the processor begins

execution at address 0. Also used during a power-on sequence to force ISP mode.

When using an oscillator frequency above 12 MHz, the reset input function of

P1.5 must be enabled. An external circuit is required to hold the device in reset at

power-up until V_DDhas reached its speciﬁed level. When system power is

removed V_DDwill fall below the minimum speciﬁed operating voltage. When

using an oscillator frequency above 12 MHz, in some applications, an external

brownout detect circuit may be required to hold the device in reset when V_DDfalls

below the minimum speciﬁed operating range.

P1.6/OCB

I/O

P1.6 — Port 1 bit 6.

OCB — Output Compare B.

P1.7 — Port 1 bit 7.

P1.7/OCC/

AD04

I/O

OCC — Output Compare C.

AD04 — ADC0 channel 4 analog input.

P2.0 to P2.3,

P2.5

I/O

Port 2: Port 2 is an 5-bit I/O port with a user-conﬁgurable output type. During reset

Port 2 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of Port 2 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 7.13.1 “Port

conﬁgurations” and Table 12 “Static electrical characteristics” for details.

All pins have Schmitt trigger inputs.

Port 2 also provides various special functions as described below:

P2.0 — Port 2 bit 0.

P2.0/ICB/

AD07

I/O

ICB — Input Capture B.

AD07 — ADC0 channel 7 analog input.

P2.1 — Port 2 bit 1.

P2.1/OCD/

AD06

I/O

OCD — Output Compare D.

AD06 — ADC0 channel 6 analog input.

P2.2 — Port 2 bit 2.

P2.2/MOSI

P2.3/MISO

I/O

MOSI — SPI master out slave in. When conﬁgured as master, this pin is output; when

conﬁgured as slave, this pin is input.

I/O

P2.3 — Port 2 bit 3.

MISO — When conﬁgured as master, this pin is input, when conﬁgured as slave, this

pin is output.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

8 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

Table 3:

Symbol

Pin description …continued

Pin Type Description

P2.5/SPICLK 20

I/O

P2.5 — Port 2 bit 5.

SPICLK — SPI clock. When conﬁgured as master, this pin is output; when conﬁgured

as slave, this pin is input.

P3.0 to P3.1

I/O

Port 3: Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During reset

Port 3 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of Port 3 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 7.13.1 “Port

conﬁgurations” and Table 12 “Static electrical characteristics” for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

P3.0 — Port 3 bit 0.

P3.0/XTAL2/

CLKOUT

I/O

XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is

selected via the ﬂash conﬁguration.

CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It

can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or

external clock input, except when XTAL1/XTAL2 are used to generate clock source for

the RTC/system timer.

P3.1/XTAL1

I/O

P3.1 — Port 3 bit 1.

XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

selected via the ﬂash conﬁguration). It can be a port pin if internal RC oscillator or

watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used

to generate the clock for the RTC/system timer.

SDA_LCD

SCL_LCD

BP0 to BP3

S0 to S31

V_SS

I/O

SDA LCD — I²C-bus data signal for the LCD controller.

SCL LCD — I²C-bus clock signal for the LCD controller.

BP0 to BP3: LCD backplane outputs.

S0 to S31: LCD segment outputs

27 to 30

31 to 62

Ground: 0 V reference.

V_DD

Power supply: This is the power supply voltage for normal operation as well as Idle

and Power-down modes.

V_LCD

LCD power supply: LCD supply voltage.

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

9 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

7. Functional description

Remark: Please refer to the P89LPC9408 User manual for a more detailed functional

description.

7.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in

future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

10 of 69

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Table 4:

Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

E0H

ACC*

Accumulator

0000 0000

AD0CON

ADC0 control

97H

ENBI0

ENADCI0

TMM0

EDGE0

ADCI0

ENADC0 ADCS01

ADCS00 00

AD0INS

ADC0 input select

A3H

C0H

ADI07

BNDI0

ADI06

ADI05

SCC0

ADI04

ADI03

ADI02

ADI01

ADI00

0000 0000

AD0MODA ADC0 mode

BURST0

SCAN0

AD0MODB ADC0 mode

A1H

A2H

CLK2

CLKLP

CLK1

EBRR

CLK0

ENT1

000x 0000

0000 00x0

AUXR1

Auxiliary function

ENT0

SRST

DPS

Bit address

B register

F0H

0000 0000

BRGR0^[1]Baud rate generator BEH

rate low

BRGR1^[1]Baud rate generator BFH

rate high

0000 0000

xxxx xx00

0000 0000

xxxx x000

xx00 0000

0000 1110

BRGCON Baud rate generator BDH

control

ICECA0

ICECB0

SBRGS

OCMA1

OCMB1

OCMC1

OCMD1

CO1

BRGEN 00^[1]

OCMA0 00

OCMB0 00

OCMC0 00

OCMD0 00

CCCRA

CCCRB

CCCRC

CCCRD

CMP1

Capture compare A EAH

control register

ICECA2

ICECA1

ICESA

ICESB

ICNFA

FCOA

FCOB

FCOC

FCOD

OE1

OE2

Capture compare B EBH

control register

ICECB2

ICECB1

ICNFB

Capture compare C ECH

control register

Capture compare D EDH

control register

Comparator 1

control register

ACH

ADH

F1H

CE1

CE2

ECTL1

CP1

CP2

ECTL0

CN1

CN2

CMF1

CMF2

00^[2]

CMP2

Comparator 2

control register

CO2

DEECON Data EEPROM

control register

EEIF

HVERR

EADR8 0E

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Special function registers …continued

Table 4:

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

DEEDAT

DEEADR

DIVM

Data EEPROM data F2H

0000 0000

Data EEPROM

address register

F3H

CPU clock

95H

divide-by-M control

DPTR

Data pointer

(2 bytes)

DPH

DPL

Data pointer high

Data pointer low

83H

82H

E7H

0000 0000

FMADRH Program ﬂash

address high

FMADRL

Program ﬂash

address low

E6H

E4H

0000 0000

0111 0000

FMCON

Program ﬂash

control (Read)

BUSY

HVA

HVE

Program ﬂash

control (Write)

E4H FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0

FMDATA

I2ADR

Program ﬂash data

I²C slave address

E5H

0000 0000

DBH I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

Bit address

I2CON*

I2DAT

I²C control register

I²C data register

D8H

DAH

DDH

I2EN

STA

STO

CRSEL 00

x000 00x0

0000 0000

I2SCLH

Serial clock

generator/SCL duty

cycle register high

I2SCLL

Serial clock

DCH

0000 0000

generator/SCL duty

cycle register low

I2STAT

ICRAH

I²C status register

D9H

ABH

STA.4

STA.3

STA.2

STA.1

STA.0

1111 1000

0000 0000

Input capture A

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Special function registers …continued

Table 4:

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

ICRAL

ICRBH

ICRBL

Input capture A

AAH

AFH

AEH

0000 0000

Input capture B

Bit address

Interrupt enable 0 A8H

Bit address

EIEE

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

IEN0*

0000 0000

IEN1*

IEN2

Interrupt enable 1

Interrupt enable 2

E8H

D5H

EST

ECCU

ESPI

EKBI

EADC

EI2C

00^[2]

00x0 0000

Bit address

PBO

PBOH

IP0*

Interrupt priority 0

B8H

B7H

PWDRT

PWDRTH

PS/PSR

PT1

PT1H

PX1

PX1H

PT0

PT0H

PX0

PX0H

00^[2]

x000 0000

IP0H

Interrupt priority 0

high

PSH/

PSRH

Bit address

IP1*

Interrupt priority 1

F8H

F7H

PADEE

PADEEH

PST

PCCU

PCCUH

PSPI

PSPIH

PKBI

PKBIH

PI2C

PI2CH

00^[2]

00x0 0000

IP1H

Interrupt priority 1

high

PSTH

PCH

IP2

Interrupt priority 2

D6H

D7H

PADC

00 ^[2]

00^[2]

00x0 0000

IP2H

Interrupt priority 2

high

PADCH

KBCON

KBMASK

KBPATN

OCRAH

OCRAL

Keypad control

94H

86H

PATN

_SEL

KBIF

00^[2]

xxxx xx00

0000 0000

1111 1111

0000 0000

Keypad interrupt

mask register

Keypad pattern

Output compare A

EFH

EEH

Output compare A

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Special function registers …continued

Table 4:

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

OCRBH

OCRBL

OCRCH

OCRCL

OCRDH

OCRDL

Output compare B

FBH

FAH

FDH

FCH

FFH

FEH

0000 0000

Output compare B

Output compare C

Output compare D

Bit address

[2]

P0*

Port 0

80H

T1/KB7

CMP1

/KB6

CMPREF/

KB5

CIN1A

/KB4

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

CMP2

/KB0

Bit address

90H

OCC

OCB

RST

INT1

INT0/SDA

T0/SCL

RXD

TXD

[2]

P1*

P2*

Port 1

Port 2

Port 3

Bit address

A0H

ICA

OCA

SPICLK

MISO

MOSI

OCD

ICB

Bit address

[2]

P3*

B0H

XTAL1

XTAL2

P0M1

Port 0 output

mode 1

84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF^[2]

1111 1111

P0M2

P1M1

P1M2

P2M1

P2M2

Port 0 output

mode 2

85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00^[2]

0000 0000

11x1 xx11

00x0 xx00

1111 1111

0000 0000

Port 1 output

mode 1

91H (P1M1.7) (P1M1.6)

92H (P1M2.7) (P1M2.6)

(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3^[2]

(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00^[2]

Port 1 output

mode 2

Port 2 output

mode 1

A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF^[2]

A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00^[2]

Port 2 output

mode 2

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Special function registers …continued

Table 4:

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

Hex Binary

addr.

MSB

LSB

P3M1

Port 3 output

mode 1

B1H

B2H

87H

B5H

(P3M1.1) (P3M1.0) 03^[2]

xxxx xx11

xxxx xx00

0000 0000

P3M2

Port 3 output

mode 2

(P3M2.1) (P3M2.0) 00^[2]

PCON

PCONA

Power control

SMOD1

RTCPD

SMOD0

DEEPD

BOPD

VCPD

BOI

ADPD

GF1

I2PD

GF0

SPPD

PMOD1

SPD

PMOD0 00

CCUPD 00^[2]

Power control

Bit address

PSW*

Program status

word

D0H

RS1

RS0

0000 0000

PT0AD

RSTSRC

Port 0 digital input

disable

F6H

DFH

PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1

xx00 000x

[3]

Reset source

BOF

POF

R_BK

R_WD

R_SF

ERTC

R_EX

RTCCON RTC control

D1H

D2H

D3H

A9H

RTCF

RTCS1

RTCS0

RTCEN 60 ^{[2] [4]}011x xx00

RTCH

RTCL

RTC register high

00^[4]

0000 0000

RTC register low

SADDR

Serial port address

SADEN

SBUF

Serial port address

enable

B9H

99H

0000 0000

xxxx xxxx

Serial Port data

buffer register

Bit address

TB8

RB8

SCON*

SSTAT

Serial port control

98H

SM0/FE

DBMOD

SM1

SM2

CIDIS

REN

0000 0000

Serial port extended BAH

status register

INTLO

DBISEL

STINT

Stack pointer

81H

E2H

E1H

E3H

0000 0111

0000 0100

00xx xxxx

0000 0000

SPCTL

SPSTAT

SPDAT

SPI control register

SPI status register

SPI data register

SSIG

SPIF

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

WCOL

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Special function registers …continued

Table 4:

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

TAMOD

Timer 0 and 1

auxiliary mode

8FH

T1M2

T0M2

xxx0 xxx0

Bit address

TCON*

TCR20*

TCR21

Timer 0 and 1

control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

0000 0000

0xxx 0000

CCU control

C8H

F9H

PLEEN

TCOU2

HLTRN

HLTEN

ALTCD

ALTAB

TDIR2

TMOD21 TMOD20 00

CCU control

PLLDV.3

PLLDV.2

PLLDV.1

PLLDV.0 00

TH0

Timer 0 high

Timer 1 high

CCU timer high

8CH

8DH

CDH

C9H

0000 0000

0000 0x00

TH1

TH2

TICR2

CCU interrupt

control register

TOIE2

TOIF2

TOCIE2D TOCIE2C TOCIE2B TOCIE2A

TICIE2B

TICF2B

TICIE2A 00

TIFR2

TISE2

CCU interrupt ﬂag

E9H

DEH

TOCF2D TOCF2C

TOCF2B

TOCF2A

TICF2A 00

0000 0x00

xxxx x000

CCU interrupt

status encode

ENCINT.2 ENCINT.1 ENCINT.0 00

TL0

Timer 0 low

Timer 1 low

CCU timer low

8AH

8BH

CCH

0000 0000

TL1

TL2

TMOD

TOR2H

Timer 0 and 1 mode 89H

T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

CCU reload register CFH

high

TOR2L

TPCR2H

TPCR2L

TRIM

CCU reload register CEH

low

0000 0000

xxxx xx00

Prescaler control

CBH

CAH TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0 00

96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

TPCR2H. TPCR2H. 00

Prescaler control

0000 0000

[4] [5]

Internal oscillator

trim register

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Special function registers …continued

Table 4:

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

[4] [6]

WDCON

Watchdog control

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

WDL

Watchdog load

Watchdog feed 1

Watchdog feed 2

C1H

C2H

C3H

1111 1111

WFEED1

WFEED2

[1] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[2] All ports are in input only (high-impedance) state after power-up.

[3] The RSTSRC register reﬂects the cause of the P89LPC9408 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset value is

xx11 0000.

[4] The only reset source that affects these SFRs is power-on reset.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 5:

Name

P89LPC938 extended special function registers

Description

SFR addr. Bit functions and addresses

Reset value

LSB Hex Binary

MSB

ADC0HBND

ADC0 high _boundary register, left

(MSB)

FFEFH

1111 1111

ADC0LBND

AD0DAT0R

AD0DAT0L

AD0DAT1R

AD0DAT1L

AD0DAT2R

AD0DAT2L

AD0DAT3R

AD0DAT3L

AD0DAT4R

AD0DAT4L

AD0DAT5R

AD0DAT5L

AD0DAT6R

AD0DAT6L

AD0DAT7R

AD0DAT7L

BNDSTA0

ADC0 low_boundary register (MSB)

ADC0 data register 0, right (LSB)

ADC0 data register 0, left (MSB)

ADC0 data register 1, right (LSB)

ADC0 data register 1, left (MSB)

ADC0 data register 2, right (LSB)

ADC0 data register 2, left (MSB)

ADC0 data register 3, right (LSB)

ADC0 data register 3, left (MSB)

ADC0 data register 4, right (LSB)

ADC0 data register 4, left (MSB)

ADC0 data register 5, right (LSB)

ADC0 data register 5, left (MSB)

ADC0 data register 6, right (LSB)

ADC0 data register 6, left (MSB)

ADC0 data register 7, right (LSB)

ADC0 data register 7, left (MSB)

ADC0 boundary status register

FFEEH

0000 0000

FFFEH

FFFFH

FFFCH

FFFDH

FFFAH

FFFBH

FFF8H

FFF9H

FFF6H

FFF7H

FFF4H

FFF5H

FFF2H

FFF3H

FFF0H

FFF1H

FFEDH

AD0DAT0[7:0]

AD0DAT0[9:2]

AD0DAT1[7:0]

AD0DAT1[9:2]

AD0DAT2[7:0]

AD0DAT2[9:2]

AD0DAT3[7:0]

AD0DAT3[9:2]

AD0DAT4[7:0]

AD0DAT4[9:2]

AD0DAT5[7:0]

AD0DAT5[9:2]

AD0DAT6[7:0]

AD0DAT6[9:2]

AD0DAT7[7:0]

AD0DAT7[9:2]

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

7.2 Enhanced CPU

The P89LPC9408 uses an enhanced 80C51 CPU which runs at six times the speed of

standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most

instructions execute in one or two machine cycles.

7.3 Clocks

7.3.1 Clock deﬁnitions

The P89LPC9408 device has several internal clocks as deﬁned below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources (see Figure 6) and can also be optionally divided to a slower frequency (see

Section 7.8 “CCLK modiﬁcation: DIVM register”).

Note: f_oscis deﬁned as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine

cycle, and most instructions are executed in one to two machine cycles (two or four CCLK

cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is ^CCLK⁄₂.

7.3.2 CPU clock (OSCCLK)

The P89LPC9408 provides several user-selectable oscillator options in generating the

CPU clock. This allows optimization for a range of needs from high precision to lowest

possible cost. These options are conﬁgured when the ﬂash is programmed and include an

on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external

crystal, or an external clock source. The crystal oscillator can be optimized for low,

medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.

7.3.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic

resonators are also supported in this conﬁguration.

7.3.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic

resonators are also supported in this conﬁguration.

7.3.5 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic

resonators are also supported in this conﬁguration. When using an oscillator frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit

is required to hold the device in reset at power-up until V_DDhas reached its

speciﬁed level. When system power is removed V_DDwill fall below the minimum

speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in

some applications, an external brownout detect circuit may be required to hold the

device in reset when V_DDfalls below the minimum speciﬁed operating range.

P89LPC9408_1

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19 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

7.3.6 Clock output

The P89LPC9408 supports a user-selectable clock output function on the

XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if

another clock source has been selected (on-chip RC oscillator, watchdog oscillator,

external clock input on XTAL1) and if the RTC is not using the crystal oscillator as its clock

source. This allows external devices to synchronize to the P89LPC9408. This output is

enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is ¹⁄₂that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering idle, saving additional power.

7.4 On-chip RC oscillator option

The P89LPC9408 has a 6-bit TRIM register that can be used to tune the frequency of the

RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value

to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. End-user

applications can write to the TRIM register to adjust the on-chip RC oscillator to other

frequencies.

7.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator

can be used to save power when a high clock frequency is not needed.

7.6 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving the

P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be

used as a standard port pin or a clock output. When using an oscillator frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit

is required to hold the device in reset at power-up until V_DDhas reached its

speciﬁed level. When system power is removed V_DDwill fall below the minimum

speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in

some applications, an external brownout detect circuit may be required to hold the

device in reset when V_DDfalls below the minimum speciﬁed operating voltage.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

20 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

XTAL1

XTAL2

RTC

ADC0

OSCCLK

CCLK

DIVM

CPU

WDT

RCCLK

OSCILLATOR

÷2

PCLK

(7.3728 MHz ± 1 %)

WATCHDOG

OSCILLATOR

PCLK

(400 kHz +30 % −20 %)

32 × PLL

TIMER 0 AND

TIMER 1

CCU

I C-BUS

SPI

UART

002aab102

Fig 6. Block diagram of oscillator control

7.7 CPU Clock (CCLK) wake-up delay

The P89LPC9408 has an internal wake-up timer that delays the clock until it stabilizes

depending on the clock source used. If the clock source is any of the three crystal

selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus

60 µs to 100 µs. If the clock source is either the internal RC oscillator, watchdog oscillator,

or external clock, the delay is 224 OSCCLK cycles plus 60 µs to 100 µs.

7.8 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

7.9 Low power select

The P89LPC9408 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is

8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power

consumption further. On any reset, CLKLP is logic 0 allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

21 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

7.10 Memory organization

The various P89LPC9408 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status

registers, accessible only via direct addressing.

• XDATA

‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space

addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this

space could be implemented on-chip. The P89LPC9408 has 512 bytes of on-chip

XDATA memory, plus extended SFRs located in XDATA.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC9408 has 8 kB of on-chip Code memory.

7.11 Data RAM arrangement

The 768 bytes of on-chip RAM are organized as shown in Table 6.

Table 6:

Type

On-chip data memory usages

Data RAM

Size (bytes)

128

DATA

Memory that can be addressed directly and indirectly

Memory that can be addressed indirectly

IDATA

XDATA

256

Auxiliary (‘External Data’) on-chip memory that is accessed

using the MOVX instructions

512

7.12 Interrupts

The P89LPC9408 uses a four priority level interrupt structure. This allows great ﬂexibility

in controlling the handling of the many interrupt sources. The P89LPC9408 supports

16 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port

RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I²C-bus, keyboard,

comparators 1 and 2, SPI, CCU, data EEPROM write, and ADC completion.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in

the interrupt enable registers IEN0, IEN1, or IEN2. The IEN0 register also contains a

global disable bit, EA, which disables all interrupts.

P89LPC9408_1

Product data sheet

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22 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, IP1H, IP2, and

IP2H. An interrupt service routine in progress can be interrupted by a higher priority

interrupt, but not by another interrupt of the same or lower priority. The highest priority

interrupt service cannot be interrupted by any other interrupt source. If two requests of

different priority levels are pending at the start of an instruction, the request of higher

priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking. Note that the arbitration ranking is only used to resolve pending requests of the

same priority level.

7.12.1 External interrupt inputs

The P89LPC9408 has two external interrupt inputs as well as the Keypad Interrupt

function. The two interrupt inputs are identical to those present on the standard 80C51

microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle

and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an

interrupt request.

If an external interrupt is enabled when the P89LPC9408 is put into Power-down or Idle

mode, the interrupt will cause the processor to wake-up and resume operation. Refer to

Section 7.15 “Power reduction modes” for details.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

23 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

IE0

EX0

IE1

EX1

BOF

EBO

wake-up

(if in power-down)

RTCF

KBIF

EKBI

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF2

CMF1

EA (IE0.7)

TF0

ET0

TF1

ET1

TI and RI/RI

ES/ESR

EST

interrupt

to CPU

EI2C

SPIF

ESPI

any CCU interrupt

ECCU

EEIF

EIEE

ENADCI0

ADCI0

ENBI1

BNDI1

EADC

002aab104

Fig 7. Interrupt sources, interrupt enables, and power-down wake-up sources

7.13 I/O ports

The P89LPC9408 has four I/O ports: Port 0 and Port 1 are 8-bit ports. Port 2 is a 5-bit

port. Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock

and reset options chosen, as shown in Table 7.

Table 7:

Number of I/O pins available

Clock source

Reset option

Number of I/O pins

(not including LCD

pins)

On-chip oscillator or watchdog oscillator

No external reset (except during power-up)

External RST pin supported

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

24 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

Table 7:

Number of I/O pins available …continued

Clock source

Reset option

Number of I/O pins

(not including LCD

pins)

External clock input

No external reset (except during power-up)

External RST pin supported^[1]

Low/medium/high speed oscillator

(external crystal or resonator)

No external reset (except during power-up)

External RST pin supported^[1]

[1] Required for operation above 12 MHz.

7.13.1 Port conﬁgurations

All but three I/O port pins on the P89LPC9408 may be conﬁgured by software to one of

four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port

outputs), push-pull, open drain, and input-only. Two conﬁguration registers for each port

select the output type for each port pin.

1. P1.5 (RST) can only be an input and cannot be conﬁgured.

2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be conﬁgured to be either input-only or

open-drain.

7.13.1.1 Quasi-bidirectional output conﬁguration

Quasi-bidirectional output type can be used as both an input and output without the need

to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a fairly large current. These features are

somewhat similar to an open-drain output except that there are three pull-up transistors in

the quasi-bidirectional output that serve different purposes.

The P89LPC9408 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional

mode, if a user applies 5 V on the pin, there will be a current ﬂowing from the pin to V_DD

causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is

discouraged.

A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression

circuit.

7.13.1.2 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port conﬁgured in this manner must have an external pull-up, typically a resistor

tied to V_DD

An open-drain port pin has a Schmitt trigger input that also has a glitch suppression

circuit.

7.13.1.3 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt trigger input that

also has a glitch suppression circuit.

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7.13.1.4 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strong

pull-up when the port latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a port output. A push-pull port pin has a Schmitt

trigger input that also has a glitch suppression circuit.

7.13.2 Port 0 analog functions

The P89LPC9408 incorporates two Analog Comparators. In order to give the best analog

function performance and to minimize power consumption, pins that are being used for

analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-Only

(high-impedance) mode.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.

On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.

7.13.3 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from

the LPC76x series of devices.

• After power-up, all I/O pins except P1.5, may be conﬁgured by software.

• Pin P1.5 is input only. Pins P1.2 and P1.3 and are conﬁgurable for either input-only or

open-drain.

Every output on the P89LPC9408 has been designed to sink typical LED drive current.

However, there is a maximum total output current for all ports which must not be

exceeded. Please refer to Table 12 “Static electrical characteristics” for detailed

speciﬁcations.

All ports pins that can function as an output have slew rate controlled outputs to limit noise

generated by quickly switching output signals. The slew rate is factory-set to

approximately 10 ns rise and fall times.

7.14 Power monitoring functions

The P89LPC9408 incorporates power monitoring functions designed to prevent incorrect

operation during initial power-up and power loss or reduction during operation. This is

accomplished with two hardware functions: Power-on detect and Brownout detect.

7.14.1 Brownout detection

The Brownout detect function determines if the power supply voltage drops below a

certain level. The default operation is for a Brownout detection to cause a processor reset,

however it may alternatively be conﬁgured to generate an interrupt.

Brownout detection may be enabled or disabled in software.

If Brownout detection is enabled the brownout condition occurs when V_DDfalls below the

brownout trip voltage, V_bo(see Table 12 “Static electrical characteristics”), and is negated

when V_DDrises above V_bo. If the P89LPC9408 device is to operate with a power supply

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that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device

can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from

operating.

For correct activation of Brownout detect, the V_DDrise and fall times must be observed.

Please see Table 12 “Static electrical characteristics” for speciﬁcations.

7.14.2 Power-on detection

The Power-on detect has a function similar to the Brownout detect, but is designed to work

as power comes up initially, before the power supply voltage reaches a level where

Brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an

initial power-up condition. The POF ﬂag will remain set until cleared by software.

7.15 Power reduction modes

The P89LPC9408 supports three different power reduction modes. These modes are Idle

mode, Power-down mode, and total Power-down mode.

7.15.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor

when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle

mode.

7.15.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The

P89LPC9408 exits Power-down mode via any reset, or certain interrupts. In Power-down

mode, the power supply voltage may be reduced to the RAM keep-alive voltage V_RAM

This retains the RAM contents at the point where Power-down mode was entered. SFR

contents are not guaranteed after V_DDhas been lowered to V_RAM, therefore it is highly

recommended to wake up the processor via reset in this case. V_DDmust be raised to

within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode,

increasing the total power used during power-down. These include: Brownout detect,

watchdog timer, Comparators (note that Comparators can be powered-down separately),

and RTC/System Timer. The internal RC oscillator is disabled unless both the RC

oscillator has been selected as the system clock and the RTC is enabled.

7.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and

the voltage comparators are also disabled to conserve additional power. The internal RC

oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down, there will be high power consumption. Please use an external low frequency

clock to achieve low power with the RTC running during power-down.

7.16 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,

P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the external

reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

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Remark: During a power-up sequence, the RPE selection is overridden and this pin will

always function as a reset input. An external circuit connected to this pin should not

hold this pin LOW during a power-on sequence as this will keep the device in reset.

After power-up this input will function either as an external reset input or as a digital input

as deﬁned by the RPE bit. Only a power-up reset will temporarily override the selection

deﬁned by RPE bit. Other sources of reset will not override the RPE bit.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1).

• Power-on detect.

• Brownout detect.

• Watchdog timer.

• Software reset.

• UART break character detect reset.

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read

this register to determine the most recent reset source. These ﬂag bits can be cleared in

software by writing a logic 0 to the corresponding bit. More than one ﬂag bit may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain set.

7.16.1 Reset vector

Following reset, the P89LPC9408 will fetch instructions from either address 0000H or the

Boot address. The Boot address is formed by using the Boot Vector as the high byte of the

address and the low byte of the address = 00H.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot

Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see

P89LPC9408 User manual). Otherwise, instructions will be fetched from address 0000H.

7.17 Timers/counters 0 and 1

The P89LPC9408 has two general purpose counter/timers which are upward compatible

with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to operate either as

timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer

overﬂow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T0 or T1. In this function, the external input is sampled

once during every machine cycle.

Timer 0 and Timer 1 have ﬁve operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2

and 6 are the same for both Timers/Counters. Mode 3 is different.

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7.17.1 Mode 0

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured as a

13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

7.17.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

7.17.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload. Mode 2

operation is the same for Timer 0 and Timer 1.

7.17.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit

counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is

in Mode 3 it can still be used by the serial port as a baud rate generator.

7.17.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

7.17.6 Timer overﬂow toggle output

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a timer

overﬂow occurs. The same device pins that are used for the T0 and T1 count inputs are

also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the ﬁrst

timer overﬂow when this mode is turned on.

7.18 RTC/system timer

The P89LPC9408 has a simple RTC that allows a user to continue running an accurate

timer while the rest of the device is powered-down. The RTC can be a wake-up or an

interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a

16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded

again and the RTCF ﬂag will be set. The clock source for this counter can be either the

CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being

used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will

use CCLK as its clock source. Only power-on reset will reset the RTC and its associated

SFRs to the default state.

7.19 CCU

This unit features:

• A 16-bit timer with 16-bit reload on overﬂow.

• Selectable clock, with prescaler to divide clock source by any integral number

between 1 and 1024.

• Four compare/PWM outputs with selectable polarity

• Symmetrical/asymmetrical PWM selection

• Two capture inputs with event counter and digital noise rejection ﬁlter

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• Seven interrupts with common interrupt vector (one Overﬂow, two Capture,

four Compare)

• Safe 16-bit read/write via shadow registers.

7.19.1 CCU Clock (CCUCLK)

The CCU runs on the CCUCLK, which is either PCLK in basic timer mode, or the output of

a PLL. The PLL is designed to use a clock source between 0.5 MHz to 1 MHz that is

multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode

(asymmetrical or symmetrical). The PLL contains a 4-bit divider to help divide PCLK into a

frequency between 0.5 MHz and 1 MHz.

7.19.2 CCU clock prescaling

This CCUCLK can further be divided down by a prescaler. The prescaler is implemented

as a 10-bit free-running counter with programmable reload at overﬂow.

7.19.3 Basic timer operation

The timer is a free-running up/down counter with a direction control bit. If the timer

counting direction is changed while the counter is running, the count sequence will be

reversed. The timer can be written or read at any time.

When a reload occurs, the CCU Timer Overﬂow Interrupt Flag will be set, and an interrupt

generated if enabled. The 16-bit CCU Timer may also be used as an 8-bit up/down timer.

7.19.4 Output compare

There are four output compare channels A, B, C and D. Each output compare channel

needs to be enabled in order to operate and the user will have to set the associated I/O

pin to the desired output mode to connect the pin. When the contents of the timer matches

that of a capture compare control register, the Timer Output Compare Interrupt Flag

(TOCFx) becomes set. An interrupt will occur if enabled.

7.19.5 Input capture

Input capture is always enabled. Each time a capture event occurs on one of the two input

capture pins, the contents of the timer is transferred to the corresponding 16-bit input

capture register. The capture event can be programmed to be either rising or falling edge

triggered. A simple noise ﬁlter can be enabled on the input capture by enabling the Input

Capture Noise Filter bit. If set, the capture logic needs to see four consecutive samples of

the same value in order to recognize an edge as a capture event. An event counter can be

set to delay a capture by a number of capture events.

7.19.6 PWM operation

PWM operation has two main modes, symmetrical and asymmetrical.

In asymmetrical PWM operation the CCU Timer operates in down-counting mode

regardless of the direction control bit.

In symmetrical mode, the timer counts up/down alternately. The main difference from

basic timer operation is the operation of the compare module, which in PWM mode is

used for PWM waveform generation.

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As with basic timer operation, when the PWM (compare) pins are connected to the

compare logic, their logic state remains unchanged. However, since bit FCOx is used to

hold the halt value, only a compare event can change the state of the pin.

TOR2

compare value

timer value

0x0000

non-inverted

inverted

002aaa893

Fig 8. Asymmetrical PWM, down-counting

TOR2

compare value

timer value

non-inverted

inverted

002aaa894

Fig 9. Symmetrical PWM

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7.19.7 Alternating output mode

In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating

pairs for bridge drive control. In this mode the output of these PWM channels are

alternately gated on every counter cycle.

TOR2

COMPARE VALUE A (or C)

COMPARE VALUE B (or D)

TIMER VALUE

PWM OUTPUT (OCA or OCC)

PWM OUTPUT (OCB or OCD)

002aaa895

Fig 10. Alternate output mode

7.19.8 PLL operation

The PWM module features a Phase Locked Loop that can be used to generate a

CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module

provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal

frequency is 1 MHz or higher. The PLL is fed an input signal of 0.5 MHz to 1 MHz and

generates an output signal of 32 times the input frequency. This signal is used to clock the

timer. The user will have to set a divider that scales PCLK by a factor of 1 to 16. This

divider is found in the SFR register TCR21. The PLL frequency can be expressed as

shown in Equation 1.

PLCK

(N + 1)

PLL frequency =

(1)

------------------

Where: N is the value of PLLDV3:0.

Since N ranges in 0 to 15, the CCLK frequency can be in the range of PCLK to ^PCLK⁄₁₆.

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7.19.9 CCU interrupts

There are seven interrupt sources on the CCU which share a common interrupt vector.

EA (IEN0.7)

ECCU (IEN1.4)

TOIE2 (TICR2.7)

TOIF2 (TIFR2.7)

TICIE2A (TICR2.0)

TICF2A (TIFR2.0)

TICIE2B (TICR2.1)

TICF2B (TIFR2.1)

TOCIE2A (TICR2.3)

TOCF2A (TIFR2.3)

interrupt to

CPU

other

interrupt

sources

TOCIE2B (TICR2.4)

TOCF2B (TIFR2.4)

TOCIE2C (TICR2.5)

TOCF2C (TIFR2.5)

TOCIE2D (TICR2.6)

TOCF2D (TIFR2.6)

ENCINT.0

ENCINT.1

ENCINT.2

PRIORITY

ENCODER

002aaa896

Fig 11. CCU interrupts

7.20 UART

The P89LPC9408 has an enhanced UART that is compatible with the conventional 80C51

UART except that Timer 2 overﬂow cannot be used as a baud rate source. The

P89LPC9408 does include an independent Baud Rate Generator. The baud rate can be

selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the independent

Baud Rate Generator. In addition to the baud rate generation, enhancements over the

standard 80C51 UART include Framing Error detection, automatic address recognition,

selectable double buffering and several interrupt options. The UART can be operated in

four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.

7.20.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at ¹⁄₁₆of the CPU clock

frequency.

7.20.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),

8 data bits (LSB ﬁrst), and a stop bit (logic 1). When data is received, the stop bit is stored

in RB8 in Special Function Register SCON. The baud rate is variable and is determined

by the Timer 1 overﬂow rate or the Baud Rate Generator (described in Section 7.20.5

“Baud rate generator and selection”).

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7.20.3 Mode 2

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data

bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logic 1). When data is

transmitted, the 9^thdata bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.

Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is

received, the 9^thdata bit goes into RB8 in Special Function Register SCON, while the stop

bit is not saved. The baud rate is programmable to either ¹⁄₁₆or ¹⁄₃₂of the CPU clock

frequency, as determined by the SMOD1 bit in PCON.

7.20.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8

data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logic 1). In fact, Mode 3 is

the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable

and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in

Section 7.20.5 “Baud rate generator and selection”).

7.20.5 Baud rate generator and selection

The P89LPC9408 enhanced UART has an independent Baud Rate Generator. The baud

rate is determined by a baud rate preprogrammed into the BRGR1 and BRGR0 SFRs

which together form a 16-bit baud rate divisor value that works in a similar manner as

Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be

used for other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 12). Note

that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent Baud Rate Generator uses OSCCLK.

timer 1 overflow

SMOD1 = 1

(PCLK-based)

SBRGS = 0

SBRGS = 1

÷2

baud rate modes 1 and 3

002aaa897

SMOD1 = 0

baud rate generator

(CCLK-based)

Fig 12. Baud rate sources for UART (Modes 1, 3)

7.20.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)

is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is

logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are set up

when SMOD0 is logic 0.

7.20.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device

and force the device into ISP mode.

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7.20.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be

written to SBUF while the ﬁrst character is being transmitted. Double buffering allows

transmission of a string of characters with only one stop bit between any two characters,

as long as the next character is written between the start bit and the stop bit of the

previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is

compatible with the conventional 80C51 UART. If enabled, the UART allows writing to

SBUF while the previous data is being shifted out. Double buffering is only allowed in

Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled

(DBMOD = 0).

7.20.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the TX interrupt is generated

when the double buffer is ready to receive new data.

7.20.10 The 9^thbit (bit 8) in double buffering (modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long

as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until

the bit is shifted out, as indicated by the TX interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will

be double-buffered together with SBUF data.

7.21 I²C-bus serial interface

The I²C-bus uses two wires (SDA and SCL) to transfer information between devices

connected to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multi master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I²C-bus may be used for test and diagnostic purposes.

A typical I²C-bus conﬁguration is shown in Figure 13. The P89LPC9408 device provides a

byte-oriented I²C-bus interface that supports data transfers up to 400 kHz.

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SDA

SCL

I C-bus

OTHER DEVICE

WITH I C-BUS

INTERFACE

OTHER DEVICE

WITH I C-BUS

INTERFACE

P1.3/SDA

P1.2/SCL

I C MCU

002aab410

Fig 13. I²C-bus conﬁguration

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I2ADR

ADDRESS REGISTER

COMPARATOR

P1.3

INPUT

FILTER

P1.3/SDA

SHIFT REGISTER

ACK

I2DAT

OUTPUT

STAGE

BIT COUNTER /

ARBITRATION &

SYNC LOGIC

CCLK

INPUT

FILTER

TIMING

AND

CONTROL

LOGIC

P1.2/SCL

SERIAL CLOCK

GENERATOR

OUTPUT

STAGE

interrupt

timer 1

overflow

I2CON

I2SCLH

I2SCLL

P1.2

CONTROL REGISTERS &

SCL DUTY CYCLE REGISTERS

STATUS

DECODER

status bus

I2STAT

STATUS REGISTER

002aaa899

Fig 14. I²C-bus serial interface block diagram - P89LPC9408

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7.22 SPI

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

The P89LPC9408 provides another high-speed serial communication interface—the SPI

interface. SPI is a full-duplex, high-speed, synchronous communication bus with two

operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in

Master mode or up to 3 Mbit/s in Slave mode. It has a transfer completion ﬂag and write

collision ﬂag protection.

CPU clock

MISO

P2.3

8-BIT SHIFT REGISTER

READ DATA BUFFER

MOSI

P2.2

DIVIDER

BY 4, 16, 64, 128

CONTROL

LOGIC

SPICLK

P2.5

clock

SPI clock (master)

SELECT

CLOCK LOGIC

MSTR

SPEN

SPI CONTROL

SPI CONTROL REGISTER

SPI STATUS REGISTER

SPI

interrupt

request

internal

data

bus

002aab466

Fig 15. SPI block diagram

The SPI interface has three pins: SPICLK, MOSI, and MISO:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and ﬂows

from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output

in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,

SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port functions.

Typical connections are shown in Figure 16 through Figure 18.

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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

7.22.1 Typical SPI conﬁgurations

master

slave

MISO

MOSI

MISO

MOSI

8-BIT SHIFT

SPICLK

SPI CLOCK

GENERATOR

SS/PORT

002aab467

Fig 16. SPI single master single slave conﬁguration

master

slave

MISO

MOSI

8-BIT SHIFT

MOSI

SPICLK

SPI CLOCK

GENERATOR

SPI CLOCK

GENERATOR

SS/PORT

002aab468

Fig 17. SPI dual device conﬁguration, where either can be a master or a slave

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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

master

slave

MISO

MOSI

MISO

MOSI

8-BIT SHIFT

SPICLK

port

SPICLK

SPI CLOCK

GENERATOR

slave

MISO

MOSI

8-BIT SHIFT

SPICLK

port

002aaa903

Fig 18. SPI single master multiple slaves conﬁguration

7.23 Analog comparators

Two analog comparators are provided on the P89LPC9408. Input and output options allow

use of the comparators in a number of different conﬁgurations. Comparator operation is

such that the output is a logic 1 (which may be read in a register and/or routed to a pin)

when the positive input (one of two selectable pins) is greater than the negative input

(selectable from a pin or an internal reference voltage). Otherwise the output is a zero.

Each comparator may be conﬁgured to cause an interrupt when the output value changes.

The overall connections to both comparators are shown in Figure 19. The comparators

function to V_DD= 2.4 V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not

guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt

should not be enabled during that time, and the comparator interrupt ﬂag must be cleared

before the interrupt is enabled in order to prevent an immediate interrupt service.

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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

CP1

OE1

comparator 1

(P0.4) CIN1A

(P0.3) CIN1B

CO1

CMP1 (P0.6)

(P0.5) CMPREF

change detect

ref(bg)

CMF1

CN1

interrupt

change detect

CP2

CMF2

comparator 2

(P0.2) CIN2A

(P0.1) CIN2B

CMP2 (P0.0)

CO2

OE2

002aaa904

CN2

Fig 19. Comparator input and output connections

7.23.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to as

V_ref(bg), is 1.23 V ± 10 %.

7.23.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is

set whenever the comparator output changes state. The ﬂag may be polled by software or

may be used to generate an interrupt. The two comparators use one common interrupt

vector. If both comparators enable interrupts, after entering the interrupt service routine,

the user needs to read the ﬂags to determine which comparator caused the interrupt.

7.23.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is

activated, but both comparators are disabled automatically in Total Power-down mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of the

comparator output state will generate an interrupt and wake up the processor. If the

comparator output to a pin is enabled, the pin should be conﬁgured in the push-pull mode

in order to obtain fast switching times while in Power-down mode. The reason is that with

the oscillator stopped, the temporary strong pull-up that normally occurs during switching

on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the normal

operating mode. This fact should be taken into account when system power consumption

is an issue. To minimize power consumption, the user can disable the comparators via

PCONA.5, or put the device in Total Power-down mode.

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7.24 Keypad Interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be

generated when Port 0 is equal to or not equal to a certain pattern. This function can be

used for bus address recognition or keypad recognition. The user can conﬁgure the port

via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins

connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is

used to deﬁne a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag

(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is

matched while the Keypad Interrupt function is active. An interrupt will be generated if

enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to

deﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series,

the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key

connected to Port 0 which is enabled by the KBMASK register will cause the hardware to

set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to

wake up the CPU from Idle or Power-down modes. This feature is particularly useful in

handheld, battery-powered systems that need to carefully manage power consumption

yet also need to be convenient to use.

In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held longer

than six CCLKs.

7.25 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure to

feed the timer prior to the timer reaching its terminal count. It consists of a programmable

12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap

taken from the prescaler. The clock source for the prescaler is either the PCLK or the

nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a

power-on reset. When the watchdog feature is disabled, it can be used as an interval timer

and may generate an interrupt. Figure 20 shows the watchdog timer in Watchdog mode.

Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog

clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a

time-out period that ranges from a few µs to a few seconds. Please refer to the

P89LPC9408 User manual for more details.

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8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

WDL (C1H)

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

watchdog

oscillator

8-BIT DOWN

(1)

COUNTER

PRESCALER

reset

÷32

PCLK

SHADOW REGISTER

PRE2

PRE1

PRE0

WDRUN WDTOF WDCLK

WDCON (A7H)

002aaa905

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

Fig 20. Watchdog timer in Watchdog mode (WDTE = 1)

7.26 Additional features

7.26.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,

as if an external reset or watchdog reset had occurred. Care should be taken when writing

to AUXR1 to avoid accidental software resets.

7.26.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address

used with certain instructions. The DPS bit in the AUXR1 register selects one of the two

Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may

be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,

without the possibility of inadvertently altering other bits in the register.

7.27 LCD controller

7.27.1 General description

The LCD segment driver in the P89LPC9408 can interface to most LCDs using low

multiplex rates. It generates the drive signals for static or multiplexed LCDs containing up

to four backplanes and up to 32 segments. The LCD controller communicates to a host

using the I²C-bus. The I²C-bus clock and data signals for both the microcontroller and the

LCD controller are available on the P89LPC9408 providing system ﬂexibility.

Communication overhead to manage the display is minimized by an on-chip display RAM

with auto-increment addressing, hardware subaddressing, and display memory switching

(static and duplex drive modes).

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7.27.2 Functional description

The LCD controller is a versatile peripheral device designed to interface microcontrollers

to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up

to four backplanes and up to 32 segments. The display conﬁgurations possible with the

LCD controller depend on the number of active backplane outputs required. A selection of

display conﬁgurations is shown in Table 8. All of these conﬁgurations can be implemented

in a typical system.

The microcontroller communicates to the LCD controller using the I²C-bus.The

appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.

The only other connections required to complete the system are to the power supplies

(V_DD, V_SSand V_LCD) and the LCD panel chosen for the application.

Table 8:

Selection of display conﬁgurations

7-Segments Numeric

Number of

14- Segments Alphanumeric

Dot Matrix

Back Planes

Segments

Digits

Indicator

Symbols

Characters

Indicator

Symbols

128

7.27.3 LCD bias voltages

LCD biasing voltages are obtained from an internal voltage divider consisting of three

series resistors connected between V_LCDand V_SS. The LCD voltage can be temperature

compensated externally via the supply to pin V_LCD. A voltage selector drives the

multiplexing of the LCD based on programmable conﬁgurations.

7.27.4 Oscillator

An internal oscillator provides the clock signals for the internal logic of the LCD controller

and its LCD drive signals. After power-up, pin SDA must be HIGH to guarantee that the

clock starts.

7.27.5 Timing

The LCD controller timing controls the internal data ﬂow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. The timing

also generates the LCD frame signal whose frequency is derived from the clock

frequency. The frame signal frequency is a ﬁxed division of the clock frequency from either

the internal or an external clock.

Frame frequency = f_CLK/24.

7.27.6 Display register

A display latch holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display latch, the

LCD segment outputs, and each column of the display RAM.

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7.27.7 Segment outputs

The LCD drive section includes 32 segment outputs S0 to S31. The segment output

signals are generated according to the multiplexed backplane signals and the display

latch data. When less than 32 segment outputs are required, the unused segment outputs

should be left open-circuit.

7.27.8 Backplane outputs

The LCD drive section has four backplane outputs BP0 to BP3. The backplane output

signals are generated based on the selected LCD drive mode. If less than four backplane

outputs are required, the unused outputs can be left open-circuit. In the 1:3 multiplex drive

mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be

tied together to give enhanced drive capabilities. In the 1:2 multiplex drive mode, BP0 and

BP2, BP1 and BP3 respectively carry the same signals and may also be paired to

increase the drive capabilities. In the static drive mode the same signal is carried by all

four backplane outputs and they can be connected in parallel for very high drive

requirements.

7.27.9 Display RAM

The display RAM is a static 32 × 4-bit RAM which stores LCD data. There is a one-to-one

correspondence between the RAM addresses and the segment outputs, and between the

individual bits of a RAM word and the backplane outputs. The ﬁrst RAM column

corresponds to the 32 segments for backplane 0 (BP0). In multiplexed LCD applications

the segment data of the second, third and fourth column of the display RAM are

time-multiplexed with BP1, BP2 and BP3 respectively.

7.27.10 Data pointer

The Display RAM is addressed using the data pointer. Either a single byte or a series of

display bytes may be loaded into any location of the display RAM.

7.27.11 Output bank selector

The LCD controller includes a RAM bank switching feature in the static and 1:2 drive

modes. In the static drive mode, the BANK SELECT command may request the contents

of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the contents

of bits 2 and 3 may be selected instead of bits 0 and 1. This allows display information to

be prepared in an alternative bank and then selected for display when it is assembled.

7.27.12 Input bank selector

The input bank selector loads display data into the display RAM based on the selected

LCD drive conﬁguration. The BANK SELECT command can be used to load display data

in bit 2 in static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector

functions are independent of the output bank selector.

7.27.13 Blinker

The LCD controller has a very versatile display blinking capability. The whole display can

blink at a frequency selected by the BLINK command. Each blink frequency is a multiple

integer value of the clock frequency; the ratio between the clock frequency and blink

frequency depends on the blink mode selected, as shown in Table 9.

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An additional feature allows an arbitrary selection of LCD segments to be blinked in the

static and 1:2 drive modes. This is implemented without any communication overheads by

the output bank selector which alternates the displayed data between the data in the

display RAM bank and the data in an alternative RAM bank at the blink frequency. This

mode can also be implemented by the BLINK command.

The entire display can be blinked at a frequency other than the nominal blink frequency by

sequentially resetting and setting the display enable bit E at the required rate using the

MODE SET command.

Table 9:

Blink mode

Off

Blinking frequencies

Normal operating mode ratio Normal Blink frequency

Blinking off

2 Hz

f_osc(LCD)/768

2 Hz

1 Hz

f_osc(LCD)/1536

f_osc(LCD)/3072

1 Hz

0.5 Hz

Blink modes 0.5 Hz, 1 Hz and 2 Hz, and nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz

correspond to an oscillator frequency (f_osc(LCD)) of 1536 Hz at pin CLK. The oscillator

frequency range is 397 Hz to 3046 Hz.

7.27.13.1 I²C-bus controller

The LCD controller acts as an I²C-bus slave receiver. In the P89LPC9408 the hardware

subaddress inputs A0, A,1 and A2 are tied to V_SSsetting the hardware subaddress = 0.

7.27.14 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

7.27.15 I²C-bus slave addresses

The I²C-bus slave address is 0111 0000. The LCD controller is a write-only device and will

not respond to a read access.

7.28 Data EEPROM

The P89LPC9408 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR

based, byte readable, byte writable, and erasable (via row ﬁll and sector ﬁll). The user can

read, write and ﬁll the memory via SFRs and one interrupt. This Data EEPROM provides

100,000 minimum erase/program cycles for each byte.

• Byte Mode: In this mode, data can be read and written one byte at a time.

• Row Fill: In this mode, the addressed row (64 bytes) is ﬁlled with a single value. The

entire row can be erased by writing 00H.

• Sector Fill: In this mode, all 512 bytes are ﬁlled with a single value. The entire sector

can be erased by writing 00H.

After the operation ﬁnishes, the hardware will set the EEIF bit, which if enabled will

generate an interrupt. The ﬂag is cleared by software.

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7.29 Flash program memory

7.29.1 General description

The P89LPC9408 ﬂash memory provides in-circuit electrical erasure and programming.

The ﬂash can be erased, read, and written as bytes. The Sector and Page Erase functions

can erase any ﬂash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase

the entire program memory. ICP using standard commercial programmers is available. In

addition, IAP and byte-erase allows code memory to be used for non-volatile data storage.

On-chip erase and write timing generation contribute to a user-friendly programming

interface. The P89LPC9408 ﬂash reliably stores memory contents even after

100,000 erase and program cycles. The cell is designed to optimize the erase and

programming mechanisms. The P89LPC9408 uses V_DDas the supply voltage to perform

the Program/Erase algorithms.

7.29.2 Features

• Programming and erase over the full operating voltage range.

• Byte erase allows code memory to be used for data storage.

• Read/Programming/Erase using ISP/IAP/ICP.

• Internal ﬁxed boot ROM, containing low-level IAP routines available to user code.

• Default loader providing ISP via the serial port, located in upper end of user program

memory.

• Boot vector allows user-provided ﬂash loader code to reside anywhere in the ﬂash

memory space, providing ﬂexibility to the user.

• Any ﬂash program or erase operation in 2 ms.

• Programming with industry-standard commercial programmers.

• Programmable security for the code in the ﬂash for each sector.

• 100,000 typical erase/program cycles for each byte.

• 10 year minimum data retention.

7.29.3 Flash organization

The program memory consists of eight 1 kB sectors on the P89LPC9408 device. Each

sector can be further divided into 64-byte pages. In addition to sector erase, page erase,

and byte erase, a 64-byte page register is included which allows from 1 to 64 bytes of a

given page to be programmed at the same time, substantially reducing overall

programming time.

7.29.4 Using ﬂash as data storage

The ﬂash code memory array of this device supports individual byte erasing and

programming. Any byte in the code memory array may be read using the MOVC

instruction, provided that the sector containing the byte has not been secured (a MOVC

instruction is not allowed to read code memory contents of a secured sector). Thus any

byte in a non-secured sector may be used for non-volatile data storage.

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7.29.5 Flash programming and erasing

Four different methods of erasing or programming of the ﬂash are available. The ﬂash may

be programmed or erased in the end-user application (IAP) under control of the

application’s ﬁrmware. Another option is to use the ICP mechanism. This ICP system

provides for programming through a serial clock - serial data interface. As shipped from

the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing

for the device to be programmed in circuit through the serial port. The ﬂash may also be

programmed or erased using a commercially available EPROM programmer which

supports this device. This device does not provide for direct veriﬁcation of code memory

contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire

user code space.

7.29.6 In-Circuit Programming

In-Circuit Programming is performed without removing the microcontroller from the

system. The ICP facility consists of internal hardware resources to facilitate remote

programming of the P89LPC9408 through a two-wire serial interface. The Philips ICP

facility has made ICP in an embedded application—using commercially available

programmers—possible with a minimum of additional expense in components and circuit

board area. The ICP function uses ﬁve pins. Only a small connector needs to be available

to interface your application to a commercial programmer in order to use this feature.

Additional details may be found in the P89LPC9408 User manual.

7.29.7 In-Application Programming

In-Application Programming is performed in the application under the control of the

microcontroller’s ﬁrmware. The IAP facility consists of internal hardware resources to

facilitate programming and erasing. The Philips IAP has made IAP in an embedded

application possible without additional components. Two methods are available to

accomplish IAP. A set of predeﬁned IAP functions are provided in a Boot ROM and can be

called through a common interface, PGM_MTP. Several IAP calls are available for use by

an application program to permit selective erasing and programming of ﬂash sectors,

pages, security bits, conﬁguration bytes, and device ID. These functions are selected by

setting up the microcontroller’s registers before making a call to PGM_MTP at FF03H.

The Boot ROM occupies the program memory space at the top of the address space from

FF00H to FEFFH, thereby not conﬂicting with the user program memory space.

In addition, IAP operations can be accomplished through the use of four SFRs consisting

of a control/status register, a data register, and two address registers. Additional details

may be found in the P89LPC9408 User manual.

7.29.8 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility

consists of a series of internal hardware resources coupled with internal ﬁrmware to

facilitate remote programming of the P89LPC9408 through the serial port. This ﬁrmware is

provided by Philips and embedded within each P89LPC9408 device. The Philips ISP

facility has made ISP in an embedded application possible with a minimum of additional

expense in components and circuit board area. The ISP function uses ﬁve pins (V_DD, V_SS

TXD, RXD, and RST). Only a small connector needs to be available to interface your

application to an external circuit in order to use this feature.

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7.29.9 Power-on reset code execution

The P89LPC9408 contains two special ﬂash elements: the Boot Vector and the Boot

Status Bit. Following reset, the P89LPC9408 examines the contents of the Boot Status

Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which

is the normal start address of the user’s application code. When the Boot Status Bit is set

to a value other than zero, the contents of the Boot Vector are used as the HIGH byte of

the execution address and the LOW byte is set to 00H.

Table 10 shows the factory default Boot Vector settings for these devices. Note: These

settings are different than the original P89LPC932. Tools designed to support the

P89LPC9408 should be used to program this device, such as Flash Magic version

1.98, or later. A factory-provided boot loader is preprogrammed into the address space

indicated and uses the indicated boot loader entry point to perform ISP functions. This

code can be erased by the user. Users who wish to use this loader should take

precautions to avoid erasing the 1 kB sector that contains this boot loader. Instead,

the page erase function can be used to erase the ﬁrst eight 64-byte pages located in

this sector. A custom boot loader can be written with the Boot Vector set to the custom

boot loader, if desired.

Table 10: Default Boot Vector values and ISP entry points

Device

Default

Defaultboot loader 1 kB sector

Boot Vector

boot loader

entry point

code range

range

P89LPC9408

1FH

1F00H

1E00H to 1FFFH

1C00H to 1FFFH

7.29.10 Hardware activation of the boot loader

The boot loader can also be executed by forcing the device into ISP mode during a

power-on sequence (see the P89LPC9408 User manual for speciﬁc information). This has

the same effect as having a non-zero status byte. This allows an application to be built that

will normally execute user code but can be manually forced into ISP operation. If the

factory default setting for the Boot Vector (1FH) is changed, it will no longer point to the

factory preprogrammed ISP boot loader code. After programming the ﬂash, the status

byte should be programmed to zero in order to allow execution of the user’s application

code beginning at address 0000H.

7.30 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC9408 must be deﬁned at power-up and

therefore cannot be set by the program after start of execution. These features are

conﬁgured through the use of the ﬂash byte UCFG1. Please see the P89LPC9408 User

manual for additional details.

7.31 User sector security bytes

There are eight User Sector Security Bytes on the P89LPC9408 device. Each byte

corresponds to one sector. Please see the P89LPC9408 User manual for additional

details.

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8. ADC

8.1 General description

The P89LPC9408 has a 10-bit, 8-channel multiplexed successive approximation

analog-to-digital converter module. A block diagram of the ADC is shown in Figure 21.

The ADC consists of an 8-input multiplexer which feeds a sample-and-hold circuit

providing an input signal to one of two comparator inputs. The control logic in combination

with the SAR drives a digital-to-analog converter which provides the other input to the

comparator. The output of the comparator is fed to the SAR.

8.2 Features

■ 10-bit, 8-channel multiplexed input, successive approximation ADC.

■ Eight result register pairs.

■ Six operating modes

◆ Fixed channel, single conversion mode

◆ Fixed channel, continuous conversion mode

◆ Auto scan, single conversion mode

◆ Auto scan, continuous conversion mode

◆ Dual channel, continuous conversion mode

◆ Single step mode

■ Three conversion start modes

◆ Timer triggered start

◆ Start immediately

◆ Edge triggered

■ 10-bit conversion time of 4 µs at an ADC clock of 9 MHz

■ Interrupt or polled operation

■ High and Low Boundary limits interrupt; selectable in or out-of-range

■ Clock divider

■ Power-down mode

8.3 Block diagram

comp

INPUT

MUX

SAR

–

CONTROL

LOGIC

DAC0

CCLK

002aab103

Fig 21. ADC block diagram

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8.4 ADC operating modes

8.4.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be

performed and the result placed in the result register pair which corresponds to the

selected input channel. An interrupt, if enabled, will be generated after the conversion

completes.

8.4.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the

conversions will be sequentially placed in the eight result register pairs. The user may

select whether an interrupt can be generated after every four or every eight conversions.

Additional conversion results will again cycle through the result register pairs, overwriting

the previous results. Continuous conversions continue until terminated by the user.

8.4.3 Auto scan, single conversion mode

Any combination of the eight input channels can be selected for conversion. A single

conversion of each selected input will be performed and the result placed in the result

whether an interrupt, if enabled, will be generated after either the ﬁrst four conversions

have occurred or all selected channels have been converted. If the user selects to

generate an interrupt after the four input channels have been converted, a second

interrupt will be generated after the remaining input channels have been converted. If only

a single channel is selected this is equivalent to single channel, single conversion mode.

8.4.4 Auto scan, continuous conversion mode

Any combination of the eight input channels can be selected for conversion. A conversion

of each selected input will be performed and the result placed in the result register pair

which corresponds to the selected input channel. The user may select whether an

interrupt, if enabled, will be generated after either the ﬁrst four conversions have occurred

or all selected channels have been converted. If the user selects to generate an interrupt

after the four input channels have been converted, a second interrupt will be generated

after the remaining input channels have been converted. After all selected channels have

been converted, the process will repeat starting with the ﬁrst selected channel. Additional

conversion results will again cycle through the eight result register pairs, overwriting the

previous results. Continuous conversions continue until terminated by the user.

8.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs

on two user-selectable inputs. The result of the conversion of the ﬁrst channel is placed in

the result register pair, AD0DAT0R and AD0DAT0L. The result of the conversion of the

second channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The ﬁrst

channel is again converted and its result stored in AD0DAT2R and AD0DAT2L. The

second channel is again converted and its result placed in AD0DAT3R and AD0DAT3L,

etc. An interrupt is generated, if enabled, after every set of four or eight conversions (user

selectable).

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

51 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

8.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any

combination of the eight input channels can be selected for conversion. After each

channel is converted, an interrupt is generated, if enabled, and the ADC waits for the next

start condition. May be used with any of the start modes.

8.5 Conversion start modes

8.5.1 Timer triggered start

The ADC is started by the overﬂow of Timer 0. Once a conversion has started, additional

Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start

mode is available in all ADC operating modes.

8.5.2 Start immediately

Programming this mode immediately starts a conversion.This start mode is available in all

ADC operating modes.

8.5.3 Edge triggered

The ADC is started by rising or falling edge of P1.4. Once a conversion has started,

additional edge triggers are ignored until the conversion has completed. The edge

triggered start mode is available in all ADC operating modes.

8.6 Boundary limits interrupt

The ADC has both a high and low boundary limit register. The user may select whether an

interrupt is generated when the conversion result is within (or equal to) the high and low

boundary limits or when the conversion result is outside the boundary limits. An interrupt

will be generated, if enabled, if the result meets the selected interrupt criteria. The

boundary limit may be disabled by clearing the boundary limit interrupt enable.

An early detection mechanism exists when the interrupt criteria has been selected to be

outside the boundary limits. In this case, after the four MSBs have been converted, these

four bits are compared with the four MSBs of the boundary high and low registers. If the

four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)

an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt

criteria, the boundary limits will again be compared after all 8 MSBs have been converted.

A boundary status register (BNDSTA0) ﬂags the channels which caused a boundary

interrupt.

8.7 Clock divider

The ADC requires that its internal clock source be in the range of 500 kHz to 3 MHz to

maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is

provided for this purpose.

8.8 Power-down and Idle mode

In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit

Idle mode when the conversion is completed if the ADC interrupt is enabled. In

Power-down mode or Total Power-down mode, the ADC does not function. If the ADC is

enabled, it will consume power. Power can be reduced by disabling the ADC.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

52 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

9. Limiting values

Table 11: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). ^[1]

Symbol

T_amb(bias)

T_stg

Parameter

Conditions

Min

−55

−65

Max

+125

+150

Unit

°C

bias ambient temperature

storage temperature

°C

I_OH(I/O)

HIGH-state output current per

input/output pin

I_OL(I/O)

LOW-state output current per

input/output pin

I_I/Otot(max)

V_n

maximum total input/output current

voltage on any other pin

100

3.5

except V_SS, with respect to

V_DD

P_tot(pack)

total power dissipation (per package) based on package heat

transfer, not device power

1.5

consumption

[1] The following applies to Table 11:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

10. Static characteristics

Table 12: Static electrical characteristics

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ ^[1]

Max

Unit

µA

[2]

I_DD(oper)

I_DD(idle)

I_DD(pd)

operating supply current

V_DD= 3.6 V; f_osc= 12 MHz

V_DD= 3.6 V; f_osc= 18 MHz

3.6 V; 12 MHz

Idle mode supply current

3.7

3.6 V; 18 MHz

Power-down mode supply

current

voltage comparators

powered down;

_DD= 3.6 V

[3]

I_DD(tpd)

total Power-down mode supply V_DD= 3.6 V

current

µA

(dV/dt)_r

(dV/dt)_f

V_DDR

V_th(HL)

V_IL

rise rate

of V_DD

mV/µs

fall rate

mV/µs

data retention supply voltage

HIGH-LOW threshold voltage

LOW-state input voltage

LOW-HIGH threshold voltage

HIGH-state input voltage

hysteresis voltage

1.5

except SCL, SDA

SCL, SDA only

except SCL, SDA

SCL, SDA only

port 1

0.22V_DD

0.4V_DD

−0.5

+0.3V_DD

0.7V_DD

5.5

V_th(LH)

V_IH

0.6V_DD

0.7V_DD

V_hys

0.2V_DD

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

53 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

Table 12: Static electrical characteristics …continued

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol

V_OL

Parameter

Conditions

Min

Typ ^[1]

Max

Unit

[4]

LOW-state output voltage

I_OL= 20 mA;

0.6

1.0

_DD= 2.4 V to 3.6 V,

all ports, all modes except

high-Z

[4]

_OL= 3.2 mA; V_DD= 2.4 V

0.2

0.3

to 3.6 V; all ports; all

modes except high-Z

V_OH

HIGH-state output voltage

I_OH= −20 µA;

all ports;

quasi-bidirectional mode

_DD− 0.3

_DD− 0.2 -

_DD= 2.4 V to 3.6 V;

I_OH= −3.2 mA;

_DD− 0.7

_DD− 0.4 -

_DD= 2.4 V to 3.6 V;

all ports; push-pull mode

V_xtal

V_n

crystal voltage

with respect to V_SS

−0.5

+4.0

voltage on any other pin

except XTAL1, XTAL2, V_DD

with respect to V_SS

;

+5.5

[5]

[6]

[7]

[8]

C_i

input capacitance

µA

kΩ

I_IL

LOW-state input current

input leakage current

HIGH-LOW transition current

V_I= 0.4 V

−80

±10

−450

I_LI

V_I= V_ILor V_IH

I_THL

V_I= 1.5 V at V_DD= 3.6 V

−30

R_{RST_N(int)}internal pull-up resistance on

pin RST_N

V_bo

brownout trip voltage

2.4 V < V_DD< 3.6 V; with

BOE = 1, BOPD = 0

2.40

2.70

V_ref(bg)

TC_bg

band gap reference voltage

1.11

1.23

1.34

band gap temperature

coefﬁcient

ppm/°C

[1] Typical ratings are not guaranteed. The values listed are at room temperature, V_DD= 3 V.

[2] The I_DD(oper), I_DD(idle), and I_DD(pd)speciﬁcations are measured using an external clock with the following functions disabled: comparators,

real-time clock, and watchdog timer.

[3] The I_DD(tpd)speciﬁcation is measured using an external clock with the following functions disabled: comparators, real-time clock,

brownout detect, and watchdog timer.

[4] See Section 9 “Limiting values” on page 53 for steady state (non-transient) limits on I_OLor I_OH. If I_OL/I_OHexceeds the test condition,

V_OL/V_OHmay exceed the related speciﬁcation.

[5] Pin capacitance is characterized but not tested.

[6] Measured with port in quasi-bidirectional mode.

[7] Measured with port in high-impedance mode.

[8] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is

highest when V_Iis approximately 2 V.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

54 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

11. Dynamic characteristics

Table 13: Dynamic characteristics (12 MHz)

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed. ^{[1] [2]}

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz Unit

Min Max

7.189 7.557 MHz

Min

Max

7.557

520

f_osc(RC)

f_osc(WD)

f_osc

internal RC oscillator frequency

internal watchdog oscillator frequency

oscillator frequency

7.189

320

520 kHz

MHz

T_cy(clk)

f_CLKLP

Glitch ﬁlter

t_gr

clock cycle time

see Figure 23

P1.5/RST pin

low-power select clock frequency

MHz

glitch rejection time

any pin except

P1.5/RST

t_sa

signal acceptance time

P1.5/RST pin

125

any pin except

P1.5/RST

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

clock HIGH time

see Figure 23

_cy(clk)− t_CLCX

clock LOW time

clock rise time

clock fall time

_cy(clk)− t_CHCX

Shift register (UART mode 0)

T_XLXLserial port clock cycle time

t_QVXH

see Figure 22

16T_cy(clk)

13T_cy(clk)

1333

1083

output data setup to clock rising edge see Figure 22

time

t_XHQX

t_XHDX

t_XHDV

output data hold after clock rising

edge time

see Figure 22

T_cy(clk)+ 20

103 ns

input data hold after clock rising edge see Figure 22

time

input data valid to clock rising edge

time

see Figure 22

150

SPI interface

f_SPI

SPI operating frequency

CCLK

slave

⁄

2.0 MHz

3.0 MHz

CCLK

master

⁄

T_SPICYC

SPI cycle time

slave

seeFigure 24,

25, 26, 27

⁄

500

333

CCLK

master

⁄

CCLK

t_SPILEAD

SPI enable lead time

slave

seeFigure 26,

250

t_SPILAG

SPI enable lag time

slave

seeFigure 26,

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

55 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

Table 13: Dynamic characteristics (12 MHz) …continued

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed. ^{[1] [2]}

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz Unit

Min

Max

Min

Max

t_SPICLKH

SPICLK HIGH time

master

seeFigure 24,

25, 26, 27

⁄

165

250

CCLK

slave

t_SPICLKL

SPICLK LOW time

master

seeFigure 24,

25, 26, 27

⁄

165

250

100

CCLK

slave

t_SPIDSU

t_SPIDH

t_SPIA

SPI data setup time

seeFigure 24,

25, 26, 27

100

SPI data hold time

seeFigure 24,

25, 26, 27

100

SPI access time

seeFigure 26,

slave

120

240

120 ns

240 ns

t_SPIDIS

SPI disable time

seeFigure 26,

slave

t_SPIDV

SPI enable to output data valid time

seeFigure 24,

25, 26, 27

slave

240

167

240 ns

167 ns

master

t_SPIOH

t_SPIR

SPI output data hold time

seeFigure 24,

25, 26, 27

SPI rise time

seeFigure 24,

25, 26, 27

SPI outputs

100

100 ns

2000 ns

(SPICLK, MOSI, MISO)

SPI inputs (SPICLK, MOSI, MISO)

SPI fall time

2000

t_SPIF

seeFigure 24,

25, 26, 27

SPI outputs

(SPICLK, MOSI, MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK, MOSI, MISO)

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

56 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

Table 14: Dynamic characteristics (18 MHz)

V_DD= 3.0 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed. ^{[1] [2]}

Symbol

Parameter

Conditions

Variable clock

f_osc= 18 MHz Unit

Min Max

7.189 7.557 MHz

Min

Max

7.557

520

f_osc(RC)

f_osc(WD)

f_osc

internal RC oscillator frequency

internal watchdog oscillator frequency

oscillator frequency

7.189

320

520 kHz

MHz

T_cy(clk)

f_CLKLP

Glitch ﬁlter

t_gr

clock cycle time

see Figure 23

P1.5/RST pin

low-power select clock frequency

MHz

glitch rejection time

any pin except

P1.5/RST

t_sa

signal acceptance time

P1.5/RST pin

125

any pin except

P1.5/RST

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

clock HIGH time

see Figure 23

_cy(clk)− t_CLCX

clock LOW time

clock rise time

clock fall time

_cy(clk)− t_CHCX

Shift register (UART mode 0)

T_XLXLserial port clock cycle time

t_QVXH

see Figure 22

16T_cy(clk)

13T_cy(clk)

888

722

output data setup to clock rising edge see Figure 22

time

t_XHQX

t_XHDX

t_XHDV

output data hold after clock rising

edge time

see Figure 22

T_cy(clk)+ 20

input data hold after clock rising edge see Figure 22

time

input data valid to clock rising edge

time

see Figure 22

150

SPI interface

f_SPI

SPI operating frequency

CCLK

slave

⁄

3.0 MHz

4.5 MHz

CCLK

master

⁄

T_SPICYC

SPI cycle time

slave

seeFigure 24,

25, 26, 27

⁄

333

222

CCLK

master

⁄

CCLK

t_SPILEAD

SPI enable lead time

slave

seeFigure 26,

250

t_SPILAG

SPI enable lag time

slave

seeFigure 26,

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

57 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

Table 14: Dynamic characteristics (18 MHz) …continued

V_DD= 3.0 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed. ^{[1] [2]}

Symbol

Parameter

Conditions

Variable clock

f_osc= 18 MHz Unit

Min

Max

Min

Max

t_SPICLKH

SPICLK HIGH time

master

seeFigure 24,

25, 26, 27

⁄

111

167

CCLK

slave

t_SPICLKL

SPICLK LOW time

master

seeFigure 24,

25, 26, 27

⁄

111

167

100

CCLK

slave

t_SPIDSU

t_SPIDH

t_SPIA

SPI data setup time

seeFigure 24,

25, 26, 27

100

SPI data hold time

seeFigure 24,

25, 26, 27

100

SPI access time

seeFigure 26,

slave

t_SPIDIS

SPI disable time

seeFigure 26,

slave

160

160 ns

t_SPIDV

SPI enable to output data valid time

seeFigure 24,

25, 26, 27

slave

160

111

160 ns

111 ns

master

t_SPIOH

t_SPIR

SPI output data hold time

seeFigure 24,

25, 26, 27

SPI rise time

seeFigure 24,

25, 26, 27

SPI outputs (SPICLK, MOSI,

MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK, MOSI, MISO,

SS)

2000

t_SPIF

SPI fall time

seeFigure 24,

25, 26, 27

SPI outputs (SPICLK, MOSI,

MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK, MOSI, MISO)

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

58 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

11.1 Waveforms

XLXL

clock

XHQX

QVXH

output data

write to SBUF

input data

XHDX

set TI

valid

XHDV

valid

clear RI

set RI

002aaa906

Fig 22. Shift register mode timing

− 0.5 V

0.2V

+ 0.9 V

0.2V

− 0.1 V

0.45 V

CHCX

CHCL

CLCX

CLCH

cy(clk)

002aaa907

Fig 23. External clock timing

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

59 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

SPICYC

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPIF

SPIR

SPICLKL

SPICLKH

SPICLK

(CPOL = 1)

(output)

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIR

SPIDV

SPIOH

SPIDV

MOSI

SPIF

(output)

master MSB/LSB out

master LSB/MSB out

002aaa908

Fig 24. SPI master timing (CPHA = 0)

SPICYC

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(output)

SPICLKH

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIDV

SPIOH

SPIDV

SPIF

SPIR

MOSI

(output)

master MSB/LSB out

master LSB/MSB out

002aaa909

Fig 25. SPI master timing (CPHA = 1)

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

60 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

SPIR

SPICYC

SPIR

SPIF

SPILEAD

SPILAG

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(input)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(input)

SPICLKH

SPIOH

SPIDIS

SPIOH

SPIA

SPIDV

MISO

(output)

slave MSB/LSB out

slave LSB/MSB out

not defined

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa910

Fig 26. SPI slave timing (CPHA = 0)

SPIR

SPICYC

SPIR

SPIF

SPILAG

SPILEAD

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(input)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(input)

SPICLKH

SPIOH

SPIDIS

SPIDV

SPIA

MISO

(output)

slave LSB/MSB out

slave MSB/LSB out

not defined

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa911

Fig 27. SPI slave timing (CPHA = 1)

P89LPC9408_1

Product data sheet

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61 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

11.2 ISP entry mode

Table 15: Dynamic characteristics, ISP entry mode

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

µs

t_VR

t_RH

t_RL

V_DDactive to RST active delay time

RST HIGH time

µs

RST LOW time

µs

RST

002aaa912

Fig 28. ISP entry waveform

12. Other characteristics

12.1 Comparator electrical characteristics

Table 16: Comparator electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IO

input offset voltage

±20

V_IC

common-mode input voltage

common-mode rejection ratio

total response time

V_DD− 0.3

[1]

CMRR

t_res(tot)

t_(CE-OV)

I_LI

−50

500

250

chip enable to output valid time

input leakage current

µs

0 V < V_I< V_DD

±10

µA

[1] This parameter is characterized, but not tested in production.

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

62 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

13. ADC electrical characteristics

Table 17: ADC electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

All limits valid for an external source impedance of less than 10 kΩ.

Symbol

V_IA

Parameter

Conditions

Min

Typ

Max

V_SS+ 0.2

Unit

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

V_SS− 0.2

C_ia

E_D

±1

LSB

INL

±1

E_offset

E_G

±2

gain error

±1

E_u(tot)

M_CTC

α_ct(port)

SR_in

T_cy(ADC)

t_ADC

total unadjusted error

channel-to-channel matching

crosstalk between port inputs

input slew rate

±2

LSB

±1

0 kHz to 100 kHz

ADC enabled

−60

100

3125

V/ms

ADC clock cycle time

ADC conversion time

111

36T_cy(ADC)µs

P89LPC9408_1

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P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

14. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 14 x 14 x 1.4 mm

SOT791-1

(A )

w M

pin 1 index

detail X

w M

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.45 0.20 14.1 14.1

0.30 0.09 13.9 13.9

16.15 16.15

15.85 15.85

0.75

0.45

1.2

0.8

1.2

0.8

1.6

0.25

0.8

0.2

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-22

SOT791-1

136E18

MS-026

ED-7311EC

Fig 29. Package outline SOT791-1 (LQFP64)

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

64 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

15. Abbreviations

Table 18: Acronym list

Acronym

ADC

Description

Analog to Digital Converter

Central Processing Unit

CPU

EPROM

EEPROM

EMI

Erasable Programmable Read-Only Memory

Electrically Erasable Programmable Read-Only Memory

Electro-Magnetic Interference

In-System Programming

ISP

LCD

Liquid Crystal Display

LED

Light Emitting Diode

PWM

RAM

Pulse Width Modulator

Random Access Memory

Resistance-Capacitance

SFR

Special Function Register

SPI

Serial Peripheral Interface

UART

Universal Asynchronous Receiver/Transmitter

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

65 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

16. Revision history

Table 19: Revision history

Document ID

Release date Data sheet status

20051216 Product data sheet

Change notice Doc. number

Supersedes

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

66 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

17. Data sheet status

Level Data sheet status^[1]Product status^{[2] [3]}

Deﬁnition

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

18. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

makes no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

20. Trademarks

Notice — All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.

19. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

21. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

67 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

22. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.16.1

7.17

Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Timers/counters 0 and 1 . . . . . . . . . . . . . . . . 28

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Timer overﬂow toggle output . . . . . . . . . . . . . 29

RTC/system timer. . . . . . . . . . . . . . . . . . . . . . 29

CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

CCU Clock (CCUCLK) . . . . . . . . . . . . . . . . . . 30

CCU clock prescaling. . . . . . . . . . . . . . . . . . . 30

Basic timer operation . . . . . . . . . . . . . . . . . . . 30

Output compare . . . . . . . . . . . . . . . . . . . . . . . 30

Input capture . . . . . . . . . . . . . . . . . . . . . . . . . 30

PWM operation . . . . . . . . . . . . . . . . . . . . . . . 30

Alternating output mode. . . . . . . . . . . . . . . . . 32

PLL operation. . . . . . . . . . . . . . . . . . . . . . . . . 32

CCU interrupts . . . . . . . . . . . . . . . . . . . . . . . . 33

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Baud rate generator and selection. . . . . . . . . 34

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 34

Break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 34

Double buffering. . . . . . . . . . . . . . . . . . . . . . . 35

Transmit interrupts with double buffering

2.1

2.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Principal features . . . . . . . . . . . . . . . . . . . . . . . 1

Additional features . . . . . . . . . . . . . . . . . . . . . . 1

7.17.1

7.17.2

7.17.3

7.17.4

7.17.5

7.17.6

7.18

3.1

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

7.19

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.19.1

7.19.2

7.19.3

7.19.4

7.19.5

7.19.6

7.19.7

7.19.8

7.19.9

7.20

7.20.1

7.20.2

7.20.3

7.20.4

7.20.5

7.20.6

7.20.7

7.20.8

7.20.9

7.1

7.2

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.4

Functional description . . . . . . . . . . . . . . . . . . 10

Special function registers . . . . . . . . . . . . . . . . 10

Enhanced CPU. . . . . . . . . . . . . . . . . . . . . . . . 19

Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Clock deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . 19

CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 19

Low speed oscillator option . . . . . . . . . . . . . . 19

Medium speed oscillator option . . . . . . . . . . . 19

High speed oscillator option . . . . . . . . . . . . . . 19

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 20

On-chip RC oscillator option. . . . . . . . . . . . . . 20

Watchdog oscillator option . . . . . . . . . . . . . . . 20

External clock input option . . . . . . . . . . . . . . . 20

CPU Clock (CCLK) wake-up delay . . . . . . . . . 21

CCLK modiﬁcation: DIVM register . . . . . . . . . 21

Low power select . . . . . . . . . . . . . . . . . . . . . . 21

Memory organization . . . . . . . . . . . . . . . . . . . 22

Data RAM arrangement . . . . . . . . . . . . . . . . . 22

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

External interrupt inputs . . . . . . . . . . . . . . . . . 23

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Port conﬁgurations . . . . . . . . . . . . . . . . . . . . . 25

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.12.1

7.13

7.13.1

enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . 35

7.20.10 The 9^thbit (bit 8) in double buffering

(modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . . . 35

7.21

7.22

7.22.1

7.23

7.23.1

7.23.2

7.23.3

7.24

7.25

7.26

7.26.1

7.26.2

7.27

7.27.1

7.27.2

7.27.3

I²C-bus serial interface. . . . . . . . . . . . . . . . . . 35

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Typical SPI conﬁgurations . . . . . . . . . . . . . . . 39

Analog comparators. . . . . . . . . . . . . . . . . . . . 40

Internal reference voltage. . . . . . . . . . . . . . . . 41

Comparator interrupt . . . . . . . . . . . . . . . . . . . 41

Comparators and power reduction modes . . . 41

Keypad Interrupt (KBI) . . . . . . . . . . . . . . . . . . 42

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 42

Additional features . . . . . . . . . . . . . . . . . . . . . 43

Software reset . . . . . . . . . . . . . . . . . . . . . . . . 43

Dual data pointers . . . . . . . . . . . . . . . . . . . . . 43

LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 43

General description . . . . . . . . . . . . . . . . . . . . 43

Functional description . . . . . . . . . . . . . . . . . . 44

LCD bias voltages . . . . . . . . . . . . . . . . . . . . . 44

7.13.1.1 Quasi-bidirectional output conﬁguration . . . . . 25

7.13.1.2 Open-drain output conﬁguration . . . . . . . . . . . 25

7.13.1.3 Input-only conﬁguration . . . . . . . . . . . . . . . . . 25

7.13.1.4 Push-pull output conﬁguration . . . . . . . . . . . . 26

7.13.2

7.13.3

7.14

7.14.1

7.14.2

7.15

7.15.1

7.15.2

7.15.3

7.16

Port 0 analog functions. . . . . . . . . . . . . . . . . . 26

Additional port features. . . . . . . . . . . . . . . . . . 26

Power monitoring functions. . . . . . . . . . . . . . . 26

Brownout detection. . . . . . . . . . . . . . . . . . . . . 26

Power-on detection. . . . . . . . . . . . . . . . . . . . . 27

Power reduction modes . . . . . . . . . . . . . . . . . 27

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Power-down mode . . . . . . . . . . . . . . . . . . . . . 27

Total Power-down mode . . . . . . . . . . . . . . . . . 27

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

continued >>

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

68 of 69

P89LPC9408

Philips Semiconductors

8-bit two-clock 80C51 core with 32 segment × 4 LCD driver, 10-bit ADC

7.27.4

7.27.5

7.27.6

7.27.7

7.27.8

7.27.9

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.1

Other characteristics . . . . . . . . . . . . . . . . . . . 62

Comparator electrical characteristics. . . . . . . 62

ADC electrical characteristics . . . . . . . . . . . . 63

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 64

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 65

Revision history . . . . . . . . . . . . . . . . . . . . . . . 66

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 67

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Contact information . . . . . . . . . . . . . . . . . . . . 67

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Display register. . . . . . . . . . . . . . . . . . . . . . . . 44

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 45

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 45

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.27.10 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.27.11 Output bank selector. . . . . . . . . . . . . . . . . . . . 45

7.27.12 Input bank selector . . . . . . . . . . . . . . . . . . . . . 45

7.27.13 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.27.13.1 I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 46

7.27.14 Input ﬁlters . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.27.15 I²C-bus slave addresses. . . . . . . . . . . . . . . . . 46

7.28

7.29

Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . 46

Flash program memory. . . . . . . . . . . . . . . . . . 47

General description. . . . . . . . . . . . . . . . . . . . . 47

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Flash organization . . . . . . . . . . . . . . . . . . . . . 47

Using ﬂash as data storage . . . . . . . . . . . . . . 47

Flash programming and erasing. . . . . . . . . . . 48

In-Circuit Programming. . . . . . . . . . . . . . . . . . 48

In-Application Programming . . . . . . . . . . . . . . 48

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Power-on reset code execution. . . . . . . . . . . . 49

7.29.1

7.29.2

7.29.3

7.29.4

7.29.5

7.29.6

7.29.7

7.29.8

7.29.9

7.29.10 Hardware activation of the boot loader. . . . . . 49

7.30

7.31

User conﬁguration bytes. . . . . . . . . . . . . . . . . 49

User sector security bytes . . . . . . . . . . . . . . . 49

8.1

8.2

8.3

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

General description. . . . . . . . . . . . . . . . . . . . . 50

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 50

ADC operating modes . . . . . . . . . . . . . . . . . . 51

Fixed channel, single conversion mode . . . . . 51

Fixed channel, continuous conversion mode . 51

Auto scan, single conversion mode . . . . . . . . 51

Auto scan, continuous conversion mode . . . . 51

Dual channel, continuous conversion mode . . 51

Single step mode . . . . . . . . . . . . . . . . . . . . . . 52

Conversion start modes . . . . . . . . . . . . . . . . . 52

Timer triggered start . . . . . . . . . . . . . . . . . . . . 52

Start immediately . . . . . . . . . . . . . . . . . . . . . . 52

Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 52

Boundary limits interrupt. . . . . . . . . . . . . . . . . 52

Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Power-down and Idle mode . . . . . . . . . . . . . . 52

8.4

8.4.1

8.4.2

8.4.3

8.4.4

8.4.5

8.4.6

8.5

8.5.1

8.5.2

8.5.3

8.6

8.7

8.8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 53

Static characteristics. . . . . . . . . . . . . . . . . . . . 53

11.1

11.2

Dynamic characteristics . . . . . . . . . . . . . . . . . 55

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . 62

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 16 December 2005

Document number: P89LPC9408_1

Published in the Netherlands

P89LPC9408FBD [NXP]

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