PC33701DWB_技术文档

Freescale Semiconductor, Inc.

Order this document from Analog Marketing: MC33701/D

MOTOROLA

Rev 1.0, 05/2003

SEMICONDUCTOR TECHNICAL DATA

Preliminary Information

33701

1.5 A Switch-Mode Power Supply

with Linear Regulator

The 33701 provides the means to efficiently supply the Power QUICC™ I,

II, and other families of Motorola microprocessors and DSPs. The 33701

incorporates a high-performance switching regulator, providing the direct

supply for the microprocessor’s core, and a low dropout (LDO) linear regulator

control circuit providing the microprocessor I/O and bus voltage.

POWER SUPPLY

INTEGRATED CIRCUIT

The switching regulator is a high-efficiency synchronous buck regulator with

integrated 50 mΩ N-channel power MOSFETs to provide protection features

and to allow space-efficient, compact design.

The 33701 incorporates many advanced features; e.g., precisely

maintained up/down power sequencing, ensuring the proper operation and

protection of the CPU and power system.

Features

• Operating Voltage: 2.8 V to 6.0 V

• High-Accuracy Output Voltages

• Fast Transient Response

• Switcher Output Current Up to 1.5 A

• Undervoltage Lockout

DWB SUFFIX

CASE 1324-02

32-LEAD SOICW

ORDERING INFORMATION

Temperature

• Power Sequencing

• Programmable Watchdog Timer

Package

32 SOICW

Device

Range (T )

A

• Voltage Margining via I²C™ Bus

• Overcurrent Protection

PC33701DWB/R2

-40 to 85°C

• Reset with Programmable Power-ON Delay

• Enable Inputs

I²C is a trademark of Phillips Corporation.

33701 Simplified Application Diagram

2.8 V to 6.0 V

2.8 V to 1 3. 5 V In put

M

3

C

3

7

3

0

703

V

VIN1

IN1

1

V

IN2

VIN2

Other

Circuits

V

VBD

BD

V

BST

LDRV

CS

V

=

LDO

0.8 to 5.0 V

SR

RT

(Adjustable)

LDO

LFB

VDDH (I/Os)

ADDR

MPC8XXX

MPC85xx

SDA

SCL

RESET

BOOT

PORESET

GND

V

=

OUT

VBST

0.8 to 5.0 V

(Adjustable)

EN1

EN2

SW

VDDL (Core)

V

VOUT

OUT

CLKSYN

CLKSEL

FREQ

PGND

INV

Optional

This document contains information on a product under development.

Motorola reserves the right to change or discontinue this product without notice.

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V

V^II^NN¹1

VVIN

IN

V_DDI

VDDI

V

VDDDDII

Internal

Supply

V

VDDI

DDI

V_BST

VBST

8.0V

V

V_BB_SS_TT

V

VBST

BST

Power

LDRV

-

+

Enable

Vref

V_DDI

CS

VDDI

Linear

Regulator

Control

LDO

V

VBD

BD

Boost

Bandgap

Voltage

Vref

Control

Vref

I

I-lim

LIM

Reference

LFB

Vref

V_DDI

VDDI

EN1

V_LDO

LCMP

Pow. Seq.

PWR Seq.

VLDO

Q4

Power

EN2

Power

Sequencing

Down

V

VBST

BST

UVLO

RESET

Voltage Margining

Reset

V_OUT

Reset

VOUT

BOOT

V_BST

Control

VBST

W-dog Timer

Watchdog Timer

Current

Limit

SysCon

INV

POR

V_IN2

VIN2

RT

Timer

2

I C

V_DDI

(2)

VDDI

LFB

Control

Buck

HS

Q1

Q2

2

I C

&

SysCon

SoftSt

Control

LS

Thermal

Limit

Buck

Control

Logic

SW

(2)

Driver

ADDR

SDA

2

I C

PGND

Interface

(2)

Error

Amp.

PWM

To Reset

Control

0.8V

+

-

Switcher

Comp.

SCL

Oscillator

300kHz

+

-

INV

V

VOUT

OUT

Slope

Comp.

V

VOUT

OUT

Q3

Pow.

PWR Seq.

Seq.

(4)

CLKSYN

CLKSEL

FREQ

PGND

Figure 1. 33701 Simplified Block Diagram

33701

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FREQ

INV

CLKSYN

CLKSEL

RESET

RT

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V

OUT

V

IN2

V

EN2

IN2

SW

EN1

ADDR

GND

PGND

V_BD

9

GND

10

11

12

13

14

15

16

V

DD1

IN1

LDRV

CS

V_BST

BOOT

SDA

LDO

LFB

SCL

LCMP

PIN FUNCTION DESCRIPTION

Pin Name

Formal Name

Definition

This selection switcher pin can be adjusted by connecting external resistor R to the

1

FREQ

Oscillator Frequency

F

FREQ pin. The default switching frequency (FREQ pin left open or tied to V ) is set

DDI

to 300 kHz.

2

3

Inverting Input

Output Voltage

Buck Controller Error Amplifier inverting input.

INV

Output voltage of the buck converter. Input pin of the switching regulator power

sequence control circuit.

V

OUT

4, 5

6, 7

Input Voltage 2

Buck regulator power input. Drain of the high-side power MOSFET.

V

IN2

SW

Switch

Buck regulator switching node. This pin is connected to the inductor.

Analog ground of the IC, thermal heatsinking.

8, 9

24, 25

Ground

GND

10, 11

12

PGND

Power Ground

Boost Drain

Buck regulator power ground.

V

Drain of the internal boost regulator power MOSFET.

BD

13

Boost Voltage

Internal boost regulator output voltage. The internal boost regulator provides a 20 mA

output current to supply the drive circuits for the integrated power MOSFETs and the

V

BST

external N-channel power MOSFET of the linear regulator. The voltage at the V

is 8.0 V nominal.

BST

14

15

BOOT

SDA

Bootstrap

Bootstrap capacitor input.

I²C bus pin. Serial data.

Serial Data

I²C bus pin. Serial clock.

16

Serial Clock

SCL

17

18

19

20

Linear Compensation

Linear Feedback

Linear Regulator

Current Sense

Linear regulator compensation pin.

Linear regulator feedback pin.

LCMP

LFB

LDO

CS

Input pin of the linear regulator power sequence control circuit.

Current sense pin of the LDO. Overcurrent protection of the linear regulator external

power MOSFET. The voltage drop over the LDO current sense resistor R is sensed

S

between the CS and LDO pins. The LDO current limit can be adjusted by selecting the

proper value of the current sensing resistor R .

S

21

22

Linear Drive

LDO gate drive of the external pass N-channel MOSFET.

LDRV

V

Input Voltage 1

The input supply pin for the integrated circuit. The internal circuits of the IC are supplied

through this pin.

IN1

33701

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PIN FUNCTION DESCRIPTION (continued)

Pin Name

Formal Name

Definition

23

V

Power Supply

Internal supply voltage.

DDI

I²C address selection. This pin can be either left open, tied to V , or grounded through

26

ADDR

Address

DDI

a 10 kΩ resistor.

27

28

29

30

EN1

EN2

Enable 1

Enable 2

Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs

determine operation mode and type of power sequencing of the IC.

Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs

determine operation mode and type of power sequencing of the IC.

RT

Reset Timer

Reset Overbar

This pin allows programming the Power-ON Reset delay by means of an external RC

network.

The Reset Control circuit monitors both the switching regulator and the LDO feedback

voltages. It is an open drain output and has to be pulled up to some supply voltage (e.g.,

the output of the LDO) by an external resistor.

RESET

31

32

CLKSEL

CLKSYN

Clock Selection

This pin sets the CLKSYN pin either as an oscillator output or synchronization input pin.

The CLKSEL pin is also used for the I²C address selection.

Clock Synchronization

Oscillator output/synchronization input pin.

33701

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MAXIMUM RATINGS

All voltages are with respect to ground unless otherwise noted.

Rating

Symbol

Value

Unit

Supply Voltage

V

, V

-0.3 to 7.0

V

IN1 IN2

Switching Node

SW

-1.0 to 7.0

-0.3 to 8.5

V

Buck Regulator Bootstrap Input (BOOT - SW)

Boost Regulator Output

BOOT

V

BST

Boost Regulator Drain

V

-0.3 to 9.5

V

BD

-0.3 to 7.0

V

RESET

RESET Drain Voltage

–

Enable Pins (EN1, EN2)

Logic Pins (SDA, SCL, CLKSYN)

Analog Pins (INV, V

, RESET)

OUT

–

Analog Pins (LDRV LFB, LDO, LCMP, CS)

,

-0.3 to 8.5

-0.3 to 3.6

V

Analog Pins (CLKSEL, ADDR, RT, FREQ, V

)

DDI

ESD Voltage

V

Human Body Model (Note 1)

Machine Model (Note 2)

±2000

±200

ESD1

V

ESD2

Storage Temperature

T

-65 to 150

TBD

260

°C

W

STG

Power Dissipation (T = 85°C) (Note 3)

A

P

D

Lead Soldering Temperature (Note 4)

Maximum Junction Temperature

T

°C

SOLDER

T

125

°C

JMAX

Thermal Resistance, Junction to Ambient (Note 5)

Thermal Resistance, Junction to Base (Note 6)

OPERATING CONDITIONS

R

68

°C/W

θJA

θJB

R

18

Supply Voltage (V , V

)

V

, V

2.8 to 6.0

-40 to 85

V

IN1 IN2

Operational Package Temperature (Ambient Temperature)

T

°C

A

Notes

1. ESD1 testing is performed in accordance with the Human Body Model (C

=100 pF, R

=1500 Ω).

ZAP

2. ESD2 testing is performed in accordance with the Machine Model (C

3. Maximum power dissipation at indicated junction temperature.

=200 pF, R

=0 Ω).

ZAP

4. Lead soldering temperature limit is for 10 seconds maximum duration. Contact Motorola Sales Office for device immersion soldering time/

temperature limits.

5. Thermal resistance measured in accordance with EIA/JESD51-2.

6. Theoretical thermal resistance from the die junction to the exposed pins.

33701

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STATIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions -40°C ≤ T_J≤ 125°C unless otherwise noted. Input voltages V_IN1= V_IN2= 3.3 V using the typical

application circuit (see Figure 20) unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

GENERAL

V

2.8

–

1.6

6.0

60

6.0

1.8

–

V

Operating Voltage Range (V , V

)

IN

IN1 IN2

V

Start-Up Voltage Threshold (Boost Switching)

Undervoltage Lockout

ST

V

–

V

BST_UVLO

BST

I

–

mA

µA

V

Input DC Supply Current (Normal Operation Mode, Enabled)

IN

I

–

9.0

TBD

–

V

Pin Input Supply Current (EN1 = EN2 = 0)

Pin Input Leakage Current (EN1 = EN2 = 0)

Internal Supply Voltage

IN1

IN2

DDI

I

–

IN2

V

3.0

–

3.3

–

DDI

I

TBD

µA

Maximum Output Current

DDI

BUCK CONVERTER

V

Buck Converter Output Voltage Range

OUT

0.8

–

5.0

I

= 15 mA to 1.5 A, V

= V

= 2.8 V to 6.0 V

VOUT

IN1

IN2

V

Buck Converter Feedback Voltage

= 15 mA to 1.5 A, V = V

INV

I

= 2.8 V to 6.0 V. No R Resistor.

B

VOUT

IN1

IN2

0.784

–

0.8

1.0

0.816

–

Includes Load Regulation Error

V

%

Buck Converter Voltage Margining Step

MVO

REG

I

Buck Converter Line Regulation

LNVO

-1.0

–

1.0

–

V

= V

= 2.8 V to 6.0 V, I = 1.5 A

VOUT

IN1

IN2

%

Buck Converter Load Regulation

LDVO

I

= 15 mA to 1.5 A

VOUT

µA

V

Input Leakage Current

VOUTLK

OUT

TBD

V

= 5.0 V

OUT

R

mΩ

High-Side Power MOSFET Q1 R

DS(ON)

H_LIM

DS(ON)

–

50

I

= 1.0 A, T = 25°C, V

= 8.0 V

BST

D

A

R

I

Low-Side Power MOSFET Q2 R

DS(ON)

I

= 1.0 A, T = 25°C, V

= 8.0 V

BST

D

A

1.65

2.25

3.0

A

Buck Converter Peak Current Limit (High Level)

Buck Converter Valley Current Limit (Low Level)

I

0.825

1.125

1.45

L_LIM

I

V

Pull-Down MOSFET Q3 Current Limit

Q3_LIM

OUT

–

2.0

–

T

= 25°C, V

= 8.0 V

BST

A

R

Ω

V

Pull-Down MOSFET Q3 R

DS(ON)

OUT

DS(ON)

–

1.0

I

= 1.0 A, T = 25°C, V

= 8.0 V

BST

D

A

T

150

–

170

15

190

–

°C

Thermal Shutdown (Switcher, V

Thermal Shutdown Hysteresis

FET)

SD

OUT

T

SDHys

33701

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STATIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions -40°C ≤ T_J≤ 125°C unless otherwise noted. Input voltages V_IN1= V_IN2= 3.3 V using the typical

application circuit (see Figure 20) unless otherwise noted.

Characteristic

ERROR AMPLIFIER (BUCK CONVERTER)

Input Impedance (Note 7)

Symbol

Min

Typ

Max

Unit

R_IN

R_OUT

A_VOL

GBW

SR

–

500

150

80

–

kΩ

Ω

Output Impedance (Note 7)

dB

DC Open Loop Gain (Note 7)

35

MHz

V/µs

V

Gain Bandwidth Product (Note 7)

Slew Rate (Note 7)

200

V_{EA_OH}

Output Voltage Swing – High Level

–

2.0

–

V

> 3.3 V, I

= -1.0 mA (Note 7)

IN1

OEA

V_{EA_OL}

V

Output Voltage Swing – Low Level

= -1.0 mA (Note 7)

–

0.4

0.6

–

I

OEA

V_SCRamp

Slope Compensation Ramp (Note 7)

OSCILLATOR

V_{OSC_OL}

V_{OSC_OH}

V_{OSC_IH}

V_FREQ

–

0.4

–

V

Oscillator Low Level Output Voltage (Pin CLKSYN), CLKSEL Open

Oscillator High Level Output Voltage (Pin CLKSYN), CLKSEL Open

Oscillator Input Voltage Threshold (Pin CLKSYN), CLKSEL Grounded

Oscillator Frequency Adjusting Reference Voltage (FREQ)

Oscillator Frequency Adjusting Resistor Range

BOOST REGULATOR

3.0

1.2

–

1.6

1.29

–

2.0

–

V

R_FREQ

100

200

kΩ

V_BST

V

Boost Regulator Output Voltage

7.5

8.0

8.5

I

= 20 mA, V

= V

= 2.8 V to 6.0 V

BST

IN1

IN2

V_{IN_BSU}

I_{P_BD}

–

1.6

1.0

600

1.8

1.5

800

V

A

Boost Regulator Start-Up Voltage

0.75

450

Boost Regulator Peak Current Limit (Power FET Peak Current)

Boost Regulator Power FET Valley Current Limit (Low Level)

I_{L_BD}

mA

mΩ

R_DS(ON)

Boost Power FET R

DS(ON)

–

150

400

I

= 1.0 A, T = 25°C

A

BD

C_BST

–

10

–

µF

Boost Regulator Recommended Output Capacitor

ESR_CBST

100

mΩ

Boost Regulator Recommended Output Capacitor Maximum ESR

Notes

7. Design information only. It is not production tested.

33701

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STATIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions -40°C ≤ T_J≤ 125°C unless otherwise noted. Input voltages V_IN1= V_IN2= 3.3 V using the typical

application circuit (see Figure 20) unless otherwise noted.

Characteristic

Symbol

V_LDO

Min

Typ

Max

Unit

V

LINEAR REGULATOR (LDO)

LDO Output Voltage Range

= V = 2.8 V to 6.0 V, I = 10 mA to 1000 mA

LDO

0.8

–

5.0

V

IN1

IN2

V_LDO

V

LDO Feedback Voltage, LFB Pin Connected to LDO Pin

= V = 2.8 V to 6.0 V, I = 10 mA to 1000 mA. Includes Load

V

IN1

IN2

LDO

0.784

–

0.8

1.0

0.816

–

Regulation Error

V_MLDO

%

LDO Voltage Margining Step Size

REG_LNVLDO

LDO Line Regulation

-1.0

–

1.0

–

V

= V

= 2.8 V to 6.0 V, I

= 1000 mA

IN1

IN2

LDO

REG_LDVLDO

%

LDO Load Regulation

= 10 mA to 1000 mA

I

LDO

V_{LDO_RR}

dB

LDO Ripple Rejection, Dropout Voltage V

= 1.0 V, V

= +1.0 V p-p

RIPPLE

DO

40

Sinusoidal, f = 300 kHz, I

= 500 mA

LDO

V_DO

V

LDO Maximum Dropout Voltage (V - V

)

IN

LDO

–

TBD

55

V

= 2.5 V, I

= 1000 mA

LDO

V_CSTH

35

45

mV

LDO Current Sense Comparator Threshold Voltage (V - V

CS

)

LDO

I_LDO

I_LFB

1.6

-5.0

2.0

–

2.4

5.0

mA

µA

LDO Pin Input Current

LDO Feedback Input Current (LFB Pin)

LDO Drive Output Current (LDRV Pin)

I_LDRV

3.6

mA

I_DRLIM

I_CSLK

–

3.6

–

mA

LDO Drive Current Limit (LDRV Pin)

CS Pin Input Leakage Current

µA

50

–

300

V

= 5.0 V

CS

R_IN

–

TBD

–

Ω

A

LDO Error Amplifier Input Impedance (LFB Pin)

LDO Error Amplifier Output Impedance (LCMP Pin)

LDO Pull-Down MOSFET Q4 Current Limit

R_OUT

I_{Q4_LIM}

–

-2.0

–

T

= 25°C, V

= 8.0 V (LDO Pin)

A

BST

R_DS(ON)

Ω

LDO Pull-Down MOSFET Q4 R

DS(ON)

= 8.0 V

–

1.0

I

= 1.0 A, T = 25°C, V

A BST

D

C

–

10

TBD

170

15

–

µF

mΩ

°C

LDO Recommended Output Capacitance

LDO Recommended Output Capacitor ESR

Thermal Shutdown (LDO Pull-Down FET Q4)

Thermal Shutdown Hysteresis

LDO

ESR

CLDO

T

150

–

190

–

SD

T

°C

SDHys

33701

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STATIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions -40°C ≤ T_J≤ 125°C unless otherwise noted. Input voltages V_IN1= V_IN2= 3.3 V using the typical

application circuit (see Figure 20) unless otherwise noted.

Characteristic

CONTROL AND SUPERVISORY CIRCUITS

Enable (EN1, EN2) Input Voltage Threshold

Enable (EN1, EN2) Input Voltage Threshold Hysteresis

Enable (EN1, EN2) Pull-Down Resistance

Symbol

Min

Typ

Max

Unit

V_{TH_EN}

V_IHYS

R_PU

1.2

–

1.6

0.1

60

–

2.0

–

V

30

–

120

0.4

kΩ

V

V_OL

RESET Low-Level Output Voltage, I = 5.0 mA

OL

I_LKG-RST

V_OUTITh

–

10

µA

RESET Leakage Current, OFF State, Pulled Up to 5.0 V

-10

-7.5

-5.0

%

RESET Undervoltage Threshold on V

(∆V

/V

(Note 8)

OUT

OUT OUT)

V_OUTITh

V_LDOITh

5.0

-10

5.0

7.5

-7.5

7.5

10

-5.0

10

%

RESET Overvoltage Threshold on V

(∆V

/V

(Note 8)

/V (Note 8)

LDO LDO)

OUT

OUT OUT)

RESET Undervoltage Threshold on V

(∆V

LDO

RESET Overvoltage Threshold on V

(∆V

/V

(Note 8)

LDO

LDO LDO)

V_TH-RT

I_S-RT

I_LKG-RT

V_SAT-RT

TBD

20

-1.0

–

1.2

–

TBD

30

V

mA

µA

mV

µF

V

Reset Timer Voltage Threshold

Reset Timer Source Current

Reset Timer Leakage Current

–

1.0

TBD

47

100

–

Reset Timer Saturation Voltage, Reset Timer Current = 300 µA

Maximum Value of the Reset Timer Capacitor

CLKSEL Threshold Voltage

C

t

–

V

1.2

60

1.2

60

1.6

120

1.6

120

2.0

240

2.0

240

CLKS

th

R_PU-CLKS

V

kΩ

V

CLKSEL Pull-Up Resistance

ADDR Threshold Voltage

ADDR

th

R_PU-ADDR

kΩ

ADDR Pull-Up Resistance

SDA, SCL Pins I²C Bus (STANDARD)

Input Threshold Voltage

V

1.3

–

0.2

–

1.7

–

V

Ith

V_IHYS

I_I

Input Voltage Threshold Hysteresis

SDA, SCL Input Current, Input Voltage = 0.4 V to 6.0 V

SDA Low-Level Output Voltage, 3.0 mA Sink Current

SCA, SCL Capacitance

–

10

0.4

10

µA

V

V_OL

C_I

–

pF

Notes

8. This parameter does not include the tolerance of the external resistor divider.

33701

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DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions -40°C ≤ T_J≤ 125°C unless otherwise noted. Input voltages V_IN1= V_IN2= 3.3 V using the typical

application circuit (see Figure 20) unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

BUCK CONVERTER

Duty Cycle Range (Normal Operation)

D

0

–

90

–

%

Switching Node SW Rise Time (Note 9)

t_RISE

ns

TBD

I

= 1.5 A

LOAD

Switching Node SW Fall Time (Note 9)

= 1.5 A

t_FALL

ns

TBD

I

–

LOAD

Maximum Deadtime (Note 9)

t_D

ns

Buck Control Loop Propagation Delay (Note 9)

t_PD

V

< 0.8 V to V

> 90% of High Level or V

> 0.8 V to V

< 10% of

INV

SW

INV

SW

–

200

–

50

350

10

–

800

–

Low Level

Soft Start Duration (Power Sequencing Disabled, EN1 = 1, EN2 = 1)

Fault Condition Timeout

t_SS

µs

ms

t_FAULT

Retry Timer Cycle

t_R

–

100

–

et

OSCILLATOR

Oscillator Default Frequency (Switching Frequency), FREQ Pin Open

f_OSC

270

200

300

330

400

kHz

Oscillator Frequency Range

Oscillator Frequency Accuracy

R

= 100 kΩ

360

180

400

200

440

220

F

Oscillator Frequency Accuracy

= 200 kΩ

f_OSC

kHz

R

F

Oscillator Output Signal Duty Cycle (Square Wave, 180° Out-of-Phase with the

Internal Suitable Oscillator)

D_OSC

t_SYNC

%

–

50

–

Synchronization Pulse Minimum Duration

300

ns

BOOST REGULATOR

Boost Regulator FET Maximum ON Time

t_ON

–

24

50

–

µs

ns

Boost Regulator Control Loop Propagation Delay (Note 9)

t_{BST_PD}

t_{B_RISE}

Boost Switching Node V Rise Time (Note 9)

BD

–

15

40

I

= 20 mA

BST

Boost Switching Node V Fall Time (Note 9)

t_{B_FALL}

ns

BD

I

= 20 mA

BST

Notes

9. Design Information only. Not production tested.

33701

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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions -40°C ≤ T_J≤ 125°C unless otherwise noted. Input voltages V_IN1= V_IN2= 3.3 V using the typical

application circuit (see Figure 20) unless otherwise noted.

Characteristic

LINEAR REGULATOR (LDO)

Symbol

Min

Typ

Max

Unit

LDO Output Current Slew Rate

Fault Condition Timeout

Retry Timer Cycle

I_SR

–

TBD

1.0

–

mA/µs

ms

t_FAULT

t_R

100

ms

et

SCA, SCL PIN, I²C BUS (STANDARD)

SCL Clock Frequency

f_SCL

t_BUF

0

–

100

–

kHz

µs

4.7

Bus Free Time Between a STOP and a START Condition

t_HD-STA

µs

Hold Time (Repeated) START Condition (After this period, the first clock pulse

is generated.)

4.0

4.7

–

t_LOW

t_HIGH

µs

ns

Low Period of the SCL Clock

High Period of the SCL Clock

4.0

–

t

SDA Fall Time from V

3.0 mA Sink Current

to V

, Bus Capacitance 10 pF to 400 pF,

IL_MIN

F

IH_MAX

–

250

–

t_SU-STA

t_HD-DAT

4.7

µs

Setup Time for a Repeated START Condition

Data Hold Time for I²C bus devices (Note 10), (Note 11)

Data Setup Time

0

–

t_SU-DAT

t_SU-STO

C_B

250

4.0

–

ns

µs

pF

Setup Time for STOP Condition

Capacitive Load for Each Bus Line

400

Notes

10. Design Information only. Not production tested.

11. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the V

region of the falling edge of SCL.

of the SCL signal) to bridge the undefined

IH_MIN

Timing Diagram

t

HD-STA

t

SU-STO

HD-STA

SU-STA

t

SU-DAT

HD-DAT

Figure 2. Definition of Time on the I²C Bus

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Electrical Performance Curves

Figure 3. Buck R_DS(ON)(Temp)

Figure 6. I_LIM(Temp)

Figure 4. F_OSC(R_F)

Figure 7. Vref (Temp)

Figure 5. Buck Efficiency

Figure 8. RT Timer (R , C )

t

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SYSTEM/APPLICATION INFORMATION

INTRODUCTION

The 33701 power supply integrated circuit provides the

This device incorporates many advanced features; e.g.,

precisely maintained up/down power sequencing, ensuring the

proper operation and protection of the CPU and power system.

At the same time, it provides high flexibility of configuration,

allowing the maximum optimization of the power supply system.

means to efficiently supply the Power QUICC and other families

of Motorola microprocessors. It incorporates a high-

performance synchronous buck regulator, supplying the

microprocessor’s core, and a low dropout (LDO) linear regulator

providing the microprocessor I/O and bus voltages.

FUNCTIONAL DESCRIPTION

Thermal Shutdown

Switching Regulator

The switching regulator is a high-frequency (300 kHz default,

adjustable in the range from 200 kHz to 400 kHz), synchronous

buck converter driving integrated high-side and low-side

N-channel power MOSFETs. The switching regulator output

voltage is adjustable by means of an external resistor divider to

provide the required output voltage within plus/minus two

percent accuracy, and it is intended to directly power the core

of the microprocessor. The buck controller utilizes a Sensorless

PWM Current Mode Control topology to achieve excellent line

rejection, stabilize the feedback loop, and provide cycle-by-

cycle current limiting.

To increase the overall safety of the system designed with

the 33701, an internal thermal shutdown function has been

incorporated into the switching regulator circuit. The 33701

senses the temperature of the buck regulator main switching

FET (high-side FET Q1; see Figure 1), the low-side

(synchronous FET Q2), and control circuit. If the temperature of

any of the monitored components exceeds the limit of safe

operation (thermal shutdown), the switching regulator will be

shut down. After the temperature falls below the value given by

the thermal shutdown hysteresis window, the switcher will retry

to operate again.

A typical bootstrap technique is used to provide voltage

necessary to properly enhance the high-side MOSFET gate.

When the regulator is supplied only from low-input voltage

(e.g., single +3.3 V supply rail), the bootstrap capacitor is

charged from the internal boost regulator output V_BSTthrough

The V_OUTpull-down FET Q3 has an independent thermal

shutdown control. When the Q3 temperature exceeds the

thermal shutdown limit, the Q3 will be turned off without

affecting the switcher operation.

an external diode. This arrangement allows the 33701 to

operate from very low input voltage and also comply with the

power sequencing requirements of the supplied

microcontroller.

Soft Start

A switching regulator soft start feature is incorporated in the

33701. The soft start is active each time the IC is enabled, V_IN

is reapplied, or after a fault retry. Other transient events do not

To avoid destruction of the supplied circuits, a current limit

with retry capability was implemented in the switching regulator.

When an overcurrent condition occurs and the switch current

reaches the peak current limit value, the main (high-side) switch

is turned off until the inductor current decays to the valley value,

which is one-half of the peak current limit. If an overcurrent

condition exists for 10 ms, the buck regulator control circuit

shuts the switcher OFF and the switcher retry timer starts to

time out. When the timer expires after 100 ms, the switcher

engages the start-up sequence and runs for 10 ms, repeatedly

checking for the overcurrent condition. During the current

limited operation (e.g., in case of short circuit on the switching

regulator output), the switching regulator operation is not

synchronized to the oscillator frequency.

activate the soft start.

Boost Regulator

A boost regulator provides a high voltage necessary to

properly drive the buck regulator power MOSFETs, especially

during the low input voltage condition. The LDO regulator

external N-channel MOSFET gate is also powered from the

boost regulator. In order to properly enhance the high-side

MOSFETs when only a +3.3 V supply rail powers the integrated

circuit, the boost regulator provides an output voltage of 8.0 V

nominal value.

The 33701 boost regulator uses a simple hysteretic current

control technique, which allows fast power-up and does not

require any compensation. When the boost regulator main

power switch (low side) is turned on, the current in the inductor

starts to ramp up. After the inductor current reaches the upper

current limit (nominally set at 1.0 A), the low-side switch is

turned off and the current charges the output capacitor through

the internal rectifier. When the inductor current falls below the

valley current limit value (nominally 600 mA), the low-side

switch is turned on again, starting the next switching cycle. After

The output voltage V_OUTcan be adjusted by means of an

external resistor divider connected to the feedback control pin

INV. The switching regulator output voltage can be adjusted in

the range of 0.8 V to 5.0 V, but the V_OUToutput voltage is

always lower than the input voltage to the regulator. Power-up,

power-down, and fault management are coordinated with the

linear regulator.

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the boost regulator output capacitor reaches its regulation limit,

thermal shutdown limit, the Q4 will be turned off without

the low-side switch is turned off until the output voltage falls

below the regulation limit again.

affecting the LDO operation.

Voltage Margining

Oscillator

The 33701 includes a voltage margining feature accessed

A 300 kHz (default) oscillator sets the switching frequency of

the buck regulator. The frequency of the oscillator can be

adjusted between 200 kHz and 400 kHz by an optional external

resistor R_Fconnected from the FREQ pin of the integrated

through the I²C bus. Voltage margining allows for independent

adjustment of the Switcher V_OUTvoltage and the linear output

V_LDO. Each can be adjusted up and down in 1% steps to a

range of ±7%. This feature allows for worst case system

circuit to ground. See Figure 4 for frequency resistor selection.

validation; i.e., determining the design margin. Margining

details are described in the section entitled I²C Bus Operation,

beginning on page 19 of this datasheet.

The CLKSYN pin can be configured either as an oscillator

output when the CLKSEL pin is left open or it can be used as a

synchronization input when the CLKSEL pin is grounded. The

oscillator output signal is a square wave logic signal with

50 percent duty cycle, 180 degrees out-of-phase with the

internal clock signal. This allows opposite phase

RESET

The RESET pin is an open drain output. The Reset Control

circuit supervises both output voltages—the linear regulator

output V_LDOand the switching regulator output V_OUT. When

either of these two regulators is out of regulation (high or low),

the RESET pin is pulled low. There is a 20 µs delay filter

preventing erroneous resets. During power-up sequencing,

RESET is held low until the Reset Timer times out.

synchronization of two 3370x devices.

When the CLKSYN pin is used as synchronization input

(CLKSEL pin grounded), the external resistor R_Fchosen from

the chart in Figure 4 should be used to synchronize the internal

slope compensation ramp to the external clock. Operation is

only recommended between 200 kHz and 400 kHz. The

supplied synchronization signal does not need to be 50 percent

duty cycle. Minimum pulse width is 300 ns.

Reset Timer Power-Up Delay (RT)

The Reset Timer Power-Up Delay (RT) pin is used to set the

delay between the time when the LDO and switcher outputs are

active and stable and the release of the RESET output. An

external resistor and capacitor are used to program the timer.

The power-up delay can be obtained by using the following

formula:

Low Dropout Linear Regulator (LDO)

The adjustable low dropout linear regulator (LDO) is capable

of supplying a 1.0 A output current. It has a current limit with

retry capability. When the voltage measured across the current

sense resistor reaches the 45 mV threshold, the control circuit

limits the current for 1.0 ms and if the overcurrent condition still

exists the linear regulator is turned off. At the same time the

overcurrent condition is detected, the Retry Timer starts to time

out. When the timer expires after 100 ms, the LDO tries to

power up again for 1.0 ms, repeatedly checking for the

overcurrent condition. The current limit of the LDO can be set

by using the following formula:

T_D= 10 ms + R_tC_t

Where R_tis the Reset Timer programming resistor and C_tis the

Reset Timer programming capacitor, both connected in parallel

from RT to ground.

Note Observe the maximum C_tvalue and expect reduced

accuracy if R_tis less than 10 kΩ.

I

_LIM= 45 mV/R_S

Watchdog Timer

Where R_Sis the LDO current sense resistor, connected

between the CS pin and the LDO pin output (see Figure 20).

A watchdog function is available via I²C bus communication.

It is possible to select either window watchdog or time-out

watchdog operation, as illustrated in Figure 9 on page 15.

When no current sense resistor is used, it is still possible to

detect the overcurrent condition by tying the current sense pin

CS to the V_BSTvoltage. In this case, the overcurrent condition

Watchdog time-out starts when the watchdog function is

activated via I²C bus sending a Watchdog Programming

command byte, thus determining watchdog operation (window

or time-out) and period duration (refer to Table 1, page 15). If

the watchdog is cleared by receiving a new Watchdog

is sensed by saturation of the linear regulator driver buffer.

The output voltage of the LDO can be adjusted by means of

an external resistor divider connected to the feedback control

pin LFB. The linear regulator output voltage can be adjusted in

the range of 0.8 V to 5.0 V, but the LDO output voltage is always

lower than the input voltage to the regulator. Power-up, power-

down, and fault management are coordinated with the

switching regulator.

Programming command through the I²C bus, the watchdog

timer is reset and the new time-out period begins. If the

watchdog time expires, the RESET will become active (LOW)

for a time determined by the RC components of the RT timer

plus 10 ms. After a watchdog time-out, the function is no longer

active.

Thermal Shutdown

The LDO pull-down FET Q4 has an independent thermal

shutdown control. When the Q4 temperature exceeds the

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EN1 and EN2 Control Pins

Watchdog Closed

Window Open

No Watchdog Clear Allowed

for Watchdog Clear

These two pins permit positive logic control of the Enable

function and selection of the Power Sequencing mode

concurrently. Table 2 depicts the EN1 and EN2 function and

Power Sequencing mode selection.

50% of Watchdog Period

Watchdog Period

Timing Selected via 1²C Bus – See Table 1

Both EN1 and EN2 pins have internal pull-down resistors

and both can withstand a short circuit to the supply voltage,

6.0 V.

Window Watchdog

Window Open for Watchdog Clear

Table 2. Operating Mode Selection

EN1

EN2

Operating Mode

Regulators Disabled

Watchdog Period

0

1

0

1

0

1

Timing Selected via I²C Bus – See Table 1

Standard Power Sequencing

Inverted Power Sequencing

Time-Out Watchdog

Figure 9. Watchdog Operation

Regulators Enabled,

No Power Sequencing

Table 1. Watchdog Programming Command Byte

(as a 2nd Command Byte)

Power Sequencing Modes

Address

Value

Action

The power sequencing of the two outputs of this power

supply IC is in compliance with the Motorola Power QUICC and

other 32-bit microprocessor requirements. When the input

voltage is applied, the switcher and linear regulator outputs

follow the supply rail voltage during power-up and power-down

in the limits given by the microcontroller power sequencing

specification, illustrated in Figures 10 through 12. There are two

possible power sequencing modes, Standard and Inverted, as

explained in more detail below. The third mode of operation is

Power Sequencing Disabled.

0

1

0

1st Command

WD OFF

(Note 12)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

WD 1280 ms

WinOFF

WD 320 ms

WinOFF

WD 80 ms

WinOFF

3.3 V Input Supply (I/O Voltage)

∆V = 2.0 V

WD 20 ms

WinOFF

Max. Lead

WD 1280 ms

WinON

V Start-Up

1.8 V Core Voltage

Slope

WD 320 ms

WinON

∆V = 2.0 V

1.0 V/ms

(typ.)

Max. Lead

∆V = 0.4 V

Max. Lag

WD 80 ms

WinON

Figure 10. Standard Power Up/Down Sequence

in +3.3 V Supply System

WD 20 ms

WinON

Notes

12. The Watchdog feature will be turned

ON automatically after receiving any

other valid command byte changing

watchdog time.

5.0 V Input Supply

3.3 V I/O Voltage (V

∆V = 2.0 V

Max. Lead

∆V = 2.0 V

)

LDO

Max. Lead

V Start-Up

1.8 V Core Voltage

(V

)

OUT

When the Window Watchdog function is selected, the timer

cannot be cleared during the Closed Window time, which is

50% of the total watchdog period. When the watchdog is

cleared, the timer is reset and starts a new time-out period. If

the watchdog is not cleared during the Open Window time, the

RESET will become active (LOW) for a time determined by the

RC components of the RT timer plus 10 ms.

∆V = 0.4 V

Max. Lag

Figure 11. Standard Power Up/Down Sequence

in +5.0 V Supply System

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Standard Power Sequencing

5.0 V Input Supply

∆V = 2.0 V

When the power supply IC operates in the Standard Power

Max. Lead

Sequencing mode, the switcher output provides the core

voltage for the microprocessor. This situation and operating

conditions are illustrated in Figure 10 and Figure 11. Table 2,

page 15, shows the Power Sequencing mode selection.

∆V = 2.0 V

3.3 V I/O Voltage (V

)

OUT

Max. Lead

V Start-Up

(V

)

1.8 V Core Voltage

LDO

∆V = 0.4 V

Max. Lag

Inverted Power Sequencing

When the power supply IC is operating in the Inverted Power

Sequencing mode, the linear regulator (LDO) output provides

the core voltage for the microprocessor, as illustrated in

Figure 12. Table 2 shows the Power Sequencing mode

selection.

Figure 12. Inverted Power Up/Down Sequence in +5.0 V

Supply System

33701 POWER SEQUENCING

Standard Power Sequencing Control

Requirements

1. I/O supply voltage not to exceed core voltage by more than

Comparators monitor voltage differences between the LDO

(LDO pin) and the switcher (V_OUTpin) outputs as follows:

2.0 V.

1. LDO > V_OUT+ 1.8 V, turn off LDO. The LDO can be

2. Core supply voltage not to exceed I/O voltage by more

than 0.4 V.

forced off. This occurs whenever the LDO output voltage

exceeds the switcher output voltage by more than 1.8 V.

Methods of Control

2. LDO > V_OUT+ 1.9 V, shunt LDO to ground. If turning off

the LDO is insufficient and the LDO output voltage

exceeds the switcher output voltage by more than 1.9 V,

a 1.0 Ω shunt FET is turned on that discharges the LDO

load capacitor to ground. The shunt FET is used for

switcher output shorts to ground and for power down in

case of V_IN1≠ V_IN2with the switcher output falling faster

The 33701 has several methods of monitoring and

controlling the regulator output voltages, as described in the

paragraphs below. Power sequencing control is also achieved

through the intrinsic operation of the regulators. The EN1 and

EN2 pins can be used to disable the power sequencing (refer to

Table 2, page 15.

than the LDO.

Intrinsic Operation

3. LDO < V_OUT+ 1.7 V, cancel (1) and (2) above, re-enable

LDO. Normal operation resumes when the LDO output

voltage is less than 1.7 V above the switcher output

voltage.

For both the LDO and switcher, whenever the output voltage

is below the regulation point, the LDO external Pass FET will be

on or the Buck High-Side FET will be on at a duty cycle

controlled by the switcher. Because these devices are FETs,

current can flow in either direction, balancing the voltages via

the common supply pin. The ability to maintain the FETs on will

depend on the available gate voltage, and thus the size of the

boost regulator storage capacitor.

4. LDO < V_OUT- 0.2 V, turn off switcher. The switcher can

be forced off. This occurs whenever the LDO is less than

V_OUT- 0.2 V.

5. LDO < V_OUT- 0.3 V, turn on Sync (LS) FET and 1.0 Ω

V_OUTsink FET. The Buck High-Side FET is forced off and

the Sync FET is forced on. This occurs when the switcher

output voltage exceeds the LDO output by more than

300 mV.

6. LDO > V_OUT, reset (4) and (5) above. Normal operation

resumes when LDO > V_OUT

.

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Inverted Power Sequencing Control

than V_OUT, the Buck High-Side FET is also on, and the V_OUT

load capacitor will be discharged through the Buck High-Side

Comparators monitor voltage differences between the

switcher (V_OUTpin) and LDO (LDO pin) outputs as follows:

FET to V_IN. Thus, provided V_INdoes not fall too fast, the core

voltage (V_OUT) will not exceed the I/O voltage (V_IN) by more

than a maximum of 0.4 V.

1. V_OUT> LDO + 1.8 V, turn off V_OUT. The switcher V_OUT

can be forced off. This occurs whenever the V_OUToutput

voltage exceeds the LDO output voltage by more than

Shorted Load

1.8 V.

1. V_OUTshorted to ground. This will cause the I/O voltage to

2. V_OUT> LDO + 1.9 V, shunt V_OUTto ground. If turning off

exceed the core voltage by more than 2.0 V. No load

the switcher V_OUTis insufficient and the V_OUToutput

protection.

voltage exceeds the LDO output voltage by more than

1.9 V, a 1.0 Ω shunt FET is turned on that discharges the

V_OUTload capacitor to ground. The shunt FET is used for

2. V_INshorted to ground. Until the switcher load

capacitance is discharged, the core voltage will exceed

the I/O voltage by more than 0.4 V. By the intrinsic

operation of the switcher, the load capacitor will be

discharged rapidly through the Buck High-Side FET to

V_IN.

LDO output shorts to ground and for power-down in case

of V_IN1≠ V_IN2with LDO output falling faster than the

V_OUT

.

3. V_OUT< LDO + 1.7 V, cancel (1) and (2) above, re-enable

V_OUT. Normal operation resumes when the V_OUToutput

voltage is less than 1.7 V above the LDO output voltage.

4. V_OUT< LDO - 0.2 V, turn off LDO. The LDO can be

forced off. This occurs whenever the V_OUTis less than

V_LDO- 0.2 V.

3. V_OUTshorted to supply. No load protection. 33701

protected by current limit and thermal limit.

2. Single 5.0 V Supply, V_IN1= V_IN2, or Dual Supply V_IN1

V_IN2

≠

The LDO supplies the microprocessor I/O voltage. The

5. V_OUT< LDO - 0.3 V, turn on the 1.0 Ω LDO sink FET.

switcher supplies the core (e.g., 1.8 V nominal) (see Figure 11,

page 15).

This occurs when the LDO output voltage exceeds the

V_OUToutput by more than 300 mV.

Power Up

6. V_OUT> LDO, reset (4) and (5) above. Normal operation

This condition depends upon the regulator current limit, load

current and capacitance, and the relative rise times of the V_IN1

and V_IN2supplies. There are 2 cases:

resumes when V_OUT> LDO.

Standard Operating Mode

1. LDO rises faster than V_OUT. The LDO uses control

1. Single 3.3 V Supply, V_IN= V_IN1= V_IN2= 3.3 V

methods (1) and (2) described in the Methods of Control

section, page 16.

The 3.3 V supplies the microprocessor I/O voltage, the

switcher supplies core voltage (e.g., 1.8 V nominal), and the

LDO operates independently (see Figure 10, page 15). Power

sequencing depends only on the normal switcher intrinsic

operation to control the Buck High-Side FET.

2. V_OUTrises faster than LDO. The switcher uses control

methods (4) and (5) described in the Methods of Control

section, page 16.

Power Down

Power Up

This condition depends upon the regulator load current and

capacitance and the relative fall times of the V_IN1and V_IN2

supplies. There are 2 cases:

When V_INis rising, initially V_OUTwill be below the regulation

point and the Buck High-Side FET will be on. In order not to

exceed the 2.0 V differential requirement between the I/O (V_IN)

1. V_OUTfalls faster than LDO. The LDO uses control

and the core (V_OUT), the switcher must start up at 2.0 V or less

methods (1) and (2) described in the Methods of Control

and be able to maintain the 2.0 V or less differential. The

section, page 16.

maximum slew rate for V_INis 1.0 V/ms.

In the case V_IN1= V_IN2, the intrinsic operation will turn on

both the Buck High-Side FET and the LDO external Pass

Power Down

FET, and will discharge the LDO load capacitor into the V_IN

When V_INis falling, V_OUTwill be below the regulation point;

therefore the Buck High-Side FET will be on. In the case where

supply.

2. LDO falls faster than V_OUT. The switcher uses control

V

_OUTis falling faster than V_IN, the Buck High-Side FET will

methods (4) and (5) described in the Methods of Control

attempt to maintain V_OUT. In the case where V_INis falling faster

section, page 16.

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Shorted Load

the load capacitor will be discharged rapidly through the

Pass FET to V_IN.

1. V_OUTshorted to ground. The LDO uses method (1) and

(2) described in the Methods of Control section, page 16.

3. LDO shorted to supply. No load protection.

2. LDO shorted to ground. The switcher uses control

methods (4) and (5) described in the Methods of Control

section, page 16.

2. Single 5.0 V Supply, V_IN1= V_IN2, or Dual Supply V_IN1

V_IN2

≠

3. V_IN1shorted to ground. This is equivalent to the LDO

output shorted to ground.

4. V_IN2shorted to ground. This is equivalent to the switcher

output shorted to ground.

5. V_OUTshorted to supply. No load protection. 33701

protected by current limit and thermal limit.

The switcher V_OUTsupplies the microprocessor I/O voltage.

The LDO supplies the core (e.g., 1.8 V nominal) (see Figure 12,

page 16).

Power Up

This condition depends upon the regulator current limit, load

current and capacitance, and the relative rise times of the V_IN1

and V_IN2supplies. There are 2 cases:

6. LDO shorted to supply. No load protection. 33701

protected by current limit and thermal limit.

1. V_OUTrises faster than LDO. The switcher V_OUTuses

Inverted Operating Mode

control methods (4) and (5) described in the Methods of

Control section, page 17.

2. LDO rises faster than V_OUT. The LDO uses control

1. Single 3.3 V Supply, V_IN= V_IN1= V_IN2= 3.3 V

The 3.3 V supplies the microprocessor I/O voltage, the LDO

supplies core voltage (e.g., 1.8 V nominal), and the switcher

methods (1) and (2) described in the Methods of Control

section, page 17.

V

_OUToperates independently. Power sequencing depends only

on the normal LDO intrinsic operation to control the Pass FET.

Power Down

This condition depends upon the regulator load current and

capacitance and the relative fall times of the V_IN1and V_IN2

Power Up

When V_INis rising, initially LDO will be below the regulation

supplies. There are 2 cases:

point and the Pass FET will be on. In order not to exceed the

1. LDO falls faster than V_OUT. The V_OUTuses control

2.0 V differential requirement between the I/O (V_IN) and the

methods (4) and (5) described in the Methods of Control

core (LDO), the LDO must start up at 2.0 V or less and be able

to maintain the 2.0 V or less differential. The maximum slew

rate for V_INis 1.0 V/ms.

section, page 17.

In the case V_IN1= V_IN2the intrinsic operation will turn both

the Buck High-Side FET and the LDO external Pass FET,

and will discharge the V_OUTload capacitor into the V_IN

Power Down

supply.

When V_INis falling, LDO will be below the regulation point;

2. V_OUTfalls faster than LDO. The LDO uses control

therefore the Pass FET will be on. In the case where LDO is

methods (1) and (2) described in the Methods of Control

falling faster than V_IN, the Pass FET will attempt to maintain

section, page 17.

LDO. In the case where V_INis falling faster than LDO, the Pass

FET is also on, and the LDO load capacitor will be discharged

Shorted Load

through the Pass FET to V_IN. Thus, provided V_INdoes not fall

1. LDO shorted to ground. The V_OUTuses methods (4) and

too fast, the core voltage (LDO) will not exceed the I/O voltage

(V_IN) by more than maximum of 0.4 V.

(5) described in the Methods of Control section, page 17.

2. V_OUTshorted to ground. The LDO uses control methods

(1) and (2) described in the Methods of Control section.

Shorted Load

3. V_IN1shorted to ground. This is equivalent to the LDO

output shorted to ground.

4. V_IN2shorted to ground. This is equivalent to the switcher

V_OUToutput shorted to ground.

1. LDO shorted to ground. This will cause the I/O voltage to

exceed the core voltage by more than 2.0 V. No load

protection.

2. V_INshorted to ground. Until the LDO load capacitance is

discharged, the core voltage will exceed the I/O voltage

5. LDO shorted to supply. No load protection.

by more than 0.4 V. By the intrinsic operation of the LDO,

6. V_OUTshorted to supply. No load protection. 33701

protected by current limit and thermal limit.

33701

18

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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2

I C BUS OPERATION

Introduction

Table 3. Definition of Selectable Portion of Device Address

The 33701 device is compatible with the I²C interface

CLKSEL Pin

Low

ADDR Pin

Low

A1

0

A0

0

standard. SDA and SCL pins are the Serial Data and Serial

Clock pins of the I²C bus.

Low

Open

Low

0

1

2

Open

1

0

I C Command and Data Formats

Open

1

Communication Start

Communication starts with a START condition, followed by

the slave device unique address. Figure 13 illustrates the data

Writing Data Into the Slave Device

After the address acknowledgment by the slave, DATA can

be written into the slave registers. The R/W bit must be set to 0

so DATA will be read. Figure 15 shows the data write

transfer beginning an I²C communication for a 7-bit slave

address.

sequence. Actions performed by the slave device are grayed.

Ack

S

7-Bit Address

R/W

S

7-Bit Address

0

Ack

DATA

Ack

Figure 13. Communication Using 7-Bit Address

Slave Address Definition

Figure 15. Data Transfer for Write Operations

Data Definition

33701 has the two LSB’s address bits defined by the state of

the CLKSEL pin and the ADDR pin.

For the sake of 33701 acting as a slave device, the master

writes a Command Byte and writes one Data Byte. The

Command Byte identifies the kind of operation required by the

master and has two fields, as illustrated in Figure 16:

Note The state of the CLKSEL pin also defines the

configuration of the oscillator synchronization CLKSYN pin.

1. Address field

2. Value field

This feature allows up to four 33701 ICs to communicate in

the same I²C bus, all of them sharing the same high-order

address bits. A different combination of bits A1 and A0 is

assigned to each individual part to assure its unique address.

Figure 14 illustrates the flexible addressing feature for a 7-bit

address. Table 3 provides the definition of the selectable

portion of the device address.

The address field is selected from the list in Table 4.

Bits

7

6

5

4

3

2

1

0

D6 D5 D4 D3 D2 D1 D0

D7

Bits

6

5

4

3

2 1 0

Address Field

Value Field

1

0

1

A1 A0

Figure 16. Command Byte

Table 4. Address Field Definitions

Fixed Address Selectable

Address

Figure 14. Address Bit Definition for 7-Bit Address

Code

001

Operation

Voltage Margining

Not Used

Write

W

–

010

011

Watchdog

W

Refer to Table 5, page 20, which summarizes the value field

definitions for the entire set of operation options.

33701

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19

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Security in Writing Commands

Table 5. Command Byte Definitions

Operation

Address

Value

Action

1st Command

Output Normal

+ 1%

All writing operations are critical and must not be

inadvertently latched after a false command. To improve the

security level, a so-called first command is defined to initiate

each write communications.

Voltage Margining

(As a 2nd

Command Byte)

0

1

0

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A first command has the Command Byte address field equal

to the related operation one, followed by a null value field (all

zeros). Table 6 summarizes first command definitions. The

master sends the first command before the Command Byte for

the intended operation.

+ 2%

+ 3%

+ 4%

LDO Output: x=0

+ 5%

Table 6. First Command Definitions

Switcher Output x=1

+ 6%

First Command

001 00000

Operation

+ 7%

Voltage Margining

- 1%

011 00000

Watchdog Programming

- 2%

- 3%

Voltage Margining Operation

- 4%

After starting the communication in Writing mode, the master

sends the first command followed by the specific Command

Byte to set the required voltage margining for either the LDO or

the switcher (see Figure 17). To achieve a simultaneous set for

both LDO and switcher, two specific commands must be issued

in sequence after the first command, one for each supply.

- 5%

- 6%

- 7%

Watchdog

Programming

(As a 2nd

Command Byte)

1st Command

WD OFF

(Note 13)

0

1

0 0

0

0 0 1 x x x x x

Ack

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

WD 1280 ms

WinOFF

First Byte for Voltage Margining

Command Byte

Figure 17. Voltage Margining Programming

(One Supply Only)

WD 320 ms

WinOFF

WD 80 ms

WinOFF

Note x bits are defined in Table 5.

Watchdog Programming Operation

WD 20 ms

WinOFF

For watchdog operation control, the master periodically

sends a watchdog first command followed by a command byte

selecting, or confirming, the watchdog period according to the

options listed in Table 5. Also see Figure 18.

WD 1280 ms

WinON

WD 320 ms

WinON

The internal watchdog timer will be cleared each time a

watchdog command is written into the device, provided it

arrives during the window open time. The Command 01100000

sent twice will shut the time OFF, and the watchdog function will

be disabled. Any other valid watchdog command turns on the

timer again.

WD 80 ms

WinON

WD 20 ms

WinON

Notes

13. The Watchdog feature will be turned ON automatically

after receiving any other valid command byte changing

watchdog time.

0

1

0 0

0

0 1 1 x x x x x

Ack

First Byte for Watchdog Programming

Command Byte

Figure 18. Watchdog Timer Programming

Note x bits are defined in Table 5.

33701

20

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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setting for switcher is needed, a fourth byte should be included

Communication Stop

before the STOP condition (P); for instance, 001 10010 to set

switcher in its second setting (switcher output voltage = +2%

above its nominal value).

Only the master can terminate the data transfer by issuing a

STOP condition. The slave waits for this condition to resume its

initial state waiting for the next START condition (see

Figure 19).

A2 A1

S A6 A5 A4 A3

START

A0 0 Ack

Write

Data Transfer Example

Slave Address

The master device controlling the I²C bus will always start

addressing a 33701 slave IC in writing mode (R/W = 0) in order

to be able to write a Command Byte just after the address

0

1

0

0 Ack

0

acknowledge. I²C bus protocol defines this circumstance as a

master-transmitter and slave-receiver configuration.

First Command for Voltage Margining

Eventually this Command Byte can again define a Write

operation (e.g., Voltage Margining, see Figure 19), and the

master will keep the data transfer direction.

0

1

0

1

0

1 Ack

P

STOP

Address Field Value Field = LDO

^thSetting

Figure 19 illustrates a communication beginning with the

slave address, the first command for voltage margining, and a

third byte containing the address field 001 and the value field

00101 corresponding with the LDO fifth setting (LDO output

voltage = +5% above its nominal value). If a simultaneous

5

Figure 19. Complete Data Transfer Example

33701

21

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APPLICATION INFORMATION

V

IN1

VIN1

V

VIN

+3.3 V

IN

+3.3V

V

DDI

VDDI

V

Supply

VDDI

DDI

Supply

C_IN

10 µF

Internal

Supply

Voltage

10uF

Voltage

1.0 uF

VVDDI

DDI

V

BST

VBST

8.0V

V

VBST

BST

VVBST

BST

C_BST

10 µF

Power

LDRV

-

+

10uF

Q_LDO

Enable

Vref

V

DDI

CS

10 µH

10uH

VDDI

DDI

VDDI

R_S

0.068 RΩ

Linear

Regulator

Control

VV_LDO==22..55VV

^LDO@ 1.0A

LDO

L_BST

V

VBD

BD

@ 1.0 A

Boost

Bandgap

Voltage

Vref

Control

Vref

I

I-lim

?k

Reference

LIM

LFB

Vref

+3.3V

C_LDO

V

DDI

VDDI

+3.3 V or

5 x 2.2 uF

or

5 x 2.2 µF

V

EN1

EN2

V_LDO

LDO

V

LDO

LCMP

100pF

1.5k

Pow. Seq.

PWR Seq.

VLDO

Q4

Power

6.8nF

Sequencing

Voltage Margining

W-dog Timer

5.1k

Down

V

VBST

BST

UVLO

V

RESET

Reset

RESET

V

OUT

Reset

VOUT

BOOT

to MCU

Control

BST

VBST

V

VBST

BST

Current

Limit

SysCon

INV

LFB

POR

V

IN2

VIN2

RT

Timer

+3.3 V

+3.3V

2

I C

V

DDI

VDDI

(2)

Supply

Control

C

t

Ct

Buck

HS

R

C_IN

Rt

t

Voltage

Q1

Q2

2 x 10 uF

100k

2

I C

2 x 10 µF

100nF

&

SysCon

SoftSt

D_B

Control

LS

VV_OOUUTT==11..88VV

@ 1.5 A

L1

C_B

Thermal

Limit

00.1.1uFµF

Buck

Control

Logic

SW

(2)

Driver

4.7 uH

4.7 µH

1.5 A

@

50 µF

ADDR

SDA

C_O

50 uF

R_pd

10k

2

I C

PGND

(2)

?k

Interface

Error

Amp.

PWM

To Reset

Control

0.8V

+

-

Switcher

Comp.

SCL

Oscillator

300kHz

+

-

INV

?k

V

VOUT

OUT

Slope

R_b

?k

Comp.

?

V

VOUT

OUT

Q3

?pF

Pow.

PWR Seq.

Seq.

FREQ

R_F

(4)

CLKSYN

CLKSEL

GND

(Optional)

Figure 20. Simplified Block Diagram and Typical Application

33701

22

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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PACKAGE DIMENSIONS

DWB SUFFIX

32-LEAD SOIC WIDE BODY

PLASTIC PACKAGE

CASE 1324-02

ISSUE A

10.3

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

7.6

7.4

C

B

2.65

2.35

3. DATUMS B AND C TO BE DETERMINED AT THE PLANE

WHERE THE BOTTOM OF THE LEADS EXIT THE

PLASTIC BODY.

4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,

PROTRUSION OR GATE BURRS. MOLD FLASH,

PROTRUSION OR GATE BURRS SHALL NOT EXCEED

0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED

AT THE PLANE WHERE THE BOTTOM OF THE LEADS

EXIT THE PLASTIC BODY.

5

9

30X

0.65

1

32

PIN 1 ID

5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSIONS. INTERLEAD FLASH AND

PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER

SIDE. THIS DIMENSION IS DETERMINED AT THE

PLANEWHERETHEBOTTOMOFTHELEADSEXITTHE

PLASTIC BODY.

4

11.1

10.9

C

L

9

B

6. THIS DIMENSION DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4

MM PER SIDE. DAMBAR CANNOT BE LOCATED ON

THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSION AND ADJACENT LEAD

SHALL NOT LESS THAN 0.07 MM.

7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

8. THESE DIMENSIONS APPLY TO THE FLAT SECTION

OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM

THE LEAD TIP.

16

17

SEATING

A

PLANE

5.15

2X 16 TIPS

0.3

32X

0.10

A

9. THE PACKAGE TOP MAY BE SMALLER THAN THE

PACKAGE BOTTOM. THIS DIMENSION IS

A

B C

DETERMINED AT THE OUTERMOST EXTREMES OF

THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE

BAR BURRS, GATE BURRS AND INTER-LEAD FLASH,

BUT INCLUDING ANY MISMATCH BETWEEN THE TOP

AND BOTTOM OF THE PLASTIC BODY.

A

(0.29)

BASE METAL

0.25

0.19

(0.203)

R0.08 MIN

0.25

GAUGE PLANE

°

0

0.38

0.22

0.29

0.13

MIN

PLATING

6

M

0.13

C A

B

8

0.9

0.5

SECTION A-A

°

8

0

ROTATED 90 CLOCKWISE

°

SECTION B-B

33701

23

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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied

copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee

regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product

or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be

provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license

under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for

surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product

could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or

unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all

claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated

with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their

respective owners.

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center

3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan

81-3-3440-3569

Motorola Literature Distribution

P.O. Box 5405, Denver, Colorado 80217

1-800-521-6274 or 480-768-2130

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre

2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong

852-26668334

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MC33701/D


型号：	PC33701DWB
厂家：	NXP
描述：	3A SWITCHING REGULATOR, 400kHz SWITCHING FREQ-MAX, PDSO32, PLASTIC, SOIC-32 开关光电二极管
文件：	总24页 (文件大小：841K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PC33701DWB [NXP]

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