PC33710EW [NXP]
IC,SMPS CONTROLLER,VOLTAGE-MODE,SSOP,32PIN,PLASTIC;
| 型号： | PC33710EW |
| 厂家： | 
NXP |
| 描述： | IC,SMPS CONTROLLER,VOLTAGE-MODE,SSOP,32PIN,PLASTIC 光电二极管 |
| 文件： | 总17页 (文件大小：1307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document order number: MC34710
Rev. 3.0, 3/2006
Freescale Semiconductor
Technical Data
Dual Output DC-DC & Linear
Regulator IC
The 34710 is a dual-output power regulator IC integrating
switching regulator, linear regulator, supervisory and power supply
sequencing circuitry. With a wide operating input voltage range of
13 V to 32 V, the 34710 is applicable to many commercial and
industrial applications using embedded MCUs.
33710
34710
DUAL OUTPUT DC-DC & LINEAR
REGULATOR
A mode-selected 5.0 Vor 3.3 V DC-DC switching regulator is
provided for board-level I/O and user circuitry up to 700 mA. A linear
regulator provides mode-selected core supply voltages of either 3.3V,
2.5V,1.8V, or 1.5V at currents up to 500 mA.
The supervisor circuitry ensures that the regulator outputs follow a
predetermined power-up and power-down sequence.
Features
DW SUFFIX
EW SUFFIX (PB-FREE)
98ASA10627D
• Efficient 5.0 V/3.3 V Buck Regulator
• Low Noise LDO Regulator (mode-selected 3.3V, 2.5V,1.8V, or
1.5V)
32-TERMINAL SOICW
• On-Chip Thermal Shutdown Circuitry
• Supervisory Functions (Power-ON Reset and Error Reset
Circuitry)
• Sequenced I/O and Core Voltages
• Pb-Free Packaging Designated by Suffix Code EW
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
A
*PC33710EW/R2
-40°C to 105°
0°C to 85°C
32 SOICW-EP
32 SOICW-EP
MC34710EW/R2
*Device in development.
Electrical parameters being defined.
VI/O
13 V to 32 V
34710
B+
VB
CT
V
I/O
VSWITCH
VFB
CP2
CP1
MCU
MODE0
MODE1
MODE2
LINB
+
V
RST
CORE
VCORE
GND
Figure 1. 34710 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
CP1
CP2
VB
200 kHz
Oscillator
Charge
Pump
B+
Supervisory and
Temperature
Shutdown
RST
CT
Bandgap
VI/O
VFB
Switching
Regulator
MODE0
VSWITCH
VCORE
MODE1
MODE2
LINB+
VCORE
Linear
Regulator
GND
Figure 2. 34710 Simplified Internal Block Diagram
34710
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
RST
MODE0
MODE1
MODE2
N/C
1
32
CT
2
31
CP1
CP2
VB
3
30
4
29
28
27
26
25
24
23
22
21
20
19
18
17
5
B+
6
N/C
VSWITCH
VFB
LINB+
N/C
VCORE
N/C
7
N/C
8
N/C
9
N/C
10
11
12
13
14
15
16
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
Figure 3. 34710 Terminal Connections
Table 1. 34710 Terminal Definitions
Terminal
Number
Terminal
Name
Terminal
Function
Formal Name
Definition
Reset is an open drain output only.
1
Reset
Input
Reset
RST
2
3
4
Mode0
Mode1
Mode2
Mode Control
These input terminals control V and V
FB
output voltages.
CORE
5–12,
14–22, 24
NC
NC
No Connects
Ground
No internal connection to this terminal.
13
23
GND
Ground
Output
Ground.
VCORE
Core Voltage
Core regulator output voltage.
Regulator Output
25
26
LINB+
VFB
Input
Input
Core Voltage
Regulator Input
Core regulator input voltage.
V
Switching
Feedback terminal for V switching regulator and internal logic supply.
I/O
I/O
Regulator
Feedback
27
28
VSWITCH
B+
Output
V
Switching
V
switching regulator switching output.
I/O
I/O
Regulator Switch
Output
Input
Power Supply
Input
Regulator input voltage.
29
30
VB
Output
Boost Voltage
Boost voltage storage node.
CP2
Passive
Component
CP Capacitor
Positive
Charge pump capacitor connection 2.
31
32
CP1
CT
Passive
Component
CP Capacitor
Negative
Charge pump capacitor connection 1.
Reset delay adjustment capacitor.
Passive
Component
Reset Delay
Capacitor
34710
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
MAXIMUM RATINGS
MAXIMUM RATINGS
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Rating
Symbol
Max
Unit
ELECTRICAL RATINGS
VB
+
V
Input Power Supply Voltage
-0.3 to 36
260
IB = 0.0 A
+
Terminal Soldering Temperature (1)
Power Dissipation (2)
T
°C
W
V
SOLDER
P
3.0
D
ESD Standoff Voltage
V
±2000
Non-Operating, Unbiased, Human Body Model (3)
ESD1
°C/W
Thermal Resistance
R
45
25
Junction-to-Ambient (4)
θJA
θJA
θJC
R
Junction-to-Ambient (2)
R
2.0
Junction-to-Exposed-Pad
THERMAL RATINGS
T
0 to 85
°C
°C
V
Operating Ambient Temperature
Operating Junction Temperature
Input Power Supply Voltage
A
T
0 to 105
J
VB
+
13 to 32
7.5
IB = 0.0 A to 3.0 A
+
Quiescent Bias Current from B+ (5)
I
(Q)
mA
B+
VB = 13 V to 32 V
+
VI/O SWITCHING REGULATOR (6)
V
(STARTUP)
V
Maximum Output Voltage Startup Overshoot (C
= 330 µF)
I/O
OUT
5.4
3.6
Mode0 = 0
Mode0 = Open
I
mA
Maximum Output Current
VI/O
700
T
= 0°C to 105°C
A
Notes
1. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
2
2. With 2.0 in of copper heatsink.
3. ESD1 testing is performed in accordance with the Human Body Model (C
= 100 pF, R
= 1500 Ω).
ZAP
ZAP
4. With no additional heatsinking.
5. Maximum quiescent power dissipation is 0.25 W.
6. 13 V ≤ VB+ ≤ 32 V and -20°C ≤ TJ ≤ 145°C unless otherwise noted.
34710
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
MAXIMUM RATINGS
MAXIMUM RATINGS (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent
damage to the device.
Rating
VCORE LINEAR REGULATOR (7)
Symbol
Max
Unit
= 10 µF) (8)
V
(STARTUP)
V
CORE
Maximum Output Voltage Startup Overshoot (C
Mode2=Low, Mode1=Low, Mode0=Low
OUT
3.6
2.7
Mode2=Open, Mode1=Low, Mode0=Don’t Care
Mode2=Low, Mode1=Open, Mode0=Don’t Care
Mode2=Open, Mode1=Open, Mode0=Don’t Care
2.0
1.65
I
mA
Maximum Output Current
VCORE
500
T = 0°C to 105°C, V
≤ V
(NOM) + 0.8 V (9)
CORE
J
LINB+
Notes
7. 13 V ≤ VB+ ≤ 32 V and -20°C ≤ TJ ≤ 145°C unless otherwise noted.
8. Refer to Table 2, page 9.
9. Pulse testing with low duty cycle used.
34710
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ V ≤ 5.25 V, 13 V ≤ V ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted.
IO
B
+
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SWITCHING REGULATOR (VI/O, MODE0)
V
V
Logic Supply Voltage (I
Mode0 = 0
= 25 to 700 mA)
I/O
VI/O
4.8
5.0
5.2
3.15
3.25
3.45
Mode0 = Open (floating)
R
Ω
Output On Resistance
DS(ON)
0.5
–
1.0
2.5
2.0
3.1
VB = 13 V to 32 V
+
V
(SOFT)
V
A
Soft Start Threshold Voltage
Mode0 = any
I/O
Current Limit Threshold (T = 25°C to 100°C)
J
I
(OP)
1.9
1.0
2.4
–
2.9
1.9
LIMIT
Normal Operation
I
(SOFT)
Soft Start, V
≤ 2.5 V
LIMIT
I/O
VVSWITCH(MIN)
V
V
Minimum Voltage Allowable on VSWITCH Terminal
-0.5
–
–
T = 25°C to 100°C
J
LINEAR REGULATOR (VCORE, MODE 1, 2, 3, 4)
Supply Voltage (I
= 5.0 mA) (10)
V
V
(NOM)
(NOM)
CORE
VCORE
3.15
2.45
1.7
3.3
2.5
1.8
1.5
3.45
2.75
Mode2=Low, Mode1=Don’t Care, Mode0=Low
Mode2=Low, Mode1=Don’t Care, Mode0=Open
Mode2=Open, Mode1=Don’t Care, Mode0=Low
Mode2=Open, Mode1=Don’t Care, Mode0=Open
2.05
1.425
1.575
Supply Voltage (I
= 500 mA) (10)
V
CORE
VCORE
3.0
2.2
–
–
–
–
3.4
2.6
Mode2=Low, Mode1=Don’t Care, Mode0=Low
Mode2=Low, Mode1=Don’t Care, Mode0=Open
Mode2=Open, Mode1=Don’t Care, Mode0=Low
Mode2=Open, Mode1=Don’t Care, Mode0=Open
1.55
1.33
1.9
1.53
I
(DROPOUT)
V
V
Dropout Voltage
VCORE
CORE
–
0.5
0.8
V
= V
(NOM), I = 0.5 A
VCORE
CORE
CORE
I
mA
Normal Current Limit Threshold
T = 25°C to 100°C, V
LIMIT
600
800
1000
= V (NOM) + 1.0 V
CORE
J
LINB+
Notes
10. Refer to Table 2, page 9.
34710
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ V ≤ 5.25 V, 13 V ≤ V ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted.
IO
B
+
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
MODE TERMINALS OPERATING VOLTAGES
Mode Control Terminals Low Voltage
Symbol
Min
Typ
Max
Unit
V (Mode )
V
V
V
IL
n
–
–
–
0.825
–
Mode Control Terminals High Voltage
V
(Mode )
IH
n
2.6
7.0
Mode Control Terminals Voltage with Input Floating
V
(FLOAT)
Mode
VB = 13 V to 14 V
+
8.0
13
SUPERVISOR CIRCUITRY (RST, VCORE)
Minimum Function VB for Charge Pump and Oscillator Running
+
VB (MIN)
–
–
–
9.0
2.2
V
V
V
+
Minimum VB for RST Assertion, VB Rising
V
(ASSERT)
B+
1.9
+
+
RST Low Voltage
V
OL
VB = 2.0 V, IRST ≤ 5.0 mA
–
0.25
–
0.4
+
RST V
Threshold
V
I/O
V
(NOM)
I/O
V
V
Rising
V
–
I/O
I/O
I/OT
+
- 50 mV
–
V
(NOM)
Falling
I/O
V
I/OT
-
–
–
- 300 mV
10
V
100
mV
V
RST Hysteresis for V
HYSVI/O
I/O
RST V
Threshold
CORE
CORE
CORE
V
(NOM)
CORE
V
–
–
–
CORET
+
V
V
Rising
Falling
- 30 mV
V
(NOM)
CORE
V
CORE
T
-
–
- 300 mV
V
mV
V
RST Hysteresis for V
HYS CORE
CORE
10
50
–
100
VB = 13 V to 32 V
+
VCORE(SHUTDOWN)
VCORE - V for V
Shutdown
I/O
CORE
0.5
0.9
VB = 13 V to 32 V
+
T (TSD)
J
°C
°C
Thermal Shutdown Temperature
–
–
–
170
–
T Rising
J
TJ(HYSTERESIS)
20
Overtemperature Hysteresis
VB CHARGE PUMP
Boost Voltage (11)
V
VB
8
VB
9
+
VB 10
+
VB
VB
+
VB = 12 V, I = 0.5 mA
vb
+
VB 10
VB 12
VB 14
+
+
+
VB = 32 V, I = 0.5 mA
vb
+
Notes
11. Bulk capacitor ESR ≤ 10 milliohms
34710
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ V ≤ 5.25 V, 13 V ≤ V ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted.
IO
B
+
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted
Characteristic
SWITCHING REGULATOR
Symbol
Min
Typ
Max
Unit
V
I/O
D
45
20
49
35
55
50
%
Duty Cycle
tR, tF
ns
Switching Rise and Fall Time
Load Resistance = 100 Ω, VB = 30 V
+
SUPERVISOR CIRCUITRY (RST)
ms
µs
ns
t
RST Delay
DELAY
40
2.0
–
60
4.0
25
80
8.0
75
C
= 0.1 µF
delay
t
RST Filter Time
FILTER
VB = 9.0 V
+
t
RST Fall Time
CL = 100 pF, R
F
= 4.7 kΩ, 90% to 10%
PULLUP
C Delay
I
2.0
1.7
3.5
2.0
5.0
2.2
µA
Charge Current
CDLY
V
Threshold Voltage
V
THCD
INTERNAL OSCILLATOR
f
kHz
Charge Pump and V
Switching Regulator Operating Frequency
OP
I/O
140
170
260
VB = 12 V to 32 V
+
34710
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
selected VCORE voltage + 0.8 V. (I.e., 0.8V is the LDO
regulator drop out voltage.)
V
Switching Regulator
I/O
The V switching regulator output voltage is determined
I/O
The Mode terminals select the output voltage as depicted
in Table 2.
by the Mode digital input terminals. The 34710’s Mode
terminals select the output voltage. For example, if Mode2,
Mode1, and Mode0 are set to 0, 0, 0 (respectively) then V
I/O
Table 2. V and VCORE Regulator
I/O
will be set to 5.0 V; if Mode2, Mode1, and Mode0 are all left
floating (i.e., Open, Open, and Open), then the voltage for
Output Voltage Selection
V
will be set to 3.3 V. Table 2 provides the truth table for
VI/O (V)
VCORE (V)
Mode2
0
Mode1
0
Mode0
0
I/O
setting the various combination of regulator outputs via the
Mode pins.
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
3.3
2.5
1.8
1.8
2.5
2.5
1.5
1.5
0
0
Open
0
The topology of the regulator is a hysteretic buck regulator
operating from the internal ~200 kHz oscillator.
0
Open
Open
0
0
Open
0
V
Linear Regulator
CORE
Open
Open
Open
Open
The VCORE linear LDO (low drop-out) regulator can
0
Open
0
produce either a +3.3 V, 2.5 V, 1.8 V, or 1.5 V output voltage
at currents up to 500 mA. The input to the VCORE regulator
is a terminal that may be connected to the V regulator
Open
Open
Open
I/O
output or to an external power supply. Note, the minimum
input voltage level must be equal to or greater than the
Open indicates terminal is not connected externally (i.e. floating).
FUNCTIONAL TERMINAL DESCRIPTION
Power Supply Input (B+)
during fault conditions. This terminal has no input function
and requires an external pull-up resistor.
Main supply voltage for the VI/O Switching Regulator and
general chip bias circuitry.
The RST terminal is an open drain output driver to prevent
oscillations during the transition. It is recommended to
connect a 0.1 uF capacitor between the CT pin and RST pin.
Note: error conditions must be present for a minimum time,
Core Voltage Regulator Input (Lin B+)
Supply voltage for the VCORE Regulator. May be provided
by the VI/O regulator output or from an independent supply.
t
FILTER, before the 34710 responds to them. Once all error
conditions have been cleared, RST is held low for an
additional time of tDELAY
.
Mode Control (MODE 0,1,2)
Mode select terminals to select the VI/O and VCORE output
voltages per table 2. Pull to ground for low state, float for high
state.
Reset Delay Capacitor (CT)
This terminal is the external delay. It is used with a
capacitor to ground to delay RST turn-on time and to RST to
prevent RST oscillations during chip power-on.
Switching Capacitors 1 and 2 (CP1/CP2)
Terminals for the Charge Pump capacitor.
VI/O Switching Regulator Feedback (VFB)
Boost Voltage (VB)
This terminal is the feedback input for the VI/O Switching
Regulator and the output of the regulator application.
The Boost Voltage is an output terminal used for the
charge pump boost voltage and is a connection point for the
Charge Pump bulk capacitor.It provides a gate drive for the
VI/O Switch FET.
VI/O Switching Regulator output (VSWITCH)
This terminal is the Switching output for the VI/O Buck
Regulator. It has internal high side FET.
Reset (RST)
Reset is an output terminal for supervisory functions. This
terminal is in high state during normal operation and low state
34710
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
operation will be suppressed during startup and shutdown to
ensure that VCORE - VI/O = 0.9 V.
SUPERVISORY FUNCTIONS
Supervisory Circuitry
VB Charge Pump
The supervisory circuitry provides control of the RST line,
an open drain signal, based on system operating conditions
monitored by the 34710. VI/O, VCORE, VB+, and thermal
The high-side MOSFET in the switching regulator (buck
converter) requires a gate drive supply voltage that is biased
higher than the B+ voltage, and this boosted voltage is
provided by the internal charge pump and stored in a
capacitor between the VB pin and the B+ pin. The charge
pump operates directly from the B+ supply, and uses an
shutdown (TSD) detectors in various parts of the chip are
monitored for error conditions. VI/O, VCORE, VB+, and thermal
shutdown have both positive- and negative-going thresholds
for triggering the reset function.
internal oscillator operating at 200 kHz.
The supervisor circuitry also ensures that the regulator
outputs follow a predetermined power-up and power-down
sequence. Specifically, the sequencing ensures that VI/O is
Internal Oscillator
The internal oscillator provides a 200 kHz square wave
signal for charge pump operation and for the buck converter.
never less than 0.9 V below VCORE. This means that VCORE
I/O will be clamped at 0.5 V, and that the VCORE regulator
-
V
34710
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
C1
330 µF
B+
13 V - 32 V
R1
1 K
C1
0.1 mF
SW1
C5
32
1
0.1 µF
CT
CP1
CP2
VB
RST
2
3
4
31
30
29
28
27
26
25
24
23
MODE0
MODE1
MODE2
CHARGE
PUMP
C6
10 µF
L1
100 µH
B+
BUCK
REG
SUPERVISORY
& SHUTDOWN
VSW
VFB
LINB
C8
330 µF
LDO
RSERIES
1.8
D1
VCORE
MBRS130LT3
13
GND
MC34710
1
2
V I/O
VCORE
Figure 4. Typical Application Diagram
The MC34710 provides both a buck converter and an LDO
regulator in one IC. Figure 4 above shows a typical
application schematic for the MC34710. L1 is the buck
converter's inductor. The buck inductor is a key component
and must not only present the required reactance, but do so
at a dc resistance of less than 20 milliohms in order to
preserve the converter's efficiency. Also important to the
converter's efficiency is the utilization of a low Vf Schottky
diode for D1.
temperature is maintained below 105 degrees C. The heat-
generating power dissipation of the LDO is primarily a
function of the Volt x Amp product across the LINB+ and
VCORE terminals. Therefore, if the LINB+ voltage is >> than
the selected VCORE voltage + 0.8 V, it is recommended to use
a power resistor in series with the LINB+ input to drop the
voltage and dissipate the heat externally from the IC. For
example, if the output of the buck regulator (V I/O on the
schematic) is used as the input to LINB+, and the mode
switches are set such that V I/O = 5 V and VCORE = 3.3 V,
then a series resistance of 1.8 ohms at the LINB+ pin would
provide an external voltage drop at 500 mA while still leaving
the minimum required headroom of 0.8 V. Conversely, if the
Note that a 0.1uF capacitor is connected between CT and
the reset pins; this prevents any possibility of oscillations
occurring on the reset line during transitions by allowing the
CT terminal to discharge to ground potential via the RST pin,
and then charge when RST returns to a logic high. The
capacitor between the CP1 and CP2 pins is the charge
pump's “bucket capacitor”, and sequentially charges and
discharges to pump up the reservoir capacitor connected to
the VB pin. Note that the reservoir capacitor's cathode is
connected to B+ rather than ground. Also note that the
charge pump is intended only to provide gate-drive potential
for the buck regulator's internal power MOSFET, and
therefore connecting external loads to the VB pin is not
recommended.
mode switches are set such that V I/O = 3.3 V and VCORE
=
2.5 V, then no series resistance would be required, even at
the maximum output current of 500 mA.
Designing a power supply circuit with the MC34710, like all
dc-dc converter ICs, requires special attention not only to
component selection, but also to component placement (i.e.,
printed circuit board layout). The MC34710 has a nominal
switching frequency of 200 kHz, and therefore pcb traces
between the buck converter discrete component terminals
and the IC should be kept as short and wide as possible to
keep the parasitic inductance low. Likewise, keeping these
The IC's internal VCORE LDO regulator can provide up to
500 mA of current as long as the operating junction
34710
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
TYPICAL APPLICATIONS
pcb traces short and wide helps prevent the converter's high
di/dt switching transients from causing EMI/RFI.
possible. The square vias in the plane are located to provide
an immediate path to ground from the top copper circuitry.
Figure 5. Typical PCB Layout
Figure 5 shows a typical layout for the pcb traces
connecting the IC's switching terminal (VSWITCH) and the
power inductor, rectifier, and filter components.
Also, it is recommended to design the component layout
so that the switching currents can be immediately sunk into a
broad full-plane ground that provides terminations physically
right at the corresponding component leads. This helps
prevent switching noise from propagating into other sections
of the circuitry.
Figure 7. Top Copper Layout
Figure 7 shows the corresponding top copper circuit area
with the component placement.
Again, the ground plane and the vias have been
highlighted so the reader may note the proximity of these
current sink pathways to the key converter components. It is
also important to keep the power planes of the switching
converter's output spread as broad as possible beneath the
passive components, as this helps reduce EMI/RFI and the
potential for coupling noise transients into adjacent circuitry.
Figure 6. Bottom Copper Layout
Figure 6 illustrates a pcb typical bottom copper layout for
the area underneath a buck converter populated on the top of
the same section of pcb.
Figure 8. Output Plane of Buck Converter
The ground plane is highlighted so the reader may note
how the ground plane has been kept as broad and wide as
Figure 8 shows the output plane of the buck converter
highlighted.
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TYPICAL APPLICATIONS
This layout provides the lowest possible impedance as
well as lowest possible dc resistance for the power routing.
Note that the power path and its return should be placed, if
possible, on top of each other on different layers or opposite
sides of the pcb.
An additional feature of the MC34710 is the 32 SOICW-EP
exposed pad package. The package allows heat to be
conducted from the die down through the exposed metal pad
underneath the package and into the copper of the pcb. In
order to best take advantage of this feature, a grid array of
thru-hole vias should be placed in the area corresponding to
the exposed pad, and these vias then should then connect to
a large ground plane of copper to dissipate the heat into the
ambient environment. An example of these vias can be seen
in the previous figures of a typical pcb layout.
Small ceramic capacitors are placed in parallel with the
Aluminum electrolytics so that the overall bulk filtering
presents a low ESL to the high di/dt switching currents.
Alternatively, special low ESL/ESR switching-grade
electrolytics may be used.
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PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
EW (Pb-FREE) SUFFIX
32-LEAD SOICW-EXPOSED PAD
PLASTIC PACKAGE
98ASA10627D
ISSUE O
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PACKAGING
PACKAGE DIMENSIONS
EW (Pb-FREE) SUFFIX
32-LEAD SOICW-EXPOSED PAD
PLASTIC PACKAGE
98ASA10627D
ISSUE O
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REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
•
•
•
•
•
Converted to Freescale format
Updated Maximum Ratings, Static and Dynamic Characteristics tables.
Updated packaging drawing
Changed terminal VI/O_OUT to VFB
Implemented Revision History page
3/2006
2.0
•
•
Updated format from Preliminary to Advance Information.
Format and style corrections to match standard template.
3/2006
3.0
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MC34710
Rev. 3.0
3/2006
相关型号：
PC33710EW/R2
0.7A SWITCHING REGULATOR, 260kHz SWITCHING FREQ-MAX, PDSO32, 0.65 MM PITCH, ROHS COMPLIANT, PLASTIC, SOIC-32
NXP
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