PC33970DWR2 [NXP]
IC,MOTOR CONTROLLER,SOP,24PIN;
| 型号： | PC33970DWR2 |
| 厂家： | 
NXP |
| 描述： | IC,MOTOR CONTROLLER,SOP,24PIN 电动机控制 光电二极管 |
| 文件： | 总36页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33970/D
Rev 2.0, 03/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
33970
Dual Gauge Driver Integrated Circuit
with Improved Damping Algorithms
This 33970 is a single-packaged, Serial Peripheral Interface (SPI)
controlled, dual step motor gauge driver integrated circuit (IC). This monolithic
IC consists of four dual output H-Bridge coil drivers and the associated control
logic. Each pair of H-Bridge drivers is used to automatically control the speed,
direction, and magnitude of current through the two coils of a two-phase
instrumentation step motor, similar to an MMT-licensed AFIC 6405.
IMPROVED GAUGE DRIVER
INTEGRATED CIRCUIT
The 33970 is ideal for use in automotive instrumentation systems requiring
distributed and flexible step motor gauge driving. The device also eases the
transition to step motors from air core motors by emulating the air core pointer
movement with little additional processor bandwidth utilization.
Features
• MMT-Licensed Two-Phase Step Motor Compatible
• Minimal Processor Overhead Required
• Fully Integrated Pointer Movement and Position State Machine with Air
Core Movement Emulation
DW SUFFIX
CASE 751E-04
24-LEAD SOICW
• 4096 Possible Steady State Pointer Positions
• 340° Maximum Pointer Sweep
ORDERING INFORMATION
Temperature
• Fixed Maximum Acceleration and Deceleration of 4500°/sec2
• Maximum Pointer Velocity of 400°/s
Device
Package
Range (T )
A
• Analog Microstepping (12 Steps/Degree of Pointer Movement)
• Pointer Calibration and Return to Zero
PC33970DW/R2
-40°C to 125°C
24 SOICW
• SPI-Controlled 16-Bit Word
• Calibratable Internal Clock
• Low Sleep Mode Current
• Backward Compatible with MC33991
• Improved Pointer Movement, Diagnostics, and Return to Zero (RTZ)
33970 Simplified Application Diagram
VPWR
33970
VPWR
SIN0+
SIN0-
VDD
5.0 V
VDD
Regulator
Motor 0
Motor 1
COS0+
COS0-
RTZ
RST
CS
SCLK
SI
SIN1+
SIN1-
MCU
COS1+
COS1-
SO
GND
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
For More Information On This Product,
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© Motorola, Inc. 2004
Freescale Semiconductor, Inc.
VPWR
Internal
VDD
Regulator
COS0+
COS0-
COS0
SIN0
CS
SCLK
SO
SIN0+
SIN0-
SPI
SI
COS1+
COS1-
COS1
RTZ
RTZ
RST
Logic
H-Bridge
SIN1+
SIN1-
and
Under-
and
ILIM
Control
Overvoltage
Detect
Overtemperature
Detect
SIN1
Oscillator
GND (8)
Figure 1. 33970 Simplified Internal Block Diagram
33970
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1
24
23
22
21
20
19
18
17
16
15
14
13
COS0+
COS0-
SIN0+
SIN0-
GND
GND
GND
GND
CS
COS1+
COS1-
SIN1+
SIN1-
GND
GND
GND
GND
2
3
4
5
6
7
8
9
V
PWR
10
11
12
SCLK
SO
RST
V
DD
SI
RTZ
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Formal Name
Definition
1
2
3
4
COS0+
COS0−
SIN0+
SIN0−
H-Bridge Outputs 0
Each pin is the output pin of a half bridge, designed to source or sink current.
The H-Bridge pins linearly drive the sine and cosine coils of two separate step
motors to provide four-quadrant operation.
5–8,
17–20
GND
Ground
These pins serve as the ground for the source of the low-side output transistors
as well as the logic portion of the device. They also help dissipate heat from the
device.
9
Chip Select
CS
This pin is connected to a chip select output of a LSI IC. This IC controls which
device is addressed by pulling the CS pin of the desire device low, enabling the
SPI communication with the device, while other devices on the serial link keep
their serial outputs tri-stated. This input has an internal active pull-up, requiring
CMOS logic levels. This pin is also used to calibrate the internal clock.
10
11
SCLK
SO
Serial Clock
Serial Output
This pin is connected to the SCLK pin of the master device and acts as a bit
clock for the SPI port. It transitions on time per bit transferred at an operating
frequency, fSPI, defined in the Coil Output Timing Table. It is idle between
command transfers. The pin is 50 percent duty cycle, with CMOS logic levels.
This signal is used to shift data to and from the device.
This pin is connected to the SPI Serial Data Input pin of the master device, or
to the SI pin of the next device in a daisy chain. This output will remain tri-stated
unless the device is selected by a low CS signal. The output signal generated
will have CMOS logic levels and the output will transition on the rising edges of
SCLK. The serial output data provides status feedback and fault information for
each output and is returned MSB first when the device is addressed.
12
13
SI
Serial Input
This pin is connected to the SPI Serial Data Output pin of the master device
from which it receives output command data. This input has an internal active
pull down requiring CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, controlling the gauge functions. The
master ensures data is available on the falling edge of SCLK.
RTZ
Multiplexed Output
This multiplexed output pin of the non-driven coil during a Return to Zero (RTZ)
event.
14
15
V
Voltage
Reset
This SPI and logic power supply input will work with 5.0 V supplies.
DD
RST
If the master decides to reset the device, or place it into a sleep state, the RST
pin is driven to a logic [0]. A logic [0] on the RST pin will force all internal logic
to the known default state. This input has an internal active pull-up.
16
V
Battery Voltage
Power supply.
PWR
21
22
23
24
SIN1−
SIN1+
COS1−
COS1+
H-Bridge Outputs 1
Each of this pins is the output pin of a half bridge, designed to source or sink
current. The H-Bridge pins linearly drive the sine and cosine coils of two
separate step motors to provide four-quadrant operation.
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Power Supply Voltage
Steady State
V
V
PWR(sus)
-0.3 to 41
-0.3 to 7.0
Input Pin Voltage (Note 1)
V
V
mA
°C
IN
SIN+/- COS+/- Continuous Per Output Current (Note 2)
Storage Temperature
I
40
OUTMAX
T
-55 to 150
-40 to 150
STG
Operating Junction Temperature
T
°C
J
Thermal Resistance
Junction to Ambient
Junction to Lead
°C/W
R
60
20
θJA
R
θJL
ESD Voltage
V
V
V
±2000
±200
ESD1
ESD2
Human Body Model (Note 3)
Machine Model (Note 4)
Notes
1. Exceeding voltage limits on Input pins may cause permanent damage to the device.
2. Output continuous output rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient temperature will
require maximum output current computation using package thermal resistances.
3. ESD1 testing is performed in accordance with the Human Body Model (C
= 100 pF, R
= 1500 Ω).
ZAP
ZAP
4. ESD2 testing is performed in accordance with the Machine Model (C
= 200 pF, R
= 0 Ω).
ZAP
ZAP
33970
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TJ < 150°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
V
V
Supply Voltage Range
Fully Operational
PWR
6.5
4.0
–
–
26
26
Limited Operational (Note 5), (Note 6)
I
mA
V
V
Supply Current
PWR(ON)
PWR
–
4.0
6.0
Gauge 1 and 2 Outputs ON, No Output Loads
Supply Current (All Outputs Disabled)
µA
PWR
I
–
–
42
15
60
25
PWSLP1
Reset = Logic [0], V
Reset = Logic [0], V
= 5.0 V
= 0 V
DD
DD
I
PWRSLP2
V
26
5.0
4.5
32
5.6
5.0
38
6.2
5.5
4.5
V
V
V
V
Overvoltage Detection Level (Note 7)
PWROV
PWRUV
V
Undervoltage Detection Level (Note 8)
V
Logic Supply Voltage Range (5.0 V Nominal Supply)
DD
V
Under V
Logic Reset
–
–
DDUV
DD
V
Supply Current
DD
I
–
–
40
1.0
65
1.8
µA
mA
DD(OFF)
Sleep: Reset Logic [0]
Outputs Enabled
I
DD(ON)
Notes
5. Outputs and logic remain active; however, the larger coil voltage levels may be clipped. The reduction in drive voltage may result in a loss
of position control.
6. The logic will reset at some level below the specified Limited Operational minimum.
7. Outputs will disable and must be re-enabled via the PECCR command.
8. Outputs remain active; however, the reduction in drive voltage may result in a loss of position control.
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TJ < 150°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUTS
V
Microstep Output (Measured Across Coil Outputs)
SIN0,1, ± (COS0,1, ±) (refer to PIN FUNCTION DESCRIPTION,
pp. 3–4)
R
= 200 Ω
OUT
Vst6
Vst5
Vst4
Vst3
Vst2
Vst1
Vst0
4.82
5.3
6.0
Steps 6, 18 (0, 12)
0.94 x Vst6
0.84 x Vst6
0.68 x Vst6
0.47 x Vst6
0.23 x Vst6
-0.1
0.97 x Vst6
0.87 x Vst6
0.71 x Vst6
0.50 x Vst6
0.26 x Vst6
0
1.0 x Vst6
0.96 x Vst6
0.8 x Vst6
0.57 x Vst6
0.31 x Vst6
0.1
Steps 5, 7, 17, 19 (1, 11, 13, 23)
Steps 4, 8, 16, 20 (2, 10, 14, 22)
Steps 3, 9, 15, 21 (3, 9, 15, 21)
Steps 2, 10, 14, 22 (4, 8,16, 20)
Steps 1, 11, 13, 23 (5, 7, 17, 19)
Steps 0, 12 (6, 18)
V
V
V
Full Step Active Output (Measured Across Coil Outputs)
SIN0, 1, ± (COS0, 1, ±) (see Figure 7, page 27)
FS
4.9
5.3
6.0
Steps 1, 3 (0, 2)
V
Microstep, Full Step Output (Measured from Coil Low Side to Ground)
LS
SIN0, 1, ± (COS0, 1, ±), I
= 30 mA
0
–
0.1
0.3
Vst1 + 1.0
170
OUT
V
Vst1 + 0.5
V
Output Flyback Clamp (Note 10)
Output Current Limit (Output = Vst6)
Overtemperature Shutdown (Note 9)
Overtemperature Hysteresis (Note 10)
CONTROL I/O
FB
I
40
155
8.0
100
–
mA
°C
°C
LIM
OT
SD
180
OT
–
16
HYST
V
2.0
–
–
–
–
V
V
Input Logic High Voltage (Note 11)
Input Logic Low Voltage (Note 11)
Input Logic Voltage Hysteresis (Note 12)
Input Logic Pull Down Current (SI, SCLK)
Input Logic Pull-Up Current (CS, RST)
IH
V
IL
0.8
–
V
–
100
–
mV
µA
µA
V
IN(HYST)
I
3.0
5.0
20
20
–
DWN
I
–
UP
V
0.8 V
DD
–
SO High-State Output Voltage (I
= 1.0 mA)
SOH
OH
V
–
-5.0
–
0.2
0
0.4
5.0
12
20
V
SO Low-State Output Voltage (I = -1.6 mA)
OL
SOL
I
µA
pF
pF
SO Tri-State Leakage Current (CS ≥ 3.5 V)
Input Capacitance (Note 13)
SO Tri-State Capacitance (Note 13)
Notes
SOLK
C
4.0
–
IN
C
–
SO
9. This parameter is guaranteed by design, but it is not production tested.
10. Not 100 percent tested
11. .V
= 5.0 V.
DD
12. This parameter is guaranteed by design, but it is not production tested.
13. Capacitance not measured. This parameter is guaranteed by design, but it is not production tested.
33970
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TJ < 150°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Units
POWER OUTPUT AND CLOCK TIMINGS
ms
ms
tDLY(ON)
SIN, COS Output Turn ON Delay Time (Time from Rising CS Enabling
Outputs to Steady State Coil Voltages and Currents) (Note 14)
–
–
1.0
tDLY(OFF)
SIN, COS Output Turn OFF Delay Time (Time from Rising CS Disables Outputs
to Steady State Coil Voltages and Currents) (Note 14)
–
–
1.0
1.7
0.65
1.0
µs
µs
tCLU
tCLC
Uncalibrated Oscillator Cycle Time
Calibrated Oscillator Cycle Time
1.0
0.9
1.1
1.0
1.2
1.1
Cal Pulse = 8.0 µs, PECCR D4 = Logic [0]
Cal pulse = 8.0 µs, PECCR D4 = Logic [1]
V
–
–
–
–
400
°/s
Maximum Pointer Speed (Note 15)
Maximum Pointer Acceleration (Note 15)
Notes
MAX
A
4500
MAX
°/s2
14. Maximum specified time for the 33970 is the minimum guaranteed time needed from the microcontroller.
15. The minimum and maximum value will vary proportionally to the internal clock tolerance. These numbers are based on an ideally calibrated
clock frequency of 1.0 MHz. These are not 100 percent tested.
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TJ < 150°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Units
(Note 16)
SPI INTERFACE TIMING
f
–
–
–
–
–
–
–
1.0
50
50
25
–
3.0
167
167
83
MHz
ns
Recommended Frequency of SPI Operation
SPI
t
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 17)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 17)
SI to Falling Edge of SCLK (Required Setup Time) (Note 17)
Required High State Duration of SCLK (Required Setup Time (Note 17)
Required Low State Duration of SCLK (Required Setup Time (Note 17)
Falling Edge of SCLK to SI (Required Hold Time) (Note 17)
SO Rise Time
LEAD
t
ns
LAG
tSISU
ns
t
167
167
83
ns
SCLK
w
h
t
–
ns
SCLK
w
l
tSI(
25
ns
HOLD)
t
ns
rSO
–
25
50
C = 200 pF
L
t
ns
SO Fall Time
fSO
–
–
–
–
–
25
–
50
50
C = 200 pF
L
t
ns
ns
µs
µs
SI, CS, SCLK, Incoming Signal Rise Time (Note 18)
rSI
t
–
50
SI, CS, SCLK, Incoming Signal Fall Time (Note 18)
fSI
t
–
3.0
5.0
Falling Edge of RST to Rising Edge of RST (Required Setup Time) (Note 17)
RST
w
tCS
–
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 17),
(Note 19)
t
–
–
–
–
–
5.0
145
4.0
µs
ns
µs
ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 17)
Time from Falling Edge of CS to SO Low Impedance (Note 20)
Time from Rising Edge of CS to SO High Impedance (Note 21)
Time from Rising Edge of SCLK to SO Data Valid (Note 22)
EN
t
SO(EN)
t
1.3
SO(DIS)
t
VALID
–
65
105
0.2 V ≤ SO ≥ 0.8 V , C = 200 pF
DD
DD
L
Notes
16. The device shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the temperature
range specified. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device shall
be fully functional for slower clock speeds.
17. The maximum setup time specified for the 33970 is the minimum time needed from the microcontroller to guarantee correct operation.
18. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
19. The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes.
20. Time required for output status data to be terminated at SO. 1.0 kΩ load on SO
21. Time required for output status data to be available for use at SO. 1.0 kΩ load on SO.
22. Time required to obtain valid data out from SO following the rise of SCLK.
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Timing Diagrams
VIN
VIL
RST
CS
0.2 VDD
tWRST
tCS
tEN
VIH
VIL
0.7 VDD
0.7 VDD
twSCLKh
trSI
tLAG
tLEAD
0.7 VDD
0.2 VDD
VIH
VIL
SCLK
SI
tLEAD
twSCLKl
tSI(HOLD)
tfSI
VIH
VIL
0.7 VDD
0.2 VDD
Don’t Care
Valid
Don’t Care
Valid
Don’t Care
Figure 2. Input Timing Switching Characteristics
trSI
tfSI
VOH
3.5 V
SCLK
50%
1.0 V
VOL
tSO(EN)
0.2 VDD
VOH
VOL
0.7 VDD
SO
Low-to-High
trSO
tVALID
SO
tfSO
VOH
VOL
0.7 VDD
tSO(DIS)
High-to-Low
0.2 VDD
Figure 3. Valid Data Delay Time and Valid Time Waveforms
33970
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
This 33970 is a single-packaged, Serial Peripheral Interface
The 33970 is ideal for use in automotive instrumentation
systems requiring distributed and flexible step motor gauge
driving. The device also eases the transition to step motors from
air core motors by emulating the air core pointer movement with
little additional processor bandwidth utilization.
(SPI) controlled, dual step motor gauge driver integrated circuit
(IC). This monolithic IC consists of four dual output H-Bridge
coil drivers and the associated control logic. Each pair of
H-Bridge drivers is used to automatically control the speed,
direction, and magnitude of current through the two coils of a
two-phase instrumentation step motor, similar to an
MMT-licensed AFIC 6405.
SPI PROTOCOL DESCRIPTION
The SPI interface has a full-duplex, three-wire synchronous,
16-bit serial synchronous interface data transfer and four I/O
lines associated with it (SI, SO, SCLK, and CS). The SI/SO pins
of the 33970 follow a first in/first out (D15/D0) protocol with both
input and output words transferring the most significant bit first.
All inputs are compatible with 5.0 V CMOS logic levels.
on the rising edge of the SCLK signal. It is important that the
SCLK pin be in a logic [0] state whenever the CS makes any
transition. SCLK has an internal pull down (lDWN), as specified
in the section of the Static Electrical Characteristics table
entitled CONTROL I/O, which is found on page 6. When CS is
logic [1], signals at the SCLK and SI pins are ignored and SO is
tri-stated (high impedance). Refer to the data transfer timing
diagrams in Figure 4 and Figure 5 on page 11.
Chip Select (CS)
The CS pin enables communication with the master device.
When this pin is in a logic [0] state, the 33970 is capable of
transferring information to, and receiving information from, the
master. The 33970 latches data in from the Input Shift registers
to the addressed registers on the rising edge of CS. The output
driver on the SO pin is enabled when CS is logic [0]. When CS
is logic high, signals at the SCLK and SI pins are ignored and
the SO pin is tri-stated (high impedance). CS will only be
transitioned from a logic [1] state to a logic [0] state when SCLK
is a logic [0]. CS has an internal pull-up (lUP) connected to the
pin, as specified in the section of the Static Electrical
Characteristics table entitled CONTROL I/O, which is found on
page 6.
Serial Input (SI)
The SI pin is the input of the Serial Peripheral Interface (SPI).
Serial Input (SI) information is read on the falling edge of SCLK.
A 16-bit stream of serial data is required on the SI pin,
beginning with the most significant bit (MSB). Messages that
are not multiples of 16 bits (e.g., daisy chained device
messages) are ignored. After transmitting a 16-bit word, the CS
pin must be de-asserted (logic [1]) before transmitting a new
word. SI information is ignored when CS is in a logic high state.
Serial Output (SO)
The SO data pin is a tri-stateable output from the Shift
register. The Status register bits are the first 16 bits shifted out.
Those bits are followed by the message bits clocked in FIFO,
when the device is in a daisy chain connection or being sent
words that are multiples of 16 bits. Data is shifted on the rising
edge of the SCLK signal. The SO pin will remain in a high
impedance state until the CS pin is put into a logic low state.
Serial Clock (SCLK)
SCLK clocks the Internal Shift registers of the 33970 device.
The Serial Input (SI) pin accepts data into the Input Shift
register on the falling edge of the SCLK signal, while the Serial
Output pin (SO) shifts data information out of the SO Line Driver
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TIMING DESCRIPTION
This section provides a description of the 33970 SPI
behavior. To follow the explanations below, refer to Table 1 and
to the timing diagrams shown in Figure 4 and Figure 5.
Table 1. Data Transfer Timing
Pin
Description
SO pin is enabled.
CS (1-to-0)
CS (0-to-1)
33970 configuration and desired output states are transferred and executed according to the data in the
Shift registers.
SO
SI
Will change state on the rising edge of the SCLK pin signal.
Will accept data on the falling edge of the SCLK pin signal.
CS
SCLK
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
SI
OD0
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
SO
Output shift register is loaded here.
Note SO is tri-stated when CS is logic [1].
Figure 4. Single 16-Bit Word SPI Communication
CS
SCLK
SI
D0*
D15
D14
D13
D2
D1
D0
D15*
D14*
D13*
D2*
D1*
D0
OD15
OD14
OD13
OD2
OD1
OD0
D15
D14
D13
D2
D1
SO
Notes 1. SO is tri-stated when CS is logic [1].
2. D15, D14, D13, ..., and D0 refer to the first 16 bits of data into the 33970.
3. D15*, D14*, D13*, ..., and D0* refer to the most recent entry of program data into the 33970.
4. OD15, OD14, OD13, ..., and OD0 refer to the first 16 bits of fault and status data out of the 33970.
Figure 5. Multiple 16-Bit Word SPI Communication
capture the data from the Input Shift register and transfer it to
the internal registers.
Data Input
The Input Shift register captures data at the falling edge of
the SCLK clock. The SCLK clock pulses exactly 16 times only
inside the transmission windows (CS in a logic [0] state). By the
time the CS signal goes to logic [1] again, the contents of the
Input Shift register are transferred to the appropriate internal
register, to the address contained in bits 15:13. The minimum
time CS should be kept high depends on the internal clock
speed. That data is specified in the SPI INTERFACE TIMING
section of the Static Electrical Characteristics, which is found on
page 6. It must be long enough so the internal clock is able to
Data Output
At the first rising edge of the SCLK clock, with the CS at
logic [0], the contents of the selected Status Word register are
transferred to the Output Shift register. The first 16 bits clocked
out are the status bits. If data continues to clock in before the
CS transitions to a logic [1], the device begins to shift out the
data previously clocked in FIFO after the CS first transitioned to
logic [0].
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COMMUNICATION MEMORY MAPS AND REGISTER DESCRIPTIONS
The 33970 device is capable of interfacing directly with a
Table 2 provides the registers available to control the above
microcontroller via the 16-bit SPI protocol described and
specified below. The device is controlled by the microprocessor
and reports back status information via the SPI. This section
provides a detailed description of all registers accessible via
serial interface. The various registers control the behavior of
this device.
functions.
Table 2. Module Memory Map
Address
[15:13]
Register
Name
See Page
000
Power, Enable, Calibration,
and Configuration Register
PECCR
Page 12
A message is transmitted by the master beginning with the
MSB (D15) and ending with the LSB (D0). Multiple messages
can be transmitted in succession to accommodate those
applications where daisy chaining is desirable, or to confirm
transmitted data, as long as the messages are all multiples of
16 bits. Data is transferred through daisy-chained devices, as
illustrated in Figure 5, page 11. If an attempt is made to latch in
a message smaller than 16 bits wide, it is ignored.
001
010
011
100
101
Maximum Velocity Register
Gauge 0 Position Register
Gauge 1 Position Register
Gauge Return to 0 Register
VELR
POS0R
POS1R
RTZR
Page 14
Page 15
Page 15
Page 15
Page 16
Gauge Return to 0
Configuration Register
RTZCR
The 33970 uses six registers to configure the device, control
the state of the four H-bridge outputs, and determine the type of
status information that is clocked back to the master. The
registers are addressed via D15:D13 of the incoming SPI word
(refer to Table 2).
110
111
Not Used
–
–
–
–
Reserved for Test
Register Descriptions
The following section describes the registers, their
addresses, and their impact on device operation.
Module Memory Map
Various registers of the 33970 SPI module are addressed by
the three MSBs of the 16-bit word received serially. Functions
to be controlled include:
Address 000—Power, Enable, Calibration, and
Configuration Register (PECCR)
• Individual gauge drive enabling
• Power-up/down
• Internal clock calibration
• Gauge pointer position and velocity
• Gauge pointer zeroing
• Air core motor movement emulation
• Status information
The Power, Enable, Calibration, and Configuration Register
is illustrated in Table 3, page 13. A write to the 33970 using this
register allows the master to (1) independently enable or
disable the output drivers of the two-gauge controllers, (2)
calibrate the internal clock, (3) disable the air core emulation,
(4) select the direction of the pointer movement during pointer
positioning and zeroing, (5) configure the device for the desired
status information to be clocked out into the SO pin, or (6) send
a null command for the purpose of reading the status bits. This
register is also used to place the 33970 into a low current
consumption mode.
Status reporting includes:
• Individual gauge overtemperature condition
• Battery overvoltage
• Battery undervoltage
• Pointer zeroing status
Each of the gauge drivers can be enabled by writing a
logic [1] to their assigned address bits, PE0 and PE1
respectively. This feature could be used to disable a driver if it
is failing or is not being used. The device can be placed into a
standby current mode by writing a logic [0] to both PE0 and
PE1. During this state, most current consuming circuits are
biased off. When in the Standby mode, the internal clock will
remain ON.
• Internal clock status
• Confirmation of coil output changes that should result in
pointer movement
• Real time pointer position information
• Real time pointer velocity step information
• Pointer movement direction
• Command pointer position status
• RTZ accumulator value
The internal state machine utilizes a ROM table of step times
defining the duration that the motor will spend at each microstep
as it accelerates or decelerates to a commanded position. The
accuracy of the acceleration and velocity of the motor is directly
related to the accuracy of the internal clock. Although the
accuracy of the internal clock is temperature independent, the
non-calibrated tolerance is +70% to -35%. The 33970 was
designed with a feature allowing the internal clock to be
software calibrated to a tighter tolerance of ±10%, using the CS
pin and a reference time pulse provided by the microcontroller.
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Calibration of the internal clock is initiated by writing a
Bit D6 is logic [0] during a PECCR commands.
logic [1] to PE3. The calibration pulse, which must be 8.0 µs for
an internal clock speed of 1.0 MHz, will be sent on the CS pin
immediately after the SPI word is sent. No other SPI lines will
be toggled. A clock calibration will be allowed only if the gauges
are disabled or the pointers are not moving, as indicated by
status bits MOV0 and MOV1. Additional details are provided in
the Internal Clock Calibration section, beginning on page 26.
The default Pointer Position 0 (PE7 = 0) will be the farthest
counter-clockwise position. A logic [1] written to bit PE7 will
change the location of the position 0, for the Gauge selected by
bit PE8, to the farthest clockwise position. A change in position
0 of only one, or both, of the two coils can be accomplished by
using bits PE8 and PE7. Performing an RTZ will always move
the pointer to position 0. Exercise care when writing to PECCR
bits PE8 and PE7 in order to prevent accidental changes of the
position 0 locations.
Some applications may require a guaranteed maximum
pointer velocity and acceleration. Guaranteeing these
maximums requires that the nominal internal clock frequency
fall below 1.0 MHz. The frequency range of the calibrated clock
will always be below 1.0 MHz if bit PE4 is logic [0] when
initiating a calibration command, followed by an 8.0 µs
reference pulse. The frequency will be centered at 1.0 MHz if bit
PE4 is logic [1].
Bits PE11:PE8 determine the content of the bits clocked out
of the SO pin. When bit PE11 is at logic [0], the clocked out bits
will provide device status. If a logic [1] is written to bit PE11, the
bits clocked out of the SO pin, depending upon the state of bits
PE10:PE8, provides either:
• Accumulator information and detection status during the
RTZ (PE10 logic [0])
Some applications may require a slower calibrated clock due
to a lower motor gear reduction ratio. Writing a logic [1] to bit
PE2 will slow the internal oscillator by one-third. Slowing the
clock accommodates a longer calibration pulse without
overrunning the internal counter—a condition designed to
generate a CAL fault indication. For example, calibration for a
clock frequency of 667 kHz would require a calibration pulse of
12 µs. Unless the internal oscillator is slowed by writing PE2 to
logic [1], a 12 µs calibration pulse may overrun the counter and
generate a CAL fault indication.
• Real time pointer position location at the time CS goes low
(PE10 logic [1] and PE9 logic [0]), or
• The real time step position of the pointer as described in
the velocity Table 17, page 24 (PE10, PE9, and PE8
logic [1]).
Additional details are provided in the SO Communication
section beginning on page 18.
If bit PE12 is logic [1] during a PECCR command, the state
of PE11:PE0 is ignored. This is referred to as the null command
and can be used to read device status without affecting device
operation.
Some applications may require faster pointer positioning
than is provided with the air core motor emulation feature. This
feature is enabled with the device that is in the default mode.
Writing logic [1] to bit PE5 will disable the air core emulation and
provide a constant acceleration and deceleration at the
maximum rate.
Table 3. Power, Enable, Calibration, and Configuration Register (PECCR)
Address 000
Bits
Read
Write
D12
–
D11
–
D10
–
D9
–
D8
–
D7
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
–
PE12
PE11
PE10
PE9
PE8
PE7
0
PE5
PE4
PE3
PE2
PE1
PE0
The bits in Table 3 are write-only.
PE9 (D9)—Pointer Position or Pointer Speed Select bit. This
bit is recognized only if PE11 and PE10 = 1.
• 0 = Gauge 0 or Gauge 1 Pointer Position
• 1 = Gauge 0 and Gauge 1 Pointer Speed
PE12 (D12)—Null Command for Status Read
• 0 = Disable
• 1 = Enable
PE8 (D8)—Pointer Position Gauge Select bit. Also the
Position 0 of the selected gauge is determined by the PE7
selection. This bit is recognized only if PE11 and PE10 = 1 and
PE9 = 0.
PE11 (D11) —Status Select bit. This bit selects the
information clocked out of the SO pin.
• 0 = Device Status (the logic states of PE10, PE9, and PE8
don’t cares)
• 0 = Gauge 0 position
• 1 = Gauge 1 position
• 1 = RTZ Accumulator Value, Gauge 0 or 1 Pointer
position, or Gauge 0 and 1 Velocity ramp position
(depending upon the logic states of PE10, PE9, and
PE8)
PE7 (D7)—Position 0 Location Select bit. This bit
determines the Position 0 of the gauge selected by PE8. RTZ
direction will always be to the position 0.
PE10 (D10)—RTZ Accumulator or Pointer Status Select bit.
This bit is recognized only when PE11 = 1.
• 0 = RTZ Accumulator Value and status
• 1 = Pointer Position or Speed
• 0 = Position 0 is the most CCW (counterclockwise)
position
• 1 = Position 0 is the most CW (clockwise) position
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PE6 (D6)—This bit must be transmitted as logic [0] for valid
PE2 (D2)—Oscillator Adjustment
• 0 = tCLU
PECCR commands.
• 1 = 0.66 x tCLU
PE5 (D5)—Air Core Motor Emulation bit. This bit is enabled
or disabled (acceleration and deceleration is constant if
PE1 (D1)—Gauge 1 Enable bit. This bit enables or disables
disabled).
the output driver of Gauge 1.
• 0 = Disable
• 0 = Enable
• 1 = Disable
• 1 = Enable
PE4 (D4)—Clock Calibration Frequency Selector
• 0 = Maximum f =1.0 MHz (for 8.0 µs calibration pulse)
• 1 = Nominal f =1.0 MHz (for 8.0 µs calibration pulse)
PE0 (D0)—Gauge 0 Enable bit. This bit enables or disables
the output driver of Gauge 0.
• 0 = Disable
• 1 = Enable
PE3 (D3)—Clock Calibration Enable bit. This bit enables or
disables the clock calibration.
• 0 = Disable
• 1 = Enable
Address 001—Maximum Velocity Register (VELR)
The Gauge Maximum Velocity Register is used to set a
maximum velocity for each gauge (refer to Table 4). Bits V7:V0
contain a position value from 1–225 that is representative of the
velocity position value described in Table 17, Velocity Table,
page 24. The table value becomes the maximum velocity until
it is changed to another value. If a maximum value is chosen
greater than the maximum velocity in the acceleration table, the
maximum table value becomes the maximum velocity. If the
motor is turning at a speed greater than the new maximum, the
motor immediately moves down the velocity ramp until the
speed falls equal to or below it. Velocity for each motor can be
changed simultaneously or independently by writing V8 and/or
V9 to a logic [1]. Bits V12:V10 must be at logic [0] for valid
VELR commands.
Table 4. Maximum Velocity Register (VELR)
Address 001
Bits
Read
Write
D12
–
D11
–
D10
–
D9
–
D8
–
D7
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
–
0
0
0
V9
V8
V7
V6
V5
V4
V3
V2
V1
V0
The bits in Table 4 are write-only.
V8 (D8) — Gauge 0 Velocity. Specifies whether the
maximum velocity specified in the V7: V0 field will apply to
Gauge 0.
V12:V10 (D12:D10)—These bits must be transmitted as
logic [0] for valid VELR commands
• 0 = Velocity does not apply to Gauge 0
• 1 = Velocity applies to Gauge 0
V9 (D9) —Gauge 1 Velocity. Specifies whether the
maximum velocity determined in the V7: V0 field will apply to
Gauge 1.
V7:V0 (D7:D0)—Maximum Velocity. Specifies the maximum
velocity position from Table 17, page 24. This velocity will
remain the maximum of the intended gauge until changed by
command. Velocities can range from position 1 (00000001) to
position 225 (11111111).
• 0 = Velocity does not apply to Gauge 1
• 1 = Velocity applies to Gauge 1
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Addresses 010 and 011—Gauge 0/1 Position Registers (POS0R, POS1R)
Gauge 0 Position Register (SI Addresses 010) bits
P011:P00 are written to when communicating the desired
pointer positions, and Gauge 1 Position Register (SI Address
011) bits P111:P10 are written to when communicating the
desired pointer positions. Commanded positions can range
from 0 to 4095. The D12 bit must be at logic [0] for valid POS0R
and POS1R commands.
Table 5. Gauge 0 Position Register (POS0R)
Address 010
Bits
Read
Write
D12
–
D11
–
D10
–
D9
–
D8
–
D7
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
–
0
P011
P010
P09
P08
P07
P06
P05
P04
P03
P02
P01
P00
The bits in Table 5 are write-only.
P011:P00 (D11:D0)—Desired pointer position of Gauge 0.
Pointer positions can range from 0 (000000000000) to position
4095 (111111111111). For a step motor requiring
12 microsteps per degree of pointer movement, the maximum
pointer sweep is 341.25°.
P012 (D12)—This bit must be transmitted as logic [0] for
valid commands.
.
Table 6. Gauge 1 Position Register (POS1R)
Address 011
Bits
Read
Write
D12
–
D11
–
D10
–
D9
–
D8
–
D7
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
–
0
P111
P110
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
The bits in Table 6 are write-only.
P111:P10 (D11:D0)—Desired pointer position of Gauge 1.
Pointer positions can range from 0 (000000000000) to position
4095 (111111111111). For a step motor requiring
12 microsteps per degree of pointer movement, the maximum
pointer sweep is 341.25°.
P112 (D12)—This bit must be transmitted as logic [0] for
valid commands.
Address 100—Gauge Return to Zero Register (RTZR)
Gauge Return to Zero Register (RTZR) (refer to Table 7) is
written to return the gauge pointers to the zero position. During
an RTZ event, the pointer is returned to zero using full steps,
where only one coil is driven at any point in time. The back
electromotive force (EMF) signal present on the non-driven coil
is integrated and its results are stored in an accumulator.
Return to Zero for Gauge 0 when RZ0 is logic [0], and Gauge 1
when RZ0 is logic [1], respectively.
Bits D12:D5 and D3:D2 must be at logic [0] for valid RTZR
commands.
Bit RZ4 is used to enable an unconditional RTZ event. A
logic [0] results in a typical RTZ event, automatically providing
a Stop when a stall condition is detected. A logic [1] will result
in RTZ movement, causing a Stop if a logic [0] is written to bit
RZ0. This feature is useful during development and
characterization of RTZ requirements.
A logic [1] written to bit RZ1 enables a Return to Zero for
Gauge 0 if RZ0 is logic [0], and Gauge 1 if RZ0 is logic [1],
respectively. Similarly, a logic [0] written to bit RZ1 disables a
Table 7. Return to Zero Register (RTZR)
Address 100
Bits
Read
Write
D12
–
D11
–
D10
–
D9
–
D8
–
D7
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
–
0
0
0
0
0
0
0
0
RZ4
0
RZ2
RZ1
RZ0
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The register bits in Table 7 are write-only.
RZ2 (D2)—Return to Zero Direction bit. This bit is used to
properly sequence the integrator, depending upon the desired
zeroing direction.
RZ12:RZ5 (D12:D5)—These bits must be transmitted as
logic [0] for valid commands.
• 0 = Return to Zero will occur in the CCW direction
(PE7 = 0)
• 1 = Return to Zero will occur in the CW direction (PE7 = 1)
RZ4 (D4)—This bit is used to enable an unconditional RTZ
event.
• 0 = Automatic Return to Zero
• 1 = Unconditional Return to Zero
RZ1 (D1)—Return to Zero Direction. This bit commands the
selected gauge to return the pointer to zero position.
• 0 = Return to Zero Disabled
RZ3 (D3)—This bit must be transmitted as logic [0] for valid
commands.
• 1 = Return to Zero Enabled
RZ0 (D0)—Gauge Select: Gauge 0/Gauge 1. This bit selects
the gauge to be commanded.
• 0 = Selects Gauge 0
• 1 = Selects Gauge 1
Address 101—Gauge Return to Zero Configuration Register
Gauge Return to Zero Configuration Register (RTZCR) is
used to configure the Return to Zero Event (refer to Table 8,
page 17). It is written to modify the step time, or rate; at which
the pointer moves during an RTZ event. Also, the integration
blanking time, which is the time immediately following the
transition of a coil from a driven state to an open state in the
RTZ mode, is adjustable with this command. Finally, this
command is used to adjust the threshold of the RTZ integration
register.
When D3:D0 (RC3:RC0) = 0000
Full Step (t) = blanking (t) + 2.048 ms (2)
Note In equation (2), a 2.048 ms offset is added to the full
step time when the RC:3:RC0 = 0000. The full step time default
value after a logic reset is 12.80 ms (RC12:RC11 = 00,
RC4 = 0, and RC3:RC0 = 0011).
If there are two full steps per degree of pointer movement,
the pointer speed is 1/(FullStep x 2) deg/s.
The values used for this register should be selected during
development to optimize the RTZ for each application.
Selecting an RTZ step rate resulting in consistently successful
zero detections depends on a clear understanding of the motor
characteristics. Specifically, resonant frequencies exist due to
the interaction between the motor and the pointer. This
command allows movement of the RTZ pointer speed away
from these frequencies. Also, some motors require a significant
amount of time for the pointer to settle to a steady state position
when moving from one full step position to the next. Consistent
and accurate integration values require the pointer be
stationary at the end of the full step time.
Detecting pointer movement is accomplished by integrating
the EMF present in the non-driven coil during the RTZ event.
The integration circuitry is implemented using a Sigma-Delta
converter resulting in the placement of a value in the 15-bit RTZ
accumulator at the end of each full step. The value in the RTZ
accumulator represents the change in flux and is compared to
a threshold. Values above the threshold indicate a pointer is
moving. Values below the threshold indicate a stalled pointer,
thereby resulting in the cessation of the RTZ event.
The RTZ accumulator bits are signed and represented in
two’s complement. After a full step of integration, a sign bit of 0
is the indicator of an accumulator exceeding the decision
threshold of 0, and the pointer is assumed to still be moving.
Similarly, if the sign bit is logic [1] after a full step of integration,
the accumulator value is negative and the pointer is assumed
to be stopped. The integrator and accumulator are initialized
after each full step. If the PECCR command is written to clock
out the RTZ accumulator values via the SO, the OD14 bit
corresponds to the sign bit of the RTZ accumulator.
Bits RC3:RC0, RC12:RC11, and RC4 determine the time
spent at each full step during an RTZ event. Bits RC3:RC0 are
used to select a ∆t ranging from 0 ms (0000) to 61.44 ms (1111)
in increments of 4.096 ms (refer to Table 9, page 17). The ∆t is
multiplied by the factor M, when selected is using bits
RC12:RC11. The product is then added to the blanking time,
selected using bit RC4, to generate the full step time. The
multiplier selected with RC12:RC11 will be 1 (00), 2 (01), 4 (10),
or 8 (11) as illustrated in the equations below. The blanking time
that is selected with bit RC4 determines the time that is
provided immediately following a full step change, before
enabling the integration of the non-driven coil signal. The
blanking time is either 512 µs when RC4 is logic [0], or 768 µs
when it is logic [1].The full step time is generated using the
following equations:
Accurate pointer stall detection depends on a correctly
preloaded accumulator for specific gauge, pointer, and full step
combinations. Bits RC10:RC5 are used to offset the initial RTZ
accumulator value, properly detecting a stalled motor. The
initial accumulator value at the start of a full step of integration
is negative. If the accumulator was correctly preloaded, a free-
moving pointer will result in a positive value at the end of the
integration time, and a stalled pointer will result in a negative
value. The preloaded values associated with each combination
of bits RC10:RC5 are illustrated in Table 10, page 17. The
accumulator should be loaded with a value resulting in an
accumulator MSB to a logic [1] when the motor is stalled. For
When D3:D0 (RC3:RC0) ≠ 0000
Full Step (t) = ∆t x M + blanking (t) (1)
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the default mode, after a power-up or any reset, the 33970
.
device sets the accumulator value to -1, resulting in an
unconditional RTZ pointer movement until it is increased.
Table 8. RTZCR SI Register Assignment
Address 101
Bits
Read
Write
D12
–
D11
–
D10
–
D9
–
D8
–
D7
–
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
RC12
RC11
RC10
RC9
RC8
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
The bits in Table 8 are write-only.
Table 9. RTZCR Full Step Time
RC12:RC11 (D12:D11)— These bits, along with RC3:RC0
(D3:D0) and RC4 (D4), determine the full step time and,
therefore, the rate at which the pointer will move during an RTZ
event. The values of D12:D11 determine the multiplier (M) is
used in equation (1) (refer to page 16).
RC3
0
RC2
0
RC1
0
RC0
0
∆t (ms)
0
0
0
0
1
4.096
0
0
1
0
8.192
RD12:RC11 = M
• 00 = 1
0
0
1
1
12.288
16.384
20.480
24.576
28.672
32.768
36.864
40.960
45.056
49.152
53.248
57.344
61.440
0
1
0
0
• 01 = 2
0
1
0
1
• 10 = 4
• 11 = 8
0
1
1
0
RC10:RC5 (D10:D5)—These bits determine the value
preloaded into the RTZ integration accumulator to adjust the
detection threshold. Values range from -1 (00000000) to -4081
(11111111) as shown in Table 10.
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
RC4 (D4)—This bit determines the RTZ blanking time
(blanking (t)).
• 0 = 512 µs
• 1 = 768 µs
1
0
1
1
1
1
0
0
1
1
0
1
RC3:RC0 (D3:D0)—These bits, along with RC12:RC11
(D12:D11) and RC4 (D4), determine the time variables used to
calculate the full step times with equations (1) or (2) illustrated
above. RC3:RC0 determines the ∆t time. The ∆t values range
from 0 (0000) to 61.440 ms (1111) and are shown in Table 9.
The default ∆t is 0 (0011).
1
1
1
0
1
1
1
1
Note Equation (2) (refer to page 16) is only used to
calculate the full step time if RC3:RC0 = 0000. Use equation (1)
for all other combinations of RC3:RC0.
Table 10. RTZCR Accumulator Offset
Preload Value
Initial Accumulator
Value = (-16xPV)-1
RC10
RC9
RC8
RC7
RC6
RC5
(PV)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
2
3
4
-1
-17
-33
-49
-65
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
63
-1009
33970
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useful for daisy-chaining devices as well as message
SO Communication
verification.
When the CS pin is pulled low, the internal status register, as
configured with the PECCR command bits PE11:PE8, is loaded
into the output register and the data is clocked out MSB (OD15)
first. Following a CS transition 0 to 1, the device determines if
the shifted-in message was of a valid length (a valid message
length is one that is greater than 0 bits and a multiple of 16 bits),
and if so, latches the incoming data into the appropriate
registers.
As described above, the last valid write to bits PE11:PE8 of
the PECCR command determines the nature of the status data
that is clocked out of the SO pin.
There are five different types of status information available:
1. Device Status (refer to Table 11 below)
2. RTZ Accumulator Status (refer to Table 12, page 20)
3. Gauge 0 Pointer Position Status (refer to Table 13,
At this time, the SO pin is tri-stated and the status register is
now able to accept new status information. Fault status
information will be latched and held until the Device Status
Output register is selected and it is clocked out via the SO. If the
message length was determined to be invalid, the fault
information will not be cleared and will be transmitted again
during the next valid SPI message. Pointer status information
bits (e.g., pointer position, velocity, and commanded position
status) will always reflect the real time state of the pointer.
page 20)
4. Gauge 1 Pointer Position Status (refer to Table 14,
page 21)
5. Gauge 1 and 2 Pointer Velocity Status (refer to Table 15,
page 21)
Once a specific status type is selected, it will not change until
either the PECCR command bits PE11:PE8 (D11:D8) are
written to select another or the device is reset. Each of the
Status types and the PECCR bit necessary to select them are
described below.
Any bits clocked out of the SO pin after the first 16 are
representative of the initial message bits clocked into the SI pin
since the CS pin first transitioned to a logic [0]. This feature is
Device Status Information
Most recent valid PECCR command resulting in the Device
Status output:
D10
D9
D8
D11
0
x
x
x
x = Don’t care.
Table 11. Device Status Output Register
Bits OD15 OD14 OD13
OD12 OD11 OD10 OD9
OD8
UV
–
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OT1
–
OD0
OT0
–
Read DIR1
Write
DIR0 0POS1 0POS0 CMD1 CMD0
OV
–
CAL OVUV MOV1 MOV0 RTZ1 RTZ0
–
–
–
–
–
–
–
–
–
–
–
–
The bits in Table 11 are read-only bits.
CMD1 (OD11)—This bit indicates whether Gauge 1 is at the
most recently commanded position.
DIR1 (OD15)—This bit indicates the direction Gauge 1
pointer is moving.
• 0 = At commanded position
• 1 = Not at commanded position
• 0 = Toward position 0
• 1 = Away from position 0
CMD0 (OD10)—This bit indicates whether Gauge 0 is at the
most recently commanded position.
DIR0 (OD14)—This bit indicates the direction Gauge 0
pointer is moving.
• 0 = At commanded position
• 1 = Not at commanded position
• 0 = Toward position 0
• 1 = Away from position 0
OV (OD9)—Overvoltage Indication. A logic [1] on this bit
indicates VPWR voltage exceeded the upper limit of VPWROV
since the last SPI communication (refer to the Static Electrical
Characteristics table under POWER INPUT, page 5). An
overvoltage event will automatically disable the driver outputs.
Because the pointer may not be in the expected position, the
master may want to re-calibrate the pointer position with an
RTZ command after the voltage returns to a normal level. For
an overvoltage event, both gauges must be re-enabled as
quickly as this flag returns to logic [0]. The state machine will
0POS1 (OD13)—This bit indicates the configured Position 0
for Gauge 1.
• 0 = Farthest CCW
• 1 = Farthest CW
0POS1 (OD12)—This bit indicates the configured Position 0
for Gauge 1.
• 0 = Farthest CCW
• 1 = Farthest CW
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continue to operate properly as long as VDD is within the normal
range.
MOV0 (OD4)—Gauge 0 Movement Since last SPI
Communication. A logic [1] on this bit indicates the Gauge 1
pointer position has changed since the last SPI command. This
information allows the master to confirm the pointer is moving
as commanded.
• 0 = Normal range
• 1 = Battery voltage exceeded VPWROV
UV (OD8) —Undervoltage Indication. A logic 1] on this bit
indicates the VPWR voltage fell below VPWRUV since the last SPI
communication (refer to the Static Electrical Characteristics
table under POWER INPUT, page 5). An undervoltage event is
just flagged; however, at some voltage level below 4.0 V, the
outputs turn OFF and the state machine resets. Because the
pointer may not be in the expected position, the master may
want to re-calibrate the pointer position with an RTZ command
after the voltage returns to a normal level. For an undervoltage
event, both gauges may need to be re-enabled as quickly as
this flag returns to logic [0]. The state machine will continue to
operate properly as long as VDD is within the normal range.
• 0 = Normal range
• 0 = Gauge 0 position has not changed since the last SPI
command
• 1 = Gauge 0 pointer position has changed since the last
SPI command
RTZ1 (OD3)—RTZ1 Is Enabled or Disabled. A logic [1] on
this bit indicates Gauge 1 is in the process of returning to the
zero position as requested with the RTZ command. This bit will
continue to indicate a logic [1] until the SPI message following
a detection of the zero position, or the RTZ feature is
commanded OFF using the RTZ message.
• 0 = Return to Zero disabled
• 1 = Return to Zero enabled successfully
• 1 = Battery voltage fell below VPWRUV
RTZ0 (OD2) —RTZ0 Is Enabled or Disabled. A logic [1] on
this bit indicates Gauge 0 is in the process of returning to the
zero position as requested with the RTZ command. This bit
continues to indicate a logic [1] until the SPI message following
a detection of the zero position, or the RTZ feature is
commanded OFF using the RTZ message.
CAL (OD7)—Calibrated Clock out of Specification. A
logic [1] on this bit indicates the clock count calibrated to a value
outside the expected range given the tolerance specified by
t
CLC in the Dynamic Electrical Characteristics table under
POWER OUTPUT AND CLOCK TIMINGS, page 7.
• 0 = Clock within spec
• 0 = Return to Zero disabled
• 1 = Return to Zero enabled successfully
• 1 = Clock out of spec
OT1 (OD1)—Gauge 1 Junction Overtemperature. A logic [1]
on this bit indicates that the coil drive circuitry dedicated to drive
Gauge 1 has exceeded the maximum allowable junction
temperature since the last SPI communication and that
Gauge 1 has been disabled. It is recommended that the pointer
be re-calibrated using the RTZ command after re-enabling the
gauge using the PECCR command. This bit remains logic [1]
until the gauge is enabled.
OVUV (OD6) —Undervoltage or Overvoltage Indication. A
logic [1] on this bit indicates the VPWR voltage fell to a level
below the VPWRUV since the last SPI communication (refer to
the Static Electrical Characteristics table under POWER
INPUT, page 5). An undervoltage event is just flagged, while an
overvoltage event automatically disables the drive outputs.
Because the pointer may not be in the expected position, the
master may want to re-calibrate the pointer with an RTZ
command after the voltage returns to normal level. For an
overvoltage event, both gauges must be re-enabled as soon as
this flag returns to logic [0]. The state machine will continue to
operate properly as long as VDD is within the normal range.
• 0 = Normal range
• 0 = Temperature within range
• 1 = Gauge 1 maximum allowable junction temperature
condition has been reached
OT0 (OD0)—Gauge 0 Junction Overtemperature. A logic [1]
on this bit indicates that the coil drive circuitry dedicated to drive
Gauge 0 has exceeded the maximum allowable junction
temperature since the last SPI communication and that
Gauge 0 has been disabled. It is recommended that the pointer
be re-calibrated using the RTZ command after re-enabling the
gauge using the PECCR command. This bit remains logic [1]
until the gauge is re-enabled.
• 1 = Battery voltage fell below VPWRUV or exceeded
VPWROV
MOV1 (OD5) —This bit identifies Gauge 1 Movement since
last SPI communication. A logic [1] on this bit indicates the
Gauge 1 pointer position changed since the last SPI command.
This information allows the master to confirm the pointer is
moving as commanded.
• 0 = Temperature within range
• 1 = Gauge 0 maximum allowable junction temperature
condition is reached
• 0 = Gauge 1 position has not changed since the last SPI
command
• 1 = Gauge 1 pointer position has changed since the last
SPI command
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RTZ Accumulator Status Information
Most recent valid PECCR command resulting in the RTZ
Accumulator status output:
D10
D9
D8
D11
1
0
x
x
x = Don’t care.
Table 12. RTZ Accumulator Status Output Register
Bits
Read
Write
OD15
RTZ
–
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
ACC14 ACC13 ACC12 ACC11 ACC10 ACC9 ACC8 ACC7 ACC6 ACC5 ACC4 ACC3 AC2C ACC1 ACC0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
The bits in Table 12 are read-only bits.
ACC14:ACC0 (OD14:OD0)—These 15 bits are from the
RTZ accumulator. They represent the integrated signal present
on the non-driven coil during an RTZ event. These bits are logic
[0] after power-on reset, or after the RST pin transitions from
logic [0] to [1]. After an RTZ event, they will represent the last
RTZ accumulator result before the RTZ was stopped. ACC14 is
the MSB and is the sign bit used for zero detection.
RTZ (OD15)—RTZ Bit Is Enabled or Disabled. A logic [1] on
this bit indicates that the Gauge is in the process of returning to
the zero position as requested with the RTZ command. This bit
will continue to indicate a logic [1] until the SPI message
following a detection of the zero position, or the RTZ feature is
commanded OFF using the RTZ message.
• 0 = Return to Zero disabled
• 1 = Return to Zero enabled successfully
Gauge 0 Pointer Position Status Information
Most recent valid PECCR command resulting in the Gauge 0
Pointer Position status output:
D10
D9
D8
D11
1
1
0
0
Table 13. Gauge 0 Pointer Position Status Output Register
Bits
Read ENB0
Write
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
DIR0
–
DIRC0 CMD0 POS11 POS10 POS9 POS8 POS7 POS6 POS5 POS4 POS3 POS2 POS1 POS0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
The bits in Table 13 are read-only bits.
ENB0 (OD15)—This bit indicates whether Gauge 0 is
• 0 = Direction of the pointer movement is toward the
commanded position
• 1 = Direction of the pointer movement is away from the
commanded position
enabled.
• 0 = Disabled
• 1 = Enabled
CMD0 (OD12)—This bit indicates whether Gauge 0 is at the
most recently commanded position.
• 0 = At commanded position
DIR0 (OD14)—This bit indicates the direction Gauge 0 is
moving.
• 1 = Not at commanded position
• 0 = Toward position 0
• 1 = Away from position 0
POS11:POS0 (OD11:OD0)—These 12 bits represent the
actual position of the pointer at the time CS transitions to a
logic [0].
DIRC0 (OD13)—This bit is used to determine whether the
direction of the most recent pointer movement is toward the last
commanded position or away from it.
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Gauge 1 Pointer Position Status Information
Most recent valid PECCR command resulting in the Gauge 1
Pointer Velocity status output:
D10
D9
D8
D11
1
1
0
1
Table 14. Gauge 1 Pointer Position Status Output Register
Bits
Read ENB1
Write
OD15
OD14
OD13
OD12
OD11
OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
DIR1
–
DIRC1 CMD1 POS11 POS10 POS9 POS8 POS7 POS6 POS5 POS4 POS3 POS2 POS1 POS0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
The bits in Table 14 are read-only bits.
CMD1 (OD12)—This bit indicates if Gauge 1 is at the most
recently commanded position.
• 0 = At commanded position
• 1 = Not at commanded position
ENB1 (OD15)—This bit indicates if Gauge 1 is enabled.
• 0 = Disabled
• 1 = Enabled
POS11:POS0 (OD11:OD0)—These 12 bits represent the
actual position of the pointer at the time CS transitions to a
logic [0].
DIR1 (OD14)—This bit indicates the direction Gauge 1
pointer is moving.
• 0 = Toward position 0
• 1 = Away from position 0
DIRC1 (OD13)—This bit determines if the direction of the
most recent pointer movement is toward, or away from, the last
commanded position.
• 0 = Direction of the pointer movement is toward the
commanded position
• 1 = Direction of the pointer movement is away from the
commanded position
Gauge 0 and 1 Pointer Velocity Status Information
Most recent valid PECCR command resulting in the Gauge 0
and 1 Pointer Velocity status output:
D10
D9
D8
D11
1
1
1
x
x = Don’t care.
Table 15. Gauge 0 and 1 Pointer Velocity Status Output Register
Bits
Read
Write
OD15
1V7
–
OD14
OD13
1V5
–
OD12
1V4
–
OD11
1V3
–
OD10
1V2
–
OD9
1V1
–
OD8
1V0
–
OD7
0V7
–
OD6
0V6
–
OD5
0V5
–
OD4
0V4
–
OD3
0V3
–
OD2
0V2
–
OD1
0V1
–
OD0
0V0
–
1V6
–
The bits in Table 15 are read-only bits.
0V7:0V0 (OD7:OD0)—These eight bits represent the
velocity position value (refer to Table 17) indicating the actual
velocity of Gauge 0 pointer at the time CS transitions to a
logic 0].
1V7:1V0 (OD15:OD8)—These eight bits represent the
velocity position value (refer to Table 17, page 24) indicating
the actual velocity of Gauge 1 pointer at the time CS transitions
to a logic [0].
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DEVICE FUNCTIONAL DESCRIPTION
slowing safely to a stop at the desired position. During the
State Machine Operation
deceleration phase, the motor will not exceed the maximum
deceleration.
The two-phase step motor has maximum allowable velocities
and acceleration and deceleration.The purpose of the step
motor state machine is to drive the motor with maximum
performance while remaining within the motor’s voltage,
velocity, and acceleration constraints.
During normal operation, both step motor rotors are
microstepped with 24 steps per electrical revolution (see
Figure 6). A complete electrical revolution results in two
degrees of pointer movement. There is a second (smaller) state
machine in the IC controlling these microsteps. This state
machine receives clockwise or counter-clockwise index
commands at intervals, stepping the motor in the appropriate
direction by adjusting the current in each coil. Normalized
values are provided in Table 16, page 23.
A requirement of the state machine is to ensure the
deceleration phase begins at the correct time and pointer
position. When commanded, the motor will accelerate
constantly to the maximum velocity, then move toward the
commanded position. Eventually, the pointer will reach the
calculated location where the movement has to decelerate,
I
MAX
+
0
ICOIL
IMAX
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
IMAX
+
0
ICOIL
IMAX
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Figure 6. Clockwise Microsteps
33970
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Table 16. Coil Step Value
SINE Current 8-Bit Value 8-Bit Value
COS Current
8-Bit Value
(DEC)
8-Bit Value
(HEX)
Step
Angle
SINE Angle*
COS Angle*
Flow
(DEC)
0
(HEX)
0
Flow
0
1
0
0
+
+
+
+
+
+
+
+
1
+
+
+
+
+
+
+
255
247
222
181
128
66
FF
F7
DE
B5
80
42
0
15
0.259
0.5
66
42
0.965
0.866
0.707
0.5
2
30
128
181
222
247
255
247
80
3
45
0.707
0.866
0.966
1
B5
DE
F7
4
60
5
75
0.259
0
6
90
FF
F7
0
7
105
120
135
150
165
180
195
210
225
240
255
270
285
300
315
330
345
0.966
0.866
0.707
0.5
-0.259
-0.5
66
42
80
B5
DE
F7
FF
F7
DE
B5
80
42
0
-
-
8
+
+
+
+
+
-
222
181
128
66
DE
B5
80
42
0
128
181
222
247
255
247
222
181
128
66
9
-0.707
-0.866
-0.966
-1
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
-
0.259
0
-
0
-
-0.259
-0.5
66
42
80
B5
DE
F7
FF
F7
DE
B5
80
42
-0.966
-0.867
-0.707
-0.5
-
128
181
222
247
255
247
222
181
128
66
-
-
-0.707
-0.866
-0.966
-1
-
-
-
-
-0.259
0
-
-
+
+
+
+
+
+
0
-
-0.966
-0.866
-0.707
-0.5
0.259
0.5
66
42
80
B5
DE
F7
-
128
181
222
247
-
0.707
0.866
0.966
-
-
-0.259
-
* Denotes normalized values.
The motor is stepped by providing index commands at
intervals. The time between steps defines the motor velocity,
and the changing time defines the motor acceleration.
From an initial position of 0 with an initial velocity (u), the
motor position (s) at a time (t) is:
s = ut + 2 at 2
1
The state machine uses a table to define the allowed time
and also the maximum velocity. A useful side effect of the table
is that it also allows the direct determination of the position at
which the velocity should reduce to allow the motor to stop at
the desired position.
For unit steps, the time between steps is:
− u + u2 + 2a
⇒ t =
a
The motor equations of motion are generated as follows.
(The units of position are steps, and velocity and acceleration
are in steps/second and steps/second².)
This defines the time increment between steps when the
motor is initially travelling at a velocity u. In the ROM, this time
is quantized to multiples of the system clock by rounding
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upwards, ensuring acceleration never exceeds the allowed
Note Pn = n. This means on the nth step the motor has
indexed by n positions and has been accelerating steadily at the
maximum allowed rate. This is critical because it also indicates
the minimum distance the motor must travel while decelerating
to a stop. For example, the stopping distance is also equal to
the current value of n.
value. The actual velocity and acceleration is calculated from
the time step actually used.
Using
v2 = u2 + 2as
and
The algorithm to drive the motor is similar to:
1. While the motor is stopped, wait until a command is
v = u + at
received.
and solving for v in terms of u, s, and t gives:
2. Send index pulses to the motor at an ever-increasing
rate, according to the time steps in Table 17 until:
2
v =
/
t - u
a. The maximum velocity is reached, at which point the
The correct value of t to use in this equation is the quantized
time intervals stop decreasing, or
value obtained above.
b. The distance remaining to travel is less than the
current index in the table. At this point, the stopping
distance is equal to the remaining distance, and to
ensure it will stop at the required position, the motor
must begin decelerating.
From these equations a set of recursive equations can be
generated to give the allowed time step between motor indexes
when the motor is accelerating from a stop to its maximum
velocity.
Starting from a position p of 0 and a velocity v of 0, these
equations define the time interval between steps at each
position. To drive the motor at maximum performance, index
commands are given to the motor at these intervals. A table is
generated giving the time step ∆t at an index position n.
An example of the velocity table for a particular motor is
provided in Table 17. This motor’s maximum speed is
4800 microsteps/s (at 12 microsteps/degrees), and its
maximum acceleration is 54000 microsteps/s2. The table is
quantized to a 1.0 MHz clock.
p0 = 0
v0 = 0
− vn−1 + vn2−1 + 2a
∆tn
=
a
where
indicates rounding up.
2
vn
=
− vn−1
∆tn
Pn = n
Table 17. Velocity Table
Velocity
Time Between
Velocity
Velocity
Position
Time Between
Velocity
Velocity
Position
Time Between
Velocity
Position
Steps (µs)
(µSteps/s)
Steps (µs)
(µSteps/s)
Steps (µs)
(µSteps/s)
0
1
0
0.00
36.7
76
77
78
79
80
81
82
83
84
85
86
87
380
377
374
372
369
366
364
361
358
356
354
351
2631.6
2652.5
2673.8
2688.2
2710.0
2732.2
2747.3
2770.1
2793.3
2809.0
2824.9
2849.0
152
153
154
155
156
157
158
159
160
161
162
163
257
256
255
254
254
253
252
251
250
249
248
248
3891.1
3906.3
3921.6
3937.0
3937.0
3952.6
3968.3
3984.1
4000.0
4016.1
4032.3
4032.3
27217
13607
11271
7970
5858
4564
3720
3132
2701
2373
2115
2
73.5
3
88.7
4
125.5
170.7
219.1
268.8
319.3
370.2
421.4
472.8
5
6
7
8
9
10
11
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Table 17. Velocity Table (continued)
Velocity
Position
Time Between
Velocity
Velocity
Position
Time Between
Velocity
Velocity
Position
Time Between
Velocity
Steps (µs)
(µSteps/s)
Steps (µs)
(µSteps/s)
Steps (µs)
(µSteps/s)
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1908
1737
1594
1473
1369
1278
1199
1129
1066
1010
960
916
877
842
812
784
760
737
716
697
680
663
648
634
621
608
596
585
575
565
555
546
538
529
521
514
507
500
493
524.1
575.7
88
89
349
347
344
342
340
338
336
334
332
330
328
326
324
322
321
319
317
315
314
312
310
309
307
306
304
303
301
300
298
297
295
294
293
291
290
289
287
286
285
2865.3
2881.8
2907.0
2924.0
2941.2
2958.6
2976.2
2994.0
3012.0
3030.3
3048.8
3067.5
3086.4
3105.6
3115.3
3134.8
3154.6
3174.6
3184.7
3205.1
3225.8
3236.2
3257.3
3268.0
3289.5
3300.3
3322.3
3333.3
3355.7
3367.0
3389.8
3401.4
3413.0
3436.4
3448.3
3460.2
3484.3
3496.5
3508.8
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
247
246
245
244
244
243
242
241
241
240
239
238
238
237
236
235
235
234
233
233
232
231
231
230
229
229
228
227
227
226
226
225
224
224
223
222
222
221
221
4048.6
4065.0
4081.6
4098.4
4098.4
4115.2
4132.2
4149.4
4149.4
4166.7
4184.1
4201.7
4201.7
4219.4
4237.3
4255.3
4255.3
4273.5
4291.8
4291.8
4310.3
4329.0
4329.0
4347.8
4366.8
4366.8
4386.0
4405.3
4405.3
4424.8
4424.8
4444.4
4464.3
4464.3
4484.3
4504.5
4504.5
4524.9
4524.9
627.4
90
678.9
91
730.5
92
782.5
93
834.0
94
885.7
95
938.1
96
990.1
97
1041.7
1091.7
1140.3
1187.6
1231.5
1275.5
1315.8
1356.9
1396.6
1434.7
1470.6
1508.3
1543.2
1577.3
1610.3
1644.7
1677.9
1709.4
1739.1
1769.9
1801.8
1831.5
1858.7
1890.4
1919.4
1945.5
1972.4
2000.0
2028.4
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
33970
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Table 17. Velocity Table (continued)
Velocity
Position
Time Between
Velocity
Velocity
Position
Time Between
Velocity
Velocity
Position
Time Between
Velocity
Steps (µs)
(µSteps/s)
Steps (µs)
(µSteps/s)
Steps (µs)
(µSteps/s)
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
487
481
475
469
464
458
453
448
444
439
434
430
426
422
418
414
410
406
403
399
396
393
389
386
383
2053.4
2079.0
2105.3
2132.2
2155.2
2183.4
2207.5
2232.1
2252.3
2277.9
2304.1
2325.6
2347.4
2369.7
2392.3
2415.5
2439.0
2463.1
2481.4
2506.3
2525.3
2544.5
2570.7
2590.7
2611.0
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
284
282
281
280
279
278
277
275
274
273
272
271
270
269
268
267
266
265
264
263
262
261
260
259
258
3521.1
3546.1
3558.7
3571.4
3584.2
3597.1
3610.1
3636.4
3649.6
3663.0
3676.5
3690.0
3703.7
3717.5
3731.3
3745.3
3759.4
3773.6
3787.9
3802.3
3816.8
3831.4
3846.2
3861.0
3876.0
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
220
220
219
218
218
217
217
216
216
215
215
214
214
213
212
212
211
211
210
210
209
209
208
4545.5
4545.5
4566.2
4587.2
4587.2
4608.3
4608.3
4629.6
4629.6
4651.2
4651.2
4672.9
4672.9
4694.8
4717.0
4717.0
4739.3
4739.3
4761.9
4761.9
4784.7
4784.7
4807.7
Calibrating the internal 1.0 MHz clock is initiated by writing a
logic [1] to PECCR bit PE3 (see Figure 7, page 27). The 8.0 µs
calibration pulse that is then provided by the controller will
ideally result in an internal 33970 clock speed of 1.0 MHz. The
pulse is sent on the CS pin immediately after the SPI word is
sent. No other SPI lines should be toggled. At the moment the
CS pin transitions from logic [1] to logic [0], an internal 7-bit
counter counts the number of cycles of an internal, non-
calibrated, and temperature-dependent 8.0 MHz clock. The
counter stops when the CS pin transitions from logic [0] to
logic [1]. The value in the counter represents the number of
cycles of the 8.0 MHz clock occurring in the 8.0 µs window; it
should range from 32 to 119. An offset is added to this number
to help center or skew the calibrated result to generate a
desired maximum or nominal frequency. The modified counter
value is truncated by 4 bits to generate the calibration divisor,
which should range from 4 to 15. The 8.0 MHz clock is divided
by the calibration divisor, resulting in a calibrated 1.0 MHz
clock. If the calibration divisor lies outside the range of 4 to 15,
Internal Clock Calibration
Timing-related functions on the 33970 (e.g., pointer
velocities, acceleration, and Return To Zero Pointer speeds)
depend upon a precise, consistent time reference to control the
pointer accurately and reliably. Generating accurate time
references on an integrated circuit can be accomplished;
however, they tend to be costly due to the large amount of die
area required for trim pads and the associated trim procedure.
One possibility is an externally generated clock signal;
however, this requires a dedicated pin on the device and
controller. Another expensive approach would require the use
of an additional crystal or resonator.
The internal clock in the 33970 is temperature independent
and area efficient; however, it can vary by as much as ±35
percent due to process variation. Using the existing SPI inputs
and the precision timing reference already available to the
microcontroller, the 33970 allows clock calibration to within ±10
percent.
33970
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the 33970 flags the CAL bit of the status bits, indicating the
allowed only if the gauges are disabled or the pointers are not
moving, as indicated by status bits MOV1 and MOV0.
calibration procedure was not successful. A clock calibration is
D0
D15
SI
SCLK
CS
PECCR Command
8.0 µs Calibration Pulse
Figure 7. Gauge Enable and Clock Calibration Example
Some applications may require a guaranteed maximum
pointer velocity and acceleration. Guaranteeing these
maximums requires nominal internal clock frequency falls
below 1.0 MHz. The frequency range of the calibrated clock will
always be below 1.0 MHz if PECCR bit PE4 is logic [0] prior to
initiating a calibration command, followed by an 8.0 µs
reference pulse. The frequency will be centered at 1.0 MHz if bit
D4 is logic [1].
The resolution of the pointer positioning decreases from
0.083 deg/microstep (180:1) to 0.125 deg/microstep (120:1).
The pointer sweep range increases from approximately
340 degrees to over 500 degrees.
Note Be aware that a fast calibration could result in
violations of the motor acceleration and velocity maximums,
resulting in missed steps.
The 33970 can be fooled into calibrating faster or slower than
the optimal frequency by sending a calibration pulse longer or
shorter than the intended 8.0 µs. As long as the count remains
between 4 and 15, there will be no clock calibration flag. For
applications requiring a slower calibrated clock—e.g., a motor
designed with a gear ratio of 120:1 (8 microsteps/deg)—the
user will have to provide a longer calibration pulse. The device
allows a SPI-selectable slowing of the internal oscillator, using
the PECCR command, so that the calibration divisor safely falls
within the 4-to-15 range when calibrating with a longer time
reference. For example, for the 120:1 motor, the pulse would be
12 µs instead of 8.0 µs. The result of this slower calibration
results in the longer step times necessary to generate pointer
movements meeting acceleration and velocity requirements.
Pointer Deceleration
Constant acceleration and deceleration of the pointer
produces relatively choppy movements when compared to
those of an air core gauge. Air core behavior can be simulated
with appropriate ramp modification during deceleration. This
shaping can be accomplished by adding repetitive steps at
several of the last step values as the pointer decelerates. The
default movement in the 33970 uses this ramp modification
feature. An example is shown in Figure 8. If the maximum
acceleration and deceleration of the pointer is desired, the
repetitive steps can be disabled by writing logic [1] to the
PECCR bit PE5.
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
VELOCITY
9
9
8
8
HOLDCNT = 2
7
7
2
6
6
5
3
5
3
4
4
3
3
3
2
4
2
1
6
1
n = 0
0
STEPS
Figure 8. Deceleration Ramp
33970
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working properly (i.e., the RTZ taking too long), it can disable
Return to Zero Calibration
the command via the RTZR bit RZ1.
Many step motor applications require that the IC detect when
the motor is stalled after commanded to return to the zero
position for calibration purposes. The stalling occurs when the
pointer hits the end stop on the gauge bezel, which is usually at
the zero position. It is important that when the pointer reaches
the end stop it immediately stops without bouncing away.
RTZCR bits RC10:RC5 are written to preload the
accumulator with a predetermined value that will assure an
accurate pointer stall detection. This preloaded value is
determined during application development by disabling the
automatic shutdown feature of the device with the RTZR bits
RZ4 and RZ2. This operating mode allows the master to
monitor the RTZ event, using the accumulator information
available via the SO if the device is configured to provide the
RTZ Accumulator Status. The unconditional RTZ event can be
turned OFF using the RTZR bit RZ1.
The 33970 device provides the ability to automatically and
independently return each of the two pointers to the zero
position via the RTZR and RTZCR SPI commands. An
automatic RTZ is initiated using the RZ0, RZ1, and RZ2 bits.
Unconditional RTZ movement is initiated using the RZ0, RZ2,
and RZ4 bits. During an RTZ event, all commands related to the
gauge being returned are ignored until the pointer has
successfully zeroed or the RTZR bit RZ1 is written to disable
the event. Once an RTZ event is initiated, the device reports
back via the SO pin that an RTZ is underway.
If the Position 0 location bit is in the default logic [0] mode,
then during an RTZ event the pointer is returned counter-
clockwise (CCW) using full steps at a constant speed
determined by the RTZCR RC3:RC0 and RC12:RC11 bits
during RTZ configuration (see Figure 9). Full steps are used
during an RTZ so that only one coil of the motor is being driven
at any time. The coil not being driven is used to determine if the
pointer is moving. If the pointer is moving, the EMF signal that
is present in the non-driven coil is processed by integrating the
signal present on the opened terminal of the coil while
essentially grounding the other end.
The RTZCR command is used to set the RTZ pointer speed,
choose an appropriate blanking time, and preload the
integration accumulator with an appropriate offset. On reaching
the end stop, the device reports back to the microcontroller via
the status message that the RTZ was successful. The RTZ
automatically disables, allowing other commands to be valid. In
the event the master determines an RTZ sequence is not
IMAX
ICOIL
0
SINE
IMAX
0
1
2
3
0
IMAX
COSINE
ICOIL
0
IMAX
0
1
2
3
0
Figure 9. Full Steps Counterclockwise
The IC automatically prepares the non-driven coil at each
step, waits for a predetermined blanking time, then processes
the signal for the duration of the full step. When the pointer
reaches the stop and no longer moves, the dissipating EMF is
detected. The processed results are placed in the RTZ
accumulator, then compared to a decision threshold. If the
signal exceeds the decision threshold, the pointer is assumed
to be moving. If the threshold value is not exceeded, the drive
sequence is stopped if RTZR bit RZ4 is logic [0]. If bit RZ4 is
logic [1], the RTZ movement will continue indefinitely until the
RTZR bit RZ1 is used to stop the RTZ event.
A pointer that is not on a full step location or that is in
magnetic alignment prior to the RTZ event may cause a false
33970
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RTZ detection. More specifically, an RTZ event beginning from
means, for example, all outputs will be disabled and the RTZ full
a non-full step position may result in an abbreviated integration
value potentially interpreted as a stalled pointer. Advancing the
pointer by at least 12 microsteps clockwise (if PE7 = 0) to the
nearest full step position (e.g., 0, 6, 12, 18, 24, etc.) prior to
initiating an RTZ ensures the magnetic fields line up and
increases the chances of a successful pointer stall detection. It
is important that the pointer be in a static, or commanded,
position before starting the RTZ event. Because the time
duration and the number of steps the pointer moves prior to
reaching the commanded position can vary depending upon its
status at the time a position change is communicated, the
master should assure sufficient elapsed time prior to starting an
RTZ. If an RTZ is desired after first enabling the outputs or after
forcing a reset of the device, the pointer should first be
commanded to move 12 microsteps clockwise to the nearest
full step location. Because the pointer was in a static position at
default, the master could determine the number of microsteps
the device has taken by monitoring and counting the MOV0.
MOV1 device status bit transitions to confirm the pointer is
again in a static position. Alternatively, the user could monitor
the device status bits CMD1 and CMD2.
step time will be set to 12.80 ms.
Fault Logic Requirements
The 33970 device indicates each of the following faults as
they occur:
• Overtemperature fault
• Undervoltage VPWR
• Overvoltage VPWR
• Clock out of spec
These fault bits remain enabled until they are clocked out of the
SO pin with a valid SPI message.
Overcurrent faults are not reported directly; however, it is
likely an overcurrent condition will become a thermal issue and
be reported.
Overtemperature Fault Requirements
The 33970 incorporates overtemperature protection
circuitry, which shuts off the affected gauge driver when
excessive temperatures are detected. In the event of a thermal
overload, the affected gauge driver is automatically disabled.
The overtemperature fault is flagged via the OT0 and/or OT1
device status bits. The indicating flag continues to be set until
the affected gauge is successfully re-enabled, provided the
junction temperature has fallen to a temperature below the
hysteresis level.
Only one gauge at a time can be returned to the zero
position. The gauge not returning to zero can continue to be
controlled. An RTZ should not begin until the gauge to be
calibrated is at a static position and its pointer is at a full step
position. An attempt to calibrate a gauge while the other is in the
process of an RTZ event is ignored by the device. In most
applications of the RTZR command, it is possible to avoid a
visually obvious sequential calibration by first bringing the
pointers back close to their previous zero positions, then re-
calibrating them sequentially.
Overvoltage Fault Requirements
The device is capable of surviving VPWR voltages within the
maximum specified in MAXIMUM RATINGS table, page 4.
After completion of an RTZ, the 33970 automatically assigns
the zero-step position to the full step position at the end-stop
location. Because the actual zero position could lie anywhere
within the full step where the zero was detected, the assigned
zero position could be within a window of ±0.5 degree. An RTZ
can be used to detect stall, even if the pointer already rests on
the end stop when an RTZ sequence is initiated. However, it is
recommended the pointer be advanced by at least
VPWR levels resulting in an Overvoltage Shutdown condition
can result in uncertain pointer positions. Therefore, the pointer
position should be re-calibrated. The master will be notified of
an overvoltage event via the SO pin if the device status is
selected. Overvoltage detection and notification occurs
regardless of whether the gauge(s) are enabled or disabled.
Overcurrent Fault Requirements
12 microsteps to the nearest full step prior to initiating the RTZ.
Output currents are limited to safe levels allowing the device
to rely on thermal shutdown to protect itself.
RTZ Output
During an RTZ event the non-driven coil is analyzed to
determine the state of the motor. The 33970 multiplexes the coil
voltages and provides the signal from the non-driven coil to the
RTZ pin.
Undervoltage Fault Requirements
Undervoltage VPWR conditions may result in uncertain
pointer positions. Therefore, the internal clock and the pointer
position may require re-calibration. The state machine
continues with VPWR voltage levels as low as 4.0 V; however,
the coil voltages may be clipped. The master can be notified of
an undervoltage event via the SO pin. Undervoltage detection
and notification are disabled if both outputs are disabled.
Default Mode
Default mode refers to the state of the 33970 after an internal
or external reset prior to SPI communication. An internal reset
occurs during VDD power-up or if VPWR falls below 4.0 V. An
external reset is initiated by the RST pin driven to a logic [0].
During this mode all outputs will be OFF. All specific pin
functions and internal registers operate as though all
addressable configuration register bits were set to logic [0]. This
33970
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the RST pin is driven to a logic [0], the device resets to its
Reset (Sleep Mode)
default state. The device consumes the least amount of current
(IDD and IPWR) when the RST pin is logic 0]. This is also referred
to as the Sleep mode.
The device can reset internally or externally. If the VDD level
falls below the VDDUV level (refer to the Static Electrical
Characteristics table under POWER INPUT, page 5), the
device resets and powers up in the Default mode. Similarly, If
APPLICATION INFORMATION
The 33970 is an extremely versatile device used in a variety
of applications. Table 18 provides a step-by-step example of
configuring and using many of the features designed into the IC.
This example is intended to give a generic overview how the
device could be used. Further, it is intended to familiarize users
with some of its capabilities.
Table 18. 33970 Setup, Configuration, and Usage Example
Reference Table
and or Figure
Step
Command
Description
(a) Enable Gauges
- Bit PE0: Gauge 0
- Bit PE1: Gauge 1
Table 3 (page 13),
Figure 7 (page 27)
(b) Clock Calibration
1
PECCR
- Bit PE3: Enables Calibration Procedure
- Bit PE4: Set clock f = 1.0 MHz maximum or nominal
(c) Send 8.0 µs pulse on CS to calibrate 1.0 MHz clock
(a) Set RTZ Full Step Time
- Bits RC3:RC0
Table 8 (page 17),
Table 9 (page 17)
(b) Set RTZ Blanking Time
- Bit RC4
2
RTZCR
(c) Preload RTZ Accumulator
Table 10 (page 17)
- Bits RC12:RC11 and RC10:RC5
(d) Check SO for an Out-of-Range Clock Calibration
- Is bit CAL logic [1]? If so, then repeat Steps 1 and 2
Table 3 (page 13),
Table 11 (page 18)
3
4
POS0R
POS1R
(a) Move pointer to position 12 prior to RTZ
(a) Move pointer to position 12 prior to RTZ
Table 5 (page 15)
Table 6 (page 15)
(b) Check SO to see if Gauge 0 has moved
Table 3 (page 13),
Table 11 (page 18)
- Is bit MOV0 (OD4) logic [1]? If so then the Gauge 0 has moved to the first microstep
(a) Send null command to see if gauges have moved
- Bit PE12
Table 3 (page 13)
(b) Check SO to see if Gauge 0 (Gauge 1) has moved
5
PECCR
- Is bit MOV0 (OD4) (MOV1 (OD5)) logic [1]? If so, then Gauge 0 (Gauge 1) moved another
microstep. Keep track of movement and if 12 steps are finished and both gauges are at a
static position, then RTZ. Otherwise, repeat steps (a) and (b)
Table 3 (page 13),
Table 11 (page 18)
- Bit CMD0 (OD10) (CMD1 (OD11)) could also be monitored to determine that the pointer is
static
33970
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Table 18. 33970 Setup, Configuration, and Usage Example (continued)
Description
Reference Table
and or Figure
Step
Command
(a) Return one gauge at a time to the zero stop using RTZ command
- Bit RZ0 selects the gauge
Table 7 (page 15)
- Bit RZ1 is used to enable or disable an RTZ
- Bits RZ2 is used to select the direction (along with PE7)
6
RTZ
(b) Select the RTZ accumulator bits to clock out on the SO bits using bits PE11:PE10. These will
be used if characterizing the RTZ.
Table 3 (page 13),
Table 12 (page 20)
(a) Check the Status of the RTZ by sending the null command to monitor SO bit RTZ0, RTZ1 of
Device Status SO
Table 3 (page 13),
Table 11 (page 18)
7
PECCR
- Bit PE12 is the null command
(b) Is RTZ0 (OD2) logic [0]? If not, Gauge 0 still returning and null command should be resent.
(a) Return the other gauge to the zero stop. If the second gauge is driving a different pointer than
the first, a new RTZCR command may be required to change the Full Step time.
8
9
RTZ
Table 7 (page 15)
(a) Check the Status of the RTZ by sending the null command to monitor SO, bit RTZ1 (OD3)
- Bit PE12 is the null command
Table 3 (page 13),
Table 11 (page 18)
PECCR
(b) Is RTZ1 (OD3) logic [0]? If not, Gauge 1 still returning and null command should be resent.
(a) Change the maximum velocity of the gauge
Table 3 (page 14),
Table 17 (page 24)
- Bits V8:V9 determine which gauge(s) will change the maximum velocity
- Bits V7:V0 determine the maximum velocity position from Table 17, Velocity Table
10
VELR
(a) Position Gauge 0 pointer
- Bits P011:P00: Desired Pointer Position
(b) Check SO for Out-of-Range V
PWR
- Bit OVUV (OD6) logic [1]? If so, use UV (OD8) and OV (OD9) to decide whether to RTZ after
valid V
Table 5 (page 15),
Table 17 (page 24)
11
POS0R
PWR
(c) Check SO for overtemperature
- Bit OT0 logic [1]? If so, enable driver again. If OT0 continues to indicate overtemperature,
shut down Gauge 0
- If RTZ0 returns to normal, re-establish the zero reference by RTZ command
(a) Position Gauge 1 pointer
- Bits P1 11:P1 0: Desired Pointer Position
(b) Check SO for Out-of-Range V
PWR
- Bit OVUV logic [1]? If so, use UV (OD8) and OV (OD9) to decided whether to RTZ after valid
Table 6 (page 15),
Table 17 (page 24)
12
13
POS1R
POS0R
V
PWR
(c) Check SO for overtemperature
- Bit OT1 logic [1]? If so, enable driver again. If OT1 continues to indicate overtemperature,
shut down Gauge 1.
- If OT1 returns to normal, re-establish the zero reference by RTZ command
(a) Return the pointers close to zero position using POS0R
Table 5 (page 15)
(b) Move pointer position at least 12 microsteps CW to the nearest full step prior to RTZ
33970
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Table 18. 33970 Setup, Configuration, and Usage Example (continued)
Description
Reference Table
and or Figure
Step
Command
(c) Return the pointers close to zero position using POS1R
Table 6 (page 15)
(d) Move pointer position at least 12 microsteps CW to the nearest full step position prior to RTZ
14
POS1R
(e) Check SO to see if Gauge 0 has moved
Table 6 (page 15),
Table 11 (page 18)
- Bit MOV0 logic [1]? If so, Gauge 0 moved to the first microstep
(f) Send null command to see if gauges have moved
- Bits PE12
(g) Check SO to see if Gauge 0 (Gauge 1) moved
Table 3 (page 13),
Table 11 (page 18)
15
16
PECCR
- Bit MOV0 (MOV1) logic [1]? If so, Gauge 0 (Gauge 1) moved another microstep. Keep track
of movement. If 12 steps are finished, and both gauges are at a static position, then RTZ.
Otherwise repeat steps (a) and (b)
- Bit CMD0 (OD10) (CMD1 (OD1)) could also be monitored to determine that the pointer is
static
(a) Return one gauge at a time to the zero stop using RTZ command
- Bit RZ0 selects the gauge
Table 3 (page 13),
Table 7 (page 15),
Table 12 (page 20)
- Bit RZ1 is used to enable or disable an RTZ
- Bit RZ2 is used to select the direction (along with PE7)
RTZ
(b) Select the RTZ accumulator bits clocking out on the SO bits using bits PE11:PE10. These
will be used if characterizing the RTZ
(a) Check the status of the RTZ by sending the null command to monitor SO bit RTZ0
- Bit PE12 is the null command
Table 3 (page 13),
Table 11 (page 18)
17
18
19
PECCR
RTZ
(b) Is RTZ0 logic [0]? If not, Gauge 0 still returning and null command should be resent
(c) Return the other gauge to the zero stop. If the second gauge is driving a different pointer than
the first, a new RTZCR command may be required to change the Full Step time
Table 7 (page 15),
Table 10 (page 17)
(a) Check the status of the RTZ by sending the null command to monitor SO bit RTZ1
- Bit PE12 is the null command
Table 3 (page 13),
Table 11 (page 18)
PECCR
(b) Is RTZ1 logic [0]? If not, Gauge 1 still returning and null command should be resent
Table 7 (page 15)
(a) Disable both gauges and go to standby
- Bit PE0:PE1 are used to disable the gauges
20
PECCR
Table 3 (page 13)
(b) Put the device to sleep
- RST pin is pulled to logic [0]
33970
32
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
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Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
DW SUFFIX
24-LEAD SOICW
PLASTIC PACKAGE
CASE 751E-04
ISSUE E
-A-
NOTES:
24
13
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
-B- 12X P
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T A
B
DIM MIN
MAX
15.54
7.60
2.65
0.49
0.90
MIN
MAX
0.612
0.299
0.104
0.019
0.035
A
B
C
D
F
15.25
7.40
2.35
0.35
0.41
0.601
0.292
0.093
0.014
0.016
F
R X 45
°
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.23
0.13
0
0.32
0.29
8
0.009
0.005
0
0.013
0.011
8
C
K
-T-
SEATING
°
°
°
°
M
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
PLANE
22X G
33970
33
MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfToArmation On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
NOTES
33970
34
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
NOTES
33970
35
MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfToArmation On This Product,
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Freescale Semiconductor, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do
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TECHNICAL INFORMATION CENTER: 1-800-521-6274
MC33970/D
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