PC33975AEK [FREESCALE]
Multiple Switch Detection Interface with Suppressed Wake-Up and 32mA Wetting Current; 多交换检测接口与抑制唤醒和32毫安湿电流
| 型号： | PC33975AEK |
| 厂家： | 
Freescale |
| 描述： | Multiple Switch Detection Interface with Suppressed Wake-Up and 32mA Wetting Current |
| 文件： | 总32页 (文件大小：884K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document order number: MC33975
Rev 4.0, 08/2005
Freescale Semiconductor
Technical Data
Multiple Switch Detection
Interface with Suppressed
Wake-Up and 32mA Wetting
Current
Freescale offers multiple Switch Detection Interface Devices. The
33975 Multiple Switch Detection Interface with Suppressed Wake-Up
is designed to detect the closing and opening of up to 22 switch
contacts. The switch status, either open or closed, is transferred to the
microprocessor unit (MCU) through a serial peripheral interface (SPI).
The device also features a 22-to-1 analog multiplexer for reading
inputs as analog.
33975
33975A
MULTIPLE SWITCH
DETECTION INTERFACE WITH
SUPPRESSED WAKE-UP
The 33975 device has two modes of operation, Normal and Sleep.
Normal mode allows programming of the device and supplies switch
contacts with pull-up or pull-down current as it monitors switch change
of state. The Sleep mode provides low quiescent current, which makes
the 33975 ideal for automotive and industrial products requiring low
sleep state currents.
EK Suffix (Pb-Free)
98ARL10543D
32-TERMINAL SOICW EP
Improvements are a programmable interrupt timer for Sleep mode
that can be disabled, switch detection currents of 32 mA and 4.0 mA
for switch-to-ground inputs, and an interrupt bit that can be reset.
ORDERING INFORMATION
Temperature
Features
• Designed to Operate 5.5 V ≤ VPWR ≤ 28 V
• Switch Input Voltage Range -14 V to VPWR
• Interfaces Directly to Microprocessor Using 3.3 V/5.0 V SPI
Protocol
Device
Package
Range (T )
A
MC33975EK/R2
PC33975AEK/R2
-40°C to 125°C
32 SOICW-EP
• Selectable Wake-Up on Change of State
• Selectable Wetting Current (32 mA or 4.0 mA for switch-to-ground
inputs)
• 8 Programmable Inputs (Switches to Battery or Ground)
• 14 Switch-to-Ground Inputs
• VPWR Standby Current 100 µA Typical, VDD Standby Current 20 µA Typical
• Pb-free 32-terminal suffix EK
V
DD
V
Power Supply
LVI
BAT
V
V
33975
BAT
Enable
SP0
SP1
VPWR
MCU
V
Watchdog
Reset
DD
VDD
BAT
SP7
WAKE
SI
SCLK
CS
MOSI
SCLK
CS
SG0
SG1
SO
MISO
INT
INT
AMUX
AN0
SG12
SG13
GND
Figure 1. 33975 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Freescale Part No.
Reference
Location
Switch Input Voltage Range
Other Significant Device Variations
MC33975
None
None
5
5
-14 to 38 V
-14 to 40 V
DC
DC
PC33975A
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
5.0 V
V
PWR
V
V
SP0
PWR PWR
V
, V , 5.0 V
DD
VPWR
VDD
PWR
32.0
mA
4.0
mA
POR
Bandgap
Sleep PWR
GND
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
To
+
4.0 V
Ref
2.0
mA
16.0
mA
–
SPI
Comparator
V
V
SP7
PWR PWR
32.0
mA
4.0
mA
5.0 V
Oscillator
and
Clock Control
V
PWR
To
SPI
+
4.0 V
Ref
2.0
mA
16.0
mA
–
Comparator
5.0 V
Temperature
Monitor and
Control
5.0 V
V
V
SG0
5.0 V
125 kΩ
PWR PWR
32.0
mA
4.0
mA
V
PWR
5.0 V
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
To
+
4.0 V
Ref
–
SPI
WAKE Control
Comparator
V
DD
SPI Interface
and Control
125 kΩ
INT
INT Control
VDD
MUX Interface
40 µA
CS
SCLK
SI
VDD
SO
V
V
SG13
PWR PWR
32.0
mA
4.0
mA
V
DD
Analog Mux
Output
+
–
AMUX
To
SPI
+
4.0 V
Ref
–
Comparator
Figure 2. 33975 Simplified Internal Block Diagram
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
GND
SI
SCLK
CS
SO
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
AMUX
INT
SP7
SP6
2
3
4
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG5
SG6
VPWR
5
6
7
SP5
SP4
8
9
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
10
11
12
13
14
15
16
Figure 3. 33975 Terminal Connections
Table 2. Terminal Definitions
A functional description of each terminal can be found in the Functional Terminal Description section on page 11.
Terminal
Name
Terminal
Formal Name
Description
Ground for logic, analog, and switch-to-battery inputs.
SPI control data input terminal from MCU to 33975.
SPI control clock input terminal.
1
2
3
4
GND
SI
Ground
SPI Slave In
Serial Clock
Chip Select
SCLK
CS
SPI control chip select input terminal from MCU to 33975. Logic [0] allows data
to be transferred in.
Programmable switch-to-battery or switch-to-ground input terminals.
5–8
25–28
SPn
SGn
Programmable Switches 0–3
Programmable Switches 4–7
Switch-to-ground input terminals.
9–15,
18–24
Switch-to-Ground Inputs 0–6
Switch-to-Ground Inputs 13–7
Battery supply input terminal. This terminal requires external reverse battery
protection.
16
17
VPWR
WAKE
Battery Input
Open drain wake-up output is designed to control a power supply enable
terminal.
Wake-Up
Open-drain output to MCU is used to indicate input switch change of state.
Analog multiplex output.
29
30
31
32
INT
AMUX
VDD
SO
Interrupt
Analog Multiplex Output
Voltage Drain Supply
SPI Slave Out
3.3/5.0 V supply sets SPI communication level for SO driver.
Provides digital data from 33975 to MCU.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these limits may cause malfunction or permanent
damage to the device.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
VDD Supply Voltage
–
-0.3 to 7.0
V
DC
CS, SI, SO, SCLK, INT, AMUX
WAKE
–
–
–
-0.3 to 7.0
-0.3 to 40
-0.3 to 50
V
V
V
DC
DC
DC
VPWR Supply Voltage
Switch Input Voltage Range
MC33975
–
V
DC
-14 to 38
-14 to 40
PC339775A
Frequency of SPI Operation (VDD = 5.0 V)
ESD Voltage (1)
–
6.0
MHz
V
VESD
±4000
±2500
±200
Human Body Model (2)
Applies to all non-input terminals
Machine Model
Charge Device Model
Corner Terminals
750
500
Interior Terminals
THERMAL RATINGS
Operating Temperature
Ambient
°C
TA
TJ
-40 to 125
-40 to 150
-40 to 125
Junction
Case
TC
Storage Temperature
Power Dissipation (3)
T
-55 to 150
1.7
°C
STG
P
D
W
Thermal Resistance
Junction to Ambient
°C/W
°C
R
71
θJA
R
1.2
Between the Die and the Exposed Die Pad (4)
Peak Package Reflow Temperature During Solder Mounting (5)
Notes
θJC
TSOLDER
245
1. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (CZAP = 200
pF, RZAP = 0 Ω), and the Charge Device Model.
2. All Programmable Switches (SP) and Switch-to-Ground (SG) input terminals when tested individually.
3. Maximum power dissipation at TJ =150°C junction temperature with no heatsink used.
4. Thermal resistance between the die and the exposed die pad.
5. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 8.0 V ≤ VPWR ≤ 28V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Supply Voltage
V
Supply Voltage Range Quasi-Functional (6)
Fully Operational
V
V
V
5.5
8.0
28
–
–
–
8.0
28
PWR
PWR
PWR
( )
qf
( )
fo
( )
qf
Supply Voltage Range Quasi-Functional (7)
38/40
Supply Voltage
V
V
PWR
( )
POR
VPWR Supply Voltage Power On Reset
4.2
–
4.6
4.0
5.0
8.0
Supply Current
I
mA
µA
(
)
PWR on
All Switches Open, Normal Mode, Tri-State Disabled
Sleep State Supply Current
I
PWR
ss
( )
Scan Timer = 64 ms, Switches Open
40
70
–
100
5.5
Logic Supply Voltage
V
3.0
V
DD
Logic Supply Current
I
mA
DD
All Switches Open, Normal Mode
–
–
0.25
10
0.5
20
Sleep State Logic Supply Current
Scan Timer = 64 ms, Switches Open
I
µA
(
)
DD ss
SWITCH INPUT
Pulse Wetting Current Switch-to-Battery (Current Sink)
I
I
mA
mA
P
ulse
5.5 V ≤ VPWR ≤ 28 V
12
15
18
Pulse Wetting Current Switch-to-Ground (Current Source)
P
ulse
5.5 V ≤ VPWR ≤ 8.0 V
8.0 V ≤ VPWR ≤ 28 V
7.0
24
9.0
32
–
36
Sustain Current Switch-to-Battery Input (Current Sink)
I
I
mA
mA
sustain
sustain
5.5 V ≤ VPWR ≤ 28 V
1.8
2.1
2.4
Sustain Current Switch-to-Ground Input (Current Source)
5.5 V ≤ VPWR ≤ 8.0 V
8.0 V ≤ VPWR ≤ 28 V
0.5
3.6
1.0
4.0
–
4.4
Sustain Current Matching Between Channels on Switch-to-Ground Inputs
I
%
M
atch
–
2.0
5.0
ISUS(MAX)
I
SUS(MIN)
-
X 100
ISUS(MIN)
Notes
6. Device operational. Wetting and sustain currents are reduced. Operating the analog multiplexer below 8.0 V is not recommended.
7. Thermal considerations must be taken when operating the device above 28 V.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 8.0 V ≤ VPWR ≤ 28V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
SWITCH INPUT (CONTINUED)
Symbol
Min
Typ
Max
Unit
Input Offset Current when Selected as Analog
Input Offset Voltage when Selected as Analog
I
-2.0
-10
1.4
2.5
2.0
10
µA
offset
V
mV
offset
V
(SP&SGinputs) to AMUX Output
Analog Operational Amplifier Output Voltage
V
mV
V
OL
Sink 250 µA
–
10
30
Analog Operational Amplifier Output Voltage
V
OH
Source 250 µA
V
- 0.1
–
4.0
–
–
DD
Switch Detection Threshold
V
3.70
155
4.3
185
V
th
Temperature Monitor (8)
,
(9)
T
°C
LIM
Temperature Monitor Hysteresis (9)
T
5.0
10
15
°C
LIM(
)
hys
Notes
8. Thermal shutdown of 16 mA and 32 mA pull-up and pull-down current sources only. 4.0 mA and 2.0 mA current source/sink and all
other functions remain active.
9. This parameter is guaranteed by design; however it is not production tested.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 8.0 V ≤ VPWR ≤ 28V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
Input Logic High-Voltage Thresholds (10)
V
0.7 x VDD
GND - 0.3
–
–
VDD + 0.3
0.2 x VDD
V
V
IH
Input Logic Low-Voltage Thresholds (10)
V
IL
SCLK, SI, Tri-State SO Input Current
I
I
µA
SCLK, SI,
I
0.0 V to V
DD
SO(Tri)
-10
-10
30
–
–
10
10
CS Input Current
I
I
µA
CS
CS
CS = V
DD
CS Pull-Up Current
CS = 0.0 V
µA
–
–
100
SO High-State Output Voltage
V
V
SO(high)
I
= -200 µA
V
- 0.8
VDD
SO(high)
DD
SO Low-State Output Voltage
= 1.6 mA
V
V
SO(
C
low)
I
–
–
–
0.4
20
SO(high)
Input Capacitance on SCLK, SI, Tri-State SO (11)
INT Internal Pull-Up Current
–
pF
IN
–
15
40
100
µA
INT Voltage
V
V
high
INT( )
INT = Open Circuit
VDD - 0.5
–
VDD
INT Voltage
V
V
low
INT( )
I
= 1.0 mA
–
0.2
40
0.4
INT
WAKE Internal Pull-Up Current
I
20
100
µA
WAKE
(
pu
)
WAKE Voltage
V
V
WAKE
(
high
)
WAKE = Open Circuit
4.0
–
4.3
0.2
5.3
0.4
WAKE Voltage
V
V
V
WAKE(low)
WAKE(max)
I
WAKE = 1.0 mA
WAKE Voltage (11)
V
–
–
40
Maximum Voltage Applied to WAKE Through External Pull-Up
Notes
10. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK.
11. This parameter is guaranteed by design however, is not production tested.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 8.0 V ≤ VPWR ≤ 28 V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max
Unit
SWITCH INPUT
Pulse Wetting Current Time
t
15
16
22
ms
pulse
(
on
)
Interrupt Delay Time
Normal Mode
t
µs
int-dly
–
5.0
16
Sleep Mode Switch Scan Time
t
100
200
300
µs
scan
Calibrated Scan Timer Accuracy
Sleep Mode
t
%
scan timer
–
–
–
–
10
10
Calibrated Interrupt Timer Accuracy
Sleep Mode
t
%
int timer
DIGITAL INTERFACE TIMING (12)
Required Low State Duration on VPWR for Reset (13)
t
µs
RESET
–
–
10
VPWR ≤ 0.2 V
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
t
ns
ns
ns
ns
lead
100
50
–
–
–
–
–
–
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
t
lag
SI to Falling Edge of SCLK
Required Setup Time
t
SI(su
)
16
Falling Edge of SCLK to SI
Required Hold Time
t
SI(hold)
t
20
–
–
–
–
SI, CS, SCLK Signal Rise Time (14)
5.0
ns
ns
ns
ns
ns
r
f
(SI)
(SI)
SI, CS, SCLK Signal Fall Time (14)
t
–
–
–
–
5.0
–
–
Time from Falling Edge of CS to SO Low Impedance (15)
Time from Rising Edge of CS to SO High Impedance (16)
Time from Rising Edge of SCLK to SO Data Valid (17)
Notes
t
55
55
55
SO(en
)
t
–
SO(dis
)
t
25
valid
12. These parameters are guaranteed by design. Production test equipment uses 4.16 MHz, 5.0 V SPI interface.
13. This parameter is guaranteed by design but not production tested.
14. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
15. Time required for valid output status data to be available on SO terminal.
16. Time required for output states data to be terminated at SO terminal.
17. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
0.2 VDD
t
t
lag
lead
0.7 VDD
0.2 VDD
SCLK
t
t
SI(hold)
SI(su)
0.7 VDD
0.2 VDD
SI
MSB in
t
t
valid
SO(en)
t
SO(dis)
0.7 VDD
0.2 VDD
SO
MSB out
LSB out
Figure 4. SPI Timing Characteristics
VPWR
VDD
WAKE
INT
Wake-Up From Interrupt
Timer Expire
CS
Wake-Up From
Closed Switch
SGn
Power-Up
Normal Mode
Tri-State
Command
(Disable Tri-State)
Sleep
Command
Sleep Mode
Normal
Mode
Sleep Command
Sleep Mode
Normal
Mode
Sleep Command
Figure 5. Sleep Mode to Normal Mode Operation
Switch state change with
CS low generates INT
Switch state change with
CS low generates INT
INT
CS
Latch switch status
on falling edge of CS
Rising edge of CS does not
clear INT because state change
occurred while CS was low
SGn
Switch open “0”
Switch closed “1”
1
1
0
0
1
0
SGn Bit in SPI Word
Switch
Switch
Switch
Switch
Status
Switch
Status
Switch
Status
Status
Status
Status
Command
Command
Command
Command
Command
Command
Figure 6. Normal Mode Interrupt Operation
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
FUNCTIONAL DESCRIPTIONS
INTRODUCTION
The 33975 device is an integrated circuit designed to
provide systems with ultra-low quiescent sleep/wake-up
modes and a robust interface between switch contacts and a
microprocessor. The 33975 replaces many of the discrete
components required when interfacing to microprocessor-
based systems while providing switch ground offset
protection, contact wetting current, and system wake-up.
switch inputs may be read as analog inputs through the
analog multiplexer (AMUX). Other features include a
programmable wake-up timer, programmable interrupt timer,
programmable wake-up/interrupt bits, and programmable
wetting current settings.
This device is designed primarily for automotive
applications but may be used in a variety of other applications
such as computer, telecommunications, and industrial
controls.
The 33975 features 8-programmable switch-to-ground or
switch-to-battery inputs and 14 switch-to-ground inputs. All
FUNCTIONAL TERMINAL DESCRIPTION
signal on the SCLK and SI terminals will be ignored and the
SO terminal is tri-state.
CHIP SELECT (CS)
The system MCU selects the 33975 to receive
communication using the chip select (CS) terminal. With the
CS in a logic low state, command words may be sent to the
33975 via the serial input (SI) terminal, and switch status
information can be received by the MCU via the serial output
(SO) terminal. The falling edge of CS enables the SO output,
latches the state of the INT terminal, and the state of the
external switch inputs.
SERIAL INPUT (SI)
The SI terminal is used for serial instruction data input. SI
information is latched into the input register on the falling
edge of SCLK. A logic high state present on SI will program
a one in the command word on the rising edge of the CS
signal. To program a complete word, 24 bits of information
must be entered into the device.
Rising edge of the CS initiates the following operation:
1. Disables the SO driver (high impedance)
SERIAL OUTPUT (SO)
1. INT terminal is reset to logic [1], except when additional
switch changes occur during CS low (see Figure 6,
page 10).
The SO terminal is the output from the shift register. The
SO terminal remains tri-stated until the CS terminal
transitions to a logic low state. All open switches are reported
as zero, all closed switches are reported as one. The
negative transition of CS enables the SO driver.
1. Activates the received command word, allowing the
33975 to act upon new data from switch inputs.
To avoid any spurious data, it is essential the high-to-low
and low-to-high transitions of the CS signal occur only when
SCLK is in a logic low state. Internal to the 33975 device is an
active pull-up to VDD on CS.
The first positive transition of SCLK will make the status
data bit 24 available on the SO terminal. Each successive
positive clock will make the next status data bit available for
the MCU to read on the falling edge of SCLK. The SI/SO
shifting of the data follows a first-in-first-out protocol, with
both input and output words transferring the most significant
bit (MSB) first.
In Sleep mode the negative edge of CS (VDD applied) will
wake up the 33975 device. Data received from the device
during CS wake-up may not be accurate.
INTERRUPT OUTPUT (INT)
SERIAL CLOCK (SCLK)
The INT terminal is an interrupt output from the 33975
device. The INT terminal is an open-drain output with an
internal pull-up to VDD. In Normal mode, a switch state
change will trigger the INT terminal (when enabled). The INT
terminal is latched on the falling edge of CS. and cleared on
the rising edge of CS. The INT terminal will not clear with
rising edge of CS if a switch contact change has occurred
while CS was low.
The system clock (SCLK) terminal clocks the internal shift
register of the 33975. The SI data is latched into the input
shift register on the falling edge of SCLK signal. The SO
terminal shifts the switch status bits out on the rising edge of
SCLK. The SO data is available for the MCU to read on the
falling edge of SCLK. False clocking of the shift register must
be avoided to ensure validity of data. It is essential the SCLK
terminal be in a logic low state whenever CS makes any
transition. For this reason, it is recommended, though not
necessary, that the SCLK terminal is commanded to a low
logic state as long as the device is not accessed and CS is in
a logic high state. When the CS is in a logic high state, any
In a multiple 33975 device system with WAKE high and
VDD on (Sleep mode), the falling edge of INT will place all
33975s in Normal mode.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL TERMINAL DESCRIPTION
WAKE INPUT (WAKE)
GROUND (GND)
The WAKE terminal is an open-drain output and a wake-up
input. The terminal is designed to control a power supply
Enable terminal. In the Normal mode, the WAKE terminal is
low. In the Sleep mode, the WAKE terminal is high. The
WAKE terminal has a pull-up to the internal +5.0 V supply.
The GND terminal provides ground for the IC as well as
ground for inputs programmed as switch-to-battery inputs.
PROGRAMMABLE SWITCHES (SP0–SP7)
The 33975 device has 8 switch inputs capable of being
programmed to read switch-to-ground or switch-to-battery
contacts. The input is compared with a 4.0 V reference.
When programmed to be switch-to-battery, voltages greater
than 4.0 V are considered closed. Voltages less than 4.0 V
are considered open. The opposite holds true when inputs
are programmed as switch-to-ground. Programming features
are defined in Table 6 through Table 11 in the Functional
Device Operation section of this datasheet beginning on
page 14. Voltages greater than the VPWR supply voltage will
In Sleep mode with the WAKE terminal high, falling edge of
WAKE will place the 33975 in Normal mode. In Sleep mode
with VDD applied, the INT terminal must be high for negative
edge of WAKE to wake up the device. If VDD is not applied to
the device in Sleep mode, INT does not affect WAKE
operation.
LOAD SUPPLY VOLTAGE (VPWR)
The VPWR terminal is battery input and Power-ON Reset
to the 33975 IC. The VPWR terminal requires external
reverse battery and transient protection. Maximum input
voltage on VPWR is 50 V. All wetting, sustain, and internal
source current through the SP inputs to the VPWR terminal.
Transient battery voltages greater than 38/40 V must be
clamped by an external device.
logic current is provided from the VPWR terminal.
SWITCH-TO-GROUND (SG0–SG13)
The SGn terminals are switch-to-ground inputs only. The
input is compared with a 4.0 V reference. Voltages greater
than 4.0 V are considered open. Voltages less than 4.0 V are
considered closed. Programming features are defined in
Table 6 through Table 11 in the Functional Device Operation
section of this datasheet beginning on page 14. Voltages
greater than the VPWR supply voltage will source current
LOGIC VOLTAGE (VDD)
The VDD input terminal is used to determine logic levels
on the microprocessor interface (SPI) terminals. Current from
VDD is used to drive SO output and the pull-up current for CS
and INT terminals. VDD must be applied for wake-up from
negative edge of CS or INT.
through the SG inputs to the VPWR terminal. Transient
battery voltages greater than 38/40 V must be clamped by an
external device.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL TERMINAL DESCRIPTION
MCU INTERFACE DESCRIPTION
The 33975 device directly interfaces to a 3.3 V or 5.0 V
MC68HCXX
microcontroller unit (MCU). SPI serial clock frequencies up to
6.0 MHz may be used for programming and reading switch
input status (production tested at 4.16 MHz). Figure 7
illustrates the configuration between an MCU and one 33975.
Microcontroller
33975
MOSI
SI
Shift Register
MISO
Serial peripheral interface (SPI) data is sent to the 33975
device through the SI input terminal. As data is being clocked
into the SI terminal, status information is being clocked out of
the device by the SO output terminal. The response to a SPI
command will always return the switch status, reset flag, and
thermal flag. Input switch states are latched into the SO
register on the falling edge of the chip select (CS) terminal.
Twenty-four bits are required to complete a transfer of
information between the 33975 and the MCU.
SO
SCLK
SCLK
CS
Parallel
Ports
INT
INT
33975
SI
SO
SCLK
MC68HCXX
33975
Microcontroller
CS
MOSI
MISO
SI
INT
Shift Register
24-Bit Shift Register
SO
Figure 8. SPI Parallel Interface with Microprocessor
SCLK
INT
Receive
Buffer
MC68HCXX
Microcontroller
To Logic
33975
CS
Parallel
Ports
MOSI
INT
SI
Shift Register
MISO
SO
SCLK
SCLK
Figure 7. SPI Interface with Microprocessor
Parallel
Ports
CS
Two or more 33975 devices may be used in a module
system. Multiple ICs may be SPI-configured in parallel or
serial. Figures 8 and 9 show the configurations. When using
the serial configuration, 48-clock cycles are required to
transfer data in/out of the ICs.
INT
INT
33975
SI
SO
SCLK
CS
INT
Figure 9. SPI Serial Interface with Microprocessor
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
POWER SUPPLY
POWER-ON RESET (POR)
The 33975 is designed to operate from 5.5 V to 38/40 V on
the VPWR terminal. Characteristics are provided from 8.0 V
to 28 V for the device. Switch contact currents and the
internal logic supply are generated from the VPWR terminal.
The VDD supply terminal is used to set the SPI
Applying VPWR to the device will cause a Power-ON
Reset and place the device in Normal mode.
Default settings from Power-ON Reset via VPWR or Reset
Command are as follows:
• Programmable Switch – Set to Switch-to-Battery
• All Inputs Set as Wake-Up
communication voltage levels, current source for the SO
driver, and pull-up current on INT and CS.
• Wetting Current On (16 mA pull down, 32 mA pull up)
• Wetting Current Timer On (20 ms)
• All Inputs Tri-State
VDD supply may be removed from the device to reduce
quiescent current. If VDD is removed while the device is in
Normal mode, the device will remain in Normal mode. If VDD
is removed in Sleep mode, the device will remain in Sleep
mode until wake-up input is received (WAKE high to low,
switch input or interrupt timer expires).
• Analog Select 00000 (No Input Channel Selected)
Note The 33975 device provides indication that a reset
has occurred by placing a logic [1] in bit 22 of the SO buffer.
The reset bit is cleared on rising edge of CS.
Removing VDD from the device disables SPI
communication and will not allow the device to wake up from
INT and CS terminals.
OPERATIONAL MODES
The 33975 has two operating modes, Normal mode and
Sleep mode. A discussion on Normal mode begins below.
A discussion on Sleep Mode begins on page 20.
• Tri-State Register (Tri-State Command)
• Analog Select Register (Analog Command)
• Calibration of Timers (Calibration Command)
• Reset (Reset Command)
NORMAL MODE
Figure 6, page 10, is a graphical description of the device
operation in Normal mode. Switch states are latched into the
input register on the falling edge of CS. The INT to the MCU
is cleared on the rising edge of CS. However, INT will not
clear on rising edge of CS if a switch has closed during SPI
communication (CS low). This prevents switch states from
being missed by the MCU.
Normal mode may be entered by the following events:
• Application of VPWR to the IC
• Change-of-Switch State (when enabled)
• Falling Edge of WAKE
• Falling Edge of INT (with VDD = 5.0 V and WAKE at
Logic [1])
• Falling Edge of CS (with VDD = 5.0 V)
• Interrupt Timer Expires
PROGRAMMABLE SWITCH REGISTER
Inputs SP0 to SP7 may be programmable for switch-to-
battery or switch-to-ground. These inputs types are defined
using the settings command (refer to Table 6). To set an SPn
input for switch-to-battery, a logic [1] for the appropriate bit
must be set. To set an SPn input for switch-to-ground, a
logic [0] for the appropriate bit must be set. The MCU may
change or update the Programmable Switch Register via
software at any time in Normal mode. Regardless of the
setting, when the SPn input switch is closed a logic [1] will be
placed in the Serial Output Response Register (refer to
Table 17, page 19).
Only in Normal mode with VDD applied can the registers
of the 33975 be programmed through the SPI.
The registers that may be programmed in Normal mode
are listed below. Further explanation of each register is
provided in subsequent paragraphs.
• Programmable Switch Register (Settings Command)
• Wake-Up/Interrupt Register (Wake-Up/Interrupt
Command)
• Wetting Current Register (Metallic Command)
• Wetting Current Timer Register (Wetting Current Timer
Enable Command)
Table 6. Settings Command
Settings Command
Not used
Battery/Ground Select
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
the wake-up/interrupt bit to logic [1] will enable the specific
input to generate an interrupt with switch change of state and
will enable the specific input as wake-up. The MCU may
change or update the Wake-Up/Interrupt Register via
software at any time in Normal mode.
WAKE-UP/INTERRUPT REGISTER
The Wake-Up/Interrupt Register defines the inputs that
are allowed to wake the 33975 from Sleep mode or set the
INT terminal low in Normal mode. Programming the wake-up/
interrupt bit to logic [0] will disable the specific input from
generating an interrupt and will disable the specific input from
waking the IC in Sleep mode (refer to Table 7). Programming
Table 7. Wake-Up /Interrupt Command
Wake-Up/Interrupt Command
Command Bits
23
0
22
0
21
0
20
0
19
0
18
0
17
1
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
0
0
0
0
0
0
1
1
X
X
sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3
2
1
0
WETTING CURRENT REGISTER
The 33975 has two levels of switch-to-ground contact
current, 32 mA and 4.0 mA, and two levels of switch-to-
battery contact current, 16 mA and 2.0 mA (see Figure 10).
The metallic command is used to set the switch contact
current level (refer to Table 8). Programming the metallic bit
to logic [0] will set the switch wetting current to 2.0 mA/4.0
mA. Programming the metallic bit to logic [1] will set the
switch contact wetting current to 16 mA/32 mA. The MCU
may change or update the Wetting Current Register via
software at any time in Normal mode.
Switch Contact Voltage
32 mA Switch Wetting Current
Wetting current is designed to provide higher levels of
current during switch closure. The higher level of current is
designed to keep switch contacts from building up oxides that
form on the switch contact surface.
4.0 mA Switch Sustain Current
20 ms Wetting Current Timer
Figure 10. Contact Wetting and Sustain Current
for Switch-to-Ground Input
Table 8. Metallic Command
Metallic Command
Command Bits
23
0
22
0
21
0
20
0
19
0
18
1
17
0
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
0
0
0
0
0
1
0
1
X
X
sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3
2
1
0
current timers disabled, power dissipation for the IC must be
considered.
WETTING CURRENT TIMER REGISTER
Each switch input has a designated 20 ms timer. The timer
starts when the specific switch input crosses the comparator
threshold (4.0 V). When the 20 ms timer expires, the contact
current is reduced from 16 mA to 2.0 mA for switch-to-battery
inputs and 32 mA to 4.0 mA for switch-to-ground inputs. The
wetting current timer may be disabled for a specific input.
When the timer is disabled, wetting current will continue to
flow through the closed switch contact. With multiple wetting
The MCU may change or update the Wetting Current
Timer Register via software at any time in Normal mode. This
allows the MCU to control the amount of time wetting current
is applied to the switch contact. Programming the wetting
current timer bit to logic [0] will disable the wetting current
timer. Programming the wetting current timer bit to logic [1]
will enable the wetting current timer (refer to Table 9).
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 9. Wetting Current Timer Enable Command
Wetting Current Timer Commands
Command Bits
23
0
22
0
21
0
20
0
19
0
18
1
17
1
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
0
0
0
0
1
0
0
0
X
X
sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3
2
1
0
comparator on each input remains active. This command
allows the use of each input as a comparator with a 4.0 V
threshold. The MCU may change or update the Tri-State
Register via software at any time in Normal mode.
TRI-STATE REGISTER
The tri-state command is use to set the SPn or SGn input
node as high impedance (refer to Table 10). By setting the
Tri-State Register bit to logic [1], the input will be high
impedance regardless of the metallic command setting. The
Table 10. Tri-State Command
Tri-State Commands
Command Bits
23 22 21 20 19 18 17 16 15 14
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
bit 6 and bit 5 to 1,1 in the Analog Select Register is not
allowed and will place the input as an analog input with high
impedance.
ANALOG SELECT REGISTER
The analog voltage on switch inputs may be read by the
MCU using the analog command (refer to Table 11). Internal
to the IC is a 22-to-1 analog multiplexer. The voltage present
on the selected input terminal is buffered and made available
on the AMUX output terminal. The AMUX output terminal is
clamped to a maximum of VDD volts regardless of the higher
voltages present on the input terminal. After an input has
been selected as the analog, the corresponding bit in the next
SO data stream will be logic [0]. When selecting a channel to
be read as analog, the user must also set the desired current
(32 mA, 4.0 mA, or high impedance). Setting bit 6 and bit 5 to
0,0 selects the input as high impedance. Setting bit 6 and
bit 5 to 0,1 selects 4.0 mA, and 1,0 selects 32 mA. Setting
Analog currents set by the analog command are pull-up
currents for all SGn and SPn inputs (refer to Table 11). The
analog command does not allow pull-down currents on the
SPn inputs. Setting the current to 32 mA or 4.0 mA may be
useful for reading sensor inputs. Further information is
provided in the Typical Applications section of this datasheet
beginning on page 22. The MCU may change or update the
Analog Select Register via software at any time in Normal
mode.
Table 11. Analog Command
Current
Select
Analog Command
Not used
Analog Channel Select
23
0
22
0
21
0
20
0
19
0
18
1
17
1
16
0
15
X
14
X
13
X
12
11
X
10
9
8
7
6
5
4
0
3
0
2
0
1
0
0
0
X
X
X
X
X
32 4.0
mA mA
Table 12. Analog Channel
Bits 43210
Analog Channel Select
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
No Input Selected
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Because the oscillator frequency changes with temperature,
calibration is required for an accurate time base. Calibrating
the timers has no affect on the quiescent current
measurement. The calibration command simply makes the
time base more accurate. The calibration command may be
used to update the device on a periodic basis. All reset
conditions clear the calibration register and places the device
in the uncalibrated state.
CALIBRATION OF TIMERS
In cases where an accurate time base is required, the user
may calibrate the internal timers using the calibration
command (refer to Table 13). After the 33975 device
receives the calibration command, the device expects 512 µs
logic [0] calibration pulse on the CS terminal. The pulse is
used to calibrate the internal clock. No other SPI terminals
should transition during this 512 µs calibration pulse.
Table 13. Calibration Command
Calibration Command
Command Bits
23
0
22
0
21
0
20
0
19
1
18
0
17
1
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
states or the paragraph entitled Power-ON Reset (POR) on
page 14 of this datasheet.
RESET
The reset command resets all registers to Power-ON
Reset (POR) state. Refer to Table 15, page 18, for POR
Table 14. Reset Command
Reset Command
Command Bits
23
0
22
1
21
1
20
1
19
1
18
1
17
1
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
threshold level. Open switches are always indicated with a
logic [0], closed switches are indicated with logic [1].
SPI COMMAND SUMMARY
Table 15 below provides a comprehensive list of SPI
commands recognized by the 33975 and the reset state of
each register. Table 16 and Table 17 contain the Serial
Output (SO) data for input voltages greater or less than the
Table 15. SPI Command Summary
MSB
Command Bits
Setting Bits
LSBI
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
X
14
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
Switch Status
Command
X
X
X
X
X
X
X
X
X
X
X
X
Settings Command
Bat=1, Gnd=0
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
(Default state =
1)
Wake-Up/Interrupt Bit
Wake-Up=1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Nonwake-Up=0
(Default state = 1)
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Metallic Command
Metallic = 1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Non-metallic = 0
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
(Default state =
1)
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
MSB
Command Bits
Setting Bits
LSBI
Analog Command
0
0
0
0
0
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
32mA 4.0m
0
0
0
0
0
0
A
0
Wetting Current Timer
Enable Command
Timer ON = 1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Timer OFF = 0
(Default state = 1)
Tri-State Command
Input Tri-State=1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Input Active = 0
Calibration Command
0
0
0
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(Default state -
uncalibrated)
Sleep Command
0
0
0
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
int
int
int scan scan scan
(See Sleep
Mode on page
20)
timer timer timer timer timer timer
Reset Command
0
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SO Response Will
Always Send
therm RST SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
flg flg
Table 16. Serial Output (SO) Bit Data
Input
Programmed
Voltage on
Input terminal
Type of Input
SO SPI Bit
SP
Switch to Ground
Switch to Ground
Switch to Battery
Switch to Battery
N/A
SPn < 4.0 V
SPn > 4.0 V
SPn < 4.0 V
SPn > 4.0 V
SGn < 4.0 V
SGn > 4.0 V
1
0
0
1
1
0
SG
N/A
Table 17. Serial Output (SO) Response Register
SO Response Will
Always Send
therm RST SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SG13 SG12 SG11 SG10 SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
flg flg
• Wetting Current Timer On (20 ms)
EXAMPLE OF NORMAL MODE OPERATION
• All inputs Tri-State-Disabled (comparator is active)
• Analog select 00000 (no input channel selected)
The operation of the device in Normal Mode is defined by
the states of the programmable internal control registers. A
typical application may have the following settings:
• Programmable Switch – Set to Switch-to-Ground
• All Inputs Set as Wake-Up
With the device programmed as above, an interrupt will be
generated with each switch contact change of state (open-to-
close or close-to-open) and 32 mA of contact wetting current
will be source for 20 ms. The INT terminal will remain low until
switch status is acknowledged by the microprocessor. It is
• Wetting Current On (32 mA)
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
critical to understand INT will not be cleared on the rising
edge of CS if a switch closure occurs while CS is low. The
maximum duration a switch state change can exist without
acknowledgement depends on the software response time to
the interrupt. Figure 6, page 10, shows the interaction
between changing input states and the INT and CS terminals.
• Interrupt Timer Expire
• Falling Edge of WAKE
• Falling Edge of INT (with VDD = 5.0 V and WAKE at
Logic [1])
• Falling Edge of CS (with VDD = 5.0 V)
• Power-ON Reset (POR)
If desired the user may disable interrupts (wake up/
interrupt command) from the 33975 device and read the
switch states on a periodic basis. Switch activation and
deactivation faster than the MCU read rate will not be
acknowledged.
The VDD supply may be removed from the device during
Sleep mode. However removing VDD from the device in
Sleep mode will disable a wake-up from falling edge of INT
and CS.
Note In cases where CS is used to wake the device, the
first SO data message is not valid.
The 33975 device will exit the Normal mode and enter the
Sleep mode only with a valid sleep command.
The sleep command contains settings for two
programmable timers for Sleep mode, the interrupt timer and
the scan timer, as shown in Table 18 The interrupt timer is
used as a periodic wake-up timer. When the timer expires, an
interrupt is generated and the device enters Normal mode.
SLEEP MODE
Sleep mode is used to reduce system quiescent currents.
Sleep mode may be entered only by sending the sleep
command. All register settings programmed in Normal mode
will be maintained in Sleep mode.
Note The interrupt timer in the 33975 device may be
disabled by programming the interrupt bits to logic [1 1 1].
The 33975 will exit Sleep mode and enter Normal mode
when any of the following events occur:
• Input Switch Change of State (when enabled)
Table 18. Sleep Command
Table 19 shows the programmable settings of the Interrupt
timer.
Sleep Command
Command Bits
23
0
22
0
21
0
20
0
19
1
18
1
17
0
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
When switch state changes are detected, an interrupt (when
enabled; refer to wake-up/interrupt command description on
page 15) is generated and the device enters Normal mode.
Without switch state changes, the 33975 will reset the scan
timer, inputs become tri-state, and the Sleep mode continues
until the scan timer expires again.
Table 19. Interrupt Timer
Bits 543
Interrupt Period
000
001
010
011
100
101
110
111
32 ms
64 ms
Table 20 shows the programmable settings of the Scan
128 ms
timer.
Table 20. Scan Timer
256 ms
Bits 210
Scan Period
512 ms
000
001
010
011
100
101
110
111
No Scan
1.0 ms
2.0 ms
4.0 ms
8.0 ms
16 ms
1.024 s
2.048 s
No interrupt wake-up
The scan timer sets the polling period between input
switch reads in Sleep mode. The period is set in the sleep
command and may be set to 000 (no period) to 111 (64 ms).
In Sleep mode when the scan timer expires, inputs will
behave as programmed prior to sleep command. The 33975
will wake up for approximately 125 µs and read the switch
inputs. At the end of the 125 µs, the input switch states are
compared with the switch state prior to sleep command.
32 ms
64 ms
Note The interrupt and scan timers are disabled in the
Normal mode.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 5, page 10, is a graphical description of how the
33975 device exits Sleep mode and enters Normal mode.
Notice that the device will exit Sleep mode when the interrupt
timer expires or when a switch change of state occurs. The
falling edge of INT triggers the MCU to wake from Sleep state.
Figure 11 illustrates the current consumed during Sleep
mode. During the 125 µs, the device is fully active and switch
states are read. The quiescent current is calculated by
integrating the normal running current over scan period plus
approximately 60 µA.
TEMPERATURE MONITOR
With multiple switch inputs closed and the device
programmed with the wetting current timers disabled,
considerable power will be dissipated by the IC. For this
reason temperature monitoring has been implemented. The
temperature monitor is active in the Normal mode only. When
the IC temperature is above the thermal limit, the temperature
monitor will do all of the following:
• Generate an interrupt.
• Force all wetting current sources to revert to 2.0 mA/
4.0 mA sustain currents
• Maintain the 2.0 mA/4.0 mA sustain currents and all
other functionality.
• Set the thermal flag bit in the SPI output register.
I=V/R or 0.270 V/100 Ω=2.7 mA
The thermal flag bit in the SPI word will be cleared on rising
edge of CS provided the die temperature has cooled below
the thermal limit. When die temperature has cooled below
thermal limit, the device will resume previously programmed
settings.
Inputs active for
A
6.0 mV/100 Ω=60 µA
I=V/R or
125 µs out of 32 ms
Figure 11. Sleep Current Waveform
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
TYPICAL APPLICATIONS
OPERATIONAL MODES
TYPICAL APPLICATIONS
The 33975’s primary function is the detection of open or
closed switch contacts. However, there are many features
that allow the device to be used in a variety of applications.
The following is a list of applications to consider for the IC:
• Sensor Power Supply
METALLIC/ELASTOMERIC SWITCH
Metallic switch contacts often develop higher contact
resistance over time owing to contact corrosion. The
corrosion is induced by humidity, salt, and other elements
that exist in the environment. For this reason the 33975
provides two settings for contacts. When programmed for
metallic switches, the device provides higher wetting current
to keep switch contacts free of oxides. The higher current
occurs for the first 20 ms of switch closure. Where longer
duration of wetting current is desired, the user may send the
wetting current timer command and disable the timer. Wetting
current will be continuous to the closed switch. After the time
period set by the MCU, the wetting current timer command
may be sent again to enable the timer. The user must
consider power dissipation on the device when disabling the
timer. (Refer to the paragraph entitled Temperature Monitor,
page 21.)
• Switch Monitor for Metallic or Elastomeric Switches
• Analog Sensor Inputs (Ratiometric)
• Power MOSFET/LED Driver and Monitor
• Multiple 33975 Devices in a Module System
The following paragraphs describe the applications in
detail.
SENSOR POWER SUPPLY
Each input may be used to supply current to sensors
external to a module. Many sensors such as Hall effect,
pressure sensors, and temperature sensors require a supply
voltage to power the sensor and provide an open collector or
analog output. Figure 12 shows how the 33975 may be used
to supply power and interface to these types of sensors. In an
application where the input makes continuous transitions,
consider using the wake-up/interrupt command to disable
the interrupt for the particular input.
To increase the amount of wetting current for a switch
contact, the user has two options. Higher wetting current to a
switch may be achieved by paralleling SGn or SPn inputs.
This will increase wetting current by 32 mA for each input
added to the switch-to- ground contact and 16 mA for switch-
to-battery contacts. The second option is to simply add an
external resistor pull-up to the VPWR supply for switch-to-
ground inputs or a resistor to ground for a switch-to-battery
input. Adding an external resistor has no effect on the
operation of the device.
33975
VBAT
SP0
VPWR
SP1
V
DD
Elastomeric switch contacts are made of carbon and have
a high contact resistance. Resistance of 1.0 kΩ is common.
In applications with elastomeric switches, the pull-up and
pull-down currents must be reduced to prevent excessive
power dissipation at the contact. Programming for a lower
current settings is provided in the Functional Device
Operation Section beginning on page 14 under Table 8,
Metallic Command.
MCU
VDD
VBAT
SP7
WAKE
SI
MOSI
SCLK
CS
SG0
SG1
SCLK
CS
VPWR VPWR
SO
MISO
INT
32
mA
4.0
mA
INT
32 mA
SG12
ANALOG SENSOR INPUTS (RATIOMETRIC)
VPWR VPWR
The 33975 features a 22-to-1 analog multiplexer. Setting
the binary code for a specific input in the analog command
allows the microcontroller to perform analog to digital
conversion on any of the 22 inputs. On rising edge of CS the
multiplexer connects a requested input to the AMUX terminal.
The AMUX terminal is clamped to max of VDD volts
regardless of the higher voltages present on the input
terminal. After an input has been selected as the analog, the
corresponding bit in the next SO data stream will be logic [0].
Hall-Effect
Sensor
32
mA
4.0
mA
Reg
SG13
IOC[7:0]
Input Capture
Timer Port
AMUX
X
VDD
0V
VPWR
0V
AMUX
SG13
Figure 12. Sensor Power Supply
The input terminal, when selected as analog, may be
configured as analog with high impedance, analog with
4.0 mA pull-up, or analog with 32 mA pull-up. Figure 13,
page 23, shows how the 33975 may be used to provide a
ratiometric reading of variable resistive input.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
TYPICAL APPLICATIONS
OPERATIONAL MODES
Using the equation yields the
following:
33975
VBAT
VBAT
I1 x R1
I2 x R2
SP0
SP1
VPWR
VDD
ADC =
x 225
VDD
MCU
4.0 mA x 1.0 kΩ
4.0 mA x 1.21 kΩ
ADC =
x 225
SP7
WAKE
SI
ADC = 210 counts
MOSI
SCLK
CS
SG0
SG1
SCLK
CS
V
PWR VPWR
The ADC value of 213 counts is the value with 0% error
(neglecting the resistor tolerance and AMUX input offset
voltage). Now we can calculate the count value induced by
the mismatch in current sources. From a sample device the
maximum current source was measured at 3.979 mA and
minimum current source was measured at 3.933 mA. This
yields 1.16% error in A/D conversion due to the current
source mismatch. The A/D measurement will be as follows:
MISO
INT
SO
32
mA
4.0
mA
I
1
INT
4.0 mA
SG12
AMUX
AN0
V
PWR VPWR
R1
Analog
Ports
32
mA
4.0
mA
Analog Sensor
or Analog Switch
SG13
I
2
4.36 V to 5.32 V
R2
4.0 mA
3.933 mA x 1.0 kΩ
V
REF(H)
1.21 k
Ω
ADC =
x 225
0.1%
3.979 mA x 1.21 kΩ
V
REF(L)
ADC = 208 counts
Figure 13. Analog Ratiometric Conversion
This A/D conversion is 1.16% low in value. The error
correction factor of 1.0115 may be used to correct the value:
To read a potentiometer sensor, the wiper should be
grounded and brought back to the module ground, as
illustrated in Figure 13. With the wiper changing the
impedance of the sensor, the analog voltage on the input will
represent the position of the sensor.
ADC = 208 counts x 1.0116
ADC = 210 counts
An error correction factor may then be stored in E2
memory and used in the A/D calculation for the specific input.
Each input used as analog measurement will have a
dedicated calibrated error correction factor.
Using the Analog feature to provide 4.0 mA of pull-up
current to an analog sensor may induce error due to the
accuracy of the current source. For this reason, a ratiometric
conversion must be considered. Using two current sources
(one for the sensor and one to set the reference voltage to the
A/D converter) will yield a maximum error (owing to the
33975) of 4%.
POWER MOSFET/LED DRIVER AND MONITOR
Because of the flexible programming of the 33975 device,
it may be used to drive small loads like LEDs or MOSFET
gates. It was specifically designed to power up in the Normal
mode with the inputs tri-state. This was done to ensure the
LEDs or MOSFETs connected to the 33975 power up in the
off-state. The Switch Programmable (SP0–SP7) inputs have
a source-and-sink capability, providing effective MOSFET
gate control. To complete the circuit, a pull-down resistor
should be used to keep the gate from floating during the
Sleep modes. Figure 14, page 24, shows an application
where the SG0 input is used to monitor the drain-to-source
voltage of the external MOSFET. The 750 Ω resistor is used
to set the drain-to-source trip voltage. With the 4.0 mA
current source enabled, an interrupt will be generated when
the drain-to-source voltage is approximately 1.0 V.
Higher accuracy may be achieved through module level
calibration. In this example, we use the resistor values from
Figure 13 and assume the current sources are 4% from each
other. The user may use the module end-of-line tester to
calculate the error in the A/D conversion. By placing a
1.0 kΩ, 0.1% resistor in the end-of-line test equipment and
assuming a perfect 4.0 mA current source from the 33975, a
calculated A/D conversion may be obtained.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
TYPICAL APPLICATIONS
OPERATIONAL MODES
The analog command may be used to monitor the drain
voltage in the MOSFET ON state. By sourcing 4.0 mA of
current to the 750 Ω resistor, the analog voltage on the SGn
terminal will be approximately:
VBAT
V
V
PWR PWR
SG0
32
mA
4.0
mA
VSGn = ISGn x 750Ω + VDS
750 Ω
SG0
AMUX
As the voltage on the drain of the MOSFET increases, so
does the voltage on the SGn terminal. With the SGn terminal
selected as analog, the MCU may perform the A/D
conversion.
100 kΩ
+
To SPI
4.0 V Ref
-
Comparator
V
V
PWR
PWR
SG0
Using this method for controlling unclamped inductive
loads is not recommended. Inductive fly-back voltages
greater than VPWR may damage the IC.
32
4.0
mA
mA
SP0
The SP0–SP7 terminals of this device may also be used
to send signals from one module to another. Operation is
similar to the gate control of a MOSFET.
+
To SPI
4.0 V
Ref
-
16
mA
Comparator
2.0 mA
For LED applications a resistor in series with the LED is
recommended but not required. The switch-to-ground inputs
are recommended for LED application. To drive the LED use
the following commands:
V
V
PWR PWR
SG13
32
mA
4.0
mA
SG13
•
wetting current timer enable command –Disable SGn
wetting current timer.
+
To SPI
4.0 V Ref
-
•
metallic command –Set SGn to 32 mA.
Comparator
From this point forward the LED may be turned on and off
using the tri-state command:
•
•
tri-state command –Disable tri-state for SGn (LED ON).
tri-state command –Enable tri-state for SGn (LED
OFF).
Figure 14. MOSFET or LED Driver Output
The sequence of commands (from Normal mode with
inputs tri-state) required to set up the device to drive a
MOSFET are as follows:
These parameters are easily programmed via SPI
commands in Normal mode.
•
•
•
•
wetting current timer enable command –Disable SPn
wetting current timer (refer to Table 9, page 16).
metallic command –Set SPn to 16/32 mA or 2.0/4.0 mA
gate drive current (refer to Table 8, page 15).
settings command –Set SPn as switch-to-battery (refer
to Table 6, page 14).
Multiple 33975 Devices in a Module System
Connecting power to the 33975 and the MCU for Sleep
mode operation may be done in several ways. Table 21
shows several system configurations for power between the
MCU and the 33975 and their specific requirements for
functionality.
tri-state command –Disable tri-state for SPn (refer to
Table 10, page 16).
After the tri-state command has been sent (tri-state
disable), the MOSFET gate will be pulled to ground. From this
point forward the MOSFET may be turned on and off by
sending the settings command:
Table 21. Sleep Mode Power Supply
MCU
VDD
33975
VDD
Comments
•
settings command –SPn as switch-to-ground
(MOSFET ON).
settings command –SPn as switch-to-battery
(MOSFET OFF).
All wake-up conditions apply. (Refer to Sleep
Mode, page 20.)
5.0 V
5.0 V
•
SPI wake-up is not possible.
5.0 V
0 V
0 V
Monitoring of the MOSFET drain in the OFF state provides
open load detection. This is done by using an input
comparator. With the SGn input in tri-state, the load will pull
up the input to battery. With the load open, the SGn terminal
is pulled down to ground through an external resistor. The
open load is indicated by a logic [1] in the SO data bit.
Sleep mode not possible. Current from CS pull
up will flow through MCU to VDD that has been
switched off. Negative edge of CS will put 33975
in Normal mode.
5.0 V
SPI wake-up is not possible.
0 V
0 V
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
TYPICAL APPLICATIONS
OPERATIONAL MODES
Multiple 33975 devices may be used in a module system.
SPI control may be done in parallel or serial. However when
parallel mode is used, each device is addressed
mode should be updated prior to sending the sleep
command.
The 33975 IC has an internal 5.0 V supply from the VPWR
independently (refer to MCU Interface Description, page 13).
Therefore when sending the sleep command, one device will
enter sleep before the other. For multiple devices in a system,
it is recommended that the devices are controlled in serial (S0
from first device is connected to SI of second device). With
two devices, 48 clock pulses are required to shift data in.
When the WAKE feature is used to enable the power supply,
both WAKE terminals should be connected to the enable
terminal on the power supply. The INT terminals may be
connected to one interrupt terminal on the MCU or may have
their own dedicated interrupt to the MCU.
terminal. A POR circuit monitors the internal 5.0 V supply. In
the event of transients on the VPWR terminal, an internal
reset may occur. Upon reset the 33975 will enter Normal
mode with the internal registers as defined in Table 15,
page 18. Therefore it is recommended that the MCU
periodically update all registers internal to the IC.
USING THE WAKE FEATURE
The 33975 provides a WAKE output and wake-up input
designed to control an enable terminal on system power
supply. While in the Normal mode, the WAKE output is low,
enabling the power supply. In the Sleep mode, the WAKE
terminal is high, disabling the power supply. The WAKE
terminal has a passive pull-up to the internal 5.0 V supply but
may be pulled up through a resistor to VPWR supply (see
The transition from Normal to Sleep mode is done by
sending the sleep command. With the devices connected in
serial and the sleep command sent, both will enter Sleep
mode on the rising edge of CS. When Sleep mode is entered,
the WAKE terminal will be logic [1]. If either device wakes up,
the WAKE terminal will transition low, waking the other
device.
Figure 16, page 26).
When the WAKE output is not used the terminal should be
pulled up to the VDD supply through a resistor as shown in
Figure 15, page 26).
A condition exists where the MCU is sending the sleep
command (CS logic [0]) and a switch input changes state.
With this event the device that detects this input will not
transition to Sleep mode, while the second device will enter
Sleep mode. In this case two switch status commands must
be sent to receive accurate switch status data. The first
switch status command will wake the device in Sleep mode.
Switch status data may not be valid from the first switch
status command because of the time required for the input
voltage to rise above the 4.0 V input comparator threshold.
This time is dependant on the impedance of SGn or SPn
node. The second switch status command will provide
accurate switch status information. It is recommended that
software wait 10 ms to 20 ms between the two switch status
commands, allowing time for switch input voltages to
stabilize. With all switch states acknowledged by the MCU,
the sleep sequence may be initiated. All parameters for Sleep
During the Sleep mode, a switch closure will set the WAKE
terminal low, causing the 33975 to enter the Normal mode.
The power supply will then be activated, supplying power to
the VDD terminal and the microprocessor and the 33975. The
microprocessor can determine the source of the wake-up by
reading the interrupt flag.
COST AND FLEXIBILITY
Systems requiring a significant number of switch
interfaces have many discrete components. Discrete
components on standard PWB consume board space and
must be checked for solder joint integrity. An integrated
approach reduces solder joints, consumes less board space,
and offers wider operating voltage, analog interface
capability, and greater interfacing flexibility.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
TYPICAL APPLICATIONS
OPERATIONAL MODES
VPWR
VDD
VDD
VBAT
VBAT
Power
Supply
33975
VPWR
VPWR
SP0
SP1
VDD
VDD
VBAT
MC68HCXX
Microprocessor
SP7
WAKE
CS
CS
SG0
SG1
INT
SI
INT
MOSI
MISO
SO
SCLK
SCLK
AN0
AMUX
SG12
SG13
Figure 15. Power Supply Active in Sleep Mode
VPWR
VDD
VDD
VBAT
VBAT
Power
Supply
33975
VPWR
Enable
VPWR
SP0
SP1
VDD
WAKE
VDD
VBAT
MC68HCXX
Microprocessor
SP7
CS
CS
SG0
SG1
INT
SI
INT
MOSI
MISO
SO
SCLK
SCLK
AN0
AMUX
SG12
SG13
Figure 16. Power Supply Shutdown in Sleep Mode
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
The silicon device is packaged in the 32 terminal SOIC with an exposed pad. The exposed pad is thermally conductive and
electrically isolated to the die. It is recommended that the exposed pad be electrically connected to ground.
Important: For the most current revision of the package, visit www.freescale.com and perform a “keyword” search on the “98A”
number listed below.
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
NOTES
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
NOTES
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should a Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, the Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
Semiconductor was negligent regarding the design or manufacture of the part.
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
Denver, Colorado 80217
© Freescale Semiconductor, Inc., 2005. All rights reserved.
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
MC33975
Rev 4.0
08/2005
相关型号：
PC33975AEK/R2
SPECIALTY INTERFACE CIRCUIT, PDSO32, 5.70 X 4.60 MM, 0.65 MM PITCH, LEAD FREE, SOIC-32
NXP
PC33975AR2
Multiple Switch Detection Interface with Suppressed Wake-Up and 32mA Wetting Current
FREESCALE
PC33981PNA
100A PWM BASED PRPHL DRVR, PQCC16, 12 X 12 MM, 2.10 MM HEIGHT, 0.90 MM PITCH, ROHS COMPLIANT, PLASTIC, QFN-16
NXP
PC33981PNA/R2
High-Frequency, High-Current, Self-Protected High-Side Switch (4.0 mз up to 60 kHz)
MOTOROLA
PC33981PNAR2
100A PWM BASED PRPHL DRVR, PQCC16, 12 X 12 MM, 2.10 MM HEIGHT, 0.90 MM PITCH, ROHS COMPLIANT, PLASTIC, QFN-16
NXP
PC33982PNA/R2
Buffer/Inverter Based Peripheral Driver, 0.15A, PBCC16, 12 X 12 MM, PLASTIC, QFN-16
MOTOROLA
©2020 ICPDF网 联系我们和版权申明