PC33981PNAR2 [NXP]
100A PWM BASED PRPHL DRVR, PQCC16, 12 X 12 MM, 2.10 MM HEIGHT, 0.90 MM PITCH, ROHS COMPLIANT, PLASTIC, QFN-16;
| 型号： | PC33981PNAR2 |
| 厂家： | 
NXP |
| 描述： | 100A PWM BASED PRPHL DRVR, PQCC16, 12 X 12 MM, 2.10 MM HEIGHT, 0.90 MM PITCH, ROHS COMPLIANT, PLASTIC, QFN-16 驱动 接口集成电路 驱动器 |
| 文件： | 总24页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Document order number: MC33981
Rev 2.0, 10/2004
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
33981
High-Frequency, High-Current,
Self-Protected High-Side Switch
(4.0 mΩ up to 60 kHz)
HIGH-SIDE SWITCH
4.0 mΩ
The 33981 is a high-frequency, self-protected 4.0 mΩ RDS(ON) high-side
switch used to replace electromechanical relays, fuses, and discrete devices
in power management applications.
The 33981 can be controlled by pulse-width modulation (PWM) with a
frequency up to 60 kHz. It is designed for harsh environments, and it includes
self-recovery features. The 33981 is suitable for loads with high inrush current,
as well as motors and all types of resistive and inductive loads.
The 33981 is packaged in a 12x 12 nonleaded power-enhanced Power
QFN package with exposed tabs.
Features
Bottom View
PNA SUFFIX
• Single 4.0 mΩ RDS(ON) Maximum High-Side Switch
• PWM Capability up to 60 kHz with Duty Cycle from 5% to 100%
• Very Low Standby Current
CASE 1402-02
16-TERMINAL PQFN (12 X 12)
• Slew Rate Control with External Capacitor
• Overcurrent and Overtemperature Protection, Undervoltage Shutdown
and Fault Reporting
• Reverse Battery Protection
• Gate Drive Signal for External Low-Side N-Channel MOSFET with
Protection Features
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
A
16 PQFN
PC33981PNA/R2
-40°C to 125°C
• Output Current Monitoring
• Temperature Feedback
33981 Simplified Application Diagram
VDD
VDD
VPWR
33981
SR
VPWR
CBOOT
CONF
FS
INLS
EN
OUT
DLS
I/O
I/O
I/O
I/O
MCU
INHS
TEMP
CSNS
A/D
A/D
M
GLS
OCLS
GND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
For More Information On This Product,
Go to: www.freescale.com
© Motorola, Inc. 2004
Freescale Semiconductor, Inc.
V
PWR
Undervoltage
Detection
Temperature
Feedback
TEMP
SR
C
Bootstrap Supply
BOOT
Gate Driver
Slew Rate Control
OUT
FS
EN
Current Protection
Logic
100 A
OUT Current
Recopy
1/20000
INHS
INLS
Overtemperature
Detection
Low-Side
Gate Driver
and Protection
GLS
DLS
5.0 V
RDWN
ICONF
IDWN
5.0 V
IOCLS
Cross-
Conduction
CONF
GND
CSNS
OCLS
Figure 1. 33981 Simplified Internal Block Diagram
33981
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Transparent Top View of Package
CSNS
TEMP
EN
1
2
3
4
5
6
7
8
9
16
15
OUT
OUT
INHS
FS
INLS
CONF
OCLS
DLS
14
VPWR
13
GND
GLS
10
11
SR
CBOOT
12
TERMINAL DEFINITIONS
Functional descriptions of some of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Name
Terminal
Formal Name
Definition
1
CSNS
Output Current Monitoring
This terminal is used to output a current proportional to the high-side OUT current and
is used externally to generate a ground-referenced voltage for the microcontroller
(MCU) to monitor OUT current.
2
3
4
5
TEMP
Temperature Feedback
This terminal reports an analog value proportional to the temperature of the GND flag
(terminal 13). It is used by the MCU to monitor board temperature.
Enable
(Active High)
This is an input used to place the device in a low current sleep mode. This terminal has
an passive internal pulldown.
EN
INHS
Serial Input High Side
The input terminal is used to directly control the OUT. This input has an active internal
pulldown current source and requires CMOS logic levels.
Fault Status
(Active Low)
This is an open drain-configured output requiring an external pull-up resistor to
FS
V
DD (5.0 V) for fault reporting. When a device fault condition is detected, this terminal
is active LOW.
6
7
INLS
CONF
Serial Input Low Side
Configuration Input
The input terminal is used to directly control an external low-side N-channel MOSFET
and has an active internal pulldown current source and requires CMOS logic levels. It
can be controlled independently of the INHS depending of CONF terminal.
This input terminal is used to manage the cross-conduction between the internal high-
side N-channel MOSFET and the external low-side N-channel MOSFET. The terminal
has an active internal pullup current source. When CONF is at 0 V, the two MOSFETs
are controlled independently. When CONF is at 5.0 V, the two MOSFETs cannot be on
at the same time.
8
OCLS
Low-Side Overload
This terminal sets the V protection level of the external low-side MOSFET. This
DS
terminal has an active internal pullup current source. It must be connected to an
external resistor.
9
DLS
GLS
SR
Drain Low Side
Low-Side Gate
This terminal is the drain of the external low-side N-channel MOSFET. Its monitoring
allows for protection features.
10
11
This terminal is an output used to drive the gate of the external low-side N-channel
MOSFET.
Slew Rate Control
A capacitor connected between this terminal and the ground is used to control the
output slew rate.
33981
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TERMINAL DEFINITIONS (continued)
Functional descriptions of some of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Name
Terminal
Formal Name
Definition
14
V
Positive Power Supply
This terminal connects to the positive power supply and is the source input of
PWR
operational power for the device. The VPWR terminal is a backside surface mount tab
of the package.
15, 16
OUT
Output
Protected high-side power output to the load. Output terminals must be connected in
parallel for operation.
33981
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Power Supply Voltage
Steady-State
V
V
PWR
-16 to 41
-0.3 to 7.0
-5.0 to 41
40
Input/Output Terminals Voltage (Note 1)
Output Voltage
V
V
V
IN
V
OUT
OUT
Continuous Output Current (Note 2)
CSNS Input Clamp Current
SR Voltage
I
A
I
10
mA
V
CSNS
VSR
-0.3 to 54
-0.3 to 5.0
-0.3 to 54
Temperature Feedback Voltage
VTEMP
V
C
V
C
Voltage
BOOT
BOOT
OCLS Voltage
V
-0.3 to 7.0
-0.3 to 15
-5.0 to 41
V
V
V
V
OCLS
Low-Side Gate Voltage
Low-Side Drain Voltage
V
GLS
DLS
V
ESD Voltage
V
V
±2000
±200
ESD1
ESD2
Human Body Model (Note 3)
Machine Model (Note 4)
Output Clamp Energy (Note 5)
E
TBD
J
CL
THERMAL RATINGS
°C
Operating Temperature
Ambient
T
A
-40 to 125
-40 to 150
T
Junction
J
Storage Temperature
T
-55 to 150
°C
STG
Thermal Resistance (Note 6)
Junction to Power Die Case
Junction to Ambient
°C/W
R
R
1.0
20
θJC
θJA
Peak Terminal Reflow Temperature During Solder Mounting (Note 7)
T
240
°C
W
SOLDER
Power Dissipation (TA = 25°C) (Note 8)
P
TBD
D
Notes
1. Exceeding voltage limits on INHS, INLS, CONF, CSNS, FS, TEMP, and EN terminals may cause a malfunction or permanent damage to the
device.
2. Continuous high-side output rating as long as maximum junction temperature is not exceeded. Calculation of maximum output current using
package thermal resistance is required.
3. ESD1 testing is performed in accordance with the Human Body Model (C
= 100 pF, R
= 1500 Ω).
ZAP
ZAP
4. ESD2 testing is performed in accordance with the Machine Model (C
= 200 pF, R
= 0 Ω) and in accordance with the system module
ZAP
ZAP
specification with a capacitor > 0.01 µF connected from OUT to GND.
5. Active clamp energy using single-pulse method (L = 16 mH, R = 0, VPWR = 12 V, TJ = 150°C).
L
6. Device mounted on a 2s2p test board per JEDEC JESD51-2.
7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
8. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used.
33981
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Battery Supply Voltage Range
Fully Operational
V
V
PWR
6.0
4.5
–
–
27
27
Extended
V
V
Supply Current
I
mA
PWR
PWR(ON)
–
–
–
–
10
10
Output ON, I
= 0 A
OUT
Supply Current
I
mA
PWR
PWR(SBY)
Output OFF, EN = 5.0 V, OUT Connected to GND
I
µA
Sleep State Supply Current (V
< 14 V, EN = 0 V)
PWR(SLEEP)
PWR
–
–
–
–
5.0
50
T = 25°C
J
T = 125°C
J
Undervoltage Shutdown
Undervoltage Hysteresis
V
2.0
–
–
4.0
–
V
V
PWR(UV)
V
0.3
PWR(UVHYS)
POWER OUTPUT
R
mΩ
mΩ
mΩ
Output Drain-to-Source ON Resistance (I
= 20 A, T = 25°C)
DS(ON)
OUT
OUT
OUT
J
–
–
–
–
–
–
6.0
5.0
4.0
V
V
V
= 6.0 V
= 10.0 V
= 13 V
PWR
PWR
PWR
R
Output Drain-to-Source ON Resistance (I
= 20 A, T = 150°C)
DS(ON)
J
–
–
–
–
–
–
10.2
8.5
V
V
V
= 6.0 V
= 9.0 V
= 13 V
PWR
PWR
PWR
6.8
R
Output Drain-to-Source ON Resistance (I
= - 13 V
= 20 A, T = 25°C)
DS(ON)
J
–
–
–
–
8.0
V
PWR
Output Overcurrent Detection Level
Current Sense Ratio
I
100
A
–
OCH
C
SR
9.0 V < V
< 16 V, CNS < 4.5V
–
1/20000
–
PWR
Current Sense Ratio (C ) Accuracy
SR
C
%
SR_ACC
Output Current
5.0 A
-20
-14
-12
–
–
–
20
14
12
10 A
30 A
Current Sense Voltage Clamp
V
CL(CSNS)
V
I
CCNS = 15 mA
4.5
6.0
7.0
33981
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT (continued)
Overtemperature Shutdown
Overtemperature Shutdown Hysteresis (Note 9)
Low-Side Gate
T
160
5.0
175
–
190
20
°C
SD
T
°C
SD(HYS)
VGSLS
V
V
V
V
V
= 6.0 V
= 9.0 V
= 13 V
= 27 V
–
–
–
–
6.0
9.0
12
–
–
–
–
PWR
PWR
PWR
PWR
12
Low-Side Gate Current
C = 4.7 nF
IGSLS
mA
mV
–
–
100
–
–
Low-Side Overload Detection Level versus Low-Side Drain Voltage
V
DS_LS
V
OCLS - VDLS
50
Temperature Feedback
T
V
Feed
T = 25°C
J
TBD
–
4.75
-12
TBD
–
Temperature Feedback Derating
DT
mV/°C
Feed
CONTROL INTERFACE
Input Logic High Voltage (Note 10)
V
0.7
–
–
–
–
0.2
750
20
400
–
V
V
IH
DD
Input Logic Low Voltage (Note 10)
Input Logic Voltage Hysteresis (Note 10)
Input Logic Active Pulldown Current (INHS, INLS)
Input Logic Pulldown Resistor (EN)
Input Active Pullup Current (OCLS)
Input Active Pullup Current (CONF)
FS Tri-State Capacitance (Note 9)
FS Low-State Output Voltage
V
IL
DD
V
100
5.0
100
–
350
–
mV
µA
kΩ
µA
µA
pF
V
IN(HYS)
I
DWN
R
200
100
10
–
DWN
I
OCLSp
I
–
–
CONF
C
–
20
0.4
SO
V
–
0.2
SOL
Notes
9. Parameter is guaranteed by process monitoring but is not production tested.
10. Upper and lower logic threshold voltage range applies to EN, CONF, INHS, and INLS input signals.
33981
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE AND POWER OUTPUT TIMING
–
20
–
µs
tON
C
Charge Blanking Time (Note 11)
BOOT
Output Rising Slew Rate (Note 12)
SR
V/µs
R
V
= 14 V
–
–
25
–
–
–
PWR
C
= 6.8 nF, from 10% to 90% of V
SR Capacitor = 4.7 nF
SR Capacitor = 4.7 nF
GATE
OUT,
Output Falling Slew Rate (Note 12)
SR
V/µs
F
V
= 14 V
–
–
25
–
–
–
PWR
C
= 6.8 nF, from 90% to 10% of V
GATE
OUT,
Output Turn-ON Delay Time (Note 13)
Output Turn-OFF Delay Time
Input Switching Frequency (Note 14)
Notes
–
–
–
200
400
–
–
–
ns
ns
tDLY(ON)
tDLY(OFF)
f
60
kHz
PWM
11. Refer to the paragraph entitled Sleep Mode on page 19.
12. Parameter is guaranteed by process monitoring but is not production tested.
13. Turn-ON delay time measured from rising edge of INHS that turns the output ON to V
= 0.5 V with R = 5.0 Ω resistive load.
L
OUT
14. Turn-OFF delay time measured from falling edge of INHS that turns the output OFF to V
= V
-0.5 V with R = 5.0 Ω resistive load.
PWR L
OUT
33981
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Table 1. Functional Truth Table in Normal Mode
Condition
CONF INHS INLS OUT
GLS
FS
EN
Comments
Sleep
x
x
x
x
x
H
L
Device is in Sleep mode. The OUT and
low-side gate are OFF.
Normal
Normal
Normal
Normal
Normal
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
Normal mode. High side and low side are
controlled independently. The high side
and the low side are both on.
L
H
H
H
L
L
L
H
L
L
L
Normal mode. High side and low side are
controlled independently. The high side
and the low side are both off.
H
L
Normal mode. No cross-conduction. Half-
bridge configuration. The high side is off
and the low side is on.
H
H
Normal mode. No cross-conduction. Half-
bridge configuration. The high side is on
and the low side is off.
PWM
H
PWM
PWM
OR H
(Logical
OR)
Normal mode. Cross-conduction
management is activated. Half-bridge
configuration.
H = High level
L = Low level
x = Don’t care
PWM = Pulse-width modulation
Table 2. Functional Truth Table in Fault Mode
Conditions
CONF INHS INLS OUT
GLS
FS
EN
TEMP CSNS OCLS
Comments
Overtemperature
on OUT
x
x
x
L
x
x
L
L
L
x
x
L
H
L
L
x
x
x
x
L
x
x
x
x
L
The 33981 is currently in fault mode. The
OUT is OFF. TEMP at 0 V indicates this
fault. Once the fault is removed 33981
recovers its normal mode.
Overtemperature
x
x
L
x
L
L
L
L
H
H
H
The 33981 is currently in fault mode. The
OUT is OFF and GLS is at 0 V. TEMP at
0 V indicates this fault. Once the fault is
removed 33981 recovers its normal mode.
on C
or GLS
BOOT
Overcurrent
on OUT
H
x
x
The 33981 is currently in fault mode. The
OUT is OFF. It is reset by a logic [0] at
INHS for at least 200 µs. When INHS goes
to 0 V, CSNS goes to 5.0 V.
Overload
on External Low-
Side MOSFET
H
The 33981 is currently in fault mode. GLS
is at 0 V and OCLS internal current source
is off. The external resistance connected
between OCLS and GND terminal will pull
OCLS terminal to 0 V. The fault is reset by
a logic [0] at INLS for at least 200 µs.
H = High level
L = Low level
x = Don’t care
33981
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Timing Diagram
INHS
OUT
V
- 0.5 V
0.5 V
PWR
tDLY(OFF)
Figure 2. Time Delays
tDLY(ON)
33981
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Functional Diagrams
EN
CONF
0 V
High Side ON
High Side OFF
INHS
Low Side ON
INLS
OUT
Thermal Shutdown on OUT
0 V
GLS
FS
Thermal Shutdown on OUT
5.0 V
Thermal Shutdown on OUT
5.0 V
0 V
0 V
Thermal Shutdown
on OUT
Thermal Shutdown
on OUT
TEMP
0 V
Thermal Shutdown on OUT
High Side OFF
Thermal Shutdown on OUT
High Side ON
TSD
TSD
Temperature
OUT
Hysteresis
Hysteresis
Figure 3. Overtemperature on Output
33981
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EN
CONF
0 V
High Side ON
High Side OFF
INHS
Low Side ON
INLS
OUT
Thermal Shutdown on Bootstrap Circuit or on Low-Side Gate Drive
0 V
Thermal Shutdown
GLS
FS
0 V
Thermal Shutdown
Thermal Shutdown
5.0 V
15 µs After
15 µs After
0 V
0 V
Thermal Shutdown
Thermal Shutdown
TEMP
Thermal Shutdown
Thermal Shutdown
TSD
TSD
Temperature
Control
Hysteresis
Hysteresis
Figure 4. Overtemperature on Bootstrap Circuit or on Low-Side Gate Drive
33981
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EN
INLS
0 V
200 µs Min
Overload on Low Side
GLS
0 V Low Side OFF
Overload on Low Side
5.0 V
FS
0 V
Overload on Low Side
OCLS
0 V
Overload on Low Side
VDS_LS = VOCLS
V
DS_LS
Case 1: Overload Removed
Figure 5. Overload on Low-Side Gate Drive, Case 1
EN
INLS
0 V
200 µs Min
Overload on Low Side
GLS
0 V Low Side OFF
Overload on Low Side
FS
0 V
Overload on Low Side
OCLS
0 V
Overload on Low Side
VDS_LS = VOCLS
Case 2: Low Side Still Overloaded
V
DS_LS
Figure 6. Overload on Low-Side Gate Drive, Case 2
33981
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EN
INHS
0 V
200 µs Min
Overcurrent on High Side
OUT
0 V
5.0 V
Overcurrent on High Side
FS
0 V
Overcurrent on High Side
5.0 V
CSNS
0 V
Overcurrent on High Side
I
OCH
Fault Removed
I
OUT
Figure 7. Overcurrent on Output
EN
FS
15 µs After
5.0 V
CONF
INHS
INLS
OUT
GLS
Figure 8. Normal Mode. Cross-Conduction Management
33981
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EN
15 µs After
FS
CONF
0 V
High Side ON
INHS
High Side OFF
INLS
OUT
GLS
Figure 9. Normal Mode. Independent High Side and Low Side
INHS
IOUT
CSNS
CSNS
FS
Figure 10. High-Side Overcurrent
33981
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INHS
GLS
Iout
Current in Motor
Recirculation in Low Side
OUT
Figure 11. Cross-Conduction with Low Side
Overtemperature
INHS
TEMP
OUT
IOUT
Figure 12. Overtemperature on OUT
33981
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EN
Overtemperature
OUT
TEMP
IOUT
Figure 13. Overtemperature on Bootstrap Circuit or on Low-Side Gate Drive
Figure 14. Maximum Operating Frequency for SR Capacitor of 4.7 nF
33981
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Electrical Performance Curves
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-50
0
50
100
150
200
Temperature (°C)
Figure 15. R
versus Temperature
DS(ON)
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
4.5
6.0
9.0
12.0
12.5 13.0
(V)
14.0 17.0
21.0
V
PWR
Figure 16. Sleep State Supply Current versus V
at 150°C
PWR
33981
18
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33981 is a high-frequency self-protected silicon 4.0 mΩ
RDS(ON) high-side switch used to replace electromechanical
The 33981 is suitable for loads with high inrush current, as
well as motors and all types of resistive and inductive loads. A
dedicated parallel input is available for an external low-side
control with protection features and cross-conduction
management.
relays, fuses, and discrete devices in power management
applications. The 33981 can be controlled by pulse-width
modulation (PWM) with a frequency up to 60 kHz. It is designed
for harsh environments, and it includes self-recovery features.
FUNCTIONAL DESCRIPTION
terminal transition to logic [1] will be disabled typically 15 µs
after to enable the charge of the bootstrap capacitor.
Sleep Mode
Sleep mode is the state of the 33981 when the EN is logic [0].
In this mode, OUT, the gate driver for the external MOSFET,
and all unused internal circuitry are off to minimize current draw.
Figure 13, page 17, shows an overtemperature on the
bootstrap circuit or on the low-side gate drive. As the
temperature increases, TEMP voltage decreases until thermal
shutdown.
The 33981 will go to the normal operating mode when the EN
terminal is logic [1]. The INHS and INLS commands will be
disabled typically 20 µs after the EN transitions to logic [1] to
enable the charge of the bootstrap capacitor.
Overtemperature faults force the TEMP terminal to 0 V.
Overcurrent Fault on High Side
Fault Logic
The OUT terminal has a 100 A overcurrent high-detection
level for maximum device protection. If at any time the current
reaches this level, OUT will stay OFF and the CSNS terminal
will go to 0 V. The OUT terminal is reset by a logic [0] at the
INHS terminal for at least 200 µs. When INHS goes to 0 V,
CSNS goes to 5.0 V.
This 33981 indicates the faults below as they occur by
driving the FS terminal to logic [0]:
• Overtemperature
• Overcurrent fault on OUT
• Overload fault on the external low-side MOSFET
In Figure 11, page 16, the OUT terminal is short-circuited to
0 V. When the current reaches IOCH, OUT is turned OFF within
The FS terminal will return to logic [1] when the
overtemperature fault condition is removed. The two other
faults are latched.
10 µs owing to internal logic circuit.
Overload Fault on Low Side
Undervoltage
This fault detection is active when INLS is logic [1]. Low-side
overload protection does not measure the current directly but
rather its effects on the low-side MOSFET. When VGLS > VGSH
The latched faults are reset when the VPWR voltage is below
V
.
PWR(UV)
and VDLS > VDSH for at least 2.5 µs, the GLS terminal goes to
Overtemperature Fault
0 V and the OCLS internal current source is disconnected and
OCLS goes to 0 V. The GLS terminal and the OCLS terminal
are reset by a logic [0] at the INLS terminal for at least 200 µs.
The 33981 incorporates overtemperature detection and
shutdown circuitry on OUT. Overtemperature detection also
protects the bootstrap circuit (CBOOT terminal) and the low-side
When connected to an external resistor, the OCLS terminal
with its internal current source sets the VDSH level. By changing
gate driver (GLS terminal). Overtemperature detection occurs
when OUT is in the ON or OFF state and GLS is at high or low
level.
the external resistance, the protection level can be adjusted
depending on low-side characteristics. A 3.3 kΩ resistor gives
a VDSH level of 3.3 V typical.
For OUT, an overtemperature fault condition results in OUT
turning OFF until the temperature falls below TSD. This cycle will
This protection circuitry measures the voltage between the
drain of the low side (DLS terminal) and the 33981 ground
(GND terminal). It also uses the voltage across the external
resistance connected to the OCLS terminal and the GND
terminal. For this reason it is key that the low-side source, the
33981 ground, and the external resistance ground connection
are connected together in order to prevent false error detection
due to ground shifts.
continue indefinitely until the offending load is removed.
Figure 12, page 16, shows an overtemperature on OUT.
An overtemperature fault on the bootstrap circuit or on the
low-side gate drive results in OUT turning OFF and the GLS
going to 0 V until the temperature falls below TSD. This cycle will
continue indefinitely until the offending load is removed. FS
33981
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Configuration
Thermal Feedback
The CONF terminal manages the cross-conduction between
the internal MOSFET and the external low-side MOSFET. With
the CONF terminal at 0 V, the two MOSFETs can be
independently controlled. A load can be placed between the
high side and the low side.
The 33981 has an analog feedback output (TEMP terminal)
that provides a value proportional to the temperature of the
GND flag (terminal 13). The controlling microcontroller can
“read” the temperature proportional voltage with its analog-to-
digital converter (ADC). This can be used to provide real-time
monitoring of the PC board temperature to optimize the motor
speed and to protect the whole electronic system. TEMP
terminal value is typically 4.2 V at 25°C with a negative
temperature coefficient of 10 mV/K.
With the CONF terminal at 5.0 V, the two MOSFETs cannot
be on at the same time. They are in half-bridge configuration as
shown in the simplified application diagram on page 1. If INHS
and INLS are at 5.0 V at the same time, INHS has priority and
OUT will be at VPWR. If INHS changes from 5.0 V to 0 V with
Reverse Battery
INLS at 5.0 V, GLS will go to high state as soon as the VGS of
The 33981 survives the application of reverse battery voltage
as low as -16 V. Under these conditions, the output’s gate is
enhanced to decrease device power dissipation. No additional
passive components are required. The 33981 survives these
conditions until the maximum junction rating is reached.
the internal MOSFET is lower than TBD typically. A half-bridge
application could consist in sending PWM signal to the INHS
terminal and 5.0 V to the INLS terminal with the CONF terminal
at 5.0 V.
Figure 11, page 16, illustrates the simplified application
diagram on page 1 with a DC motor and external low side. The
CONF and INLS terminals are at 5.0 V. When INHS is at 5.0 V,
current is flowing in the motor. When INHS goes to 0 V, the load
current recirculates in the external low side.
In the case of reverse battery in a half-bridge application, a
direct current passes through the external freewheeling diode
and the internal high-side.
As Figure 17 shows, it is essential to protect this power line.
The proposed solution is an external low-side with its gate tied
to battery voltage through a resistor. A high-side in the VPWR
Bootstrap Supply
line could be another solution but with a more complex drive.
Bootstrap supply provides current to recharge the bootstrap
capacitor through the VPWR terminal. A short time is required
after the application of power to the device to charge the
bootstrap capacitor. A typical value for this capacitor is 100 nF.
An internal charge pump allows continuous MOSFET drive.
When the device is in the sleep mode, this bootstrap supply is
off to minimize current consumption.
V
V
PWR
DD
33981
MCU
No current
GND OUT
High-Side Gate Driver
The high-side gate driver switches the bootstrap capacitor
voltage to the gate of the MOSFET. The driver circuit has a low-
impedance drive to ensure that the MOSFET remains OFF in
the presence of fast falling dV/dt transients on the OUT
terminal.
Diode
V
M
PWR
This bootstrap capacitor connected between the power
supply and the CBOOT terminal provides the high pulse current
to drive the device. The voltage across this capacitor is limited
to about 13 V. CBOOT is protected against short by a local
overtemperature sensor.
Figure 17. Reverse Battery Protection
An external capacitor connected between terminals SR and
GND is used to control the slew rate at the OUT terminal.
Low-Side Gate Driver
The low-side control circuitry is PWM capable. It can drive a
standard MOSFET with an R
as low as 4.0 mΩ at a
DS(ON)
frequency up to 60 kHz. The V is internally clamped at 14 V
GS
typically to protect the gate of the MOSFET. The GLS terminal
is protected against short by a local overtemperature sensor.
33981
20
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APPLICATIONS
Figure 18 shows a typical application for the 33981. A brush
DC motor is connected to the output. A low-side gate driver is
used for the freewheeling phase. Typical values for the external
capacitors and resistances are given.
VPWR
VDD
VDD
33981
VPWR
330 µF
SR
1.0 kΩ
2.2 nF
CBOOT
100 nF
CONF
FS
OUT
DLS
I/O
INLS
EN
I/O
I/O
MCU
I/O
INHS
TEMP
CSNS
OCLS
A/D
A/D
M
GLS
GND
1.0 kΩ
33 kΩ
Figure 18. 33981 Typical Application Diagram
33981
21
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PACKAGE DIMENSIONS
PNA SUFFIX
16-TERMINAL PQFN
NONLEADED PACKAGE
CASE 1402-02
ISSUE B
12
A
M
2X
12
1
0.1
C
PIN 1
INDEX AREA
12
15
16
M
2X
0.1 C
PIN NUMBER
REF. ONLY
B
0.1
C
2.20
1.95
2.2
2.0
0.05 C
4
DETAIL G
0.6
0.05
0.00
10X 0.2
0.1
SEATING PLANE
C
M
M
C A B
C
DETAIL G
0.95
0.55
0.1
0.05
VIEW ROTATED 90˚ CLOCKWISE
2X
9X 0.9
M
M
C A B
C
C A B
0.1
0.05
2X 1.075
5.0
4.6
1
12
1.1
0.6
6X
2.05
6X
1.55
13
2.5
2.1
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
3.55
1.85
1.45
4X 1.05
5.5
5.1
14
4. COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
5. MINIMUM METAL GAP SHOULD BE 0.25MM.
(2)
0.1 C A B
0.8
6X
0.4
16
15
(10X 0.25)
(2X 0.75)
0.1 C A
1.28
0.88
2X
(0.5)
2.25
1.75
0.15
0.05
(10X 0.4)
(10X 0.5)
6 PLACES
10.7
B
10.3
0.1 C A
B
B
11.2
10.8
0.1 C A
VIEW M-M
33981
22
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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NOTES
33981
23
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
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© Motorola, Inc. 2004
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MC33981
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相关型号：
PC33982PNA/R2
Buffer/Inverter Based Peripheral Driver, 0.15A, PBCC16, 12 X 12 MM, PLASTIC, QFN-16
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