PC33987PNCR2 [NXP]
PC33987PNCR2;
NXP 
Freescale Semiconductor, Inc.
Document order number: MC33987
Rev 2.0, 02/2005
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
33987
Quad Intelligent High-Side Switch
(Quad 70 mΩ)
The 33987 is one in a family of devices designed for low-voltage automotive
and industrial lighting and motor control applications. Its four low RDS(ON)
MOSFETs (four 70 mΩ) can control the high sides of four separate resistive or
inductive loads.
QUAD INTELLIGENT
HIGH-SIDE SWITCH
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each output has its own parallel input for PWM control
if desired. The 33987 allows the user to program via the SPI the fault current
trip levels and duration of acceptable lamp inrush or motor stall intervals. Such
programmability allows tight control of fault currents and can protect wiring
harnesses and circuit boards as well as loads.
The 33987 is packaged in a power-enhanced 10x10 nonleaded Power
QFN package with exposed tabs.
Bottom View
Features
• Quad 70 mΩ High-Side Switches
PNC SUFFIX
98ARL10591D
24-TERMINAL PQFN
• Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 µA
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output-
OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout,
Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe
Terminal Status, and Program Status
ORDERING INFORMATION
Temperature
Device
Package
Range (T )
A
• Analog Current Feedback with Selectable Ratio
PC33987PNC/R2
-40°C to 125°C
24 PQFN
• Enhanced 16 V Reverse Polarity VPWR Protection
33987 Simplified Application Diagram
VPWR
VDD
VDD
VDD
VPWR
33987
VDD
VPWR
HS0
WAKE
FS
I/O
SI
LOAD 0
LOAD 1
SO
SO
SI
HS1
HS2
HS3
SCLK
CS
SCLK
CS
MCU
I/O
RST
IN0
I/O
LOAD 2
LOAD 3
I/O
IN1
I/O
IN2
I/O
IN3
A/D
CSNS
FSI
GND
GND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
For More Information On This Product,
Go to: www.freescale.com
© Motorola, Inc. 2005
Freescale Semiconductor, Inc.
V
V
PWR
DD
V
IC
Internal
Regulator
Over/Undervoltage
Protection
I
I
UP
CS
SCLK
Selectable Slew
Rate Gate Drive
SPI
3.0 MHz
DWN
HS0
Selectable Overcurrent
High Detection
HS[0:3]: 26 A to 36 A
SO
SI
RST
WAKE
FS
Selectable Over-
current Low Detection
Blanking Time
Selectable Over-
current Low Detection
HS[0:3]: 1.8 A to 6.7 A
Logic
IN0
0.15 ms–155 ms
IN1
IN2
IN3
Open Load
Detection
Overtemperature
Detection
HS0
R
I
DWN
DWN
HS1
HS1
HS2
HS3
V
IC
Programmable
Watchdog
HS2
HS3
310 ms–2500 ms
FSI
Selectable Output Current
Recopy (Analog MUX)
HS[0:3]: 1/4600 or 1/13500
GND
CSNS
Figure 1. 33987 Simplified Internal Block Diagram
33987
2
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Transparent Top View of Package
10
9
8
7
6
5
4
3
2 1
24
11
12
13
VDD
SO
NC
IN0
23
22
CSNS
FSI
GND
14
15
21
NC
NC
16
VPWR
HS3
HS2
17
18
19
20
HS1
HS0
TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section beginning on page 15.
Terminal
Name
Terminal
Formal Name
Definition
The IN0:IN3 high-side input terminals are used to directly control HS0:HS3 high-side
output terminals, respectively.
1
2
3
IN1
IN2
IN3
IN0
Serial Inputs
24
This terminal is an open drain configured output requiring an external pullup resistor to
4
5
FS
Fault Status
(Active Low)
V
for fault reporting. If a device fault condition is detected, this terminal is active
DD
LOW. Specific device diagnostic faults are reported via the SPI SO terminal.
This terminal is an input that controls the device mode and watchdog timeout feature if
enabled.
WAKE
Wake
These terminals are the ground for the logic and analog circuitry of the device.
6, 15
7
GND
RST
Ground
Reset
This terminal is an input used to initialize the device configuration and fault registers,
as well as place the device in a low-current sleep mode. The terminal also starts the
watchdog timer when transitioning from logic [0] to logic [1]. This terminal should not be
allowed to be logic [1] until V is in regulation. This terminal has a passive internal
DD
pulldown.
This input terminal is connected to a chip select output of a master microcontroller
(MCU). The MCU determines which device is addressed (selected) to receive data by
pulling the CS terminal of the selected device logic LOW, thereby enabling SPI
communication with the device. Other unselected devices on the serial link having their
CS terminals pulled up logic HIGH disregard the SPI communication data sent. This
terminal has an active internal pullup current source and requires CMOS logic levels.
8
9
CS
Chip Select
(Active Low)
This input terminal is connected to the MCU providing the required bit shift clock for SPI
communication. It transitions one time per bit transferred at an operating frequency,
SCLK
Serial Clock
f
, defined by the communication interface. The 50 percent duty cycle CMOS level
SPI
serial clock signal is idle between command transfers. The signal is used to shift data
into and out-of the device. This terminal has an active internal pulldown current source.
33987
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TERMINAL DEFINITIONS (continued)
A functional description of each terminal can be found in the System/Application Information section beginning on page 15.
Terminal
Name
Terminal
Formal Name
Definition
This terminal is a command data input terminal connected to the SPI Serial Data Output
of the MCU or to the SO terminal of the previous device of a daisy chain of devices. The
input requires CMOS logic level signals and incorporates an internal active pulldown.
Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control
command. The MCU ensures data is available upon the falling edge of SCLK. The logic
state of SI present upon the rising edge of SCLK loads that bit command into the
internal command shift register. This terminal has an active internal pulldown current
source.
10
SI
Serial Input
This terminal is an external voltage input terminal used to supply power to the SPI
11
12
V
Digital Drain Voltage
(Power)
DD
circuit. In the event V is lost, an internal supply provides power to a portion of the
DD
logic, ensuring limited functionality of the device.
This terminal is an output terminal connected to the SPI Serial Data Input terminal of
the MCU or to the SI terminal of the next device of a daisy chain of devices. This output
will remain tri-stated (high impedance OFF condition) so long as the CS terminal of the
device is logic HIGH. SO is only active when the CS terminal of the device is asserted
logic LOW. The generated SO output signals are CMOS logic levels. SO output data is
available on the falling edge of SCLK and transitions immediately on the rising edge of
SCLK.
SO
Serial Output
These terminals may not be connected.
13, 14, 21
16
NC
No Connect
This terminal connects to the positive power supply and is the source of operational
V
Positive Power Supply
PWR
power for the device. The V
package.
contact is the backside surface mount tab of the
PWR
Protected 70 mΩ high-side power output terminals to the load.
17
18
19
20
HS3
HS1
HS0
HS2
Outputs
The value of the resistance connected between this terminal and ground determines
the state of the outputs after a Watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF or the output HSO only is ON.
22
FSI
Fail-Safe Input
The Current Sense terminal sources a current proportional to the designated HS0:HS3
output.
23
CSNS
Output Current
Monitoring
33987
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Operating Voltage Range
Steady-State
V
V
PWR(SS)
-16 to 41
0 to 5.5
V
Supply Voltage
V
V
V
DD
DD
Input/Output Voltage (Note 1)
V
, RST, FSI,
-0.3 to 7.0
IN[0:3]
CSNS, SI, SCLK,
CS, FS
SO Output Voltage (Note 1)
WAKE Input Clamp Current
CSNS Input Clamp Current
Output Current (Note 2)
V
-0.3 to V +0.3
V
mA
mA
A
SO
CL(WAKE)
DD
I
2.5
2.5
I
CL(CSNS)
I
5.0
HS[0:3]
Output Clamp Energy (Note 3)
E
TBD
J
CL
ESD Voltage
V
Human Body Model (Note 4)
Machine Model (Note 5)
Charge Device Model
V
±2000
±200
TBD
ESD1
ESD2
ESD3
V
V
THERMAL RATINGS
Operating Temperature
Ambient
°C
T
-40 to 125
-40 to 150
A
Junction
T
J
Storage Temperature
T
-55 to 150
°C
STG
Thermal Resistance (Note 6)
Junction to Case
°C/W
R
JC
JA
θ
<1.0
25
R
Junction to Ambient
θ
Peak Package Reflow Temperature During Solder Mounting (Note 7)
Notes
T
240
°C
SOLDER
1. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, SI, SO, SCLK, CS, or FS terminals may cause a malfunction or permanent damage to
the device.
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = TBD mH, R = 0 Ω, V
= 12 V, T = 150°C).
J
L
PWR
4. ESD1 testing is performed in accordance with the Human Body Model (C
= 100 pF, R
= 1500 Ω).
ZAP
ZAP
5. ESD2 testing is performed in accordance with the Machine Model (C
= 200 pF, R
= 0 Ω) and in accordance with the system module
ZAP
ZAP
specification with a capacitor > 0.01 µF connected from high-side outputs to GND.
6. Device mounted on a 2s2p test board per JEDEC JESD51-2
7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
33987
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Battery Supply Voltage Range
Fully Operational
V
V
PWR
6.0
–
–
–
27
20
V
Operating Supply Current (Measured with All Outputs ON,
I
mA
mA
PWR
PWR(
)
on
HS[0:3] Open)
V
Supply Current
I
PWR
PWR(
)
sby
Outputs OFF, Open Load Detection Disabled, WAKE > 0.7 V
,
DD
RST = V
–
–
5.0
LOGIC HIGH
Sleep State Supply Current (V
< 14 V, RST < 0.5 V, WAKE < 0.5 V)
I
µA
PWR
PWR(
)
sleep
–
–
–
–
10
50
T = 25°C
J
T = 85°C
J
V
V
Supply Voltage
V
4.5
5.0
5.5
V
DD
DD(
)
on
Supply Current
I
mA
DD
DD(
)
on
No SPI Communication
–
–
–
–
1.0
5.0
3.0 MHz SPI Communication
V
Sleep State Current
I
–
28
–
33
5.0
36
µA
V
DD
DD(
)
sleep
Overvoltage Shutdown Threshold
Overvoltage Shutdown Hysteresis
V
PWR(OV)
V
0.1
4.7
0.24
–
1.0
5.3
0.38
–
2.0
6.2
0.54
5.0
V
PWR(OVHYS)
Undervoltage Output Shutdown Threshold (Note 8)
Undervoltage Hysteresis (Note 9)
V
V
PWR(UV)
V
V
V
PWR(UVHYS)
PWR(UVPOR)
Undervoltage Power-ON Reset on Internal Logic
V
OUTPUTS HS0 TO HS3
Output Drain-to-Source ON Resistance (I
= 1.0 A, T = 25°C)
R
mΩ
mΩ
mΩ
HS[0:3]
J
DS(ON)
V
V
V
= 6.0 V
= 10 V
= 13 V
–
–
–
–
–
–
105
70
PWR
PWR
PWR
70
Output Drain-to-Source ON Resistance (I
= 1.0 A, T = 150°C)
R
HS[0:3]
J
DS(ON)
V
V
V
= 6.0 V
= 10 V
= 13 V
–
–
–
–
–
–
178
119
119
PWR
PWR
PWR
Output Source-to-Drain ON Resistance (Note 10)
= -1.0 A, T = 25°C, V = -12 V
R
SD(ON)
I
–
70
140
HS[0:3]
J
PWR
Notes
8. Output will automatically recover to instructed state when V
voltage is restored to normal so long as the V
degradation level did not
PWR
PWR
go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by V
and assumes that the
PWR
external V supply is within specification.
DD
9. This applies when the undervoltage fault is not latched (IN[0:3] = 0).
10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V
.
PWR
33987
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS HS0 TO HS3 (continued)
Output Overcurrent High Detection Levels (9.0 V < V
< 16 V)
A
PWR
SOCH = 0
SOCH = 1
I
I
28.4
20
36
26
45.8
33.4
OCH0
OCH1
Overcurrent Low Detection Levels (SOCL[2:0], (9.0 V < V
< 16 V)
A
PWR
000
001
010
011
100
101
110
111
I
I
I
I
I
I
I
I
5.2
4.6
4.1
3.6
3.0
2.4
1.6
1.3
6.7
6.0
5.3
4.7
3.9
3.2
2.5
1.8
8.6
7.7
6.9
6.1
5.1
4.2
3.5
2.4
OCL0
OCL1
OCL2
OCL3
OCL4
OCL5
OCL6
OCL7
Current Sense Ratio (9.0 V < V
(Note 14)
< 16 V, CSNS < 4.5 V, I
= 1.0 A)
HS[0:3]
–
PWR
C
C
1/3700
1/4600
1/5700
SR0
SR1
DICR D2 = 0
DICR D2 = 1
1/10900
1/13500
1/16800
Current Sense Ratio (C ) Drift (Note 11) (Note 14)
C
%
SR
SR_DR
9.0 V < V
< 16 V, CSNS < 4.5 V, -40°C < T < 125°C, I
= 1.0 A
-5.0
–
5.0
PWR
J
HS[0:3]
Current Sense Clamp Voltage at I = 5.0 A (CSNS open) CSR0 (Note 15)
V
4.5
30
5.3
–
7.0
V
µA
V
HS
CL(MaxCSNS)
Open Load Detection Current (Note 12)
I
100
OLDC
Output Fault Detection Threshold (open load detection)
Output Programmed OFF
V
OFD(THRES)
2.0
-20
3.0
–
4.0
–
Output Negative Clamp Voltage
V
V
CL
0.5 A < I
< 2.0 A, Output OFF
HS[0:3]
Overtemperature Shutdown Hysteresis (Note 13)
Overtemperature Shutdown (Note 13)
T
5.0
–
20
°C
°C
SD(HYS)
T
155
175
190
SD
Notes
11. Based on statistical data. Not production tested.
12. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
13. Guaranteed by process monitoring. Not production tested.
14. For one current recopy enabled
15.
I
= I
+ I
+ I
+ I
HS2 HS3
HS
HS0
HS1
33987
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE
Input Logic High Voltage (Note 16)
V
0.7V
–
–
–
–
V
V
IH
DD
Input Logic Low Voltage (Note 16)
V
0.2V
DD
IL
Input Logic Voltage Hysteresis (Note 17)
Input Logic Pulldown Current (SCLK, SI, IN[0:3]),
V
100
5.0
750
–
1060
20
mV
µA
IN(HYS)
I
DWN
Voltage<0.2 V
DD
SO, FS Tri-State Capacitance (Note 16)
Input Logic Pulldown Resistor (RST) and WAKE
Input Capacitance (Note 18)
C
–
100
–
–
20
400
12
pF
kΩ
pF
V
SO
R
200
4.0
DWN
C
IN
CL(WAKE)
Wake Input Clamp Voltage (Note 19)
V
I
< 2.5 mA
7.0
-2.0
–
–
14
-0.1
–
CL(WAKE)
Wake Input Forward Voltage
= -2.5 mA
V
V
V
F(WAKE)
I
CL(WAKE)
SO High-State Output Voltage
= 1.0 mA
V
SOH
I
0.8V
–
OH
DD
FS, SO Low-State Output Voltage
= -1.6 mA
V
V
SOL
I
–
0.2
0.0
–
0.4
5.0
20
OL
SO Tri-State Leakage Current
I
µA
µA
kW
SO(LEAK)
CS > 0.7 V
DD
-5.0
5.0
Input Logic Pullup Current (Note 20)
CS, V > 0.7 V
I
UP
IN
DD
FSI Input terminal External Pulldown Resistance (Note 21)
FSI Disabled, HS[0:3] Indeterminate
R
FS
R
–
0.0
6.5
1.0
7.0
19
–
FSdis
FSI Enabled, all HS OFF
R
R
R
6.0
15
30
FSoffoff
FSonoff
FSonon
FSI Enabled, HS0 ON, HS[1:3] OFF
17
FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF
Infinite
RSTB & Wake input voltage threshold (when waking the device)
V
1.0
2.0
3.5
V
WAKE
Notes
16. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST signals
may be supplied by a derived voltage referenced to V
.
PWR
17. No hysteresis on FSI and wake pins. Parameter is guaranteed by process monitoring but is not production tested.
18. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
19. The current must be limited by a series resistance when using voltages > 7.0 V.
20. Pullup current is with CS OPEN. CS has an active internal pullup to V
.
DD
21. The selection of the RFS must take into consideration the tolerance, temperature coefficient, and lifetime duration to assure that the
resistance value will always be within the desired (specified) range.
33987
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING HS0 TO HS3
Output Rising Slow Slew Rate A (DICR D3 = 0 (Note 22)
SR
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
RA_SLOW
RB_SLOW
9.0 V < V
< 16 V
1.0
0.15
1.5
3.0
0.4
5.0
1.0
3.0
0.5
12
6.0
1.5
13
PWR
Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 23)
9.0 V < V < 16 V
SR
PWR
Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 22)
9.0 V < V < 16 V
SR
SR
SR
RA_FAST
RB_FAST
PWR
Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 23)
9.0 V < V < 16 V
0.15
1.0
6.0
6.0
1.5
24
PWR
Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 22)
9.0 V < V < 16 V
FA_SLOW
PWR
Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 23)
9.0 V < V < 16 V
SR
FB_SLOW
0.15
5.0
PWR
Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 22)
9.0 V < V < 16 V
SR
SR
FA_FAST
FB_FAST
PWR
Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 23)
9.0 V < V < 16 V
0.6
2.5
6.0
PWR
Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 24)
DICR = 0, DICR = 1 9.0 V <VPWR <16 V
tDLY(ON)
µs
µs
0.1
4.0
4.0(slow)
25(slow)
20
40
Output Turn-OFF Delay Time in Fast/slow Slew Rate (Note 25)
DICR = 0 and DICR = 1 9.0 V < VPWR < 16 V
tDLY(OFF)
Overcurrent Low Detection Blanking Time (OCLT[1:0])
9.0 V < VPWR < 16 V
ms
tOCL0
tOCL2
tOCL3
100
50
150
75
200
100
0.25
00
10
11
0.08
0.15
Overcurrent High Detection Blanking Time 9.0 V<VPWR<16 V
t
1.0
4.0
20
µs
OCH
Notes
22. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to V
-3.5 V (see Figure 2, page 12). These
PWR
parameters are guaranteed by process monitoring.
23. Rise and Fall Slew Rates B measured across a 5.0 Ω resistive load at high-side output = V
-3.5 V to V
-0.5 V (see Figure 2). These
PWR
PWR
parameters are guaranteed by process monitoring.
24. Turn-ON delay time measured from rising edge of any signal (IN[0:3], SCLK, CS) that would turn the output ON to V
= 0.5 V.
HS[0:3]
25. Turn-OFF delay time measured from falling edge of any signal (IN[0:3], SCLK, CS) that would turn the output OFF to V
= V
-0.5 V.
PWR
HS[0:3]
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING HS0, HS1, HS2, AND HS3 (continued)
CS to CSNS Valid Time (Note 26)
tCNSVAL
–
–
200
µs
Watchdog Timeout (WD[1:0]) (Note 27)
ms
00
01
10
11
tWDTO0
tWDTO1
tWDTO2
tWDTO3
434
217
620
310
806
403
1750
875
2500
1250
3250
1625
Notes
26. Time necessary for the CSNS to be with ±5% of the targeted value.
27. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output driven
OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t
is consistent for all configured watchdog
WDTO
timeouts.
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
fSPI
tWRST
tCS
–
–
–
–
–
–
–
–
–
–
–
50
–
3.0
350
300
5.0
167
167
167
167
83
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Required Low State Duration for RST (Note 28)
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 29)
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 29)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 29)
Required High State Duration of SCLK (Required Setup Time) (Note 29)
Required Low State Duration of SCLK (Required Setup Time) (Note 29)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 29)
SI to Falling Edge of SCLK (Required Setup Time) (Note 30)
Falling Edge of SCLK to SI (Required Setup Time) (Note 29)
SO Rise Time
tENBL
–
tLEAD
50
–
tWSCLKH
tWSCLKL
tLAG
–
50
25
25
tSI(SU)
tSI(HOLD)
tRSO
83
C = 200 pF
–
25
50
L
SO Fall Time
tFSO
ns
C = 200 pF
–
–
–
–
–
25
–
50
50
L
SI, CS, SCLK, Incoming Signal Rise Time (Note 30)
tRSI
tFSI
ns
ns
ns
ns
ns
SI, CS, SCLK, Incoming Signal Fall Time (Note 30)
–
50
Time from Falling Edge of CS to SO Low Impedance (Note 31)
Time from Rising Edge of CS to SO High Impedance (Note 32)
tSO(EN)
tSO(DIS)
tVALID
–
145
145
65
Time from Rising Edge of SCLK to SO Data Valid (Note 33)
0.2 V ≤ SO ≥ 0.8 V , C = 200 pF
–
65
105
DD
DD
L
Notes
28. RST low duration measured with outputs enabled and going to OFF or disabled condition.
29. Maximum setup time required for the 33987 is the minimum guaranteed time needed from the microcontroller.
30. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
31. Time required for output status data to be available for use at SO. 1.0 kΩ on pullup on CS.
32. Time required for output status data to be terminated at SO. 1.0 kΩ on pullup on CS.
33. Time required to obtain valid data out from SO following the rise of SCLK.
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TIMING DIAGRAMS
CS
V
PWR
SR
SRfB
V
-0.5V
FB
PWR
SR
S
RB
V
-3.5 V
PWR
SR
SRfA
FA
SSRRrA
RA
0.5 V
t
DLY(OFF)
t
DLY(ON)
Figure 2. Output Slew Rate and Time Delays (Fast and Slow Modes)
IOCHx
ILOAD2
Load
Current
ILOAD1
tOCH
IOCLx
tOCLx
Time
Figure 3. Overcurrent Shutdown
(ILOAD Varies Upon Load Resistance Selected by Customer)
33987
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I
I
I
OCH0
OCH1
OCL0
OCL1
I
I
OCL2
Load
Current
I
OCL3
I
I
I
I
OCL4
OCL5
OCL6
OCL7
Time
t
t
t
t
OCL0
OCH
OCL3
OCL2
Figure 4. Overcurrent Low and High Detection
V
IH
RST
0.2 V
DD
D
VIL
ENBL
t
t
CS
t
WRST
V
0.7 V
DD
IH
C
0.7V
DD
V
IL
t
RSI
t
WSCLKH
t
LEAD
t
LAG
V
0.7 V
DD
IH
SCLK
0.2 V
DD
V
IL
t
SI(SU)
t
WSCLKL
t
FSI
t
SI(HOLD)
V
IH
0.7 V
DD
Don’t Care
Don’t Care
Don’t Care
Valid
Valid
SI
02V
DD
V
IH
Figure 5. Input Timing Switching Characteristics
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t
t
FSI
RSI
V
3.5 V
SOH
50%
SCLK
1.0 V
V
SOL
t
SO(EN)
0.2V
V
SOH
0.7 V
DD
SO
DD
V
SOL
Low to High
t
RSO
t
VALID
t
FSO
SO
V
SOH
0.7 V
DD
High to Low
0.2 V
DD
V
SOL
t
SO(DIS)
Figure 6. SCLK Waveform and Valid SO Data Delay Time
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33987 is one in a family of devices designed for low-
own parallel input for PWM control if desired. The 33987 allows
the user to program via the SPI the fault current trip levels and
duration of acceptable lamp inrush or motor stall intervals. Such
programmability allows tight control of fault currents and can
protect wiring harnesses and circuit boards as well as loads.
voltage automotive and industrial lighting and motor control
applications. Its four low RDS(ON) MOSFETs (four 70 mΩ) can
control the high sides of four separate resistive or inductive
loads.
Programming, control, and diagnostics are accomplished
using a 16-bit SPI interface. Additionally, each output has its
The 33987 is packaged in a power-enhanced 10 x 10
nonleaded PQFN package with exposed tabs.
FUNCTIONAL TERMINAL DESCRIPTION
Serial Input (SI)
terminals are ignored and SO is tri-stated (high impedance).
(See Figure 7, page 17.)
This is a serial interface (SI) command data input terminal.
Each SI bit is read on the falling edge of SCLK. A 16-bit stream
of serial data is required on the SI terminal, starting with D15 to
D0. The internal registers of the 33987 are configured and
controlled using a 5-bit addressing scheme described in
Table 1, page 17. Register addressing and configuration are
described in Table 4, page 19. The SI input has an active
Chip Select (CS)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic[0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33987 device latches
in data from the input shift registers to the addressed registers
on the rising edge of CS. The device transfers status
internal pulldown, IDWN
.
Serial Output (SO)
information from the power output to the Shift register on the
falling edge of CS. The SO output driver is enabled when CS is
logic [0]. CS should transition from a logic [1] to a logic [0] state
only when SCLK is a logic [0]. CS has an active internal pullup,
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high impedance state
until the CS terminal is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO terminal
changes states on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and input status descriptions are
provided in Table 11, page 22.
IUP
.
Wake (WAKE)
This terminal is an input that controls the device mode and
watchdog timeout feature if enabled. An internal clamp protects
this terminal from high damaging voltages when the output is
current limited with an external resistor. This input has a
passive internal pulldown.
Serial Clock (SCLK)
The SCLK terminal clocks the internal shift registers of the
33987 device. The serial input (SI) terminal accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output (SO) terminal shifts data information out
of the SO line driver on the rising edge of the SCLK signal. It is
important the SCLK terminal be in a logic low state whenever
CS makes any transition. For this reason, it is recommended the
SCLK terminal be in a logic [0] whenever the device is not
accessed (CS logic [1] state). SCLK has an active internal
pulldown. When CS is logic [1], signals at the SCLK and SI
Outputs (HS0-HS3)
Protected 70 mΩ high-side power output terminals to the
load.
Ground (GND)
These terminals are the ground for the logic and analog
circuitry of the device.
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Fail Safe Input (FSI)
Serial Inputs (IN0-3)
The value of the resistance connected between this terminal
and ground determines the state of the outputs after a
Watchdog timeout occurs. Depending on the resistance value,
either all outputs are OFF or the output HSO only is ON. If the
FSI terminal is left to float up to a logic [1] level, then the outputs
HS0 and HS2 will turn ON when in the Fail-Safe state. When the
FSI terminal is connected to GND, the Watchdog circuit and
Fail-Safe operation are disabled. This terminal incorporates an
active internal pullup current source.
The IN0:IN3 high-side input terminals are used to directly
control HS0:HS3 high-side output terminals, respectively. An
SPI register determines if each input is activated or if the input
logic state is OR'ed or AND'ed with the SPI instruction. These
terminals are to be driven with 5.0 V CMOS levels, and they
have an active internal pulldown current source.
Output Current Monitoring (CSNS)
The Current Sense terminal sources a current proportional
to the designated HS0:HS3 output. That current is fed into a
ground referenced resistor and its voltage is monitored by an
MCU’s A/D. The channel to be monitored is selected via the
SPI. This terminal can be tri-stated through SPI.
33987
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FUNCTIONAL DEVICE OPERATION
CS
SCLK
SI
D15
D14
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Notes 1. RST is a logic [1] state during the above operation.
2. D15:D0 relate to the most recent ordered entry of data into the device.
3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device.
Figure 7. Single 16-Bit Word SPI Communication
The 33987 has defined registers, which are used to
SPI Protocol Description
configure the device and to control the state of the outputs.
Table 4, page 19, summarizes the SI registers.
The SPI interface has a full duplex, three-wire synchronous
data transfer with four I/O lines associated with it: Serial Input
(SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select
(CS).
Table 1. SI Message Bit Assignment
The SI/SO terminals of the 33987 follows a first-in first-out
(D15:D0) protocol with both input and output words transferring
the most significant bit (MSB) first. All inputs are compatible
with 5.0 V CMOS logic levels.
Message Bit Description
Bit Sig SI Msg Bit
Watchdog in: toggled to satisfy watchdog
requirements.
MSB
D15
Serial Input Communication
Not used.
D14:D15
D12:D11
SPI communication is accomplished using 16-bit messages.
A message is transmitted by the MCU starting with the MSB
D15 and ending with the LSB, D0 (Table 1). Each incoming
command message on the SI terminal can be interpreted using
the following bit assignments: the MSB, D15, is the watchdog
bit. In some cases, output channel selection is done with bits
D12:D11. The next three bits, D10:D8, are used to select the
command register. The remaining five bits, D4:D0, are used to
configure and control the outputs and their protection features.
Register address bits used in some cases for
output channel selection.
Register address bits.
Not used.
D10:D8
D7:D5
D4:D1
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to latch
in a message that is not 16 bits will be ignored.
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
LSB
D0
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MODES OF OPERATION
The 33987 has four operating modes: Sleep, Normal, Fault,
Fail-Safe Mode
and Fail-Safe. Table 2 summarizes details contained in
succeeding paragraphs.
Fail-Safe Mode and Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or the RST input
terminal transitions from logic [0] to logic [1]. The WAKE input is
capable of being pulled up to VPWR with a series of limiting
resistance limiting the internal clamp current according to the
specification.
Table 2. Fail-Safe Operation and Transitions
to Other 33987 Modes
Mode
FS WAKE RST WDTO
Comments
Device is in Sleep mode. All
outputs are OFF
Sleep
x
0
0
x
The Watchdog timeout is a multiple of an internal oscillator
and is specified in the Table 10, page 21. As long as the WD bit
(D15) of an incoming SPI message is toggled within the
minimum watchdog timeout period (WDTO), based on the
programmed value of the WDR, the device will operate
normally. If an internal watchdog timeout occurs before the WD
bit, the device will revert to a Fail-Safe mode until the device is
reinitialized.
Normal mode. Watchdog is
active if enabled.
Normal
Fault
1
x
1
No
No
Device is currently in Fault
mode. The faulted output(s)
is (are) OFF.
0
0
0
1
1
1
1
1
x
0
1
1
1
0
1
1
1
0
Watchdog has timed out and
the device is in Fail-Safe
mode. The outputs are as
configured with the RFS
resistor connected to FSI.
RST and WAKE must be
transitioned to logic [0]
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI terminal,
regardless of the state of the various direct inputs and modes
(Table 3).
Fail-
Safe
Yes
Table 3. Output State During
Fail-Safe Mode
simultaneously to bring the
device out of the Fail-safe
mode or momentarily tied
the FSI terminal to ground.
RFS (kΩ)
High-Side State
Fail-Safe Mode Disabled
All HS OFF
0
x = Don’t care.
6.0
15
Sleep Mode
HS0 ON
HS[1:3] OFF
The default mode of the 33987 is the Sleep mode. This is the
state of the device after first applying battery voltage (VPWR
)
30
HS0 and HS2 ON
HS1 and HS3 OFF
prior to any I/O transitions. This is also the state of the device
when the WAKE and RST are both logic [0]. In the Sleep mode,
the output and all unused internal circuitry, such as the internal
5.0 V regulator, are OFF to minimize current draw. In addition,
all SPI-configurable features of the device are as if set to
logic [0]. The device will transition to the Normal or Fail-Safe
operating modes based on the WAKE and RST inputs defined
in Table 2.
In the Fail-Safe mode, the SPI register content is retained
except for overcurrent high and low detection levels and timing,
which are reset to their default value (SOCL, SOCH, and
OCLT). Then the watchdog, overvoltage, overtemperature, and
overcurrent circuitry (with default value) are fully operational.
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is logic [1] when the
device is in Fail-Safe mode. The device can be brought out of
the Fail-Safe mode by transitioning the WAKE and RST
terminals from logic [1] to logic [0] or forcing the FSI terminal to
logic [0]. Table 2 summarizes the various methods for resetting
the device from the latched Fail-Safe mode.
Normal Mode
The 33987 is in Normal mode when:
• VPWR is within the normal voltage range.
•
RST terminal is logic [1].
• No fault has occurred.
If the FSI terminal is tied to GND, the Watchdog fail-safe
operation is disabled.
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Loss of VDD
Fault Mode
The 33987 indicates the faults below as they occur by driving
the FS terminal to logic [0]:
If the external 5.0 V supply is not within specification, or even
disconnected, all register content is reset. The outputs can still
be driven by the direct inputs IN0:IN3. The 33987 uses the
battery input to power the output MOSFET-related current
sense circuitry and any other internal logic, providing fail-safe
device operation with no VDD supplied. In this state, the
watchdog, overvoltage, overtemperature, and overcurrent
circuitry are fully operational with default values.
• Overtemperature fault
• Overvoltage and Undervoltage fault
• Open load fault
• Overcurrent fault (high and low)
The FS terminal automatically returns to logic [1] when the
fault condition is removed, except for overcurrent and in some
cases undervoltage.
Fault information is retained in the Fault register and is
available (and reset) via the SO terminal during the first valid
SPI communication (refer to Table 12, page 23).
LOGIC COMMAND AND REGISTERS
Table 4. Serial Input Address and Configuration Bit Map
SI Data
SI Register
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
D4
D3
D2
D1
D0
STATR
OCR0
OCR1
WDIN
WDIN
WDIN
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
1
0
1
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SOA4
SOA3
SOA2
SOA1
SOA0
x
x
x
x
x
x
x
x
x
IN3_SPI
CSNS3 EN
SOCH_s
OL_DIS_s
IN2_SPI
IN1_SPI
IN0_SPI
CSNS2 EN CSNS1 EN CSNS0 EN
SOCHLR_s WDIN
CDTOLR_s WDIN
A
A
SOCL2_s
SOCL1_s
OCLT1_s
SOCL0_s
OCLT0_s
A/O_s
1
1
1
0
0
0
A
A
A
A
OCL_DIS_s
DICR_s
UOVR
WDIN
WDIN
WDIN
WDIN
WDIN
FAST_SR_s CSNS_high_s DIR_DIS_s
x
0
x
x
x
x
UV_DIS
WD1
OV_DIS
WD0
WDR
x
x
x
1
x
x
NAR
No Action (Allow Toggling of D15–WDIN)
Motorola Internal Use (Test)
TEST
x=Don’t care.
s=Output selection with the bits A A as defined in Table 5.
1
0
to read the content of the OCR0, OCR1, SOCHLR, CDTOLR,
DICR, UOVR, WDR, and NAR registers. (Refer to the section
entitled Serial Output Communication (Device Status Return
Data) beginning on page 21.)
Device Register Addressing
The following section describes the possible register
addresses and their impact on device operation.
Address xx000—Status Register (STATR)
Address x0001—Output Control Register (OCR0)
The STATR register is used to read the device status and the
various configuration register contents without disrupting the
device operation or the register contents. The register bits
D4:D0 determine the content of the first sixteen bits of SO data.
In addition to the device status, this feature provides the ability
The OCR0 register allows the MCU to control the ON/OFF
state of four outputs through the SPI. Incoming message bits
D3:D0 reflect the desired states of the four high-side outputs
(INx_SPI), respectively. A logic [1] enables the corresponding
output switch and a logic [0] turns it OFF.
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Address x1001—Output Control Register (OCR1)
Incoming message bits D3:D0 reflect the desired channel
that will be mirrored on the Current Sense (CSNS) terminal. A
logic [1] on message bits D3:D0 enables the CSNS terminal for
outputs HS3:HS0, respectively. In the event the current sense
is enabled for multiple outputs, the current will be summed. In
the event bits D3:D0 are all logic [0], the output CSNS will be
tri-stated. This is useful when several CSNS terminals of
several devices share the same A/D converter.
Table 7. Overcurrent High Detection
Levels
Overcurrent High
Detection (Amperes)
SOCH_s* (D3)
HS0:HS3
0
1
36
26
Address A1A0010—Select Overcurrent High and Low
* “_s” refers to the channel, which is selected
through bits D12:D11; refer to Table 5, page 20.
Register (SOCHLR_s)
The SOCHLR_s register allows the MCU to configure the
output overcurrent low and high detection levels, respectively.
Each output “s” is independently selected for configuration
based on the state of the D12:D11 bits (Table 5).
Address A1A0011—Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine the
amount of time the device will allow an overcurrent low
condition before an output latches OFF. Each output is
independently selected for configuration based on A1A0, which
are the state of the D12:D11 bits (refer to Table 5, page 20).
Table 5. Channel Selection
A (D12) A (D11)
HS_s
HS0
HS1
HS2
HS3
1
0
0
0
1
1
0
1
0
1
Bits D1:D0 (OCLT[1:0]_s) allow the MCU to select one of
three overcurrent fault blanking times defined in Table 8. Note
that these timeouts apply only to the overcurrent low detection
levels. If the selected overcurrent high level is reached, the
device will latch off within 20 µs.
Table 8. Overcurrent Low Detection
Blanking Time
Each output can be configured to different levels. In addition
to protecting the device, this slow blow fuse emulation feature
can be used to optimize the load requirements matching system
characteristics. Bits D2:D0 set the overcurrent low detection
level to one of eight possible levels, as shown in Table 6,
page 20. Bit D3 sets the overcurrent high detection level to one
of two levels, as outlined in Table 7, page 20.
OCLT[1:0]_s*
Timing
150 ms
Do not use
75 ms
00
01
10
11
150 µs
Table 6. Overcurrent Low Detection Levels
Overcurrent Low
* “_s” refers to the channel, which is selected through
bits D12:D11; refer to Table 5, page 20.
SOCL2_s* SOCL1_s* SOCL0_s*
Detection (Amperes)
(D2)
(D1)
(D0)
HS0:HS3
A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent
low detection feature. When disabled, there is no timeout for the
selected output and the overcurrent low detection feature is
disabled.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6.7
6.0
5.3
4.7
3.9
3.2
2.5
1.8
A logic [1] on bit D3 (OL_DIS_s) disables the open load (OL)
detection feature for the channel corresponding to the state of
bits D12:D11.
* “_s” refers to the channel, which is selected through bits D12:D11;
refer to Table 5, page 20.
33987
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Address A1A0100—Direct Input Control Register (DICR)
Address x1101— Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
Watchdog timeout. The Watchdog timeout is configured using
bits D1 and D0. When D1 and D0 bits are programmed for the
desired watchdog timeout period (Table 10), the WDSPI bit
should be toggled as well, ensuring the new timeout period is
programmed at the beginning of a new count sequence.
The DICR register is used by the MCU to enable, disable, or
configure the direct IN terminal control of each output. Each
output is independently selected for configuration based on the
state bits D12:D11 (refer to Table 5, page 20).
For the selected output, a logic [0] on bit D1 (DIR_DIS_s) will
enable the output for direct control. A logic [1] on bit D1 will
disable the output from direct control.
While addressing this register, if the Input was enabled for
direct control, a logic [1] for the D0 (A/O_s) bit will result in a
Boolean AND of the IN terminal with its corresponding IN_SPI
D4:D0 message bit when addressing OCR0. Similarly, a
logic [0] on the D0 terminal results in a Boolean OR of the IN
terminal to the corresponding message bits when addressing
the OCR0. This register is especially useful if several loads are
required to be independently PWM controlled. For example, the
IN terminals of several devices can be configured to operate all
of the outputs with one PWM output from the MCU. If each
output is then configured to be Boolean ANDed to its respective
IN terminal, each output can be individually turned OFF by SPI
while controlling all of the outputs, commanded on with the
single PWM output.
Table 10. Watchdog Timeout
WD[1:0] (D1:D0)
Timing (ms)
620
00
01
10
11
310
2500
1250
Address xx110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy-chain SPI configuration. This would allow
devices to be unaffected by commands being clocked over a
daisy-chained SPI configuration. By toggling the WD bit (D15)
the watchdog circuitry would continue to be reset while no
programming or data read back functions are being requested
from the device.
A logic [1] on bit D2 (CSNS_high_s) is used to select the
high ratio on the CSNS terminal for the selected output. The
default value [0] is used to select the low ratio (Table 9).
Table 9. Current Sense Ratio
Current Sense Ratio
CSNS_high_s*
Address xx111—TEST
(D2)
The TEST register is reserved for test and is not accessible
with SPI during normal operation.
HS0:HS3
0
1
1/4600
1/13500
Serial Output Communication (Device Status Return
Data)
* “_s” refers to the channel, which is selected
through bits D12:D11; refer to Table 5, page 20.
When the CS terminal is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB- (OD15-) first
as the new message data is clocked into the SI terminal. The
first 16 bits of data clocking out of the SO, and following a CS
transition, is dependent upon the previously written SPI word.
A logic [1] on bit D3 (FAST_SR_s) is used to select the high
speed slew rate for the selected output, the default value
logic [0] corresponds to the low speed slew rate
Any bits clocked out of the SO terminal after the first 16 bits
will be representative of the initial message bits clocked into the
SI terminal since the CS terminal first transitioned to a logic [0].
This feature is useful for daisy chaining devices as well as
message verification.
Address x0101—Undervoltage/Overvoltage Register
(UOVR)
The UOVR register disables the undervoltage (D1) and/or
overvoltage (D0) protection. When these two bits are logic [0],
the undervoltage and overvoltage are active (default value).
A valid message length is determined following a CS
transition of logic [0] to logic [1]. If there is a valid message
length, the data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
terminal is tri-stated and the fault status register is now able to
accept new fault status information.
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SO data will represent information ranging from fault status
Serial Output Bit Assignment
to register contents, user selected by writing to the STATR bits
OD4, OD3, OD2, OD1, and OD0. The value of the previous bits
SOA4 and SOA3 will determine which output the SO
information applies to for the registers that are output specific;
namely, Fault, SOCHLR, CDTOLR, and DICR registers.
The 16 bits of serial output data depend on the previous
serial input message, as explained in the following paragraphs.
Table 11, page 22, summarizes SO returned data for bits OD15
through OD0.
• Bit OD15 is the MSB; it reflects the state of the Watchdog bit
from the previously clocked-in message.
• Bit OD14 remains logic [0] except when an undervoltage
condition occurred.
• Bit OD13 remains logic [0] except when an overvoltage
condition occurred.
• Bits OD12:OD8 reflect the state of the bits SOA[4:0] from the
previously clocked in message.
• Bits OD7:OD4 give the fault status flag of the outputs
HS3:HS0, respectively.
• The contents of bits OD3:OD0 depend on bits D4:D0 from
the most recent STATR command SOA[4:0] as explained in
the paragraphs following Table 11.
Note that the SO data will continue to reflect the information
for each output (depending on the previous OD4, OD3 state)
that was selected during the most recent STATR write until
changed with an updated STATR write.
The output status register correctly reflects the status of the
STATR-selected register data at the time that the CS is pulled
to a logic [0] during SPI communication, and/or for the period of
time since the last valid SPI communication, with the following
exceptions:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though the
invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an under-voltage
shutdown of the outputs may result in incorrect data loaded
into the Status register. The SO data transmitted to the MCU
during the first SPI communication following an undervoltage
VPWR condition should be ignored.
• The RST terminal transition from a logic [0] to logic [1] while
the WAKE terminal is at logic [0] may result in incorrect data
loaded into the Status register. The SO data transmitted to
the MCU during the first SPI communication following this
condition should be ignored.
Table 11. Serial Output Bit Map Description
Previous STATR
SO Returned Data
SO SO SO SO SO OD
A4 A3 A2 A1 A0 15
OD
14
OD
13
OD
12
OD
11
OD
10
OD9 OD8 OD7 OD6 OD5 OD4
OD3
OD2
OD1
OD0
A1 A0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
1
0
1
1
0
0
WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0
WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0
OTF_s
OCHF_s
IN2_SPI
OCLF_s
IN1_SPI
OLF_s
x
x
0
1
IN3_SPI
IN0_SPI
WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 CSNS3 EN
CSNS2 EN
SOCL2_s
OCL_DIS_s
CSNS1 EN CSNS0 EN
A1 A0
A1 A0
A1 A0
WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0
WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0
SOCH_s
SOCL1_s
OCLT1_s
SOCL0_s
OCLT0_s
A/O_s
OL_DIS_s
WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 Fast_SR_s CSNS_high_s DIR_DIS_s
x
x
x
x
0
1
0
1
WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0
WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0
–
–
–
UV_DIS
WD1
OV_DIS
WD0
WDTO
HS0_failsaf
IN2
WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 HS2_failsaf
WDIN UVF OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 ST2 ST1 ST0 IN3
WD_en
IN1
WAKE
IN0
x=Don’t care.
s=Output selection with the bits A A as defined in Table 5, page 20.
1
0
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Previous Address SOA[4:0]=A1A0000
Previous Address SOA[4:0]=A1A0011
Bits OD3:OD0 will reflect the current state of the Fault
Register (FLTR) corresponding to the output previously
selected with the bits A1A0 (Table 12).
The returned data contains the programmed values in the
CDTOLR register for the output selected with A1A0.
Previous Address SOA[4:0]=A1A0100
The returned data contains the programmed values in the
DICR register for the output selected with A1A0.
Table 12. Channel-Specific Fault Register
OD3
OD2
OD1
OD0
OTF_s
OCHF_s
OCLF_s
OLF_s
Previous Address SOA[4:0]=x0101
The returned data contains the programmed values in the
UOVR register.
s=Selection of the output.
Note The FS terminal reports all faults. For latched faults,
this terminal is reset by a new Switch ON command (via SPI or
direct input IN).
Previous Address SOA[4:0]=x1101
The returned data contains the programmed values in the
WDR register. Bit OD2 (WDTO) reflects the status of the
watchdog circuitry. If WDTO bit is logic [1], the watchdog has
timed out and the device is in Fail-Safe mode. IF WDTO is
logic [0], the device is in Normal mode (assuming the device is
powered and not in the Sleep mode), with the watchdog either
enabled or disabled.
Previous Address SOA[4:0]=x0001
Data in bits OD3:OD0 contains IN_SPI[3:0]-programmed
bits for channel from HS3:HS0, respectively.
Previous Address SOA[4:0]=x1001
Data in bits OD3:OD0 contains the programmed
CSNS EN[3:0] bits for channels HS3:HS0, respectively.
Previous Address SOA[4:0]=x0110
The returned data OD3 and OD2 contain the state of the
outputs HS2 and HS0, respectively, in case of Fail-Safe state.
This information is stated with the external resistance placed at
the FSI terminal. OD1 indicates if the watchdog is enabled or
not. OD0 returns the state of the WAKE terminal.
Previous Address SOA[4:0]=A1A0010
Data returned in bits OD3:OD0 are programmed current
values for the overcurrent high detection level (refer to Table 7,
page 20) and the overcurrent low detection level (refer to
Table 6, page 20), corresponding to the output previously
selected with A1A0.
Previous Address SOA[4:0]=x1110
The returned data OD3:OD0 reflects the state of the direct
terminals IN3:IN0, respectively.
PROTECTION AND DIAGNOSIS FEATURES
Overtemperature Fault (Non-Latching)
Undervoltage Shutdown (Latching or Non-Latching)
The 33987 incorporates overtemperature detection and
shutdown circuitry in the output structure. Overtemperature
detection is enabled when the output is in the ON state.
The output(s) will latch off at some battery voltage below
6.2 V. As long as the VDD level stays within the normal specified
range, the internal logic states within the device will be
sustained.
For the output, an overtemperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely until
action is taken by the MCU to shut OFF the output, or until the
offending load is removed.
In the case where battery voltage drops below the
undervoltage threshold (VPWRUV) output will turn off, FS will
go to logic 0, and the fault register UVF bit is set to 1.
Two cases need to be considered when the battery level
recovers:
When experiencing this fault, the OTF fault bit will be set in
the Status register and cleared after either a valid SPI read or a
power reset of the device.
• If output(s) command is (are) low, FS will go to logic 1 but the
UVF bit will remain set to 1 until the next read operation.
• If the output command is ON, then FS will remain at logic 0.
The output must be turned OFF and ON again to re-enable
the state of output and release FS. The UVF bit will remain
set to 1 until the next read operation.
Overvoltage Fault (Non-Latching)
The 33987 shuts down the output during an overvoltage fault
(OVF) condition on the VPWR terminal. The output remains in
the OFF state until the overvoltage condition is removed. When
experiencing this fault, the OVF fault bit is set in the bit OD1 and
cleared after either a valid SPI read or a power reset of the
device.
The undervoltage protection can be disabled through SPI (bit
UV_dis = 1). In this case, the FS does not report any
undervoltage fault condition, UVF bit is set to 1, and the output
state is not changed as long as the battery voltage does not
drop any lower than 2.5 V.
The overvoltage protection can be disabled through SPI (bit
OV_DIS). When disabled, the returned SO bit OD13 still reflects
any overvoltage condition (overvoltage warning).
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Table 13. Device State Versus Battery Voltage
UV Disable
IN=0
(Falling∗∗∗ or
Rising∗∗∗∗
VPWR)
UV Enable
IN=0
(Falling∗∗∗
VPWR)
UV Enable
IN=0
(Rising∗∗∗∗
VPWR)
UV Enable
IN=1
(Falling∗∗∗
VPWR)
UV Enable
IN=1
(Rising∗∗∗∗
VPWR)
MC33987
(VPWR Battery Voltage)∗∗
State
Output State
OFF
1
OFF
ON
1
OFF
0
OFF
1
VPWR > VPWRUV
FS State
1
SPI Fault Register UVF Bit
Output State
0
1 until next read
0
1
0
OFF
0
OFF
OFF
0
OFF
0
OFF
1
VPWRUV > VPWR > UVPOR FS State
SPI Fault Register UVF Bit
0
1
1 until next read
1
1
1
Output State
OFF
1
OFF
1
OFF
1
OFF
1
OFF
1
UVPOR > VPWR > 2.5 V∗
2.5 V∗ > VPWR > 0V
FS State
SPI Fault Register UVF Bit
Output State
1 until next read 1 until next read 1 until next read 1 until next read 1 until next read
OFF
1
OFF
1
OFF
1
OFF
1
OFF
1
FS State
SPI Fault Register UVF Bit
Comments
1 until next read 1 until next read 1 until next read 1 until next read 1 until next read
UV fault is
not latched
UV fault is
not latched
UV fault
is latched
∗ = Typical value; not guaranteed
∗∗ = While VDD remains within specified range.
∗∗∗ = From VPWR normal condition to 0 V.
∗∗∗∗ = From 0 V to VPWR normal condition.
Open Load Fault (Non-Latching)
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF the
The 33987 incorporates open load detection circuitry on the
output. Output open load fault (OLF) is detected and reported
as a fault condition when the output is disabled (OFF). The
open load fault is detected and latched into the Status register
after the internal gate voltage is pulled low enough to turn OFF
the output. The OLF fault bit is set in the Status register. If the
open load fault is removed, the Status register will be cleared
after reading the register.
output, regardless of the selected tOCL driver.
x
For both cases, the device output will stay off indefinitely until
the device is commanded OFF and then ON again.
Reverse Battery
The output survives the application of reverse voltage as low
as -16 V. Under these conditions, the output’s gate is enhanced
to keep the junction temperature less than 150°C. The ON
resistance of the output is fairly similar to that in the Normal
mode. No additional passive components are required.
The open load protection can be disabled trough SPI (bit
OL_DIS).
Overcurrent Fault (Latching)
The device has eight programmable overcurrent low
Ground Disconnect Protection
detection levels (IOCL) and two programmable overcurrent high
detection levels (IOCH) for maximum device protection. The two
selectable, simultaneously active overcurrent detection levels,
defined by IOCH and IOCL, are illustrated in Figure 4, page 13.
In the event the 33987 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless of the state of the output at the time of
disconnection. A 10K resistor needs to be added between the
wake pin and the rest of the circuitry in order to ensure that the
device turns off in case of ground disconnect and to prevent this
pin to exceed its maximum ratings.
The eight different overcurrent low detection levels (IOCL0
:
I
OCL7) are illustrated in Figure 4.
If the load current level ever reaches the selected
overcurrent low detection level and the overcurrent condition
exceeds the programmed overcurrent time period (tOC ), the
x
device will latch the output OFF.
33987
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The maximum peak temperature during the soldering
Soldering Information
process should not exceed 240°C. The time at maximum
temperature should range from 10 seconds to 40 seconds
maximum.
The 33987 is packaged in a surface mount power package
intended to be soldered directly on the printed circuit board.
The 33987 was qualified in accordance with JEDEC
standards JESD22-A113-B and J-STD-020A. The
recommended reflow conditions are as follows:
Refer to Package Dimensions (starting on page 26) to define
soldering. Note that the four small metal pads surrounded by
pins 13, 14, 15, 21 and 22 are connected to ground (GND) and
are not recommended for soldering.
• Convection: 235°C +5.0/-0°C
• Vapor Phase Reflow (VPR): 235°C +5.0/-0°C
• Infrared (IR)/Convection: 235°C +5.0/-0°C
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PACKAGE DIMENSIONS
PNC SUFFIX
24-TERMINAL POWER QFN
NONLEADED PACKAGE
98ARL10591D
ISSUE B
SHEET 1 OF 2
10
A
DETAIL G
M
5
2X
10
2
1
0.1
C
11
13
24
22
5
14
21
10
PIN 1
INDEX AREA
17
18
19
20
M
2X
B
0.1
C
PIN NUMBER
REF. ONLY
5.85
PIN NUMBER
REF. ONLY
4.95
4.65
VIEW A
0.1
C
A B
1
2
10
24
22
11
2X 0.65
3.2
13
14
3.0
2.7
15
0.1
C
A
B
2.525
21
1.375
2.45
2.05
4.45
4.05
16
0.1
C A B
2.3
2X 1.43
0.93
2X 1.8
20
19
18
17
(0.25)
1.65
(0.1)
(1.25)
0.5
(0.75)
2X 1.3
0.8
NOTES:
(0.25)
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
2.2
2X1.8
0.1
C
A B
7.2
6.8
0.1
2X
4. COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
1.35
C
A B
0.1
C A B
5. METAL PADS CONNECTED TO THE GND.
6. MINIMUM METAL GAP SHOULD BE 0.25MM.
9.70
9.30
0.1
C A B
VIEW M M
33987
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PNC SUFFIX
24-TERMINAL POWER QFN
NONLEADED PACKAGE
98ARL10591D
ISSUE B
SHEET 2 OF 2
0.1 C
2.20
1.95
2.2
2.0
4
0.05 C
0.05
0.00
(0.65)
DETAIL G
SEATING
PLANE
(0.4)
C
VIEW ROTATED 90˚ CW
3.5
1.20
0.95
2X
0.47
16X 0.33
0.1
9X 0.65
0.325
M
C A B
1.20
0.95
6X
M
C
0.05
(0.05)
10
(0.2)
0.90
0.65
11
8X
0.3 0.2
5
X0.3 0.2
0.1
C
A
B
3.025
2 PLACES
5
0.25 0.2
X0.25 0.2
0.1
2.5
C
A B
2 PLACES
1.8
1.3
2.0
1.6
1.0
0.6
(0.25)
2.8
2.6
0.6
0.2
2 PLACES
VIEW A
33987
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
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could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
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MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
© Motorola, Inc. 2005
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