PC33984PNA [NXP]
2 CHANNEL, BUF OR INV BASED PRPHL DRVR, QCC16, PLASTIC, QFN-16;
| 型号： | PC33984PNA |
| 厂家： | 
NXP |
| 描述： | 2 CHANNEL, BUF OR INV BASED PRPHL DRVR, QCC16, PLASTIC, QFN-16 驱动 接口集成电路 |
| 文件： | 总24页 (文件大小：783K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Document order number: MC33984/D
Rev 3.0, 03/2004
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
33984
Dual Intelligent High-Current
Self-Protected Silicon High-Side
Switch (4.0 mΩ)
DUAL HIGH-SIDE SWITCH
The 33984 is a dual self-protected 4.0 mΩ silicon switch used to replace
electromechanical relays, fuses, and discrete devices in power management
applications. The 33984 is designed for harsh environments, and it includes
self-recovery features. The device is suitable for loads with high inrush current,
as well as motors and all types of resistive and inductive loads.
4.0 mΩ
Programming, control, and diagnostics are implemented via the Serial
Peripheral Interface (SPI). A dedicated parallel input is available for alternate
and Pulse Width Modulation (PWM) control of each output. SPI-
programmable fault trip thresholds allow the device to be adjusted for optimal
performance in the application.
The 33984 is packaged in a power-enhanced 12 x 12 PQFN package with
exposed tabs.
PNA SUFFIX
CASE 1402-02
16-TERMINALPQFN
Features
• Dual 4.0 mΩ Max High-Side Switch with Parallel Input or SPI Control
• 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 µA
• Output Current Monitoring Output with Two SPI-Selectable Current
Ratios
ORDERING INFORMATION
Temperature
Device
Package
Range (TA)
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe
Pin Status, and Program Status.
16 PQFN
PC33984PNA/R2
-40°C to 125°C
• Enhanced 16 V Reverse Polarity VPWR Protection
33984 Simplified Application Diagram
VDD
VPWR
VDD
VDD
33984
VPWR
VDD
FS
GND
I/O
I/O
SO
SCLK
CS
SI
WAKE
SI
SCLK
CS
SO
HS1
HS0
MCU
LOAD
I/O
I/O
RST
IN0
I/O
IN1
LOAD
A/D
CSNS
FSI GND
GND
PWRGND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
For More Information On This Product,
© Motorola, Inc. 2004
Go to: www.freescale.com
Freescale Semiconductor, Inc.
V
V
PWR
DD
Internal
Overvoltage
Protection
Regulator
Configurable
Switch Delay
0 ms –525 ms
Selectable Slew
Rate Gate Drive
CS
SPI
3.0 MHz
SCLK
HS0
Selectable Over-
SO
SI
current Detection High
100 A or 75 A
RST
WAKE
IN0
Logic
Selectable Current
Selectable Over-
current Detection Low
7.5 A –25 A
Detection Time
FS
0.15 ms–155 ms
Open Load
Detection
IN1
Overtemperature
Detection
HS0
HS1
HS1
Programmable
Watchdog
310ms–2500 ms
FSI
Selectable
Output Current
Recopy
1/20500 or 1/41000
GND
Figure 1. 33984 Simplified Internal Block Diagram
CSNS
33984
2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Transparent Top View of Package
CSNS
WAKE
RST
IN0
FS
FSI
CS
SCLK
SI
VDD
SO
IN1
1
2
3
4
5
6
7
8
9
16
15
HS0
HS1
14
13
VPWR
GND
10
11
12
TERMINAL FUNCTION DESCRIPTION
Terminal
Name
Terminal
Formal Name
Definition
1
CSNS
WAKE
RST
Output Current Monitoring
This terminal is used to output a current proportional to the designated HS0-1 output.
That current is fed into a ground-referenced resistor and its voltage is monitored by an
MCU's A/D. The channel to be monitored is selected via the SPI. This terminal can be
tri-stated through SPI.
2
3
Wake
This terminal is used to input a logic [1] signal so as to enable the watchdog timer
function. An internal clamp protects this terminal from high damaging voltages when the
output is current limited with an external resistor. This input has an internal passive pull-
down.
Reset (Active Low)
This input terminal is used to initialize the device configuration and fault registers, as
well as place the device in a low current sleep mode. The terminal also starts the
watchdog timer when transitioning from logic LOW to logic HIGH. This terminal should
not be allowed to be logic HIGH until VDD is in regulation. This terminal has an internal
passive pull-down.
4
5
IN0
FS
Serial Input
This input terminal is used to directly control the output HS0. This input has an internal
active pull-down and requires CMOS logic levels. This input may be configured via SPI.
Fault Status (Active Low)
This is an open drain configured output requiring an external pull-up resistor to VDD for
fault reporting. When a device fault condition is detected, this terminal is active LOW.
Specific device diagnostic faults are reported via the SPI SO terminal.
6
7
8
FSI
Fail-Safe Input
Chip Select (Active Low)
Serial Clock
The value of the resistance connected between this terminal and ground determines
the state of the outputs after a watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF, ON, or the output HSO only is ON. When the FSI
terminal is connected to GND, the watchdog circuit and fail-safe operation are disabled.
This terminal incorporates an active internal pull-up.
This input terminal is connected to a chip select output of a master microcontroller
(MCU). The MCU determines which device is addressed (selected) to receive data by
pulling the CS terminal of the selected device logic LOW, enabling SPI communication
with the device. Other unselected devices on the serial link having their CS terminals
pulled-up logic HIGH disregard the SPI communication data sent.
CS
SCLK
This input terminal is connected to the MCU providing the required bit shift clock for SPI
communication. It transitions one time per bit transferred at an operating frequency,
f
SPI, defined by the communication interface.The 50 percent duty cycle CMOS-level
serial clock signal is idle between command transfers. The signal is used to shift data
into and out of the device.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33984
3
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TERMINAL FUNCTION DESCRIPTION (continued)
Terminal
Name
Terminal
Formal Name
Definition
9
SI
Serial Input
This is a command data input terminal connected to the SPI Serial Data Output of the
MCU or to the SO terminal of the previous device of a daisy chain of devices. The input
requires CMOS logic-level signals and incorporates an internal active pull-down.
Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control
command. The MCU ensures data is available upon the falling edge of SCLK. The logic
state of SI present upon the rising edge of SCLK loads that bit command into the
internal command shift register.
10
11
VDD
SO
Digital Drain Voltage
(Power)
This is an external voltage input terminal used to supply power to the SPI circuit. In the
event VDD is lost, an internal supply provides power to a portion of the logic, ensuring
limited functionality of the device.
Serial Output
This is an output terminal connected to the SPI Serial Data Input terminal of the MCU
or to the SI terminal of the next device of a daisy chain of devices. This output will
remain tri-stated (high impedance OFF condition) so long as the CS terminal of the
device is logic HIGH. SO is only active when the CS terminal of the device is asserted
logic LOW. The generated SO output signals are CMOS logic levels. SO output data is
available on the falling edge of SCLK and transitions immediately on the rising edge of
SCLK.
12
IN1
Serial Input
This input terminal is used to directly control the output HS1. This input has an internal
active pull-down and requires CMOS logic levels. This input may be configured via SPI.
13
14
GND
Ground
This terminal is the ground for the logic and analog circuitry of the device.
VPWR
Positive Power Supply
This terminal connects to the positive power supply and is the source input of
operational power for the device. The VPWR terminal is a backside surface mount tab
of the package.
15
16
HS1
HS0
High-Side Output 1
High-Side Output 0
Protected 4.0 mΩ high-side power output to the load.
Protected 4.0 mΩ high-side power output to the load.
33984
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Operating Voltage Range
Steady-State
VPWR
V
-16 to 41
0 to 5.5
VDD Supply Voltage
VDD
V
V
Input/Output Voltage (Note 1)
-0.3 to 7.0
V
IN[0:1], RST, FSI
CSNS, SI, SCLK,
CS, FS
SO Output Voltage (Note 1)
WAKE Input Clamp Current
CSNS Input Clamp Current
Output Current (Note 2)
-0.3 to VDD+0.3
V
mA
mA
A
VSO
ICL(WAKE)
ICL(CSNS)
IHS[0:1]
ECL[0:1]
TSTG
2.5
10
30
Output Clamp Energy (Note 3)
Storage Temperature
0.75
J
-55 to 150
-40 to 150
°C
Operating Junction Temperature
TJ
°C
Thermal Resistance (Note 4)
Junction to Case
°C/W
R
R
<1.0
20
JC
θ
Junction to Ambient
JA
θ
ESD Voltage
V
VESD1
VESD2
±2000
±200
Human Body Model (Note 5)
Machine Model (Note 6)
Terminal Soldering Temperature (Note 7)
TSOLDER
240
°C
Notes
1. Exceeding voltage limits on RST, IN[0:1], or FSI terminals may cause a malfunction or permanent damage to the device.
2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150°C).
4. Device mounted on a 2s2p test board according to JEDEC JESD51-2.
5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
6. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33984
5
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Battery Supply Voltage Range
Full Operational
VPWR
V
6.0
–
–
–
27
20
IPWR(ON)
mA
VPWR Operating Supply Current
Output ON, IHS0 and IHS1 = 0 A
V
PWR Supply Current
IPWR(SBY)
mA
Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD
RST = VLOGIC HIGH
,
–
–
5.0
IPWR(SLEEP)
µA
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V)
TJ = 25°C
TJ = 85°C
–
–
–
–
10
50
V
V
DD Supply Voltage
VDD(ON)
IDD(ON)
4.5
5.0
5.5
V
DD Supply Current
mA
No SPI Communication
3.0 MHz SPI Communication
–
–
–
–
1.0
5.0
V
DD Sleep State Current
IDD(SLEEP)
–
–
5.0
µA
Overvoltage Shutdown
VPWR(ON)
VPWR(OVHYS)
VPWR(UV)
28
0.2
5.0
–
32
0.8
5.5
0.25
–
36
1.5
6.0
–
V
V
V
V
V
Overvoltage Shutdown Hysteresis
Undervoltage Output Shutdown (Note 8)
Undervoltage Hysteresis (Note 9)
Undervoltage Power-ON Reset
Notes
VPWR(UVHYS)
VPWR(UVPOR)
–
5.0
8. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not
go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the
external VDD supply is within specification.
9. This applies when the undervoltage fault is not latched (IN = 0).
33984
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT
RDS(ON)25
mΩ
Output Drain-to-Source ON Resistance (IHS[0:1] = 30 A, TJ = 25°C)
VPWR = 6.0 V
VPWR = 10 V
VPWR = 13 V
–
–
–
–
–
–
6.0
4.0
4.0
RDS(ON)150
mΩ
Output Drain-to-Source ON Resistance (IHS[0:1] = 30 A, TJ = 150°C)
VPWR = 6.0 V
VPWR = 10 V
VPWR = 13 V
–
–
–
–
–
–
10.2
6.8
6.8
RDS(ON)
mΩ
Output Source-to-Drain ON Resistance IHS[0:1] = 15 A, TJ = 25°C (Note 10)
–
–
8.0
V
PWR = -12 V
Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)
A
IOCH0
IOCH1
80
60
100
75
120
90
SOCH = 0
SOCH = 1
Overcurrent Low Detection Levels (SOCL[2:0])
A
IOCL0
IOCL1
IOCL2
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
21
18
16
14
12
10
8.0
6.0
25
22.5
20
17.5
15
12.5
10
7.5
29
27
24
21
17
15
12
9.0
000
001
010
011
100
101
110
111
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
CSR0
CSR1
–
–
1/20500
1/41000
–
–
DICR D2 = 0
DICR D2 = 1
Current Sense Ratio (CSR0) Accuracy
CSR0_ACC
%
Output Current
5.0 A
-20
-14
-13
-12
-13
-13
–
–
–
–
–
–
20
14
13
12
13
13
10 A
12.5 A
15 A
20 A
25 A
Notes
10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR
.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33984
7
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT (continued)
Current Sense Ratio (CSR1) Accuracy
CSR1_ACC
%
Output Current
5.0 A
-25
-19
-18
-17
-18
-18
–
–
–
–
–
–
25
19
18
17
18
18
10 A
12.5 A
15 A
20 A
25 A
Maximum Current Sense Clamp Voltage
VCL(MAXCSNS)
V
I
CSNS = 15 mA
4.5
30
6.0
–
7.0
Open Load Detection Current (Note 11)
IOLDC
100
µA
Output Fault Detection Threshold
Output Programmed OFF
VOLD(THRES)
V
2.0
-20
3.0
–
4.0
–
Output Negative Clamp Voltage
VCL
TSD
V
0.5 A < = IHS[0:1] < = 2.0 A, Output OFF
Overtemperature Shutdown (Note 12)
°C
°C
150
5.0
175
–
190
20
TA = 125°C, Output OFF
Overtemperature Shutdown Hysteresis (Note 12)
Notes
TSD(HYS)
11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
12. Guaranteed by process monitoring. Not production tested.
33984
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE
Input Logic High Voltage (Note 13)
Input Logic Low Voltage (Note 13)
Input Logic Voltage Hysteresis (Note 14)
Input Logic Pull-Down Current (SCLK, IN, SI)
RST Input Voltage Range
VIH
VIL
0.7VDD
–
–
–
–
0.2VDD
750
20
V
V
VIN[0:1](HYS)
IDWN
100
5.0
4.5
–
350
–
mV
µA
V
VRST
5.0
–
5.5
CSO
20
pF
kΩ
pF
V
SO, FS Tri-State Capacitance (Note 15)
Input Logic Pull-Down Resistor (RST) and WAKE
Input Capacitance (Note 15)
RDWN
CIN
100
–
200
4.0
400
12
WAKE Input Clamp Voltage (Note 16)
VCL(WAKE)
I
CL(WAKE) < 2.5 mA
7.0
-2.0
0.8VDD
–
–
–
14
-0.3
–
WAKE Input Forward Voltage
ICL(WAKE) = -2.5 mA
VF(WAKE)
V
V
SO High-State Output Voltage
VSOH
I
OH = 1.0 mA
FS, SO Low-State Output Voltage
OL = -1.6 mA
–
VSOL
V
I
0.2
0
0.4
5.0
20
SO Tri-State Leakage Current
CS > 0.7VDD
ISO(LEAK)
µA
µA
kΩ
-5.0
5.0
IUP
Input Logic Pull-Up Current (Note 17)
CS, VIN[0:1] > 0.7 VDD
–
FSI Input Pin External Pull-Down Resistance
FSI Disabled, HS[0:1] Indeterminate
FSI Enabled, HS[0:1] OFF
FSI Enabled, HS0 ON, HS1 OFF
FSI Enabled, HS[0:1] ON
RFS
RFSdis
RFSoffoff
RFSonoff
RFSonon
–
0
6.5
17
–
1.0
7.0
19
–
6.0
15
30
Notes
13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST signals
may be supplied by a derived voltage reference to VPWR
.
14. Parameter is guaranteed by processing monitoring but is not production tested.
15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
16. The current must be limited by a series resistance when using voltages > 7.0 V.
17. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD
.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33984
9
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 18)
9.0 V < VPWR < 16 V
SRRA_SLOW
SRRB_SLOW
SRRA_FAST
SRRB_FAST
SRFA_SLOW
SRFB_SLOW
SRFA_FAST
SRFB_FAST
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
0.2
0.03
0.4
0.6
0.1
1.0
0.1
0.6
0.1
2.0
0.35
1.2
0.3
4.0
1.2
1.2
0.3
4.0
1.2
Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 19)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 18)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 19)
9.0 V < VPWR < 16 V
0.03
0.2
Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 18)
9.0 V < VPWR < 16 V
Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 19)
9.0 V < VPWR < 16 V
0.03
0.8
Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 18)
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 19)
9.0 V < VPWR < 16 V
0.1
Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 20)
DICR = 0, DICR = 1
tDLY(ON)
tDLY_SLOW(OFF)
tDLY_FAST(OFF)
fPWM
µs
µs
µs
Hz
1.0
20
15
100
500
Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 21)
DICR = 0
230
Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 21)
DICR = 1
10
–
60
200
–
Direct Input Switching Frequency (DICR D3 = 0)
Notes
300
18. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR-3.5 V. These parameters are
guaranteed by process monitoring.
19. Rise and Fall Slew Rates B measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR-3.5 V. These parameters are
guaranteed by process monitoring.
20. Turn-ON delay time measured from rising edge of IN[0:1] signal that would turn the output ON to VHS[0:1] = 0.5 V with RL = 5.0 Ω resistive load.
21. Turn-OFF delay time measured from falling edge that would turn the output OFF to VHS[0:1] = VPWR -0.5 V with RL = 5.0 Ω resistive load.
33984
10
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING (continued)
Overcurrent Detection Blanking Time (OCLT[1:0])
ms
tOCL0
tOCL1
tOCL2
tOCL3
00
01
10
11
108
7.0
0.8
155
10
1.2
202
13
1.6
0.08
0.15
0.25
Overcurrent High Detection Blanking Time
CS to CSNS Valid Time (Note 22)
tOCH
1.0
–
10
–
20
10
µs
µs
CNSVAL
HS0 Switching Delay Time (OSD[2:0])
ms
tOSD0
tOSD1
tOSD2
tOSD3
tOSD4
tOSD5
tOSD6
tOSD7
000
001
010
011
100
101
110
111
–
55
0
75
–
95
110
165
220
275
330
385
150
225
300
375
450
525
190
285
380
475
570
665
HS1 Switching Delay Time (OSD[2:0])
ms
tOSD0
tOSD1
tOSD2
tOSD3
tOSD4
tOSD5
tOSD6
tOSD7
000
001
010
011
100
101
110
111
–
–
0
0
–
–
110
110
220
220
330
330
150
150
300
300
450
450
190
190
380
380
570
570
Watchdog Timeout (WD[1:0]) (Note 23)
ms
00
01
tWDTO0
tWDTO1
tWDTO2
tWDTO3
434
207
620
310
806
403
10
11
1750
875
2500
1250
3250
1625
Notes
22. Time necessary for the CSNS to be within ±5% of the targeted value.
23. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven
OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts.
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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation
fSPI
tWRST
tCS
–
–
–
–
–
–
–
–
–
–
–
50
–
3.0
350
300
5.0
167
167
167
167
83
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Required Low State Duration for RST (Note 24)
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 25)
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 25)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 25)
Required High State Duration of SCLK (Required Setup Time) (Note 25)
Required Low State Duration of SCLK (Required Setup Time) (Note 25)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 25)
SI to Falling Edge of SCLK (Required Setup Time) (Note 26)
tENBL
–
tLEAD
50
–
tWSCLKh
tWSCLKl
tLAG
–
50
25
25
tSI(SU)
tSI(HOLD)
tRSO
Falling Edge of SCLK to SI (Required Setup Time) (Note 26)
83
SO Rise Time
CL = 200 pF
–
25
50
SO Fall Time
CL = 200 pF
tFSO
ns
–
–
–
–
–
25
–
50
50
tRSI
tRSI
ns
ns
ns
ns
ns
SI, CS, SCLK, Incoming Signal Rise Time (Note 26)
–
50
SI, CS, SCLK, Incoming Signal Fall Time (Note 26)
tSO(EN)
tSO(DIS)
tVALID
–
145
145
Time from Falling Edge of CS to SO Low Impedance (Note 27)
Time from Rising Edge of CS to SO High Impedance (Note 28)
65
Time from Rising Edge of SCLK to SO Data Valid (Note 29)
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF
–
65
105
Notes
24. RST low duration measured with outputs enabled and going to OFF or disabled condition.
25. Maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller.
26. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
27. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
28. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
29. Time required to obtain valid data out from SO following the rise of SCLK.
33984
12
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Timing Diagrams
CS
V
PWR
VPWR-0.5V
V
SR
fB
FB
SR
SRrB
RB
PWR-3.5 V
SR
fA
FA
SRrA
RA
0.5 V
t
Tyf
DLY(OFF)
t
l
DLY(ON)
Figure 2. Output Slew Rate and Time Delays
IOCHx
ILOAD1
Load
ILOAD1
Current
IOCLx
tOCH
Time
tOCLx
Figure 3. Overcurrent Shutdown
I
OCH0
I
OCH1
I
I
OCL0
OCL1
I
OCL2
Load
Current
I
OCL3
I
I
I
I
OCL4
OCL5
OCL6
OCL7
Time
t
t
t
t
t
OCL0
OCHx
OCL3
OCL2
OCL1
Figure 4. Overcurrent Low and High Detection
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VIH
RST
0.2 VDD
0.2 VDD
VIL
VIL
tCS
tENBL
tWRST
VIH
VIH
0.7 V
DD
CS
00..77VVDD
DD
VIL
VIL
tRSI
TrSI
tWSCLKh
tTlead
LEAD
tLAG
H
VIH
0.7 VDD
0.7VDD
SCLK
SCLK
0.2 VDD
0.2VDD
VIL
tSI(SU)
t
TwSCLKl
WSCLKl
fSI
tFSI
t
SI(HOLD)
VIH
VIH
00..77V
DD
0.2 VDD
Don’t Care
Don’t Care
Don’t Care
Valid
Valid
SI
SI
V
IH
Figure 5. Input Timing Switching Characteristics
tRSI
tFSI
VOH
3.5 V
50%
SCLK
1.0 V
VOL
tSO(EN)
0.2V
VOH
0.7 V
DD
SO
DD
VOL
Low to High
tRSO
tVALID
tFSO
SO
VOH
0.7 V
DD
High to Low
0.2 VDD
VOL
tSO(DIS)
Figure 6. SCLK Waveform and Valid SO Data Delay Time
33984
14
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33984 is a dual self-protected 4.0 mΩ silicon switch
Programming, control, and diagnostics are implemented via
the Serial Peripheral Interface (SPI). A dedicated parallel input
is available for alternate and Pulse Width Modulation (PWM)
control of each output. SPI-programmable fault trip thresholds
allow the device to be adjusted for optimal performance in the
application.
used to replace electromechanical relays, fuses, and discrete
devices in power management applications. The 33984 is
designed for harsh environments, and it includes self-recovery
features. The device is suitable for loads with high inrush
current, as well as motors and all types of resistive and
inductive loads.
The 33984 is packaged in a power-enhanced 12 x 12 PQFN
package with exposed tabs.
FUNCTIONAL DESCRIPTION
D0. The internal registers of the 33984 are configured and
controlled using a 4-bit addressing scheme, as shown in
Table 1, page 16. Register addressing and configuration are
described in Table 2, page 17. The SI input has an internal pull-
SPI Protocol Description
The SPI interface has a full duplex, three-wire synchronous
data transfer with four I/O lines associated with it: Serial Clock
(SCLK), Serial Input (SI), Serial Output (SO), and Chip Select
(CS).
down, IDWN
.
The SI/SO terminals of the 33984 follow a first-in first-out
(D7/D0) protocol with both input and output words transferring
the most significant bit (MSB) first. All inputs are compatible
with 5.0 V CMOS logic levels.
Serial Output (SO)
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high impedance state
until the CS terminal is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO terminal
changes states on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and Input Status descriptions are
provided in Table 11, page 21.
The SPI lines perform the following functions:
Serial Clock (SCLK)
Serial clocks (SCLK) the internal shift registers of the 33984
device. The serial input (SI) terminal accepts data into the input
shift register on the falling edge of the SCLK signal while the
serial output (SO) terminal shifts data information out of the SO
line driver on the rising edge of the SCLK signal. It is important
that the SCLK terminal be in a logic low state whenever CS
makes any transition. For this reason, it is recommended that
the SCLK terminal be in a logic [0] state whenever the device is
not accessed (CS logic [1] state). SCLK has an internal pull-
down, IDWN. When CS is logic [1], signals at the SCLK and SI
terminals are ignored and SO is tri-stated (high impedance).
(See Figure 7 and Figure 8 on page 16.)
Chip Select (CS)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33984 device latches
in data from the Input shift registers to the addressed registers
on the rising edge of CS. The device transfers status
information from the power output to the shift register on the
falling edge of CS. The SO output driver is enabled when CS is
logic [0]. CS should transition from a logic [1] to a logic [0] state
only when SCLK is a logic [0]. CS has an internal pull-up, IUP
.
Serial Input (SI)
This is a serial interface (SI) command data input terminal. SI
instruction is read on the falling edge of SCLK. An 8-bit stream
of serial data is required on the SI terminal, starting with D7 to
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33984
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CSB
CS
SCLK
SI
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD7
OD6
OD5
OD4
OD3
OD2
OD1 OD0
Notes 1. RST is a logic [1] state during the above operation.
2. D7–D0 relate to the most recent ordered entry of data into the device.
3.OD7–OD0relatetothefirst8bitsoforderedfaultandstatusdataout ofthe device.
Figure 7. Single 8-Bit Word SPI Communication
CS
SCLK
SSI
D
7
D
6
D
5
D
2
D
1
D
0
D
7
*
D
6
*
D
5
*
D
2
*
D
1
*
D
0
*
O
D
7
O
D
6
O
D
5
O
D
2
O
D
1
O
D
0
D
7
D
6
D
5
D
2
D
1
D
0
SO
N
Notes
1. RST isa logic[1] state during the above operation.
2. D7–D0 relate to the most recent ordered entry of data into the device.
3. D7*–D0*relateto the previous 8 bits (last command word) of data thatwaspreviously shifted into the device.
4. OD7–OD0 relate to the first 8 bits of ordered fault and status data out of the device.
Figure 8. Multiple 8-Bit Word SPI Communication
The 33984 has defined registers, which are used to
configure the device and to control the state of the output.
Table 2 page 17, summarizes the SI registers. The registers
are addressed via D6–D4 of the incoming SPI word (Table 1).
Serial Input Communication
SPI communication is accomplished using 8-bit messages.
A message is transmitted by the MCU starting with the MSB,
D7, and ending with the LSB, D0 (Table 1). Each incoming
command message on the SI terminal can be interpreted using
the following bit assignments: the MSB (D7) is the watchdog bit
and in some cases a register address bit common to both
outputs or specific to an output; the next three bits, D6–D4, are
used to select the command register; and the remaining four
bits, D3–D0, are used to configure and control the outputs and
their protection features.
Table 1. SI Message Bit Assignment
Message Bit Description
Bit Sig SI Msg Bit
MSB
D7
Register address bit for output selection. Also
used for Watchdog: toggled to satisfy
watchdog requirements.
D6–D4
D3–D1
Register address bits.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of eight bits. Any attempt made to
latch in a message that is not eight bits will be ignored.
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
LSB
D0
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
33984
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Address x010— Select Overcurrent High and Low Register
Table 2. Serial Input Address and Configuration Bit Map
(SOCHLR)
Serial Input Data
SI
The SOCHLR register allows the MCU to configure the
output overcurrent low and high detection levels, respectively.
Each output is independently selected for configuration based
on the state of the D7 bit; a write to this register when D7 is
logic [0] will configure the current detect levels for the HS0.
Similarly, if D7 is logic [1] when this register is written, HS1 is
configured. Each output can be configured to different levels. In
addition to protecting the device, this slow blow fuse emulation
feature can be used to optimize the load requirements matching
system characteristics. Bits D2–D0 set the overcurrent low
detection level to one of eight possible levels, as shown in
Table 3. Bit D3 sets the overcurrent high detection level to one
of two levels, which is described in Table 4.
Register
D7 D6 D5 D4
D3
D2
D1
D0
SO
STATR
OCR
0
0
0
0
0
1
0
SOA2
SOA1
SOA0
A3
CSNS1
EN
CSNS0
EN
x
IN1_SPI
IN0_SPI
SOCHLR
CDTOLR
s
s
0
0
1
1
0
1
SOCHs SOCL2s SOCL1s SOCL0s
OL DIS s CD DISs OCLT1s OCLT0s
FAST
SRs
CSNS
highs
DICR
s
1
0
0
IN DIS s
A/Os
OSDR
WDR
NAR
0
1
0
1
x
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
0
0
OSD2
OSD1
WD1
0
OSD0
WD0
0
0
0
0
Table 3. Overcurrent Low Detection Levels
SOCL2
(D2)
SOCL1
(D1)
SOCL0
(D0)
Overcurrent Low Detection
(Amperes)
UOVR
TEST
UV_dis
OV_dis
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
25
22.5
20
Motorola Internal Use (Test)
x = Don’t care.
s = Selection of output: logic [0] = HS0, logic [1] = HS1.
17.5
15
Device Register Addressing
The following section describes the possible register
addresses and their impact on device operation.
12.5
10
Address x000—Status Register (STATR)
7.5
The START register is used to read the device status and the
various configuration register contents without disrupting the
device operation or the register contents. The register bits D2,
D1, D0 determine the content of the first eight bits of SO data.
When the register content is specific to one of the two outputs,
the bit D7 is used to select the desired output. In addition to the
device status, this feature provides the ability to read the
content of the OCR, SOCHLR, CDTOLR, DICR, OSDR, WDR,
NAR, and UOVR registers. (Refer to the section entitled Serial
Output Communication (Device Status Return Data) beginning
on page 19.)
Table 4. Overcurrent High Detection Levels
Overcurrent High Detection
SOCH (D3)
(Amperes)
0
1
100
75
Address x011—Current Detection Time and Open Load
Register (CDTOLR)
Address x001—Output Control Register (OCR)
The CDTOLR register is used by the MCU to determine the
amount of time the device will allow an overcurrent low
condition before output latches OFF occurs. Each output is
independently selected for configuration based on the state of
the D7 bit. A write to this register when bit 7 is logic [0] will
configure the timeout for the HS0. Similarly, if D7 is logic [1]
when this register is written, then HS1 is configured. Bits D1–
D0 allow the MCU to select one of four fault blanking times
defined in Table 5, page 18. Note that these timeouts apply only
to the overcurrent low detection levels. If the selected
overcurrent high level is reached, the device will latch off within
20 µs.
The OCR register allows the MCU to control the outputs
through the SPI. Incoming message bit D0 reflects the desired
states of the high-side output HS0 (IN_SPI): a logic [1] enables
the output switch and a logic [0] turns it OFF. A logic [1] on
message bit D1 enables the Current Sense (CSNS) terminal.
Similarly, incoming message bit D2 reflects the desired states
of the high-side output HS1 (IN_SPI). A logic [1] enables the
output switch and a logic [0] turns it OFF. A logic [1] on
message bit D3 enables the CSNS terminal. In the event that
the current sense is enabled for both outputs, the current will be
summed. Bit D7 is used to feed the watchdog if enabled.
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A write to this register configures both outputs for different
Table 5. Overcurrent Low Detection
Blanking Timing
delay. Whenever the input is commanded to transition from [0]
to [1], both outputs will be held OFF for the time delay
configured in the OSDR. The programming of the contents of
this register have no effect on device fail-safe mode operation.
The default value of the OSDR register is 000, equating to no
delay. This feature allows the user a way to minimize inrush
currents, or surges, thereby allowing loads to be switched ON
with a single command. There are eight selectable output
switching delay times that range from 0 ms to 525 ms (refer to
Table 6).
OCLT[1:0]
Timing
155 ms
10 ms
00
01
10
11
1.2 ms
150 µs
A logic [1] on bit D2 disables the overcurrent low (CD dis)
detection timeout feature. A logic [1] on bit D3 disables the open
load (OL) detection feature.
Table 6. Switching Delay
OSD[2:0]
Turn ON Delay (ms) Turn ON Delay (ms)
Address x100—Direct Input Control Register (DICR)
(D2, D1, D0)
HS0
0
HS1
0
The DICR register is used by the MCU to enable, disable, or
configure the direct IN terminal control of each output. Each
output is independently selected for configuration based on the
state of bit D7. A write to this register when bit D7 is logic [0] will
configure the direct input control for the HS0. Similarly, if D7 is
logic [1] when this register is written, then HS1 is configured.
000
001
010
011
100
101
110
111
75
0
150
225
300
375
450
525
150
150
300
300
450
450
A logic [0] on bit D1 will enable the output for direct control by
the IN terminal. A logic [1] on bit D1 will disable the output from
direct control. While addressing this register, if the input was
enabled for direct control, a logic [1] for the D0 bit will result in
a Boolean AND of the IN terminal with its corresponding D0
message bit when addressing the OCR register. Similarly, a
logic [0] on the D0 terminal results in a Boolean OR of the IN
terminal with the corresponding message bits when addressing
the OCR register.
Address 1101—Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
watchdog timeout. Watchdog timeout is configured using bits
D1 and D0. When D1 and D0 bits are programmed for the
desired watchdog timeout period, the WD bit (D7) should be
toggled as well, ensuring the new timeout period is
programmed at the beginning of a new count sequence (refer
to Table 7).
The DICR register is useful if there is a need to
independently turn on and off several loads that are PWM’d at
the same frequency and duty cycle with only one PWM signal.
This type of operation can be accomplished by connecting the
pertinent direct IN terminals of several devices to a PWM output
port from the MCU and configuring each of the outputs to be
controlled via their respective direct IN terminal. The DICR is
then used to Boolean AND the direct IN(s) of each of the
outputs with the dedicated SPI bit that also controls the output.
Each configured SPI bit can now be used to enable and disable
the common PWM signal from controlling its assigned output.
Table 7. Watchdog Timeout
WD[1:0] (D1, D0)
Timing (ms)
620
00
01
10
11
310
A logic [1] on bit D2 is used to select the high ratio (CSR1
,
2500
1/41000) on the CSNS terminal for the selected output. The
default value [0] is used to select the low ratio (CSR0, 1/20500).
1250
A logic [1] on bit D3 is used to select the high speed slew rate
for the selected output. The default value [0] corresponds to the
low speed slew rate.
Address 0110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy chain SPI configuration. This allows devices
to not be affected by commands being clocked over a daisy-
chained SPI configuration, and by toggling the WD bit (D7) the
watchdog circuitry will continue to be reset while no
programming or data readback functions are being requested
from the device.
Address 0101—Output Switching Delay Register (OSDR)
The OSDR register configures the device with a
programmable time delay that is active during Output ON
transitions initiated via SPI (not via direct input).
33984
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Address 1110—Undervoltage/Overvoltage Register
(UOVR)
is a multiple of eight bits. At this time, the SO terminal is tri-
stated and the fault status register is now able to accept new
fault status information.
The UOVR register can be used to disable or enable the
overvoltage and/or undervoltage protection. By default ([0]),
both protections are active. When disabled, an undervoltage or
overvoltage condition fault will not be reported in the output fault
register.
The output status register correctly reflects the status of the
STATR-selected register data at the time that the CS is pulled
to a logic [0] during SPI communication and/or for the period of
time since the last valid SPI communication, with the following
exceptions:
Address x111—TEST
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an under-
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following an undervoltage VPWR condition should be
ignored.
• The RST terminal transition from a logic [0] to [1] while the
WAKE terminal is at logic [0] may result in incorrect data
loaded into the status register. The SO data transmitted to
the MCU during the first SPI communication following this
condition should be ignored.
The TEST register is reserved for test and is not accessible
with SPI during normal operation.
Serial Output Communication (Device Status Return
Data)
When the CS terminal is pulled low, the output status register
is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first
as the new message data is clocked into the SI terminal. The
first eight bits of data clocking out of the SO, and following a CS
transition, are dependant upon the previously written SPI word.
Any bits clocked out of the SO terminal after the first eight will
be representative of the initial message bits clocked into the SI
terminal since the CS terminal first transitioned to a logic [0].
This feature is useful for daisy chaining devices as well as
message verification.
Serial Output Bit Assignment
The 8 bits of serial output data depend on the previous serial
input message, as explained in the following paragraphs.
Table 8 summarizes the SO register content.
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the data
is latched into the appropriate registers. A valid message length
Table 8. Serial Output Bit Map Description
Previous STATR
D7, D2, D1, D0
Serial Output Returned Data
SOA3 SOA2 SOA1 SOA0
OD7
OD6
OD5
OD4
OD3
OD2
UVF
OD1
OVF
OD0
FAULTs
IN0_SPI
SOCL0s
OCLT0s
A/Os
s
x
s
s
s
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
0
s
x
s
s
s
0
1
0
OTFs
OCHFs
OCLFs
OLFs
0
0
0
1
1
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
0
CSNS1 EN
SOCHs
IN1_SPI
SOCL2s
CD DIS s
CSNS high s
OSD2
CSNS0 EN
SOCL1s
OCLT1s
IN DIS s
OSD1
OL DIS s
Fast SRs
FSM_HS0
FSM_HS1
OSD0
WDTO
WD1
WD0
IN1 Terminal IN0 Terminal FSI Terminal
WAKE
Terminal
1
x
1
1
1
1
0
1
1
–
1
–
1
–
0
–
–
–
–
–
UV_dis
–
OV_dis
–
s = Selection of output: logic [0] = HS0, logic [1] = HS1.
x = Don’t care.
Bit OD7 reflects the state of the watchdog bit (D7) addressed
during the prior communication. The value of the previous D7
will determine which output the status information applies to for
the Fault (FLTR), SOCHLR, CDTOLR, and DICR registers. SO
data will represent information ranging from fault status to
register contents, user selected by writing to the STATR bits
D2, D1, and D0. Note that the SO data will continue to reflect
the information for each output (depending on the previous D7
state) that was selected during the most recent STATR write
until changed with an updated STATR write.
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Previous Address SOA[2:0]=000
Previous Address SOA[2:0]=100
If the previous three MSBs are 000, bits OD6–OD0 will
reflect the current state of the fault register (FLTR)
corresponding to the output previously selected with the bit
OD7 (Table 9).
The returned data contain the programmed values in the
DICR.
Previous Address SOA[2:0]=101
• SOA3 = 0. The returned data contain the programmed
values in the OSDR. Bit OD3 (FSM_HS0) reflects the
state of the output HS0 in the Fail-Safe mode after a
watchdog timeout occurs.
Table 9. Fault Register
OD7
s
OD6
OD5
OD4
OD3
OD2
OD1
OVF FAULTs
OD0
OTF OCHFs OCLFs OLFs
UVF
• SOA3 = 1. The returned data contain the programmed
values in the WDR. Bit OD2 (WDTO) reflects the status of
the watchdog circuitry. If WDTO bit is [1], the watchdog
has timed out and the device is in Fail-Safe mode. If
WDTO is [0], the device is in Normal mode (assuming the
device is powered and not in Sleep mode), with the
watchdog either enabled or disabled. Bit OD3 (FSM_HS1)
reflects the state of the output HS1 in the Fail-Safe mode
after a watchdog timeout occurs.
OD7 (s) = Selection of output: logic [0] = HS0, logic [1] = HS1.
OD6 (OTF) = Overtemperature Flag.
OD5 (OCHFs) = Overcurrent High Flag. (This fault is latched.)
OD4 (OCLFs) = Overcurrent Low Flag. (This fault is latched.)
OD3 (OLFs) = Open Load Flag.
OD2 (UVF) = Undervoltage Flag. (This fault is latched or not latched.)
OD1 (OVF) = Overvoltage Flag.
OD0 (FAULTs) = This flag reports a fault and is reset by a read
operation.
Previous Address SOA[2:0] =110
• SOA3 = 0. OD3 to OD0 return the state of the IN1, IN0,
FSI, and WAKE terminal, respectively (Table 10).
Note The FS terminal reports a fault. For latched faults, this terminal
is reset by a new Switch ON command (via SPI or direct input IN).
Table 10. Terminal Register
Previous Address SOA[2:0]=001
OD3
OD2
OD1
OD0
Data in bits OD1 and OD0 contain CSNS0 EN and IN0_SPI
programmed bits, respectively. Data in bits OD3 and OD2
contain CSNS0 EN and IN0_SPI programmed bits,
respectively.
IN1 Terminal IN0 Terminal
FSI Terminal
WAKE Terminal
• SOA3 = 1. The returned data contain the programmed
values in the UOVR. Bit OD1 reflects the state of the
undervoltage protection and bit OD0 reflects the state of
the overvoltage protection (refer to Table 8, page 19).
Previous Address SOA[2:0]=010
The data in bit OD3 contain the programmed overcurrent
high detection level (refer to Table 4, page 17), and the data in
bits OD2, OD1, and OD0 contain the programmed overcurrent
low detection levels (refer to Table 3, page 17).
Previous Address SOA[2:0]=111
Null Data. No previous register Read Back command
received, so bits OD2, OD1, and OD0 are null, or 000.
Previous Address SOA[2:0]=011
Data returned in bits OD1 and OD0 are current values for the
overcurrent dead time, illustrated in Table 5, page 18. Bit OD2
reports if the overcurrent detection timeout feature is active.
OD3 reports if the open load circuitry is active.
33984
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MODES OF OPERATION
The 33984 has four operating modes: Sleep, Normal, Fail-
Fail-Safe Mode
Safe, and Fault. Refer to Table 11 for details.
Fail-Safe Mode and Watchdog
Table 11. Fail-Safe Operation and
Transitions to Other 33984 Modes
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input terminal
transitions from logic [0] to [1]. The WAKE input is capable of
being pulled up to VPWR with a series of limiting resistance that
limits the internal clamp current according to the specification.
Mode
FS
WAKE RST WDTO
Comments
Sleep
x
0
0
x
Device is in Sleep mode.
All outputs are OFF.
The watchdog timeout is a multiple of an internal oscillator
and is specified in Table 7, page 18. As long as the WD bit (D7)
of an incoming SPI message is toggled within the minimum
watchdog timeout period (WDTO), based on the programmed
value of the WDR the device will operate normally. If an internal
watchdog timeout occurs before the WD bit, the device will
revert to a Fail-Safe mode until the device is reinitialized.
Normal
Fault
1
x
1
No
Normal mode. Watchdog
is active if enabled.
0
0
1
x
x
The device is currently in
fault mode. The faulted
output(s) is (are) OFF.
No
1
1
1
1
0
1
1
1
1
0
Watchdog has timed out
and the device is in Fail-
Safe mode. The outputs
are as configured with the
RFS resistor connected to
FSI. RST and WAKE must
be transitioned to logic [0]
simultaneously to bring
the device out of the Fail-
Safe mode or momentarily
tied the FSI terminal to
ground.
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI terminal,
regardless of the state of the various direct inputs and modes
(Table 12). In this mode, the SPI register content is retained
except for overcurrent high and low detection levels and timing,
which are reset to their default value (SOCL, SOCH, and
OCLT). Then the watchdog, overvoltage, overtemperature, and
overcurrent circuitry (with default value) are fully operational.
Fail-
Safe
Yes
Table 12. Output State During Fail-Safe Mode
x = Don’t care.
RFS (kΩ)
High-Side State
Fail-Safe Mode Disabled
Both HS0 and HS1 OFF
HS0 ON, HS1 OFF
0
Sleep Mode
6.0
15
30
The default mode of the 33984 is the Sleep mode. This is the
state of the device after first applying battery voltage (VPWR),
prior to any I/O transitions. This is also the state of the device
when the WAKE and RST are both logic [0]. In the Sleep mode,
the output and all unused internal circuitry, such as the internal
5.0 V regulator, are off to minimize current draw. In addition, all
SPI-configurable features of the device are as if set to logic [0].
The device will transition to the Normal or Fail-Safe operating
modes based on the WAKE and RST inputs as defined in
Table 11.
Both HS0 and HS1 ON
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is logic [1] when the
device is in fail-safe mode. The device can be brought out of the
Fail-Safe mode by transitioning the WAKE and RST terminals
from logic [1] to logic [0] or forcing the FSI terminal to logic [0].
Table 11 summarizes the various methods for resetting the
device from the latched Fail-Safe mode.
Normal Mode
If the FSI terminal is tied to GND, the Watchdog fail-safe
operation is disabled.
The 33984 is in Normal mode when:
• VPWR is within the normal voltage range.
Loss of V
DD
•
RST terminal is logic [1].
• No fault has occurred.
If the external 5.0 V supply is not within specification, or even
disconnected, all register content is reset. The two outputs can
still be driven by the direct inputs IN[1:0]. The 33984 uses the
battery input to power the output MOSFET-related current
sense circuitry and any other internal logic providing fail-safe
device operation with no VDD supplied. In this state, the
watchdog, overvoltage, overtemperature, and overcurrent
circuitry are fully operational with default values.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33984
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Open Load Fault (Non-Latching)
Fault Mode
The 33984 incorporates open load detection circuitry on
each output. Output open load fault (OLF) is detected and
reported as a fault condition when that output is disabled (OFF).
The open load fault is detected and latched into the status
register after the internal gate voltage is pulled low enough to
turn OFF the output. The OLF fault bit is set in the status
register. If the open load fault is removed, the status register will
be cleared after reading the register.
The 33984 indicates the following faults as they occur by
driving the FS terminal to [0]:
• Overtemperature fault
• Open load fault
• Overcurrent fault (high and low)
• Overvoltage and undervoltage fault
The FS terminal will automatically return to [1] when the fault
condition is removed, except for Overcurrent and in some cases
Undervoltage.
The open load protection can be disabled trough SPI (bit
OL_dis).
Fault information is retained in the fault register and is
available (and reset) via the SO terminal during the first valid
SPI communication (refer to Table 9, page 20).
Overcurrent Fault (Latching)
The device has eight programmable overcurrent low
detection levels (IOCL) and two programmable overcurrent high
Overtemperature Fault (Non-Latching)
detection levels (IOCH) for maximum device protection. The two
selectable, simultaneously active overcurrent detection levels,
The 33984 device incorporates overtemperature detection
and shutdown circuitry in each output structure.
Overtemperature detection is enabled when an output is in the
ON state.
defined by IOCH and IOCL, are illustrated in Figure 4, page 13.
The eight different overcurrent low detect levels (IOCL0, IOCL1
IOCL2, IOCL3, IOCL4, IOCL5, IOCL6, and IOCL7) are likewise
illustrated in Figure 4.
,
For the output, an overtemperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely until
action is taken by the MCU to shut OFF the output, or until the
offending load is removed.
If the load current level ever reaches the selected
overcurrent low detect level and the overcurrent condition
exceeds the programmed overcurrent time period (tOCx), the
device will latch the effected output OFF.
When experiencing this fault, the OTF fault bit will be set in
the status register and cleared after either a valid SPI read or a
power reset of the device.
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF the
output, regardless of the selected tOCL driver.
For both cases, the device output will stay off indefinitely until
the device is commanded OFF and then ON again.
Overvoltage Fault (Non-Latching)
The 33984 shuts down the output during an overvoltage fault
(OVF) condition on the VPWR terminal. The output remains in
the OFF state until the overvoltage condition is removed. When
experiencing this fault, the OVF fault bit is set in the bit OD1 and
cleared after either a valid SPI read or a power reset of the
device.
Reverse Battery
The output survives the application of reverse voltage as low
as -16 V. Under these conditions, the output’s gates are
enhanced to keep the junction temperature less than 150°C.
The ON resistance of the output is fairly similar to that in the
Normal mode. No additional passive components are required.
The overvoltage protection and diagnostic can be disabled
trough SPI (bit OV_dis).
Ground Disconnect Protection
Undervoltage Shutdown (Latching or Non-Latching)
In the event the 33984 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless the state of the output at the time of
disconnection.
The output latches OFF at some battery voltage between
5.0 V and 6.0 V. As long as the VDD level stays within the
normal specified range, the internal logic states within the
device will be sustained. This ensures that when the battery
level then returns above 6.0 V, the device can be returned to
the state that it was in prior to the low VPWR excursion. Once the
output latches OFF, the outputs must be turned OFF and ON
again to re-enable them. In the case IN[1:0] = 0, this fault is
non-latched.
The undervoltage protection and diagnostic can be disabled
through SPI (bit UV_dis).
33984
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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PACKAGE DIMENSIONS
PNA SUFFIX
16-TERMINAL PQFN
NON-LEADED PACKAGE
CASE 1402-02
ISSUE B
12
A
M
2X
12
1
0.1
C
PIN 1
INDEX AREA
12
15
16
M
2X
0.1 C
PIN NUMBER
REF. ONLY
B
0.1
C
2.20
1.95
2.2
2.0
0.05 C
4
DETAIL G
0.6
0.05
0.00
10X 0.2
0.1
SEATING PLANE
C
M
M
C A B
C
DETAIL G
0.95
0.55
0.1
0.05
VIEW ROTATED 90˚ CLOCKWISE
2X
9X 0.9
M
M
C A B
C
C A B
0.1
0.05
2X 1.075
5.0
4.6
1
12
1.1
0.6
6X
2.05
6X
1.55
13
2.5
2.1
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
3.55
1.85
1.45
4X 1.05
5.5
5.1
14
4. COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
5. MINIMUM METAL GAP SHOULD BE 0.25MM.
(2)
0.1 C A B
0.8
6X
0.4
16
15
(10X 0.25)
(2X 0.75)
0.1 C A B
1.28
0.88
2X
(0.5)
2.25
1.75
0.15
0.05
(10X 0.4)
(10X 0.5)
6 PLACES
10.7
10.3
0.1 C A B
11.2
10.8
0.1 C A B
VIEW M-M
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33984
23
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MC33984/D
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