PC34708VK_技术文档

Document order number: MC34708

Rev. 7.0, 10/2011

Freescale Semiconductor

Advance Information

Power Management Integrated

Circuit (PMIC) for i.MX50/53

Families

34708

The MC34708 is the Power Management Integrated Circuit (PMIC)

designed specifically for use with the Freescale i.MX50 and i.MX53

families.

POWER MANAGEMENT

Features

• Six multi-mode buck regulators for direct supply of the processor

core, memory, and peripherals

• Boost regulator for USB OTG support

• Eight regulators with internal and external pass devices for thermal

budget optimization

VK SUFFIX (PB-FREE)

206 MAPBGA

8.0 X 8.0 (0.5 MM PITCH) 13.0 X 13.0 (0.8 MM PITCH)

VM SUFFIX (PB-FREE)

206 MAPBGA

• Dual input switching charger for single cell Li-Ion battery, supports

universal charging standard for selection of optimal charging profile

• Dual path charger design enables power-on with a dead/ no battery

• Coulomb counter support module for fuel gauge monitoring

• USB/UART/Audio switching for mini-micro USB connector

• 10-bit ADC for monitoring battery and other inputs

• Real time clock and crystal oscillator circuitry with coin cell backup/

charger

Applications

Tablets

Smart Mobile Devices

eReaders

Portable Navigation Devices

• SPI/I²C bus for control and register interface

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ꢀꢁꢂꢃꢄꢁ

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ꢅꢇꢈꢛꢔ

ꢗꢀ

ꢅꢏꢐꢉꢑꢈꢒ

ꢅ!!ꢖꢊꢆꢄꢔꢚꢃꢖꢖꢔꢄ

ꢎꢏ31ꢍ&ꢉ#ꢊ

ꢅꢆ

ꢅꢇꢈ

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78

ꢀꢁꢂꢃꢄꢅꢁꢆ

7

77

8

7E

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A

F

C

B

D

9

ꢆ ꢀ

Figure 1. MC34708 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Table of Contents

1

2

Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Part Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Format and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Simplified Internal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3

4

5

5.2.1

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3.1

5.3.2

General PMIC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6

7

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 Startup Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.2 Bias and References Block Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.3 Clocking and Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.3.1

7.3.2

7.3.3

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SRTC Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Coin Cell Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.4 Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.4.1

7.4.2

Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Interrupt Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.5 Power Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

7.5.6

Power Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Power Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Buck Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Boost Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Linear Regulators (LDOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.6 Battery Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.6

7.6.7

7.6.8

7.6.9

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Buck Charger Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Over-voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Thermal Fold back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Charge Source Input Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Trickle Charge Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Battery Thermistor Check Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Charge LEDs Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Coulomb Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

7.6.10 Charger Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

7.7 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.7.1

7.7.2

7.7.3

7.7.4

7.7.5

Input Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Dedicated Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Touch Screen Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

ADC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.8 Auxiliary Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.8.1

7.8.2

7.8.3

General Purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Mini/Micro USB Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

7.9 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

7.9.1

7.9.2

7.9.3

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

SPI/I2C Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.10 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.10.1 Register Set structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.10.2 Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

7.10.3 SPI/I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7.10.4 SPI Register’s Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

8.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

8.2 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

8.3 MC34708 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

8

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

General board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

General Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Parallel Routing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Differential Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Switching Regulator Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

8.4 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

8.4.1

8.4.2

Rating Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Estimation of Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

9

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

9.1 Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

10 Reference Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

MC34708

Analog Integrated Circuit Device Data

3

Freescale Semiconductor

Orderable Parts

1

Orderable Parts

This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are

provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part

number search for the following device numbers.

Table 1. Orderable Part Variations

Part Number ⁽¹⁾

Temperature (T )

Package

A

MC34708VK

MC34708VM

Notes

206 MAPBGA - 8.0 x 8.0 mm - 0.5 mm Pitch

206 MAPBGA - 13 x 13 mm - 0.8 mm Pitch

-40 to 85 °C

1. To Order parts in Tape & Reel, add the R2 suffix to the part number.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

Part Identification

2

Part Identification

This section provides an explanation of the part numbers and their alpha numeric breakdown.

2.1

Description

Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to

determine the specific part you have received.

2.2

Format and Examples

Part numbers for a given device have the following format, followed by a device example:

Table 2 - Part Numbering - Analog:

MC tt xxx r v PPP RR - MC34708VKR2

2.3

Fields

These tables list the possible values for each field in the part number (not all combinations are valid).

Table 2: Part Numbering - Analog

FIELD

MC

DESCRIPTION

VALUES

• MC- Qualified Standard

• PC- Prototype Device

Product Category

• 33 = -40 °C to > 105 °C

• 34 = -40 °C to  105 °C

• 35 = -55 °C to  125 °C

tt

Temperature Range

xxx

r

Product Number

Revision

• Assigned by Marketing

• (default blank)

v

Variation

• (default blank)

PPP

RR

Package Identifier

Tape and Reel Indicator

• Varies by package

• R2 = 13 inch reel hub size

MC34708

Analog Integrated Circuit Device Data

5

Freescale Semiconductor

Internal Block Diagram

3

Internal Block Diagram

3.1

Simplified Internal Diagram

MC34708

Block Diagram

Rev 0.66

Freescale

SW1IN

Semiconductor

Confidential

Proprietary

SW1ALX

GNDSW1A

SW1FB

O/P

Switching Charger

Battery Interface &

Drive

Interface and Control, Protection,

Protection

Trickle Generation

SW1

Dual Phase

GP

SW1CFG

SW1VSSSNS

LICELL, UID, Die Temp

2000 mA

Buck

Voltage /

Current

GNDADC

ADIN9

SW1BLX

GNDSW1B

O/P

Drive

Sensing &

10 Bit GP

A/D Result

Translation

ADC

DVS

CONTROL

SW1PWGD

ADIN10

ADIN11

A/D

Control

SW2IN

SW2LX

MUX

O/P

Drive

SW2

ADIN12/TSX1

ADIN13/TSX2

ADIN14/TSY1

ADIN15/TSY2

TSREF

GNDSW2

LP

`

SW2FB

1000 mA

SW2PWGD

Buck

Touch

Screen

Interface

Die Temp &

Thermal Warning

Detection

SW3IN

To Interrupt

Section

SW3

INT MEM

500 mA

Buck

O/P

Drive

SW3LX

GNDSW3

SW3FB

BPTHERM

NTCREF

SW4AIN

SW4ALX

GNDSW4A

SW4FBA

O/P

BATTISNSCCP

Drive

SW4

Dual Phase

DDR

1000 mA

Buck

BATTISNSCCN

CFP

Coulomb

Counter

CCOUT

SW4CFG

To SPI

Package Pin Legend

SW4BIN

CFN

SW4BLX

GNDSW4B

SW4BFB

O/P

Drive

Output Pin

Input Pin

SPIVCC

Shift Register

Bi-directional Pin

CS

CLK

SPI

SW5IN

Interface

SW5

I/O

1000 mA

Buck

O/P

Drive

SW5LX

GNDSW5

SW5FB

SPI

+

MOSI

MISO

To Enables & Control

Muxed

I2C

Registers

Optional

Interface

GNDSPI

Shift Register

SWBSTIN

SWBSTLX

SWBSTFB

O/P

Drive

SWBST

380 mA

Boost

VALWAYS

VCORE

GNDSWBST

VCOREDIG

VDDLP

Reference

Generation

MC34708

SPI Control

VINREFDDR

VHALF

VCOREREF

GNDCORE

GNDREF

VREFDDR

10mA

VREFDDR

SPKR

SPKL

MIC

VINPLL

VPLL

50 mA

Pass

FET

VUSB2DRV

VUSB2

TXD

RXD

Pass

FET

VUSB2

350mA

VBUS/ID

Detectors, Host

Auto detection

DPLUS

DMINUS

VDACDRV

VDAC

250mA

UART Switches

Audio Switches

To

Trimmed

Circuits

DP

DM

GNDUSB

UID

SPI

Trim-In-Package

Control

Logic

VINGEN1

VGEN1

250mA

Pass

FET

VBUS

Startup

Sequencer

Decode

Trim?

OVP

Control

Logic

VGEN2DRV

VGEN2

PUMSx

PLL

Switchers

Pass

FET

VGEN2

250mA

VINUSB

VUSB

Monitor

Timer

VUSB

Regulator

RTC +

32 KHz

LDOVDD

Calibration

Internal

Osc

SPI Result

Registers

Interrupt

Inputs

Enables &

Control

32 KHz

Buffers

Best

of

GNDREG1

GNDREG2

GNDREF1

GNDREF2

BP

LCELL

Switch

LICELL

Supply

PWM

Outputs

32 KHz

Crystal

Osc

GPIO Control

Li Cell

Charger

Core Control Logic, Timers, & Interrupts

VSRTC

Figure 2. MC34708 Simplified Internal Block Diagram

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

6

Pin Connections

4

Pin Connections

4.1

Pinout Diagram

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A

B

C

D

E

F

TRICKLESEL

GNDACHRG

BATT

CFP

BP

VBUSVIN

CHRGLX

GNDCHRG

LEDVDD

LICELL

PWM1

GPIOVDD

PUMS4

AUXVIN

VAUX

AUXVIN

GOTG

PRETMR

SUBSANA3

GAUX

BPTHERM

NTCREF

SDWNB

INT

CFN

GBAT

VBUSVIN

BATTISNSP

BATTISNSN

GLBRST

MIC

CHRGLX

GNDCHRG

SUBSPWR1

SW1VSSSNS

CHRGLEDG

PWM2

GPIOLV1

GPIOLV3

GPIOLV2

GPIOLV0

GNDREF2

SW3FB

GNDGPIO

PUMS1

PUMS3

GNDSW2

SW2LX

PUMS2

GNDSW2

SW2LX

SUBSANA2

GNDSW2

SW2LX

CHRGFB

BPSNS

CHRGLX

ICTEST

PUMS5

RESETB

MISO

GNDCTRL

GNDSPI

CS

PWRON2

MOSI

BATTISNSCCN

BATTISNSCCP

ITRIC

CHRGLEDR

SW2FB

SW2IN

SPIVCC

RXD

RESETBMCU

TXD

SUBSPWR1

PWRON1

SUBSPWR1

GNDREF1

SWBSTIN

GNDSWBST

SWBSTFB

VPLL

SWBSTIN

GNDSWBST

CLK32K

GNDSW3

SW3LX

GNDSW3

SW3LX

G

H

J

CLK

VINUSB

UID

SW2PWGD

CLK32KMCU

VDACDRV

VHALF

VBUS

VUSB

VALWAYS

VDDLP

TSX1

SUBSREF

STANDBY

SUBSPWR1

TSY2

CLK32KVCC

VINPLL

SW3IN

DM

SPKR

VCOREDIG

VCORE

GNDUSB

TSY1

VSRTC

SWBSTLX

GNDRTC

LDOVDD

VUSB2DRV

VINGEN1

GNDSW1B

SWBSTLX

SUBSLDO

XTAL2

K

L

DP

SPKL

ADIN10

ADIN9

VGEN2

VDAC

GNDREG1

VUSB2

DPLUS

DMINUS

VCOREREF

TSREF

GNDCORE

GNDREF

GNDADC

GNDSW4A

SW4ALX

WDI

TSX2

ADIN11

SUBSPWR1

SW5FB

SW1CFG

SW1FB

VINREFDDR

SW1PWGD

SW1IN

GNDREG2

M

N

P

R

SW4CFG

VGEN1

XTAL1

GNDADC

SW4AIN

GNDADC

SW4BIN

SW5IN

SW5LX

GNDSW5

SW1IN

SUBSANA1

SW1BLX

VGEN2DRV

VREFDDR

SW4BFB

SW4BLX

SW4AFB

SW5IN

GNDSW1A

SW1ALX

GNDSW4B

SW5IN

Legend

Regulators

Switchers

Control Logic

Charger

RTC

Ground

USB

ADC

SPI/I2C

No Connect

Figure 3. MC34708 Top View Ballmap

MC34708

Analog Integrated Circuit Device Data

7

Freescale Semiconductor

Pin Connections

4.2

Pin Definitions

Table 3. MC34708 Pin Definitions

Pin Number

Pin Name

Rating

# Balls

Definition

Function

Charger

A7

B7

C7

D7

1. Main charger input

VBUSVIN

I

7.5

4

2. Main output to battery supplied accessories

B1

B2

C1

C2

1. Aux charger input

AUXVIN

VAUX

I

7.5

20

4

1

4

Aux V_INsense

D1

A8

B8

C8

D8

Charger switch node connection

CHRGLX

O

7.5

Charger regulator feedback

C5

D2

D3

C6

CHRGFB

GOTG

I

7.5

20

1

Gate drive for external P-channel switch MVBUS

Gate drive for external P-channel Switch MAUX

BP sense point

O

I

GAUX

20

BPSNS

5.5

1. Application supply point

2. Input supply to the IC core circuitry

3. Application supply voltage sense

A6

BP

I

5.5

1

Driver output for battery path FET

Trickle charger output

B6

E8

E7

F7

GBAT

ITRIC

O

I

5.5

1

Battery current sensing point

BATTISNSP

BATTISNSN

I

1. Battery positive terminal

2. Battery current sensing point 2

3. Battery supply voltage sense

A4

BATT

I

5.5

1

Accumulated counter current sensing point

Accumulated current counter current sensing point

Trickle current programming input

Precharge timer programming input

Accumulated current filter cap plus terminal

Accumulated current filter cap minus terminal

Trickle LED supply

F6

E6

BATTISNSCCP

BATTISNSCCN

TRICKLESEL

PRETMR

I

5.5

3.6

4.8

20

1

I

A2

I

B3

I

A5

CFP

I

B5

CFN

I

A10

E10

B10

A3

LEDVDD

O

Trickle Red LED driver

CHRGLEDR

CHRGLEDG

GNDACHRG

I

7.5

-

Trickle Green LED driver

Analog ground for charger interface

GND

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

Pin Connections

Table 3. MC34708 Pin Definitions (continued)

Pin Number

Pin Name

Rating

# Balls

Definition

Function

A9

B9

C9

D9

Ground for charger interface

GNDCHRG

GND

--

4

Bias voltage for battery thermistor

Battery pack temperature thermistor

Indication of imminent system shutdown

C4

B4

NTCREF

BPTHERM

SDWNB

O

I

3.6

1

D4

O

IC Core

K3

Regulated supply for the IC analog core circuitry

Regulated supply for the IC digital core circuitry

Best of supply between battery and charger input

Main bandgap reference

VCORE

VCOREDIG

VALWAYS

VCOREREF

VDDLP

I

3.6

1.5

7.5

3.6

-

1

J3

I

H4

I

N1

I

VDDLP reference

J4

I

Ground for the IC core circuitry

L2

GNDCORE

GNDREF

GND

Ground reference for the IC core circuitry

M2

-

Switching Regulators

N11

N12

SW1 input

SW1IN

I

5.5

4

P12

R12

P11

R11

SW1A switch node connection

SW1 feedback

SW1ALX

SW1FB

O

I

5.5

3.6

-

2

1

2

M10

P10

R10

Ground for SW1A

GNDSW1A

GND

SW1 sense

L9

SW1VSSSNS

SW1PWGD

GND

O

-

1

Powergood signal for SW1

M11

3.6

P13

R13

SW1B switch node connection

SW1BLX

O

5.5

2

P14

R14

Ground for SW1B

GNDSW1B

SW1CFG

GND

I

-

2

1

SW1A/B mode configuration

L10

3.6

E13

E14

E15

SW2 input

SW2IN

I

5.5

3

D13

D14

D15

SW2 switch node connection

SW2 feedback

SW2LX

SW2FB

O

I

5.5

3.6

3

1

E12

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

Pin Connections

Table 3. MC34708 Pin Definitions (continued)

Pin Number

Pin Name

Rating

# Balls

Definition

Function

C13

C14

C15

Ground for SW2

GNDSW2

GND

-

3

Powergood signal for SW2

SW3 input

G10

SW2PWGD

SW3IN

O

I

3.6

5.5

1

2

H14

H15

G14

G15

SW3 switch node connection

SW3 feedback

SW3LX

SW3FB

O

I

5.5

3.6

-

2

1

2

G11

F14

F15

Ground for SW3

GNDSW3

GND

Ground reference for switching regulators

SW4A input

F11

R3

R2

P6

P2

R4

R5

P5

R6

M6

GNDREF2

SW4AIN

GND

-

1

I

5.5

3.6

-

SW4A switch node connection

SW4A feedback

SW4ALX

SW4AFB

GNDSW4A

SW4BIN

O

I

Ground for SW4A

GND

SW4B input

I

5.5

3.6

-

SW4B switch node connection

SW4B feedback

SW4BLX

SW4BFB

GNDSW4B

SW4CFG

O

I

GND

I

Ground for SW4B

SW4A/B mode configuration

3.6

N7

P7

R7

SW5 input

SW5IN

I

5.5

3

N8

P8

R8

SW5 output

SW5LX

SW5FB

O

I

5.5

3.6

-

3

1

3

SW5 feedback

Ground for SW5

M7

N9

P9

R9

GNDSW5

GND

Ground reference for Switching Regulators

Boost Regulator BP supply

L8

GNDREF1

SWBSTIN

GND

I

-

1

2

F12

F13

5.5

J14

J15

SWBST switch node connection

Boost Regulator feedback

Ground for boost Regulator

SWBSTLX

SWBSTFB

GNDSWBST

O

I

7.5

5.5

-

2

1

2

H12

G12

G13

GND

Regulators

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

Pin Connections

Table 3. MC34708 Pin Definitions (continued)

Pin Number

Pin Name

Rating

# Balls

Definition

Function

VREFDDR input supply

L11

P15

K10

J11

J12

J10

K12

L14

VINREFDDR

VREFDDR

VHALF

I

O

3.6

1.5

5.5

2.5

5.5

3.6

5.5

1

VREFDDR regulator output

Half supply reference for VREFDDR

VPLL input supply

O

VINPLL

I

VPLL regulator output

VPLL

O

Drive output for VDAC regulator using external PNP device

VDAC regulator output

VDACDRV

VDAC

O

Supply pin for VUSB2, VDAC, and VGEN2

1. VUSB2 input using internal PMOS FET

2. Drive output for VUSB2 regulator using external PNP device

VUSB2 regulator output

LDOVDD

I

M14

VUSB2DRV

5.5

1

O

L13

N14

M13

VUSB2

VINGEN1

VGEN1

O

3.6

2.5

1

VGEN1 input supply

I

VGEN1 regulator output

O

1. VGEN2 input using internal PMOS FET

2. Drive output for VINT regulator using external PNP device

VGEN2 regulator output

I

N15

VGEN2DRV

5.5

1

O

K11

J13

VGEN2

VSRTC

O

3.6

2.5

-

1

Output regulator for SRTC module on processor

Ground for regulators 1

O

K13

GNDREG1

GNDREG2

GPIOVDD

GPIOLV0

GPIOLV1

GPIOLV2

GPIOLV3

PWM1

GND

I

Ground for regulators 2

L12

-

Supply for GPIOLV pins

A13

2.5

-

General purpose input/output 0

General purpose input/output 1

General purpose input/output 2

General purpose input/output 3

PWM output 1

E11

I/O

O

B11

D11

C11

A12

PWM output 2

C10

PWM2

O

GPIO ground

B12

GNDGPIO

GND

Control Logic

1. Coin cell supply input

A11

LICELL

I/O

3.6

1

2. Coin cell charger output

32.768 kHz Oscillator crystal connection 1

32.768 kHz Oscillator crystal connection 2

Ground for the RTC block

M15

L15

K14

H11

H13

H10

E1

XTAL1

XTAL2

I

2.5

-

1

I

GND

I

GNDRTC

Supply voltage for 32 k buffer

CLK32KVCC

CLK32K

3.6

32 kHz Clock output for peripherals

32 kHz Clock output for processor

Reset output for peripherals

O

CLK32KMCU

RESETB

O

Reset output for processor

F5

RESETBMCU

O

MC34708

Analog Integrated Circuit Device Data

11

Freescale Semiconductor

Pin Connections

Table 3. MC34708 Pin Definitions (continued)

Pin Number

Pin Name

Rating

# Balls

Definition

Function

Watchdog input

L4

WDI

STANDBY

INT

I

3.6

-

1

Standby input signal from processor

Interrupt to processor

J5

I

E4

O

Power on/off button connection 1

Power on/off button connection 2

Global Reset

G8

PWRON1

PWRON2

GLBRST

PUMS1

PUMS2

PUMS3

PUMS4

PUMS5

ICTEST

GNDCTRL

SPIVCC

CS

I

E3

I

G7

I

Power up mode supply setting 1

Power up mode supply setting 2

Power up mode supply setting 3

Power up mode supply setting 4

Power up mode supply setting 5

Normal mode, test mode selection

Ground for control logic

C12

I

B14

I

B13

I

A14

I

D12

I

D10

I

E2

GND

Supply for SPI bus

F4

I

3.6

-

Primary SPI select input

G2

I

Primary SPI clock input

G1

CLK

I

Primary SPI write input

F3

MOSI

Primary SPI read output

F1

MISO

O

Ground for SPI interface

F2

GNDSPI

GND

USB

USB OTG transceiver cable ID

USB Ground

H3

UID

GNDUSB

DP

I/O

GND

I/O

O

5.5

-

1

L3

USB Data +

K1

-1.3-5.5

5.5

USB Data –

J1

DM

Processor D+

Processor D-

L1

DPLUS

DMINUS

RXD

M1

5.5

UART Receive

UART Transmit

Mic output

G4

5.5

G5

TXD

I/O

O

5.5

H7

MIC

5.5

Speaker right

Speaker left

J2

SPKR

SPKL

VBUS

VUSB

VINUSB

I

-1.3-5.5

20

K2

I

USB transceiver cable interface VBUS & OTG supply output

USB transceiver regulator output

H1

I/O

O

H2

3.6

Input option for UVUSB; tie to SWBST at top level.

G3

I

5.5

A to D Converter

ADC generic input channel 9

ADC generic input channel 10,

K7

K6

ADIN9

I

4.8

1

ADIN10

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

Pin Connections

Table 3. MC34708 Pin Definitions (continued)

Pin Number

Pin Name

Rating

# Balls

Definition

ADC generic input channel 11

Function

L6

K4

L5

J7

J6

P1

ADIN11

O

I/O

-

4.8

1

Touch Screen Interface X1 or ADC generic input channel 12

Touch Screen Interface X2 or ADC generic input channel 13

Touch Screen Interface Y1 or ADC generic input channel 14

Touch Screen Interface Y2 or ADC generic input channel 15

Touch Screen Reference

TSX1/ADIN12

TSX2/ADIN13

TSY1/ADIN14

TSY2/ADIN15

TSREF

N2

N3

N4

P3

P4

Ground for A to D circuitry

GNDADC

GND

-

5

1

Thermal Grounds

Substrate ground connection for reference circuitry

H5

SUBSREF

E9

F8

F9

L7

G9

H6

H8

H9

J8

Substrate ground connection for power devices SW1, SW4, SW5,

and for analog circuitry of SW2, SW3, SWBST, and charger

SUBSPWR1

GND

-

12

J9

K8

K9

K15

N13

SUBSLDO

GND

Substrate ground connection for all LDOs

-

1

Substrate ground connection for analog circuitry of SW1, SW4,

SW5

SUBSANA1

Substrate ground connection for analog circuitry of SW2, SW3,

SWBST

B15

C3

SUBSANA2

SUBSANA3

GND

-

1

Substrate ground connection for analog circuitry of charger

MC34708

Analog Integrated Circuit Device Data

13

Freescale Semiconductor

General Product Characteristics

5

General Product Characteristics

5.1

Maximum Ratings

Table 4. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Description (Rating)

Min.

Max.

Unit

Notes

ELECTRICAL RATINGS

Charger Input Voltage Sense Pins

-

V

V_BUSSENSE

V_AUXSENSE

/

20

• VBUS, VAUX

Charger Input Voltage

• VBUSVIN, AUXVIN

V_BUSVIN

/

7.5

V_AUXVIN

-

ICTEST Pin Voltage

Battery Voltage

BP Voltage

V

V_ICTEST

V_BATT

V_BP

1.8

4.4

4.5

3.6

Coin cell Voltage

V_LICELL

V_ESD

ESD Ratings

(2)

(3)

-

• Human Body Model All pins

2000

500

• Charge Device Model All pins

• Air Gap Discharge Model for UID, VBUS, DP and DM pins

• Human Body Model (HBM) for UID, VBUS, DP and DM pins

15000

8000

Notes

2. ESD testing is performed in accordance with the Human Body Model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 ), and the Charge Device

Model (CDM), Robotic (C_ZAP= 4.0 pF).

3. Need external ESD protection diode array to meet IEC1000-4-2 15000 V Air Gap discharge requirement. (CZAP= 150 pF,

RZAP=330 ohm).

5.2

Thermal Characteristics

Table 5. Thermal Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Description (Rating)

Min.

Max.

Unit

Notes

THERMAL RATINGS

Ambient Operating Temperature Range

Operating Junction Temperature Range

-

°C

T_A

T_J

-40 to 85

-40 to 125

-65 to 150

Note 4

Storage Temperature Range

°C

T_ST

(4), (5)

Peak Package Reflow Temperature During Reflow

T_PPRT

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

General Product Characteristics

Table 5. Thermal Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Description (Rating)

Min.

Max.

Unit

Notes

8.0 X 8.0 MM, THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS

(6), (7)

(6), (8)

Junction to Ambient Natural Convection

• Single layer board (1s)

-

93

53

80

49

R_θJA

°C/W

-

Junction to Ambient Natural Convection

• Four layer board (2s2p)

R_θJMA

-

Junction to Ambient (@200 ft/min.)

• Single layer board (1s)

Junction to Ambient (@200 ft/min.)

• Four layer board (2s2p)

-

(9)

Junction to Board

Junction to Case

34

25

R_θJB

R_θJC

θJT

°C/W

(10)

(11)

Junction to Package Top

• Natural Convection

3.0

13 X 13 MM, THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS

-

(6), (7)

Junction to Ambient Natural Convection

• Single layer board (1s)

57

36

48

32

°C/W

R_θJA

(6), (7),

(8)

Junction to Ambient Natural Convection

• Four layer board (2s2p)

R_θJMA

(6), (8)

Junction to Ambient (@200 ft/min.)

• Single layer board (1s)

Junction to Ambient (@200 ft/min.)

• Four layer board (2s2p)

-

(9)

Junction to Board

Junction to Case

22

15

°C/W

R_θJB

R_θJC

θJT

(10)

(11)

Junction to Package Top

• Natural Convection

3.0

Notes

4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause a malfunction or permanent damage to the device.

5. Freescale's Package Reflow capability meets the Pb-free requirements for JEDEC standard J-STD-020C, for Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL).

6. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

7. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

8. Per JEDEC JESD51-6 with the board horizontal.

9. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top

surface of the board near the package.

10. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

11. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per

JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

MC34708

Analog Integrated Circuit Device Data

15

Freescale Semiconductor

General Product Characteristics

5.2.1

Power Dissipation

During operation, the temperature of the die should not exceed the maximum junction temperature. To optimize the thermal

management scheme and avoid overheating, the MC34708 PMIC provides a thermal management system. The thermal

protection is based on a circuit with a voltage output that is proportional to the absolute temperature. This voltage can be read

out via the ADC for specific temperature readouts, see Serial Interfaces.

This voltage is monitored by an integrated comparator. Interrupts THERM110, THERM120, THERM125 and THERM130 will be

generated when respectively crossing in either direction the thresholds specified in Table 6. The temperature range can be

determined by reading the THERMxxxS bits.

Thermal protection is integrated to power off the MC34708 PMIC and disables the charger circuitry in case of over dissipation.

This thermal protection will act above the maximum junction temperature to avoid any unwanted power downs. The protection is

debounced for 8.0 ms in order to suppress any (thermal) noise. This protection should be considered as a fail-safe mechanism

and therefore the application design should be dimensioned such that this protection is not tripped under normal conditions. The

temperature thresholds and the sense bit assignment are listed in Table 6.

Table 6. Thermal Protection Thresholds

Parameter

Thermal 110 °C threshold (THERM110)

Min

Typ

Max

Units

Notes

105

115

120

125

2.0

110

120

125

130

-

115

125

130

135

4.0

°C

Thermal 120 °C threshold (THERM120)

Thermal 125 °C threshold (THERM125)

Thermal 130 °C threshold (THERM130)

Thermal warning hysteresis

(12)

Thermal protection threshold

130

140

150

Notes

12. Equivalent to approx. 30 mW min, 60 mW max

5.3

Electrical Characteristics

General PMIC Specifications

5.3.1

Table 7. General Electrical Characteristic

Internal

Pin Name

Max ⁽²⁰⁾

Parameter

Load Condition

Min

Unit

Notes

Termination ⁽¹⁷⁾

(14)

(19)

Input Low

Input High

47 kOhm

1.0 MOhm

-

0.0

0.3

VCOREDIG

0.3

V

PWRON1, PWRON2,

GLBRST

Pull-up

1.0

Input Low

0.0

STANDBY, WDI

CLK32K

Weak Pull-down

CMOS

Input High

Output Low

Output High

Output Low

Output High

Output Low

-

0.9

3.6

-100 A

100 A

-100 A

100 A

-2.0 mA

0.0

0.2

CLK32KVCC - 0.2

CLK32KVCC

0.0

0.2

VSRTC

0.4

CLK32KMCU

CMOS

VSRTC - 0.2

(18)

RESETB,

Open Drain

0.0

-

RESETBMCU,

SDWNB, SW1PWGD,

SW2PWGD

3.6

Output High

Open Drain

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

General Product Characteristics

Table 7. General Electrical Characteristic

Internal

Pin Name

Max ⁽²⁰⁾

Parameter

Load Condition

Min

Unit

Notes

Termination ⁽¹⁷⁾

Off /Coin cell mode

-

1.15

1.28

1.25

V

PUMS[4 :0] =

(0110, 0111, 1000,

1001)

1.2 V setting

VSRTC

Voltage Output

PUMS[4 :0] =

(0110, 0111, 1000,

1001)

1.3 V setting

1.25

1.35

V

Input Low

-

0.0

0.3 * GPIOVDD

GPIOVDD + 0.3

0.2

V

Input High

Output Low

Output High

Output Low

Output High

Output Low

Output High

Input Low

-

0.7 * GPIOVDD

CMOS

-

0.0

GPIOLV1,2,3,4

-

GPIOVDD - 0.2

GPIOVDD

0.4

-2.0 mA

0

Open Drain

CMOS

Open Drain

-

GPIOVDD + 0.3

0.2

-

0.0

PWM1, PWM2

CLK, MOSI

CS

-

GPIOVDD - 0.2

GPIOVDD

0.3 * SPIVCC

SPIVCC + 0.3

0.4

(13)

-

0.0

Input High

Input Low

-

0.7 * SPIVCC

-

0.0

Weak Pull-down

Input High

Input Low

-

1.1

SPIVCC + 0.3

0.3 * VCOREDIG

VCOREDIG

0.2

(13) (21)

-

0.0

0.7 * VCOREDIG

0.0

,

Weak Pull-down

on CS

CS, MOSI (at Booting

for SPI / I²C decoding)

(13) (21)

Input High

-

,

-100 A

MISO

Output Low

Output High

(13) (22)

MISO, INT

CMOS

100 A

SPIVCC - 0.2

SPIVCC

0.3

V

MISO

(13) (22)

(15)

Input Low

PUMSxS = 0

-

0.0

1.0

PUMS1,2,3,4,5

Input High

VCOREDIG

PUMSxS = 1

(16)

Input Low

Input High

Input Low

Input Mid

Input High

Input Low

Input Float

Input High

-

0.0

1.1

0.0

1.3

2.5

0.0

Open

1.3

-

0.3

1.7

V

ICTEST

0.3

SW1CFG, SW4CFG

2.0

3.1

0.3

PRETMR, ITRICKLE

ADIN8,9,10

Open

2.0

Input must not

exceed

BP

MC34708

Analog Integrated Circuit Device Data

17

Freescale Semiconductor

General Product Characteristics

Table 7. General Electrical Characteristic

Internal

Pin Name

Max ⁽²⁰⁾

Parameter

Load Condition

Min

Unit

Notes

Termination ⁽¹⁷⁾

TSX1,TSX2, TSY1,

TSY2

Input must not

exceed

-

BP or VCORE

V

Notes

13. SPIVCC is typically connected to the output of buck regulator SW5 and set to 1.800 V

14. Input has internal pull-up to VCOREDIG equivalent to 200 kOhm

15. Input state is latched in first phase of cold start, refer to Serial Interfaces for a description of the PUMS configuration

16. Input state is not latched

17. A weak pull-down represents a nominal internal pull-down of 100 nA unless otherwise noted

18. RESETB, RESETBMCU, SDWNB, SW1PWGD, SW2PWGD have open drain outputs, external pull-ups are required

19. SPIVCC needs to remain enabled for proper detection of WDI High to avoid involuntary shutdown

20. The maximum should never exceed the maximum rating of the pin as given in Pin Connections

21. The weak pull-down on CS is disabled if a VIH is detected at startup to avoid extra consumption in I²C mode

22. The output drive strength is programmable

5.3.2

Current Consumption

The current consumption of the individual blocks is described in detail throughout this specification. For convenience, a summary

table follows for standard use cases.

Table 8. Current Consumption Summary ⁽²⁵⁾

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Mode

Description

Typ

Max

Unit

Notes

All blocks disabled, no main battery attached, coin cell is attached to LICELL 

(at 25°C only)

4.0

8.0

A

• RTC Logic

RTC / Power

cut

• VCORE Module

• VSRTC

• 32 k Oscillator

• Clk32KMCU buffer active(10 pF load)

All blocks disabled, main battery attached * Core and RTC module

20

55

A

• Digital Core

• RTC Logic

OFF (good

battery)

• VSRTC

• 32 k Oscillator

• CLK32KMCU buffer active (10 pF load)

• Charger (detect)

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

General Product Characteristics

Table 8. Current Consumption Summary ⁽²⁵⁾

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Low Power Mode (Standby pin asserted and ON_STBY_LP=1)

260

424

A

• Digital Core

• RTC Logic

• VCORE Module

• VSRTC

• CLK32KMCU/CLK32K active (10 pF load)

• 32 k Oscillator

• I_REF

ON Standby

• SW1, SW2, SW3, SW4A, SW4B, SW5 in PFM ^(24),(28)

• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC

in low power mode ^(23),(26)

• Charger

• Mini-USB

Digital Core

370

561

A

• RTC Logic

• VCORE module

• VSRTC

• CLK32KMCU/CLK32K active (10pF load)

• 32 k Oscillator

• Digital

ON Standby

• I_REF

• SW1, SW2, SW3 SW4A, SW4B, SW5 in PFM ^(24),(28)

• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on 

in low power mode ^(24),(26)

• Charger

• Mini-USB

• PLL (for mini USB)

Typical use case

1600

3000

A

• Digital Core

• RTC Logic

• VCORE Module

• VSRTC CLK32KMCU/CLK32K active (10pf)

• 32 k Oscillator

• I_REF

ON

• SW1, SW2, SW3 SW4A, SW4B, SW5 in Apskip SWBST ^{(24),(27),(28)}

• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on 

in low power mode ^(23),(26)

• Digital

• PLL

• Charger

• Mini-USB

Notes

23. Equivalent to approx. 30 mW min, 60 mW max

24. Current in RTC Mode is from LICELL=2.5 V; in all other modes from BP = 3.6 V.

25. External loads are not included (1)

26. VUSB2, VGEN2 external pass PNPs

27. SWBST in auto mode

28. SW4A output 2.5 V

MC34708

Analog Integrated Circuit Device Data

19

Freescale Semiconductor

General Description

6

General Description

The MC34708 is the PMIC designed specifically for use with the Freescale i.MX50 and i.MX53 families. As the companion PMIC

on several i.MX reference designs, it is a proven solution, which enables a faster time to market with fewer resources.

6.1

Features

Battery Management

• Buck Switching Charger for Single Cell Li-Ion Batteries

• Wall/USB Charger Input

• Coulomb Counter for Main Battery Charge Monitoring

• OV/UV Protection And Short-circuit Detection

• Dual LED Driver for Charge/Fault Indication

• Coin Cell Charger

Power Generation

• Six Buck Switching Regulators

• Two Single/Dual Phase Buck Regulators

• Four Single Phase Buck Regulators

• PFM/Auto Pulse Skip/PWM Operation Mode

• Dynamic Voltage Scaling

• 5V Boost Regulator

• USB On-the-go Support

• Eight LDO Regulators

• Two with Selectable Internal or External Pass Devices

• Five with Embedded Pass Devices

• One with an External PNP Device

Analog to Digital Converter

• Seven General Purpose Channels

• Eight Dedicated Channels for Monitoring the Charger

• Resistive Touchscreen Interface

Auxiliary Circuits

• Mini/Micro USB Switch

• Bidirectional Audio/Data/UART

• Accessory Identification Circuit

• General Purpose I/Os

• PWM Outputs

Clocking and Oscillators

• Real Time clock

• Time and day Counters

• Time of day Alarm

• 32.768 kHz Crystal Oscillator

• Coin Cell Battery Backup

Serial Interface

• SPI

• I²C

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

General Description

6.2

Block Diagram

6 BUCK

REGULATORS

Processor Core

Split Power Domains

DDR Memory

I/O

5V BOOST

REGULATOR

USB On The Go

Supply

MINI/MICRO USB

INTERFACE

USB/UART/Audio

Auto Accessory Detect

8 LDO REGULATORS

Peripherals

10 BIT ADC CORE

General Purpose

Resistive Touch

Screen Interface

GENERAL PURPOSE

I/O & PWM OUTPUTS

MC34708

32.768 kHz CRYSTAL

OSCILLATOR

POWER CONTROL

LOGIC

Real Time Clock

SRTC Support

State Machine

BATTERY MANAGEMENT

Single Cell Li-Ion Charger

Wall/USB Charger Input

OV/UV & Short Circuit Protection

Coin Cell Charger

BIAS &

REFERENCES

Trimmed Bandgap

CONTROL

INTERFACE

SPI/I²C

Coulomb Counter

LED Charging/Fault Indicator

Figure 4. MC34708 - Functional Block Diagram

6.3

Functional Description

The MC34708 Power Management Integrated Circuit (PMIC) represents a complete system power solution in a single package.

Designed specifically for use with the Freescale i.MX50/53 families. The MC34708 integrates six multi-mode buck regulators and

eight LDO regulators for direct supply of the processor core, memory and peripherals.

The integrated switching charger supports single cell applications with up to 1.55A of charge current, enabling faster charging.

The dual path design enables power on with a dead or no battery. An integrated coulomb counter measures the state of charge

of the battery.

The USB switch enables the use of a single, mini or micro USB connector for USB, UART and audio connections, switching the

relevant signals to the connector depending on the type of device connected. With support for the Universal Charging Standard,

the charge current is varied automatically depending on the capability of the source. In addition, the MC34708 also integrates a

real time clock, coin cell charger, a 16- channel 10-bit ADC, 5V USB Boost regulator, two PWM outputs, touch-screen interface,

status LED drivers and four GPIOs.

MC34708

Analog Integrated Circuit Device Data

21

Freescale Semiconductor

Functional Block Description

7

Functional Block Description

7.1

Startup Requirements

At power up, switching and linear regulators are sequentially enabled in time slots of 2.0 ms steps, to limit the inrush current after

an initial delay of 8.0 ms, in which the core circuitry gets enabled. To ensure a proper power up sequence, the outputs of the

switching regulators that are not enabled are discharged at the beginning of the Cold start with weak pull downs on the output.

For that same reason, a 8.0 ms delay allows the outputs of the linear regulators to be fully discharged as well, through the built

in discharge path. The peak inrush current per event is limited. Any under-voltage detection at BP is masked while the power up

sequencer is running. When the switching regulator is enabled it will start in PWM mode and for 3.0 ms and then it will switch

over to the mode that it is programmed to in the SPI.

The Power Up Mode Select pins PUMSx (x = 1,2,3,4,5) are used to configure the startup characteristics of the regulators. Supply

enabling and output level options are selected by hardwiring the PUMSx pins for the desired configuration. The recommended

power up strategy for end products is to bring up as little of the system as possible at booting, essentially sequestering just the

bare essentials to allow processor startup and software to run. With such a strategy, the startup transients are controlled at lower

levels, and the rest of the system power tree can be brought up by software. This allows optimization of supply ordering, where

specific sequences may be required, as well as supply default values. Software code can load up all of the required

programmable options, to avoid sneak paths, under/over-voltage issues, startup surges, etc, without any change in hardware.

The state of the PUMSx pins are latched in before any of the switching or linear regulators are enabled, with the exception of

VCORE. PUMSx options and startup configurations will be robust to a PCUT event, whether occurring during normal operation

or during the 8.0 ms of pre-sequencer initialization, i.e., the system will not end up in an unexpected / undesirable consumption

state.

Table 9 shows the initial setup for the voltage level of the switching and linear regulators, and whether they get enabled.

Table 9. Power Up Defaults

53

LPM

53

DDR2

53

DDR3

53

LVDDR3

53

LVDDR2

i.MX

Reserved

50

PUMS[4:1]

0000-0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

PUMS5=0

VUSB2

VGEN2

Ext PNP Ext PNP Ext PNP

Ext PNP

Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP

Reserved

PUMS5=1

VUSB2

VGEN2

Internal

PMOS

Internal

PMOS

Internal

PMOS

SW1A

(VDDGP)

Reserved

1.1

1.3

1.8

1.1

1.3

1.2

1.5

1.1

1.3

1.2

1.1

1.2

1.8

1.1

1.2

1.1

1.2

3.15

1.2

1.1

1.2

3.15

1.8

SW1B

(VDDGP)

(29)

SW2

1.225

1.2

1.3

1.2

(VCC)

(29)

SW3

1.2

(VDDA)

(29)

SW4A

1.5

1.35

3.15

1.2

3.15

1.8

(DDR/SYS)

(29)

SW4B

1.5

(DDR/SYS)

(29)

SW5

Reserved

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

1.8

Off

(I/O)

SWBST

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

Functional Block Description

Table 9. Power Up Defaults

53

LPM

53

DDR2

53

DDR3

53

LVDDR3

53

LVDDR2

i.MX

Reserved

50

(30)

VUSB

VUSB2

VSRTC

VPLL

Reserved

3.3

2.5

3.3

2.5

3.3

2.5

3.3

2.5

3.3

2.5

3.3

2.5

1.2

1.8

On

2.5

1.2

3.1

3.3

2.5

1.2

1.8

On

2.5

1.2

3.1

3.3

2.5

1.2

1.8

On

2.5

1.2

3.1

3.3

2.5

1.2

1.8

On

2.5

1.2

3.1

3.3

2.5

1.2

1.8

On

2.5

1.2

2.5

3.3

2.5

1.2

1.8

On

2.5

1.2

2.5

1.2

1.3

1.8

VREFDDR

VDAC

On

2.775

1.2

2.775

1.3

2.775

1.3

2.775

1.3

2.775

1.3

VGEN1

VGEN2

Notes

2.5

29. The SWx node are activated in APSKIP mode when enabled by the startup sequencer.

30. VUSB regulator is only enabled if 5.0 V is present on VBUS. By default VUSB will be supplied by VBUS. SWBST = 5.0 V powers up as

does VUSB, regardless of 5.0 V present on UVBUS. By default VUSB is supplied by SWBST.

The power up sequence is shown in Tables 10 and 11. VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer

startup.

Table 10. Power Up Sequence i.MX53

Tap x 2.0 ms

PUMS [4:1] = [0101,0110,0111,1000,1001] (i.MX53)

0

1

2

3

4

5

6

7

8

9

SW2 (VCC)

VPLL (NVCC_CKIH = 1.8 V)

VGEN2 (VDD_REG= 2.5 V, external PNP

SW3 (VDDA)

SW1A/B (VDDGP)

SW4A/B, VREFDDR (DDR/SYS)

SW5 (I/O), VGEN1

VUSB ⁽³¹⁾, VUSB2

VDAC

Notes:

31. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By

default VUSB will be supplied by the VBUS pin.

Table 11. Power Up Sequence i.MX50

Tap x 2.0 ms PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] (i.MX50/I.MX53)

0

1

2

3

4

5

SW2

SW3

SW1A/B

VDAC

SW4A/B, VREFDDR

SW5

MC34708

Analog Integrated Circuit Device Data

23

Freescale Semiconductor

Functional Block Description

Table 11. Power Up Sequence i.MX50

6

7

8

9

VGEN2, VUSB2

VPLL

VGEN1

VUSB ⁽³²⁾

Notes:

32. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By

default VUSB will be supplied by the VBUS pin.

7.2

Bias and References Block Description and Application

Information

All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. The

bandgap and the rest of the core circuitry is supplied from VCORE. The performance of the regulators is directly dependent on

the performance of VCOREDIG and the bandgap. No external DC loading is allowed on VCOREDIG or REFCORE. VCOREDIG

is kept powered as long as there is a valid supply and/or coin cell. Table 12 shows the main characteristics of the core circuitry.

Table 12. Core Voltages Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

VCOREDIG (DIGITAL CORE SUPPLY)

Output voltage

V_COREDIG

V

(33)

• ON mode and OFF with good battery mode, and charging

• RTC mode

-

1.5

0.0

-

V_COREDIGbypass capacitor

C_COREDIG

-

1.0

-

F

VDDLP (DIGITAL CORE SUPPLY - LOWER POWER)

Output voltage

• ON mode with good battery

V_DDLP

V

(34)

-

1.5

1.2

-

• OFF mode with good battery

• RTC mode

(35)

V_DDLPbypass capacitor

C_DDLP

-

100

-

pF

VCORE (ANALOG CORE SUPPLY)

Output voltage

• ON mode and charging

V_CORE

V

(33)

-

2.775

0.0

-

• OFF and RTC mode

V_COREbypass capacitor

C_CORE

-

1.0

-

F

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

24

Functional Block Description

Table 12. Core Voltages Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

VREFCORE (BANDGAP / REGULATOR REFERENCE)

(33)

Output voltage

V_REFCORE

-

1.2

0.5

-

V

Absolute Accuracy

Temperature Drift

%

0.25

100

V_REFCOREbypass capacitor

C_REFCORE

Notes

nF

33. 3.0 V < BP < 4.5 V, no external loading on VCOREDIG, VDDLP, VCORE, or REFCORE. Extended operation down to UVDET, but no

system malfunction.

34. Powered by VCOREDIG

35. Maximum capacitance on V_DDLPshould not exceed 1000 pF, including the board capacitance.

7.3

Clocking and Oscillators

Clock Generation

7.3.1

A system clock is generated for internal digital circuitry as well as for external applications utilizing the clock output pins. A crystal

oscillator is used for the 32.768 kHz time base and generation of related derivative clocks. If the crystal oscillator is not running

(for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead.

Support is also provided for an external Secure Real Time Clock (SRTC) which may be integrated on a companion system

processor IC. For media protection in compliance with Digital Rights Management (DRM) system requirements, the

CLK32KMCU can be provided as a reference to the SRTC module where tamper protection is implemented.

7.3.1.1

Clocking Scheme

The internal 32 kHz oscillator is an integrated backup for the crystal oscillator, and provides a 32.768 kHz nominal frequency at

60% accuracy, if running. The internal oscillator only runs if a valid supply is available at BP, and would not be used as long as

the crystal oscillator is active. In absence of a valid supply at the BP supply node (for instance due to a dead battery), the crystal

oscillator continues running supplied from the coin cell battery. All control functions will run off the crystal derived frequency,

occasionally referred to as “32 kHz” for brevity’s sake.

During the switch-over between the two clock sources (such as when the crystal oscillator is starting up), the output clock is

maintained at a stable active low or high phase of the internal 32 kHz clock to avoid any clocking glitches. If the XLTAL clock

source suddenly disappears during operation, the IC will revert back to the internal clock source. Given the unpredictable nature

of the event and the startup times involved, the clock may be absent long enough for the application to shut down during this

transition due to for instance a sag in the regulator output voltage or absence of a signal on the clock output pins.

A status bit, CLKS, is available to indicate to the processor which clock is currently selected: CLKS=0 when the internal RC is

used and CLKS=1 if the crystal source is used. The CLKI interrupt bit will be set whenever a change in the clock source occurs,

and an interrupt will be generated if the corresponding CLKM mask bit is cleared.

7.3.1.2

Oscillator Specifications

The crystal oscillator has been optimized for use in conjunction with the Micro Crystal CC7V-T1A32.768 kHz-9.0 pF-30 ppm or

equivalent (such as Micro Crystal CC5V-T1A or Epson FC135) and is capable of handling its parametric variations.

The electrical characteristics of the 32 kHz Crystal oscillator are given in the following table, taking into account the crystal

characteristics noted above. The oscillator accuracy depends largely on the temperature characteristics of the used crystal.

Application circuits can be optimized for required accuracy by adapting the external crystal oscillator network (via component

accuracy and/or tuning). Additionally, a clock calibration system is provided to adjust the 32,768 cycle counter that generates the

1.0 Hz timer and RTC registers; see SRTC Support for more detail.

MC34708

Analog Integrated Circuit Device Data

25

Freescale Semiconductor

Functional Block Description

Table 13. Oscillator and Clock Main Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

OSCILLATOR AND CLOCK OUTPUT

Operating Voltage

V_INRTC

V

• Oscillator and RTC Block from BP

1.8

-

4.5

3.6

• Oscillator and RTC Block from LICELL

Operating Current Crystal Oscillator and RTC Module

I_INRTC

A

• All blocks disabled, no main battery attached, coin cell is attached

to LICELL

-

2.0

5.0

RTC oscillator startup time

• Upon application of power

t_START-RTC

sec

V

-

1.0

0.2

Output Low

V_RTCLO

• CLK32K Output sink 100 A

• CLK32KMCU Output source 50 A

0.0

Output High

V_RTCHI

V

• CLK32K Output source 100 A

• CLK32KMCU Output sink 50 A

CLK32K

VCC -0.2

VSRTC-0.2

-

CLK32K

VCC

VSRTC

t_CLK32KETCLK32K Rise and Fall Time, CL = 50 pF

• CLK32KDRV [1:0] = 00

ns

-

6.0

2.5

3.0

2.0

-

• CLK32KDRV [1:0] = 01 (default)

• CLK32KDRV [1:0] = 10

• CLK32KDRV [1:0] = 11

CLK32KMCU Rise and Fall Time

• CL = 12 pF

t_CKL32K

ns

%

MCUET

-

22

-

CLK32K_DC/

CLK32K

MCU_DC

CLK32K and CLK32KMCU Output Duty Cycle

• Crystal on XTAL1, XTAL2 pins

45

55

RMS Output Jitter

ns

RMS

• 1 Sigma for Gaussian distribution

-

30

7.3.2

SRTC Support

When configured for DRM mode (SPI bit DRM = 1), the CLK32KMCU driver will be kept enabled through all operational states

to ensure that the SRTC module always has its reference clock. If DRM = 0, the CLK32KMCU driver will not be maintained in the

Off state.

It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system if it has been programmed

for such capability. This can be accomplished by connecting an open drain NMOS driver to the PWRON pin of the MC34708

PMIC, so that it is in effect, a parallel path for the power key. The MC34708 PMIC will not be able to discern the turn on event

from a normal power key initiated turn on, but the processor should have the knowledge, since the RTC initiated turn on is

generated locally.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

26

Functional Block Description

Open Drain output for RTC wake-up

34708

32 kHz

SPIVCC=1.8 V

GP Domain=1.1 V

LP Dominant=1.2 V

Processor

Core Supply

SOG Supply

I/O

VCOREDIG

PWRONx

V

COREDIG

On

Detect

SRTC

HP-RC

Best of

Supply

On/Off

Button

VSRTC=1.2 V

V

&

SRTC

32 kHz for

DSM timing

Detect

LP-RTC

CKIL: VSRTC

CLK32KMCU

+

-

Main

Battery

Coin Cell

Battery

+

-

0.1 F

Figure 5. SRTC Block Diagram

7.3.2.1

VSRTC

The VSRTC regulator provides the CLK32KMCU output level. Additionally, it is used to bias the Low Power SRTC domain of the

SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected.

The VSRTC cannot be disabled.

Depending on the configuration of the PUMS[4:0] pins, the VSRTC voltage will be set to 1.3 or 1.2 V. With PUMS[4:0] = (0110,

0111, 1000, or 1001) VSRTC will be set to 1.3 V in on mode (on, on standby and on standby low power modes). In off and coin

cell modes the VSRTC voltage will drop to 1.2 V with the PUMS[4:0] = (0110, 0111, 1000, or 1001). With PUMS[4:0] = (0110,

0111, 1000, or 1001), VSRTC will be set to 1.2 V for all modes (on, on standby, on standby low power mode, off, and coincell).

Table 14. VSRTC Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

GENERAL

V_SRTCIN

Characteristic

Min

Typ

Max

Unit Notes

Operating Input Voltage Range V_INMINto V_INMAX

• Valid Coin Cell range

V

1.8

-

3.6

4.5

• Valid BP

Operating Current Load Range IL_MINto IL_MAX

Bypass Capacitor Value

I_SRTC

0.0

-

50

-

A

F

CO_SRTC

0.1

VSRTC - ACTIVE MODE - DC

Output Voltage V_OUT

• V_INMIN< V_IN< V_INMAX

• IL_MIN< IL < IL_MAX

V_SRTC

V

1.15

1.20

1.28

• Off and coincell mode

MC34708

Analog Integrated Circuit Device Data

27

Freescale Semiconductor

Functional Block Description

Table 14. VSRTC Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

Output Voltage V_OUT

• V_INMIN< V_IN< V_INMAX

• I_LMIN< I_L< I_LMAX

V_SRTC

V

1.15

1.2

1.25

• PUMS[4:0] = (0110, 0111, 1000, 1001)

• On mode (On, Standby, Standby LPM)

Output Voltage V_OUT

• VINMIN < V_IN< V_INMAX

• I_LMIN< I_L< I_LMAX

V_SRTC

V

1.25

1.3

0.8

1.35

• PUMS[4:0] = (0110, 0111, 1000, 1001)

• On mode (On, Standby, Standby LPM)

Active Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_SRTCQ

A

-

7.3.2.2

Real Time Clock

A Real Time Clock (RTC) is provided with time and day counters as well as an alarm function. The RTC utilizes the 32.768 kHz

crystal oscillator for the time base and is powered by the coin cell backup supply when BP has dropped below operational range.

In configurations where the SRTC is used, the RTC can be disabled to conserve current drain by setting the RTCDIS bit to a 1

(defaults on at power up).

Time and Day Counters

The 32.768 kHz clock is divided down to a 1.0 Hz time tick which drives a 17 bit Time Of Day (TOD) counter. The TOD counter

counts the seconds during a 24 hour period from 0 to 86,399 and will then roll over to 0. When the roll over occurs, it increments

the 15 bit DAY counter. The DAY counter can count up to 32767 days. The 1.0 Hz time tick can be used to generate a 1HZI

interrupt if unmasked.

Time Of Day Alarm

A Time Of Day Alarm (TODA) function can be used to turn on the application and alert the processor. If the application is already

on, the processor will be interrupted. The TODA and DAYA registers are used to set the alarm time. When the TOD counter is

equal to the value in TODA and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated.

Timer Reset

As long as the supply at BP is valid, the real time clock will be supplied from VCOREDIG. If BP is not valid, the real time clock

can be backed up from a coin cell via the LICELL pin. When the VSRTC voltage drops to the range of 0.9 - 0.8 V, the RTCPORB

reset signal is generated and the contents of the RTC will be reset. Additional registers backed up by coin cell will also reset with

RTCPORB. To inform the processor that the contents of the RTC are no longer valid due to the reset, a timer reset interrupt

function is implemented with the RTCRSTI bit.

RTC Timer Calibration

A clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 Hz timer for RTC timing registers.

The general implementation relies on the system processor to measure the 32.768 kHz crystal oscillator against a higher

frequency and more accurate system clock such as a TCXO. If the RTC timer needs a correction, a 5 bit 2’s complement

calibration word can be sent via the SPI to compensate the RTC for inaccuracy in its reference oscillator.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

28

Functional Block Description

Table 15. RTC calibration Settings

Code in RTCCAL[4:0]

Correction in Counts per 32768 Relative correction in ppm

01111

00011

00001

00000

11111

11101

10001

10000

+15

+3

+1

0

+458

+92

+31

0

-1

-31

-3

-92

-15

-16

-458

-488

The available correction range should be sufficient to ensure drift accuracy in compliance with standards for DRM time keeping.

Note that the 32.768 kHz oscillator is not affected by RTCCAL settings; calibration is only applied to the RTC time base counter.

Therefore, the frequency at the clock output CLK32K is not affected.

The RTC system calibration is enabled by programming the RTCCALMODE[1:0] for desired behavior by operational mode.

Table 16. RTC Calibration Enabling

RTCCALMODE

Function

RTC Calibration disabled (default)

00

01

10

11

RTC Calibration enabled in all modes except coin cell only

Reserved for future use. Do not use.

RTC Calibration enabled in all modes

The RTC Calibration circuitry can be automatically disabled when main battery contact is lost or if it is so deeply discharged that

RTC power draw is switched to the coin cell (configured with RTCCALMODE=01).

Because of the low RTC consumption, RTC accuracy can be maintained through long periods of the application being shut down,

even after the main battery has discharged. However, it is noted that the calibration can only be as good as the RTCCAL data

that has been provided, so occasional refreshing is recommended to ensure that any drift influencing environmental factors have

not skewed the clock beyond desired tolerances.

7.3.3

Coin Cell Battery Backup

The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged,

removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the

LICELL for backup power. This switch over occurs for a BP below 1.8 V threshold with LICELL greater than BP. A small capacitor

should be placed from LICELL to ground under all circumstances.

Upon initial insertion of the coin cell, it is not immediately connected to the on chip circuitry. The cell gets connected when the IC

powers on, or after enabling the coin cell charger when the IC was already on.

The coin cell charger circuit will function as a current-limited voltage source, resulting in the CC/CV taper characteristic typically

used for rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit. The coin cell voltage is

programmable through the VCOIN[2:0] bits. The coin cell charger voltage is programmable in the ON state where the charge

current is fixed at ICOINHI.

If COINCHEN=1 when the system goes into Off or User Off state, the coin cell charger will continue to charge to the predefined

voltage setting but at a lower maximum current ICOINLO. This compensates for self discharge of the coin cell and ensures that

if/when the main cell gets depleted, that the coin cell will be topped off for maximum RTC retention. The coin cell charging will

be stopped for the BP below UVDET. The bit COINCHEN itself is only cleared when an RTCPORB occurs.

MC34708

Analog Integrated Circuit Device Data

29

Freescale Semiconductor

Functional Block Description

Table 17. Coin cell Voltage Specifications

VCOIN[2:0]

Output Voltage

000

001

010

011

100

101

110

111

2.50

2.70

2.80

2.90

3.00

3.10

3.20

3.30

Table 18. Coincell Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

COIN CELL CHARGER

Voltage Accuracy

V_LICELLACC

-

100

60

-

mV

A

Coin Cell Charge Current in On and Watchdog modes ICOINHI

I_LICELLON

Coin Cell Charge Current in Off, cold start/warm start, and Low Power Off

modes (User Off / Memory Hold) ICOINLO

I_LICELLOFF

10

Current Accuracy

I_LICELACC

CO_LICELL

-

30

100

4.7

-

%

nF

F

LICELL Bypass Capacitor

LICELL Bypass Capacitor as coin cell replacement

7.4

Interrupt Management

Control

7.4.1

The system is informed about important events, based on interrupts. Unmasked interrupt events are signaled to the processor

by driving the INT pin high; this is true whether the communication interface is configured for SPI or I²C.

Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each

interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register, which will also cause the interrupt line

to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high.

Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high,

the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor

the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the

device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked

interrupt bit was already high, the interrupt line will go high after unmasking.

The sense registers contain status and input sense bits, so the system processor can poll the current state of interrupt sources.

They are read only, and not latched or clearable.

Interrupts generated by external events are debounced. Therefore, the event needs to be stable throughout the debounce period

before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary table following

later in this section. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

30

Functional Block Description

7.4.2

Interrupt Bit Summary

Table 19 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral descriptions,

refer to the related chapters.

Table 19. Interrupt, Mask and Sense Bits

Debounce

Time

Interrupt

Mask

Sense

Purpose

Trigger

L2H

ADCDONEI

TSDONEI

ADCDONEM

TSDONEM

-

ADC has finished requested conversions

Touch screen has finished conversion

Touch screen pen detect

0

L2H

TSPENDET

TSPENDETM

Dual

1.0 ms

VBUS over-voltage

Programmable

SUP_OVP_DB

USBOVP

AUXOVP

USBOVPM

AUXOVPM

USBOVPS

AUXOVPS

Dual

Sense is 1 if above threshold

Aux charge over-voltage

Programmable

SUP_OVP_DB

Sense is 1 if above threshold

WKVBUSDET

WKAUXDET

WKVBUSDETM

WKAUXDETM

-

Weak VBUS charger detected

Weak AUX charger detected

H2L

0

Programmable

VBUSDB

VBUSREGMI

VBUSREGMIM

VBUS input regulation mode

H2L

CHRTIMEEXP

CHRCMPL

CHRTIMEEXPM

CHRCMPLM

-

Charge timer expired

Charge complete

L2H

0

Programmable

OVPDB

Battery over-voltage

BATTOVP

BATTOTP

BATTOVPM

BATTOTPM

BATTOVPS

Dual

Sense is 1 if above threshold

Off by default

BATTOTPS

Battery temp

Programmable

BATTDETDB

0 = Temp OK

1 = Out of temp

Sense is 1 if out of temp threshold hot and cold

Low battery detect

Programmable

VBATTDB

LOWBATT

USBDET

AUXDET

LOWBATTM

USBDETM

AUXDETM

-

H2L

Dual

Sense is 1 if below LOWBAT threshold

USB VBUS detect

Programmable

VBUSDB

USBDETS

AUXDETS

Sense is 1 if detected

Aux charge detect

Programmable

VAUXDB

Sense is 1 if detected

Stuck_Key_RCV Stuck_Key_RCV_m

-

Stuck key has recovered

Stuck key detected

L2H

Stuck_Key

Stuck_Key_m

ADC result changed

ADC_Change

ADC_Change_m

ADC_STATUS

L2H

Sense is 1 if conversion is completed, 0 if in

progress

Unknown_Atta

LKR

Unknown_Atta_m

LKR_m

-

Unknown accessory detected

Remote control long key is released

Remote control long key is pressed

Remote control key is pressed

Accessory detached

L2H

-

LKP

LKP_m

-

KP

KP_m

-

Detach

Attach

Detach_m

Attach_m

-

Accessory attached

ID_GNDS

ID_FLOATS

Sense is 1 if ID pin is grounded

Sense is 1 if ID pin is floating

MC34708

Analog Integrated Circuit Device Data

31

Freescale Semiconductor

Functional Block Description

Table 19. Interrupt, Mask and Sense Bits

Debounce

Interrupt

Mask

Sense

Purpose

Trigger

Time

ID_DET_ENDS

Sense is 1 if ID resistance detection is complete

VBUS_DET_ENDS Sense is 1 if VBUS PTSI is complete

min. 4.0 ms

max 8.0 ms

SCPI

SCPM

-

Regulator short-circuit protection tripped

Battery removal detect

L2H

BATTDETBS

0 = battery

Programmable

BATTDETDB

BATTDETBI

BATTDETBM

Dual

1 = no battery

1HZI

1HZM

-

1.0 Hz time tick

L2H

H2L

L2H

H2L

L2H

0

TODAI

TODAM

Time of day alarm

0

30 ms ⁽³⁶⁾

Power on button 1 event

PWRON1I

PWRON2I

PWRON1M

PWRON2M

PWRON1S

PWRON2S

Sense is 1 if PWRON1 is high.

30 ms

30 ms ⁽³⁶⁾

Power on button 2 event

Sense is 1 if PWRON2 is high.

30 ms

SYSRSTI

WDIRESETI

PCI

SYSRSTM

WDIRESETM

PCM

-

System reset through PWRONx pins

WDI silent system restart

Power cut event

0

WARMI

WARMM

Warm Start event

MEMHLDI

MEMHLDM

Memory Hold event

32 kHz clock source change

Sense is 1 if source is XTAL

CLKI

CLKM

CLKS

Dual

L2H

Dual

0

RTCRSTI

THERM110

RTCRSTM

THERM110M

-

RTC reset has occurred

0

Thermal 110C threshold

THERM110S

30 ms

Sense is 1 if above threshold

Thermal 120C threshold

THERM120

THERM125

THERM130

THERM120M

THERM125M

THERM130M

GPIOLVxM

THERM120S

THERM125S

THERM130S

GPIOLVxS

Dual

30 ms

Sense is 1 if above threshold

Thermal 125C threshold

30 ms

Sense is 1 if above threshold

Thermal 130C threshold

30 ms

Sense is 1 if above threshold

Programma

ble

GPIOLVxI

Notes

General Purpose input interrupt

Programmable

36. Debounce timing for the falling edge can be extended with PWRONxDBNC[1:0]; refer to Serial Interfaces for details.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

32

Functional Block Description

7.5

Power Generation

The MC34708 PMIC provides reference and supply voltages for the application processor as well as peripheral device.

Five buck (step down) converters and one boost (step up) converters are included. One of the buck regulators can be configured

in multiphase, single phase mode, or operate as separate independent outputs (in this case, there are 6 buck converters). The

buck converters provide the supply to processor cores and to other low voltage circuits such as IO and memory. Dynamic voltage

scaling is provided to allow controlled supply rail adjustments for the processor cores and/or other circuitry. The boost converter

provides power for the VBUS in the OTG mode, as well as the USB PHY on the processor. The VUSB regulator is powered from

the boost to ensure sufficient headroom for the LDO through the normal discharge range of the main battery.

Linear regulators are directly supplied from the battery or from the switching regulator, and include supplies for IO and

peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. Naming conventions are suggestive of typical or possible use

case applications, but the switching and linear regulators may be utilized for other system power requirements within the

guidelines of specified capabilities. Four general purpose I/Os are available, which can be configured as inputs/outputs. As inputs

they can be configured as interrupts.

7.5.1

Power Tree

Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges.

Table 20 summarizes the available power supplies.

Table 20. Power Tree Summary

Supply

Purpose (typical application)

Buck regulator for processor VDDGP domain

Buck regulator for processor VCC domain

Buck regulator for processor VDD domain and peripherals

Buck regulator for DDR memory and peripherals

Buck regulator for I/O domain

Output Voltage (in V)

Load Capability (in mA)

SW1

SW2

0.650 - 1.4375

2000

1000

500

1000

380

0.05

50

SW3

0.650 - 1.425

SW4A

SW4B

SW5

1.200 – 1.85: 2.5/3.15/3.3

1.200 – 1.85

Boost regulator for USB OTG

SWBST

VSRTC

VPLL

5.00/5.05/5.10/5.15

1.2

Secure Real Time Clock supply

Quiet Analog supply

1.2/1.25/1.5/1.8

DDR Ref supply

VREFDDR

VDAC

0.6-0.9

10

TV DAC supply, external PNP

2.5/2.6/2.7/2.775

2.5/2.6/2.75/3.0

250

65

VUSB/peripherals supply, internal PMOS

VUSB/peripherals external PNP

VUSB2

VGEN1

VGEN2

VUSB

2.5/2.6/2.75/3.0

350

250

50

General peripherals supply #1

1.2/1.25/1.3/1.35/1.4/1.45/1.5/1.55

2.5/2.7/2.8/2.9/3.0/3.1/3.15/3.3

3.3

General peripherals supply #2, internal PMOS

General peripherals supply #2, external PNP

USB Transceiver supply

250

100

7.5.2

Modes of Operation

The MC34708 PMIC is fully programmable via the SPI interface and associated register map. Additional communication is

provided by direct logic interfacing, including interrupt, watchdog, and reset. Default startup of the device is selectable by

hardwiring the Power Up Mode Select (PUMS) pins.

MC34708

Analog Integrated Circuit Device Data

33

Freescale Semiconductor

Functional Block Description

Power cycling of the application is driven by the MC34708 PMIC. It has the interfaces for the power buttons and dedicated

signaling interfacing with the processor. It also ensures the supply of the Real Time Clock (RTC), critical internal logic, and other

circuits from the coin cell, in case of brief interruptions from the main battery. A charger for the coin cell is included to ensure that

it is kept topped off until needed.

The MC34708 PMIC provides the timekeeping, based on an integrated low power oscillator running with a standard watch crystal.

This oscillator is used for internal clocking, the control logic, and as a reference for the switcher PLL. The timekeeping includes

time of day, calendar, and alarm, and is backed up by coin cell. The clock is driven to the processor for reference and deep sleep

mode clocking.

From any mode: Loss of Power with PCEN=0

PCT[7:0] Expired

Thermal Protection Trip, or System Reset

Off

Unqual’d

Turn On

WDI Low,

WDIRESET=0

WDI Low

Unqual’d

Turn On

Event

WDIRESET=1

and PCMAXCNT

is exceeded

Start Up Modes

Reset Timer

Expired

Reset Timer

Expired

Cold

Start

Warm

Start

Watchdog

WDI Low

WDIRESET=1

and PCMAXCNT

is not exceeded

Watchdog Timer

Expired

On

PCUT Timeout

PCT[7:0]

Expired

PCUTEXPB

cleared to 0

Processor Request

for User Off:

Turn On Event

(Warm Start)

Turn On Event

(Warm Boot)

USEROFFSPI=1

Low Power

Off Modes

Warm Start

Not

Enabled

Warm Start

Enabled

Memory

Hold

User

Off

User Off

Wait

WARMEN=1

WARMEN=0

Application of Power

before PCUT Timer

PCT[7:0] expiration

(PCEN=1 and

From any mode: Loss of Power

with Power Cuts enabled

(PCEN=1) and PCMAXCNT

not exceeded

PCMAXCNT not

exceeded)

Internal

MemHold

Power

Cut

Legend and Notes (refer to text for additional details)

Blue Box = Steady State, no specific timer is running

Green Circle = Transitional State, a specific timer is running, see text

Dashed Boxes = Grouping of Modes for clarification

WDI has influence only in the “On” state

Complete loss of BP and coin cell power is not represented in the state machine

Figure 6. Power Control State Machine Flow Diagram

The following are text descriptions of the power states of the system for additional details of the state machine to complement

the drawing in Figure 6. Note that the SPI control is only possible in the Watchdog, On and User Off Wait states and that the

interrupt line INT is kept low in all states except for watchdog and on.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

34

Functional Block Description

7.5.2.1

Coin Cell

The RTC module is powered from either the battery or the coincell, due to insufficient voltage at VALWAYS, and the IC is not in

a Power Cut. No Turn On event is accepted in the Coin Cell state. Transition out (to the Off state) requires VALWAYS restoration

with a threshold above UVDET. RESETB and RESETBMCU are held low in this mode.

The RTC module remains active (32 kHz oscillator + RTC timers), along with VALWAYS level detection to qualify exit to the Off

state. VCOREDIG is off and the VDDLP regulator is on, the rest of the system is put into its lowest power configuration.

If the coin cell is depleted (VSTRC drops to 0.9 V-0.8 V while in the Coin Cell state), a complete system reset will occur. At next

power application / Turn On event, the system will startup reinitialized with all SPI bits including those that reset on RTCPORB

restored to their default states.

7.5.2.2

Off (with good battery)

If the supply VALWAYS is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are

powered, all other supplies are inactive. To exit the Off mode, a valid turn on event is required. No specific timer is running in this

mode. RESETB, RESETBMCU are held low in this mode.

If the supply VALWAYS is below the UVDET threshold, no turn on events are accepted. If a valid coin cell is present, the core

gets powered from LICELL. The only active circuitry is the RTC module and the detection VCORE module powering VCOREDIG

at 1.5 V.

If there is a USB supply or Charger inserted, the IC circuitry at VCORE, VCOREDIG, and the RTC Module will be powered up.

To exit the OFF mode, a valid turn ON event is required.

7.5.2.3

Cold Start

Cold Start is entered upon a Turn On event from Off, Warm Boot, successful PCUT, or a Silent System Restart. The first 8.0 ms

is used for initialization which includes bias generation, PUMSx configuration latching, and qualification of the input supply level

BP. The switching and linear regulators are then powered up sequentially to limit the inrush current; see the Power Up section

for sequencing and default level details. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts

running when entering Cold Start. The Cold Start state is exited for the Watchdog state and both RESETB and RESETBMCU

become high (open drain output with external pull-ups) when the reset timer is expired. The input control pins WDI, and

STANDBY are ignored.

7.5.2.4

Watchdog

The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The Watchdog timer starts running

when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and

monitored. The input control pins WDI and STANDBY are ignored while in the Watchdog state.

7.5.2.5

On Mode

The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in

this mode. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW5 = 1.8 V); SPIVCC must therefore

remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start

(depending on the configuration; refer to the section on Silent System Restart with WDI Event for details).

7.5.2.6

User Off Wait

The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered

by a processor request for user off by setting the USEROFFSPI bit high. This is normally initiated by the end user via the power

key; upon receiving the corresponding interrupt, the system will determine if the product has been configured for User Off or

Memory Hold states (both of which first require passing through User Off Wait) or just transition to Off.

The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks.

When expired, the Wait mode is exited for User Off mode or Memory Hold mode depending on warm starts being enabled or not

via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low.

MC34708

Analog Integrated Circuit Device Data

35

Freescale Semiconductor

Functional Block Description

7.5.2.7

Memory Hold and User Off (Low Power Off states)

As noted in the User Off Wait description, the system is directed into low power Off states based on a SPI command in response

to an intentional turn off by the end user. The only exit then will be a turn on event. To an end user, the Memory Hold and User

Off states look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external

memory in self-refresh mode (Memory Hold and User Off mode) as well as powering portions of the processor core for state

retention (User Off only). The Switching regulator mode control bits allow selective powering of the buck regulators for optimizing

the supply behavior in the low power Off modes. Linear regulators and most functional blocks are disabled (the RTC module, SPI

bits resetting with RTCPORB, and Turn On event detection are maintained).

By way of example, the following descriptions assume the typical use case where SW1 supplies the processor core(s), SW2 is

applied to the processor’s VCC domain, SW3 supplies the processors internal memory/peripherals, and SW4 supplies the

external memory, and SW5 supplies the I/O rail. The buck regulators are intended for direct connection to the aforementioned

loads.

7.5.2.8

Memory Hold

RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). To

ensure that SW1, SW2, SW3 and SW5 shut off in Memory Hold, appropriate mode settings should be used such as

SW1MHMODE, = SW2MHMODE, = SW3MHMODE, = SW5MHMODE set to = 0 (refer to the mode control description later in

this section). Since SW4 should be powered in PFM mode, SW4MHMODE could be set to 1.

Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and the MEMHLDI interrupt bit is

set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since

software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot.

No specific timer is running in this mode.

Buck regulators that are configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when

coming out of MEMHOLD and entering a Warm Boot. The switching regulators will be reconfigured for their default settings as

selected by the PUMSx pins in the normal time slot that would affect them.

7.5.2.9

User Off

RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected

to the processor’s CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM

is set.

The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1 and/or SW2 and or SW3 supply domains can

be configured for SWxUOMODE=1 to keep them powered through the User Off event. If one of the switching regulators can be

shut down on in User Off, its mode bits would typically be set to 0.

Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the

processor’s state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be used

for very low frequency / low power idling of the core(s), minimizing battery drain, while allowing a rapid recovery from where the

system left off before the USEROFF command.

Upon a turn on event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off will

result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with

external memory. No specific timer is running in this mode.

7.5.2.10 Warm Start

Entered upon a Turn On event from User Off. The first 8.0 ms is used for initialization, which includes bias generation, PUMSx

latching, and qualification of the input supply level BP. The switching and linear regulators are then powered up sequentially to

limit the inrush current; see Startup Requirements for sequencing and default level details. If SW1, SW2, SW3, SW4, and/or

SW5, were configured to stay on in User Off mode by their SWxUOMODE settings, they will not be turned off when coming out

of User Off and entering a Warm Start. The buck regulators will be reconfigured for their default settings as selected by the

PUMSx pins in the respective time slot defined in the sequencer selection.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

36

Functional Block Description

RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts

running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is

generated, and RESETB will go high.

7.5.2.11 Internal MemHold Power Cut

As described in the Power Cut Description, a momentary power interruption will put the system into the Internal MemHold Power

Cut state if PCUTs are enabled. The backup coin cell will now supply the MC34708 core along with the 32 k crystal oscillator, the

RTC system, and coin cell backed up registers. All regulators will be shut down to preserve the coin cell and RTC as long as

possible.

Both RESETB and RESETBMCU are tripped, bringing the entire system down along with the supplies and external clock drivers,

so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start.

If the PCT timer expires before power is re-established, the system transitions to the Off state and awaits a sufficient supply

recovery.

7.5.3

Power Control Logic

Power Cut Description

7.5.3.1

When the supply at VALWAYS drops below the UVDET threshold, due to battery bounce or battery removal, the Internal

MemHold Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the

RTC as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled.

The maximum duration of a power cut is determined by the PCUT timer PCT [7:0] preset via the SPI. When a PCUT occurs, the

PCUT timer will be started. The contents of PCT [7:0] does not reflect the actual count down value, but will keep the programmed

value, and therefore does not have to be reprogrammed after each power cut.

If power is not re-established above the LOWBATT threshold before the PCUT timer expires, the state machine transitions to the

Off mode at expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an

“unsuccessful” PCUT. In addition the PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down.

Upon re-application of power before expiration (a “successful PCUT”, defined as VALWAYS first rising above the UVDET

threshold and then battery above the LOWBATT threshold before the PCUT timer expires), a Cold Start is engaged after the

UVTIMER has expired.

In order to distinguish a non-PCUT initiated Cold Start from a Cold Start after a PCUT, the PCI interrupt should be checked by

software. The PCI interrupt is cleared by software or when cycling through the Off state.

Because the PCUT system quickly disables the entire power tree, the battery voltage may recover to a level with the appearance

of a valid supply once the battery is unloaded. However, upon a restart of the IC and power sequencer, the surge of current

through the battery and trace impedances can once again cause the BP node to droop below UVDET. This chain of cyclic power

down / power up sequences is referred to as “ambulance mode”, and the power control system includes strategies to minimize

the chance of a product falling into and getting stuck in ambulance mode.

First, the successful recovery out of a PCUT requires the VABTT node to rise above LOBATT threshold, providing hysteretic

margin from the LOBATTT (H to L) threshold. Secondly, the number of times the PCUT mode is entered is counted with the

counter PCCOUNT [3:0], and the allowed count is limited to PCMAXCNT [3:0] set through SPI. When the contents of both

become equal, then the next PCUT will not be supported and the system will go to Off mode, after the PCUT time expires.

After a successful power up after a PCUT (i.e., valid power is reestablished, the system comes out of reset, and the processor

reassumes control), software should clear the PCCOUNT [3:0] counter. Counting of PCUT events is enabled via the

PCCOUNTEN bit. This mode is only supported if the power cut mode feature is enabled by setting the PCEN bit. When not

enabled, then in case of a power failure, the state machine will transition to the Off state. SPI control is not possible during a

PCUT event and the interrupt line is kept low. SPI configuration for PCUT support should also include setting the PCUTEXPB = 1

(See Silent Restart from PCUT Event).

MC34708

Analog Integrated Circuit Device Data

37

Freescale Semiconductor

Functional Block Description

7.5.3.2

Silent Restart from PCUT Event

If a short duration power cut event occurs (such as from a battery bounce, for example), it may be desirable to perform a silent

restart, so the system is reinitialized without alerting the user. This can be facilitated by setting the PCUTEXPB bit to “1” at booting

or after a Cold Start. This bit resets on RTCPORB, therefore any subsequent Cold Start can first check the status of PCUTEXPB

and the PCI bit. The PCUTEXPB is cleared to “0” when transitioning from PCUT to Off. If there was a PCUT interrupt and

PCUTEXPB is still “1”, then the state machine has not transitioned through Off, which confirms that the PCT timer has not expired

during the PCUT event (i.e., a successful power cut). In this case, a silent restart may be appropriate.

If PCUTEXPB is found to be “0” after the Cold Start where PCI is found to be “1”, then it is inferred that the PCT timer has expired

before power was reestablished, flagging an unsuccessful power cut or first power up, so the startup user greeting may be

desirable for playback.

7.5.3.3

Silent System Restart with WDI Event

A mechanism is provided for recovery if the system software somehow gets into an abnormal state which requires a system reset,

but it is desired to make the reset a silent event so as to happen without end user awareness. The default response to WDI going

low is for the state machine to transition to the Off state (when WDIRESET = 0). However, if WDIRESET = 1, the state machine

will go to Cold Start without passing through Off mode (i.e., does not generate an OFFB signal).

A WDIRESET event will generate a maskable WDIRESETI interrupt and also increment the PCCOUNT counter. This function is

unrelated to PCUTs, but it shares the PCUT counter so that the number of silent system restarts can be limited by the

programmable PCMAXCNT counter.

When PCUT support is used, the software should set the PCUTEXPB bit to “1”. Since this bit resets with RTCPORB, it will not

be reset to “0” if a WDI falls and the state machine goes straight to the Cold Start state. Therefore, upon a restart, software can

discern a silent system restart if there is a WDIRESETI interrupt and PCUTEXPB = 1. The application may then determine that

an inconspicuous restart without fanfare may be more appropriate than launching into the welcoming routine.

A PCUT event does not trip the WDIRESETI bit.

Note that the system response to WDI is gated by the Watchdog timer—once the timer has expired, then the system will respond

as programmed by WDIRESET and described above.

7.5.3.4

Turn On Events

When in Off mode, the circuit can be powered on via a Turn On event. The Turn On events are listed by the following. To indicate

to the processor what event caused the system to power on, an interrupt bit is associated with each of the Turn On events.

Masking the interrupts related to the turn on events will not prevent the part to turn on except for the time of day alarm. If the part

was already on at the time of the turn on event, the interrupt is still generated.

• Power Button Press: PWRON1, or PWRON2 pulled low with corresponding interrupts and sense bits PWRON1I or

PWRON2I, and PWRON1S or PWRON2S. A power on/off button is connected from PWRONx to ground. The PWRONx can

be hardware debounced through a programmable debouncer PWRONxDBNC [1:0] to avoid a response upon a very short (i.e.,

unintentional) key press. BP should be above UVDET to allow a power up. The PWRONxI interrupt is generated for both the

falling and the rising edge of the PWRONx pin. By default, a 30 ms interrupt debounce is applied to both falling and rising

edges. The falling edge debounce timing can be extended with PWRONxDBNC[1:0] as defined in the following table. The

PWRONxI interrupt is cleared by software or when cycling through the Off mode.

Table 21. PWRONx Hardware Debounce Bit Settings⁽³⁷⁾

Turn On

Debounce (ms)

Falling Edge INT Rising Edge INT

Bits

State

Debounce (ms)

PWRONxDBNC[1:0]

00

01

10

11

0.0

31.25

125

31.25

125

31.25

750

Notes

37. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

38

Functional Block Description

• Charger Attach: CHRGRAW pulled high with corresponding interrupt and sense bits CHGDETI and CHGDETS. This is

equivalent to plugging in a charger; BP should be above the LOWBATT threshold. For details on the charger detection and

turn on, see Serial Interfaces.

• Battery Attach: This occurs when BP crosses the LOWBATT threshold which is equivalent to attaching a charged battery to

the product.

• USB Attach: VBUS pulled high with corresponding interrupt and sense bits USBDET and USBDETS. This is equivalent to

plugging in a USB cable connected to a host powering the VBUS line. The battery voltage should be above LOWBATT. For

details on the USB detection, see Mini/Micro USB Switch.

• RTC Alarm: TOD and DAY become equal to the alarm setting programmed. This allows powering up a product at a preset

time. BP should be above LOWBATT. For details and related interrupts, see .

• System Restart: System restart which may occur after a system reset as described earlier in this section. This is an optional

function, see Turn Off Events. BP should be above LOWBATT.

• Global System Reset: The global reset feature powers down the part, disables the charger, resets the SPI registers to their

default value including all the RTCPORB registers (except the DRM bit, and the RTC registers), and then powers back on. To

enable a global reset, the GLBRST pin needs to be pulled low for greater than GLBRSTTMR [1:0] seconds and then pulled

back high (defaults to 12 s). BP should be above LOWBATT.

Table 22. Global Reset Time Settings

Bits

State

Time (s)

GLBRSTTMR[1:0]

00

01

0

4

10

8

11 (default)

12

7.5.3.5

Turn Off Events

• Power Button Press (via WDI): User shut down of a product is typically done by pressing the power button connected to the

PWRONx pin. This will generate an interrupt (PWRONxI), but will not directly power off the part. The product is powered off

by the processor’s response to this interrupt, which will be to pull WDI low. Pressing the power button is therefore under normal

circumstances not considered as a turn off event for the state machine. However, since the button press power down is the

most common turn off method for end products, it is described in this section as the product implementation for a WDI initiated

Turn Off event. Note that the software can configure a user initiated power down, via a power button press for transition to a

Low Power Off mode (Memory Hold or User Off) for a quicker restart than the default transition into the Off state.

• Power Button System Reset: A secondary application of the PWRONx pins is the option to generate a system reset. This is

recognized as a Turn Off event. By default, the system reset function is disabled but can be enabled by setting the

PWRONxRSTEN bits. When enabled, a 4 second long press on the power button will cause the device to go to the Off mode,

and as a result, the entire application will power down. An interrupt SYSRSTI is generated upon the next power up.

Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.

• Thermal Protection: If the die gets overheated, the thermal protection will power off the part to avoid damage. A Turn On

event will not be accepted while the thermal protection is still being tripped. The part will remain in Off mode until cooling

sufficiently to accept a Turn On event. There are no specific interrupts related to this other than the warning interrupts.

• Under-voltage Detection: When the voltage at BP drops below the under-voltage detection threshold UVDET, the state

machine will transition to Off mode if PCUT is not enabled, or if the PCT timer expires when PCUT is enabled. The SDWNB

pin is used to notify that the processor that the PMIC is going to immediately shut down. The PMIC will bring the SDWNB pin

low for one 32 kHz clock cycle before powering down. This signal will then be brought back high in the power Off state.

7.5.3.6

Timers

The different timers as used by the state machine are listed by the following. This listing does not include RTC timers for

timekeeping. A synchronization error of up to one clock period may occur with respect to the occurrence of an asynchronous

event, the duration listed below is therefore the effective minimum time period.

MC34708

Analog Integrated Circuit Device Data

39

Freescale Semiconductor

Functional Block Description

Table 23. Timer Main Characteristics

Timer

Duration

Clock

Under-voltage Timer

Reset Timer

4.0 ms

40 ms

32 k/32

Watchdog Timer

Power Cut Timer

128 ms

Programmable 0 to 8 seconds 32 k/1024

in 31.25 ms steps

7.5.3.6.1

Timing Diagrams

A Turn On event timing diagrams shown in Figure 7.

ow

Turn On Event

WDI Pulled Low

Sequencer time slots

System Core Active

Turn On Verification

Power Up Sequencer

UV Masking

RESETB

INT

WDI

8 ms

20 ms

12 ms

128 ms

1- Off

2- Cold Start

3- Watchdog

4- On

3- Watchdog

1- Off

Power up of the system upon a Turn On Event followed by a transition to the On state if WDI is pulled high

Turn on Event is based on PWRON being pulled low

... or transition to Off state if WDI remains low

= Indeterminate State

Figure 7. Power Up Timing Diagram

7.5.3.7

Power Monitoring

The voltage at BATT and BP are monitored by detectors as summarized in Table 24.

Table 24. LOWBATT Detection Thresholds

(39) (40)

Threshold in V

,

L to H transition

(Power on)

H to L transition

(Low battery detect)

(38)

Bit setting

LOWBATT1

LOWBATT0

UVDET

LOWBATT

0

1

0

1

0

2.55

3.1

3.2

3.3

3.0

3.1

3.2

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

40

Functional Block Description

Table 24. LOWBATT Detection Thresholds

(39) (40)

Threshold in V

,

L to H transition

(Power on)

H to L transition

(38)

Bit setting

(Low battery detect)

LOWBATT

3.3

LOWBATT1

LOWBATT0

UVDET

LOWBATT

1

2.55

3.4

Notes

38. Default setting for LOWBATT[1:0] is 11.

39. The above specified thresholds are ±50 mV accurate for the indicated transition

40. A hysteresis is applied to the detectors on the order of 100 mV

The UVDET and LOWBATT thresholds are related to the power on/off events as described earlier in this chapter. The LOWBATT

threshold when transitioned from low to a high is used to power on the MC34708. The LOWBATT threshold when transitioned

from high to low, is used as a low battery detect warning. An interrupt LOWBAT is generated when dropping below the high to

low threshold to indicate to the processor that the battery is weak and a shutdown is imminent.

The LOWBATT detection threshold is debounced by the VBATTDB[2:0] SPI bits shown in Table 25.

Table 25. VBATTDB Debounce Times

VATTDB[1:0]

Debounce Time

00

01

10

11

0 (default)

2 RTC clock cycles

4 RTC clock cycles

8 RTC clock cycles

7.5.3.8

Power Saving

System Standby

7.5.3.8.1

A product may be designed to go into DSM after periods of inactivity, the STANDBY pin is provided for board level control of

timing in and out of such deep sleep modes.

When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing

the operating mode of the switching regulators or disabling some regulators. This can be obtained by controlling the STANDBY

pin. The configuration of the regulators in standby is pre-programmed through the SPI.

A lower power standby mode can be obtained by setting the ON_STBY_LP SPI bit to a one. With the ON_STBY_LP SPI bit set

and the STANDBY pin asserted a lower power standby will be entered. In the on Standby Low Power mode, the switching

Regulators should all be programmed into PFM mode and the LDO's should be configured to Low Power mode when the

STANDBY pin is asserted. The PLL is disabled in this mode so the mini USB will only be able to detect if a charger is inserted.

If an audio device, UART, or a USB OTG device is attached the PMIC will not be able to auto detect it in Low Power Standby

mode. It will require the software to wake up occasionally to allow the mini-USB to detect if a device is attached by de-asserting

the STANDBY pin and waking up for a period to see if a device is attached and then re-asserting Standby, if a device has not

been detected. If a device has been detected then the software can bring up the appropriate application etc.

Note the STANDBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take

into account the programmed input polarity associated with each pin. For simplicity, Standby will generally be referred to as active

high throughout this document, but as defined in Table 26, active low operation can be accommodated. Finally, since STANDBY

pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin

level changes.

MC34708

Analog Integrated Circuit Device Data

41

Freescale Semiconductor

Functional Block Description

Table 26. Standby Pin and Polarity Control

STANDBY (Pin)

STANDBYINV (SPI bit)

STANDBY Control⁽⁴¹⁾

0

1

0

1

0

1

0

1

0

Notes

41. STANDBY = 0: System is not in Standby STANDBY = 1: System is in Standby

The state of the STANDBY pin only has influence in On mode, and are therefore it is ignored during start up and in the Watchdog

phase. This allows the system to power up without concern of the required Standby polarities since software can make

adjustments accordingly as soon as it is running.

A command to transition to one of the low power Off states (User Off or Memory Hold, initiated with USE-ROFFSPI=1) redefines

the power tree configuration based on SWxMODE programming, and has priority over Standby (which also influences the power

tree configuration).

7.5.3.8.2

Standby Delay

A provision to delay the Standby response is included. This allows the processor and peripherals, some time after a Standby

instruction has been received, to terminate processes to facilitate seamless Standby exiting and re-entrance into Normal

operating mode.

A programmable delay is provided to hold off the system response to a Standby event. When enabled (STBYDLY = 01, 10, or

11), STBYDLY will delay the STANDBY initiated response for the entire IC until the STBYDLY counter expires.

Note that this delay is applied only when going into Standby, and no delay is applied when coming out of Standby. Also, an

allowance should be accounted for synchronization of the asynchronous Standby event and the internal clocking edges (up to a

full 32 k cycle of additional delay).

Table 27. Delay of STANDBY- Initiated Response

STBYDLY[1:0]

Function

No Delay

00

One 32 k period (default)

Two 32 k periods

01

10

11

Three 32 k periods

7.5.4

Buck Switching Regulators

Six buck switching regulators are provided with integrated power switches and synchronous rectification. In a typical application,

SW1 and SW2 are used for supplying the application processor core power domains. Split power domains allow independent

DVS control for processor power optimization, or to support technologies with a mix of device types with different voltage ratings.

SW3 is used for powering internal processor memory as well as low voltage peripheral devices and interfaces which can run at

the same voltage level. SW4A/B is used for powering external DDR memory as well as low voltage peripheral devices and

interfaces, which can run at the same voltage level. SW5 is used to supply the I/O domain for the system.

The buck regulators are supplied from the system supply BP, which is drawn from the main battery or the battery charger (when

present).

The switching regulators can operate in different modes depending on the load conditions. These modes can be set through SPI

and include a PFM mode, PWM Pulse Skip, an Automatic Pulse Skipping mode, and a PWM mode. The previous selection is

optimized to maximum battery life based on load conditions.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

42

Functional Block Description

Table 28. Buck Operating Modes

Mode

Description

The regulator is switched off and the output voltage is discharged

OFF

PFM

The regulator is switched on and set to PFM mode operation. In this

mode, the regulator is always running in PFM mode. Useful at light

loads for optimized efficiency.

The regulator is switched on and set to Automatic Pulse Skipping.

In this mode the regulator moves automatically between pulse

skipping and full PWM mode depending on load conditions.

APSKIP

PWM

The regulator is switched on and set to PWM mode. In this mode

the regulator is always in full PWM mode operation regardless of

load conditions.

Buck modes of operation are programmable for explicitly defined or load-dependent control.

When initially activated, regulators outputs will apply controlled stepping to the programmed value. The soft start feature limits

the inrush current at startup. During soft start, the regulator will be forced to PWM mode for 3.0 ms and then default to the APSKIP

mode A built in current limiter ensures that during normal operation the maximum current through the coil is not exceeded.

Point of Load feedback is intended for minimizing errors due to board level IR drops.

7.5.4.1

General Control

Operational modes of the Buck regulators can be controlled by direct SPI programming, altered by the state of the STANDBY

pin, by direct state machine influence (i.e., entering Off or low power Off states, for example), or by load current magnitude when

so configured (Auto Pulse skip mode). Available modes include PWM with No Pulse Skipping (PWM), PWM with Pulse Skipping

(PWMPS), Pulse Frequency Mode (PFM), Automatic Pulse Skip (APS), and Off. The transition between the two modes PWMPS

and PWM can occur automatically, based on the load current (auto pulse skip mode). For light loading, the regulators should be

put into PFM mode to optimize efficiency.

SW1A/B, SW2, SW3, SW4A/B, and SW5, can be configured for mode switching with STANDBY or autonomously, based on load

current Auto pulse skip mode. Additionally, provisions are made for maintaining PFM operation in User off and Memhold modes,

to support state retention for faster startup from the Low Power Off modes for Warm Start or Warm Boot. SWxMODE[3:0] bits

will be reset to their default values defined by PUMSx settings by the startup sequencer.

Table 29 summarizes the Buck regulators programmability for Normal and Standby modes.

Table 29. Switching regulator Mode Control for Normal and Standby Operation

SWxMODE[3:0]

Normal Mode

Standby Mode

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

Off

PWM

PWMPS

PFM

Off

APS

Off

PWM

Off

PWM

APS

Off

APS

PWMPS

APS

PWM

PWMPS

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

43

Functional Block Description

Table 29. Switching regulator Mode Control for Normal and Standby Operation

SWxMODE[3:0]

Normal Mode

Standby Mode

1100

1101

1110

1111

APS

PWM

PFM

PWMPS

PFM

In addition to controlling the operating mode in Standby, the voltage setting can be changed. The transition in voltage is handled

in a controlled slope manner, see Serial Interfaces for details. Each regulator has an associated set of SPI bits for Standby mode

set points. By default, the Standby settings are identical to the non-standby settings which are initially defined by PUMSx

programming.

The actual operating mode of the Switching regulators as a function of the STANDBY pin is not reflected through the SPI. In other

words, the SPI will read back what is programmed in SWxMODE[3:0], not the actual state that may be altered as described

previously.

Two tables follow for mode control in the low power Off states. Note that a low power Off activated SWx should use the Standby

set point as programmed by SWxSTBY[4:0]. The activated regulator(s) will maintain settings for mode and voltage until the next

startup event. When the respective time slot of the startup sequencer is reached for a given regulator, its mode and voltage

settings will be updated the same as if starting out of the Off state (except that switching regulators active through a low power

Off mode will not be off when the startup sequencer is started).

Table 30. Switching regulator Control In Memory Hold

SWxMHMODE

Memory Hold Operational Mode ⁽⁴²⁾

0

1

Off

PFM

Notes:

42. For Memory Hold mode, an activated SWx should use the

Standby set point as programmed by SWxSTBY[4:0].

Table 31. Switching regulator Control In User Off

SWxUOMODE

User Off Operational Mode ⁽⁴³⁾

0

1

Off

PFM

Notes:

43. For User Off mode, an activated SWx should use the Standby

set point as programmed by SWxSTBY[4:0].

In normal steady state operating mode, the SW1xPWGD pin is high. When the buck charger set point is changed to a higher or

lower set point, the SW1xPWGD pin will go low and will go high again when the higher/lower set point is reached.

7.5.4.2

Switching Frequency

A PLL generates the Switching system clocking from the 32.768 kHz crystal oscillator reference. The switching frequency can

be programmed to 2.0 MHz or 4.0 MHz by setting the PLLX SPI bit as shown in Table 32.

Table 32. Buck Regulator Frequency

PLLX

Switching Frequency (Hz)

0

1

2 000 000

4 000 000

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

44

Functional Block Description

The clocking system provides a near instantaneous activation when the Switching regulators are enabled or when exiting PFM

operation for PWM mode. The PLL can be configured for continuous operation with PLLEN = 1.

7.5.4.3

SW1

SW1 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. It can be operated in single phase/dual

phase mode. The operating mode of the Switching regulators is configured by the SW1CFG pin. The SW1CFG pin is sampled

at startup.

Table 33. SW1 Configuration

SW1CFG

VCOREDIG

SW1A/B Configuration Mode

Single Phase Mode

Ground

Dual Phase Mode

BP

SW1IN

SW1AMODE

SW1FAULT

I_SENSE

C_{INSW 1A}

Controller

SW1

SW1ALX

Driver

L_{SW 1A}

C_OSW1A

D_SW1

GNDSW1A

SW1FB

Internal

Compensation

SPI

Z2

SPI

Interface

Z1

V_REF

EA

DAC

BP

SW1BIN

SW1BMODE

I_SENSE

C_{INSW 1B}

Controller

SW1BLX

Driver

SW1BFAULT

GNDSW1B

VCOREDIG

SW1CFG

Figure 8. SW1 Single Phase Output Mode Block Diagram

MC34708

Analog Integrated Circuit Device Data

45

Freescale Semiconductor

Functional Block Description

BP

SW1IN

SW1AMODE

SW1FAULT

I_SENSE

C_INSW1A

Controller

SW1

SW1ALX

Driver

L_SW1A

C_OSW1A

D_SW1A

GNDSW1A

Internal

Compensation

SPI

Z2

SPI

Interface

SW1FB

Z1

V_REF

EA

DAC

BP

SW1BIN

SW1BLX

SW1BMODE

I_SENSE

C_INSW1B

Controller

Driver

L_{SW 1B}

C_{OSW 1B}

D_SW1B

SW1BFAULT

GNDSW1B

SW1CFG

Figure 9. SW1 Dual Phase Output Mode Block Diagram

The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator

will limit the current through cycle by cycle operation and alert the system through the SW1FAULT SPI bit and issue an SCPI

interrupt via the INT pin.

SW1A/B output voltage is SPI configurable in step sizes of 12.5 mV as shown in the table below. The SPI bits SW1A[5:0] set the

output voltage for both the SW1A and SW1B.

Table 34. SW1A/B Output Voltage Programmability

SW1A/B

Output (V)

SW1A/B

Output (V)

Set Point SW1A[5:0]

0

1

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

0.6500

0.6625

0.6750

0.6875

0.7000

0.7125

0.7250

0.7375

0.7500

0.7625

0.7750

0.7875

0.8000

32

33

34

35

36

37

38

39

40

41

42

43

44

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

2

3

4

5

6

7

8

9

10

11

12

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

46

Functional Block Description

Table 34. SW1A/B Output Voltage Programmability

SW1A/B

Output (V)

Set Point SW1A[5:0]

Output (V)

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

0.8125

0.8250

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

Table 35. SW1A/B Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW1A/B BUCK REGULATOR

Operating Input Voltage

• PWM operation, 0 < IL < I_MAX

V_SW1IN

V

3.0

2.8

-

4.5

• PFM operation, 0 < IL < IL_MAX

(44)

Output Voltage Accuracy

V_SW1ACC

mV

• PWM mode including ripple, load regulation, and transients

• PFM Mode, including ripple, load regulation, and transients

Nom-25

Nom

Nom+25

Continuous Output Load Current, V_INMIN< BP < 4.5 V

• PWM mode single/dual phase (parallel)

• SW1 in PFM mode

I_SW1

mA

A

-

2000

-

50

Current Limiter Peak Current Detection

• V_IN= 3.6 V, Current through Inductor

I_SW1PEAK

-

4.0

-

Transient Load Change

• 100 mA/µs

I_SW1

A

TRANSIENT

-

1.0

25

V_SW1OS-

mV

Start-up Overshoot, IL = 0

START

MC34708

Analog Integrated Circuit Device Data

47

Freescale Semiconductor

Functional Block Description

Table 35. SW1A/B Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

Turn-on Time

• Enable to 90% of end value IL = 0

t_ON-SW1

µs

-

500

Switching Frequency

• PLLX = 0

f_SW1

MHz

µA

-

2.0

4.0

-

• PLLX = 1

Quiescent Current Consumption

• PWMPS MODE, IL=0 mA

• PFM MODE, IL=0 mA

I_SW1Q

-

50

15

-

(45)

Efficiency,

%

• PFM, 0.9 V, 1.0 mA

-

54

75

81

76

-

• PWM Pulse skipping, 1.1 V, 200 mA

• PWM Pulse skipping, 1.1 V, 800 mA

• PWM, 1.1 V, 1600 mA

Notes:

44. Transient loading for load steps of ILMAX/2.

45. Efficiency numbers at V_IN= 3.6 V, excludes the quiescent current

7.5.4.4

SW2

SW2 is fully integrated synchronous Buck PWM voltage-mode control DC/DC regulator.

BP

SW2IN

SW2MODE

I_SENSE

C

INSW 3

Controller

SW2

SW2LX

Driver

L_SW2

D_{SW 2}

C_OSW2

SW2FAULT

SPI

Interface

GNDSW2

Internal

Compensation

SPI

Z2

SW2FB

Z1

V_REF

EA

DAC

Figure 10. SW2 Block Diagram

The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected, the regulator

will limit the current through cycle by cycle operation, alert the system through the SW2FAULT SPI bit, and issue an SCPI

interrupt via the INT pin

SW2 can be programmed in step sizes of 12.5 mV as shown in Table 36.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

48

Functional Block Description

Table 36. SW2 Output Voltage Programmability

SW2x

SW2 Output

(V)

Set Point SW2[5:0]

Output (V)

0

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

0.6500

0.6625

0.6750

0.6875

0.7000

0.7125

0.7250

0.7375

0.7500

0.7625

0.7750

0.7875

0.8000

0.8125

0.8250

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

49

Functional Block Description

Table 37. SW2 Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW2 BUCK REGULATOR

Operating Input Voltage

• PWM operation, 0 < IL < I_MAX

V_SW2IN

V

3.0

2.8

-

4.5

• PFM operation, 0 < IL < IL_MAX

(46)

Output Voltage Accuracy

V_SW2ACC

mV

• PWM mode including ripple, load regulation, and transients

• PFM Mode, including ripple, load regulation, and transients

Nom-25

Nom

Nom+25

Continuous Output Load Current, V_INMIN< BP < 4.65 V

I_SW2

mA

• PWM mode

• PFM mode

-

1000

-

50

Current Limiter Peak Current Detection

• V_IN= 3.6 V Current through Inductor

I_SW2PEAK

A

-

2.0

-

Transient Load Change

• 100 mA/µs

I_SW2

TRANSIENT

-

0.500

25

V_SW2OS-

mV

µs

Start-up Overshoot, IL = 0

START

Turn-on Time

t_ON-SW2

• Enable to 90% of end value IL = 0

-

500

Switching Frequency

• PLLX = 0

f_SW2

-

MHz

µA

-

2.0

4.0

• PLLX = 1

Quiescent Current Consumption

I_SW2Q

• PWM MODE, IL = 0 mA; device not switching

• PFM MODE, IL = 0 mA; device not switching

-

50

15

-

(47)

Efficiency

%

• PFM, 0.9 V, 1.0 mA

-

54

75

83

78

-

• PWM Pulse skipping, 1.2 V, 120 mA

• PWM Pulse skipping, 1.2 V, 500 mA

• PWM, 1.2 V, 1000 mA

Notes:

46. Transient loading for load steps of ILMAX/2.

47. Efficiency numbers at V_IN= 3.6 V, excludes the quiescent current.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

50

Functional Block Description

7.5.4.5

SW3

SW3 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator.

BP

SW3IN

SW3MODE

I_SENSE

C

INSW 3

Controller

SW3

SW3LX

Driver

L_SW3

D_SW3

C_OSW3

SW3FAULT

SPI

Interface

GNDSW3

Internal

Compensation

SPI

Z2

SW3FB

Z1

V_REF

EA

DAC

Figure 11. SW3 Block Diagram

The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator

will limit the current through cycle by cycle operation and alert the system through the SW3FAULT SPI bit and issue an SCPI

interrupt via the INT pin.

SW3 can be programmed in step sizes of 25 mV as shown in Table 38.

Table 38. SW3 Output Voltage Programmability

Set Point

SW3[4:0]

SW3 Output (V)

Set Point

SW3[4:0]

SW3 Output (V)

0

1

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

0.6500

0.6750

0.7000

0.7250

0.7500

0.7750

0.8000

0.8250

0.8500

0.8750

0.9000

0.9250

0.9500

0.9750

1.0000

1.0250

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

1.0500

1.0750

1.1000

1.1250

1.1500

1.1750

1.2000

1.2250

1.2500

1.2750

1.3000

1.3250

1.3500

1.3750

1.4000

1.4250

2

3

4

5

6

7

8

9

10

11

12

13

14

15

MC34708

Analog Integrated Circuit Device Data

51

Freescale Semiconductor

Functional Block Description

Table 39. SW3 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW3 BUCK REGULATOR

Operating Input Voltage

• PWM operation, 0 < IL < I_MAX

V_SW3IN

V

3.0

2.8

-

4.5

• PFM operation, 0 < IL < IL_MAX

(48)

Output Voltage Accuracy

V_SW3ACC

mV

• PWM mode including ripple, load regulation, and transients

• PFM Mode, including ripple, load regulation, and transients

Nom-3%

Nom

Nom+3%

Continuous Output Load Current, V_INMIN< BP < 4.65 V

I_SW3

mA

• PWM mode

• PFM mode

-

500

-

50

Current Limiter Peak Current Detection

• V_IN= 3.6 V Current through Inductor

I_SW3PEAK

A

-

1.0

-

Transient Load Change

• 100 mA/µs

I_SW3

250

mA

TRANSIENT

V_SW3OS-

mV

µs

Start-up Overshoot, IL = 100 mA/µs

-

25

START

Turn-on Time

t_ON-SW3

• Enable to 90% of end value IL = 0

500

Switching Frequency

• PLLX = 0

f_SW3

MHz

µA

-

2.0

4.0

-

• PLLX = 1

Quiescent Current Consumption

I_SW3Q

• PWM MODE, IL = 0 mA; device not switching

• PFM MODE, IL = 0 mA; device not switching

-

50

15

-

(49)

Efficiency,

%

• PFM, 1.2 V, 1.0 mA

-

71

79

82

81

-

• PWM Pulse skipping, 1.2 V, 120 mA

• PWM Pulse skipping, 1.2 V, 250 mA

• PWM, 1.2V, 500mA

Notes:

48. Transient loading for load steps of ILMAX/2

49. Efficiency numbers at VIN=3.6 V, Excludes the quiescent current,

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

52

Functional Block Description

7.5.4.6

SW4

SW4A/B is fully integrated synchronous Buck PWM voltage-mode control DC/DC regulator. It can be operated in (single phase/

dual phase mode) or as separate independent outputs. The operating mode of the Switching regulator is configured by the

SW4CFG pin. The SW4CFG pin is sampled at startup.

Table 40. SW4A/B Configuration

SW4CFG

Ground

SW4A/B Configuration Mode

Separate Independent Output

Single Phase

VCOREDIG

VCORE

Dual Phase

BP

SW4IN

SW4AMODE

I_SENSE

C_{INSW 4A}

Controller

Driver

SW4A

SW4ALX

L_SW4A

C_OSW4A

D_{SW 4A}

SW4AFAULT

GNDSW4A

SW4AFB

Internal

Compensation

SPI

Z2

Z1

V_REF

EA

DAC

SPI

Interface

BP

SW4BIN

SW4BLX

SW4BMODE

I_SENSE

C_{INSW 4B}

Controller

Driver

SW4B

L_SW4B

C_{OSW 4B}

D_SW4B

SW4BFAULT

GNDSW4B

Internal

Compensation

SPI

Z2

SW4BFB

SW4CFG

Z1

V_REF

EA

DAC

Figure 12. SW4A/B Separate Output Mode Block Diagram

MC34708

Analog Integrated Circuit Device Data

53

Freescale Semiconductor

Functional Block Description

BP

SW4IN

SW4AMODE

SW4AFAULT

I_SENSE

C_INSW4A

Controller

SW4

SW4ALX

Driver

L_SW4A

C_OSW4a

D_SW4

GNDSW4A

Internal

SPI

Compensation

Z2

SW4AFB

Z1

V_REF

EA

DAC

SPI

Interface

BP

SW4BIN

SW4BMODE

I_SENSE

C_INSW4B

Controller

SW4BLX

Driver

SW4BFAULT

GNDSW4B

Internal

SPI

Compensation

Z2

SW4BFB

SW4CFG

Z1

V_REF

EA

DAC

VCOREDIG

Figure 13. SW4 Single Phase Output Mode Block Diagram

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

54

Functional Block Description

BP

SW4IN

SW4AMODE

I_SENSE

C_INSW4A

Controller

SW4

SW4ALX

Driver

L_SW4A

C_OSW4A

D_SW4A

SW4AFAULT

GNDSW4A

Internal

SPI

Compensation

Z2

SW4AFB

Z1

V_REF

EA

DAC

SPI

Interface

BP

SW4BIN

SW4BMODE

I_SENSE

C_INSW4B

Controller

SW4BLX

D_SW4B

Driver

L_SW4B

C_OSW4B

SW4BFAULT

GNDSW4B

Internal

SPI

Compensation

Z2

SW4BFB

SW4CFG

Z1

V_REF

EA

DAC

VCORE

Figure 14. SW4 Dual Phase Output Mode Block Diagram

The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator

will limit the current through cycle by cycle operation and alert the system through the SW4xFAULT SPI bit and issue an SCPI

interrupt via the INT pin.

SW4A/B, when configured by the PUMS bits to come into the high voltage output range (2.5/3.15/3.3 V). If the firmware tries to

change the output voltage from the high mode (3.15 V) to the low range mode, the output voltage will default to 2.5 V. If the output

voltage comes into the lower range by default (SW4xHI[1:0] = 00), the output voltage is set by the Sw4X[4:0] bits and can be

changed by software. The regulator should be forced into PWM mode to change the voltage.

Table 41. SW4A/B Output Voltage Select

SW4xHI[1:0]

Set point selected by

Output Voltage

00

01

10

11

SW4x[4:0]

SW4xHI[1:0]

See Table 42

2.5 V

3.15 V

3.3 V

Table 42. SW4A/B Output Voltage Programmability

SW4x

Output (V)

Set Point SW4x[4:0]

Output (V)

0

1

2

00000

00001

00010

1.2000

1.2250

1.2500

16

17

18

10000

10001

10010

1.6000

1.6250

1.6500

MC34708

Analog Integrated Circuit Device Data

55

Freescale Semiconductor

Functional Block Description

Table 42. SW4A/B Output Voltage Programmability

SW4x

Output (V)

Set Point SW4x[4:0]

Output (V)

3

4

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

1.2750

1.3000

1.3250

1.3500

1.3750

1.4000

1.4250

1.4500

1.4750

1.5000

1.5250

1.5500

1.5750

19

20

21

22

23

24

25

26

-

10011

10100

10101

10110

10111

11000

11001

11010

-

1.6750

1.7000

5

1.7250

6

1.7500

7

1.7750

8

1.8000

9

1.8250

10

11

12

13

14

15

1.8500

-

Table 43. SW4A/B Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW4A/B Buck Regulator

(51)

Operating Input Voltage

• PWM operation, 0 < IL < I_MAX

V_SW4IN

V

3.0

2.8

-

4.5

• PFM operation, 0 < IL < IL_MAX

(50)

Output Voltage Accuracy

V_SW4ACC

mV

• PWM mode including ripple, load regulation, and transients

• PFM Mode, including ripple, load regulation, and transients

Nom-3%

Nom

Nom+3%

Continuous Output Load Current, V_INMIN< BP < 4.5 V

• PWM mode (separate)

I_SW4

mA

-

500

1000

-

• PWM mode single/dual phase

• PFM mode

50

Current Limiter Peak Current Detection

• V_IN= 3.6 V Current through Inductor (separate)

• Current through Inductor

I_SW4PEAK

A

-

1.0

2.0

-

Transient Load Change

• Single/Dual Phase

• Separate

i_SW4

mA

TRANSIENT

-

500

250

• 100 mA/µs

V_SW4OS-

mV

µs

Start-up Overshoot, IL = 100 mA/µs

-

25

START

Turn-on Time

t_ON-SW4

• Enable to 90% of end value IL = 0

500

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

56

Functional Block Description

Table 43. SW4A/B Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

Switching Frequency

• PLLX = 0

f_SW4

MHz

-

2.0

4.0

-

• PLLX = 1

Quiescent Current Consumption

I_SW4Q

µA

• PWM MODE, IL = 0 mA; device not switching

• PFM MODE, IL = 0 mA; device not switching

-

50

15

-

(52)

%

Efficiency

-

79

93

92

82

72

71

81

78

-

• PFM, 3.15 V, 10 mA (A)

• PWM Pulse skipping, 3.15 V, 50 mA (A)

• PWM Pulse skipping, 3.15 V, 250 mA (A)

• PWM, 3.15 V, 500 mA (A)

• PFM, 1.2 V, 10 mA (B)

• PWM Pulse skipping, 1.2 V, 50 mA (B)

• PWM Pulse skipping, 1.2 V, 250 mA (B)

• PWM 1.2 V, 500 mA (B)

Notes:

50. Transient loading for load steps of IL_MAX/ 2.

51. When SW4A/B is set to 3.0 V and above the regulator may drop out of regulation when BP nears the output voltage.

52. Efficiency numbers at V_IN= 3.6 V, excludes the quiescent current.

7.5.4.7

SW5

SW5 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator.

BP

SW5IN

SW5MODE

I_SENSE

C_INSW5

Controller

SW5

SW5LX

Driver

L_SW5

C_OSW5

D_SW5

SW5FAULT

SPI

Interface

GNDSW5

Internal

SPI

Compensation

Z2

SW5FB

Z1

V_REF

EA

DAC

Figure 15. SW5 Block Diagram

The peak current is sensed internally for over-current protection purposes. If an over-current condition is detected the regulator

will limit the current through cycle by cycle operation and alert the system through the SW5FAULT SPI bit and issue an SCPI

interrupt via the INT pin.

MC34708

Analog Integrated Circuit Device Data

57

Freescale Semiconductor

Functional Block Description

SW5 can be programmed in step sizes of 25 mV as shown in Table 44. If the software wants to change the output voltage, after

power up the regulator should be forced into PWM mode to change the voltage.

Table 44. SW5 Output Voltage Programmability

SW5

Output (V)

SW5

Output (V)

Set Point SW5[4:0]

0

1

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

1.2000

1.2250

1.2500

1.2750

1.3000

1.3250

1.3500

1.3750

1.4000

1.4250

1.4500

1.4750

1.5000

1.5250

1.5500

1.5750

16

17

18

19

20

21

22

23

24

25

26

-

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

-

1.6000

1.6250

1.6500

1.6750

1.7000

1.7250

1.7500

1.7750

1.8000

1.8250

1.8500

-

2

3

4

5

6

7

8

9

10

11

12

13

14

15

-

Table 45. SW5 Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SW5 BUCK REGULATOR

Operating Input Voltage

• PWM operation, 0 < IL < I_MAX

V_SW5IN

V

3.0

2.8

-

4.5

• PFM operation, 0 < IL < IL_MAX

(53)

Output Voltage Accuracy

V_SW5ACC

mV

• PWM mode including ripple, load regulation, and transients

• PFM Mode, including ripple, load regulation, and transients

Nom-3%

Nom

Nom+3%

Continuous Output Load Current, V_INMIN< BP < 4.5 V

I_SW5

mA

A

• PWM mode

• PFM mode

-

1000

-

50

Current Limiter Peak Current Detection

• V_IN= 3.6 V Current through Inductor

I_SW5PEAK

-

1.0

-

Transient Load Change

• 100 mA/µs

I_SW5

mA

mV

TRANSIENT

-

500

25

V_SW5

Start-up Overshoot, IL = 0

OS-START

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

58

Functional Block Description

Table 45. SW5 Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

Turn-on Time

• Enable to 90% of end value IL = 0

t_ON-SW5

µs

-

500

Switching Frequency

• PLLX = 0

f_SW5

MHz

µA

-

2.0

4.0

-

• PLLX = 1

Quiescent Current Consumption

I_SW5Q

• PWM MODE, IL = 0 mA; device not switching

• PFM MODE, IL = 0 mA; device not switching

-

50

15

-

(54)

Efficiency

%

• PFM, 1.8 V, 1.0 mA

-

80

79

86

82

-

• PWM Pulse skipping, 1.8 V, 50 mA

• PWM Pulse skipping, 1.8 V, 500 mA

• PWM, 1.8 V, 1000 mA

Notes

53. Transient Loading for load Steps of ILMAX/2

54. Efficiency numbers at VIN=3.6 V, Excludes the quiescent current.

7.5.4.8

Dynamic Voltage Scaling

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the

processor. SW1A/B and SW2 allow for two different set points with controlled transitions to avoid sudden output voltage changes,

which could cause logic disruptions on their loads.

Preset operating points for SW1A/B and SW2 can be set up for:

• Normal operation: output value selected by SPI bits SWx[5:0]. Voltage transitions initiated by SPI writes to SWx[5:0] are

governed by the DVS stepping rate shown in the following tables.

• Standby (Deep Sleep): can be higher or lower than normal operation, but is typically selected to be the lowest state retention

voltage of a given process. Set by SPI bits SWxSTBY[5:0] and controlled by a Standby event. Voltage transitions initiated by

Standby are governed by the SWxDVSSPEED[1:0] SPI bits shown in Table 46.

The following table summarizes the set point control and DVS time stepping applied to SW1A/B and SW2.

Table 46. DVS Control Logic Table for SW1A/B and SW2

STANDBY

Set Point Selected by

0

1

SWx[4:0]

SWxSTBY[4:0]

Table 47. DVS Speed Selection

SWxDVSSPEED[1:0]

Function

00

01 (default)

10

12.5 mV step each 2.0 s

12.5 mV step each 4.0 s

12.5 mV step each 8.0 s

12.5 mV step each 16.0 s

11

MC34708

Analog Integrated Circuit Device Data

59

Freescale Semiconductor

Functional Block Description

The Regulator have a strong sourcing and sinking capability in the PWM mode. Therefore, the rising/falling slope is determined

by the regulator in PWM mode, however, if the regulators are programmed in PFM, PWMPS, or APSKIP mode during a DVS

transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced,

controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode

operation.

Voltage transitions programmed through SPI(SWx[4:0]) on SW3 and SW5 will step in increments of 25 mV per 4.0 s, SW4A/B

will step in increments of 25 mV per 8.0 s when SW4xHI[1:0]=00, and SW4A/B will step in increments of 25 mV per 16 s when

SW4xHI[1:0]=00. Additionally, SW3, SW4/B, and SW5 include standby mode set point programmability.

The following diagram shows the general behavior for the switching regulators when initiated with SPI programming or standby

control.

SW1 and SW2 also contain Power Good (outputs from the MC34708 to the application processor). The power good signal is an

active high signal. When SWxPWRGDB is high, it means that the regulators output has reached its programmed voltage. The

SWxPWRGDB voltage outputs will be low during the DVS period and if the current limit is reached on the switching regulator.

The SWxPWRGD will be low from a low to high or a high to low transition of the regulator output voltage. During the DVS period,

the over-current condition on the switching regulator should be masked. If the current limit is reached outside of a DVS period,

the SWxPWRGD pin will stay low until the current limit condition is removed.

Requested

Set Point

Output Voltage

with light Load

Internally

Controlled Steps

Example

Actual Output

Voltage

Output

Voltage

Init ial

Set Point

Actual

Output Voltage

Internally

Possible

Output Voltage

Window

Controlled Steps

Request for

Higher Voltage

Request for

Lower Voltage

Voltage

Change

Request

Initiated by SPI Programming, Standby Control

SWxPWGD

Figure 16. Voltage Stepping with DVS

7.5.5

Boost Switching Regulator

SWBST is a boost switching regulator with a programmable output, which defaults to 5.0 V on power up, operating at 2.0 MHz.

SWBST supplies the VUSB regulator for the USB PHY in OTG mode, as well as the VBUS voltage. Note that the parasitic

leakage path for a boost regulator will cause the output voltage SWBSTOUT and SWBSTFB to sit at a Schottky drop below the

battery voltage whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip. An external fly back Schottky

diode, inductor, and capacitor are required.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

60

Functional Block Description

BP

4.7u

SWBSTIN

SWBST

SPI

Registers

2.2uH

SPI

Boosted Output

Voltage SWBST

SWBSTIN

SWBSTLX

Output

Drive

Switcher

Core

32KHz

Control

22uF

SWBSTFB

GNDSWBST

= Package Pin

Figure 17. Boost Regulator Architecture

SWBST output voltage programmable via the SWBST[1:0] SPI bits as shown in Table 48.

Table 48. SWBST Voltage Programming

Parameter

Voltage

SWBST Output Voltage

SWBST[1:0]

00

01

10

11

5.000 (default)

5.050

5.100

5.150

SWBST can be controlled by SPI programming in PFM, PWM, and Auto mode. Auto mode transitions between PFM and PWM

mode based on the load current. By default SWBST is powered up in Auto mode.

Table 49. SWBST Mode Control

Parameter

Voltage

SWBST Mode

SWBSTMODE[1:0]

00

01

10

11

Off

PFM

SWBSTSTBYMODE[1:0]

Auto (default)

PWM

Table 50. SWBST Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V_BUS= 5.0 V, -40 C  T_A 85 C, unless otherwise noted. Typical values

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SWITCH MODE SUPPLY SWBST

(55)

Average Output Voltage

• 3.0 V < V_IN< 4.5 V, 0 < IL < IL_MAX

V_SWBST

V

Nom-4%

-

V_NOM

Nom+3%

120 mV

Output Ripple

V_SWBSTACC

Vp-p

• 3.0 V < V_IN< 4.5 V 0 < IL < IL_MAX, excluding reverse recovery of

Schottky diode

-

Average Load Regulation

SWBST_ACC

mV/mA

• V_IN= 3.6 V, 0 < IL < IL_MAX

-

0.5

-

MC34708

Analog Integrated Circuit Device Data

61

Freescale Semiconductor

Functional Block Description

Table 50. SWBST Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

BUS

A

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

50

Max

Unit Notes

Average Line Regulation

V_SWBST

mV

LINEAREG

• 3.0 V < V_IN< 4.5 V IL = IL_MAX

-

Continuous Load Current

I_SWBST

mA

• 3.0 V < V_IN< 4.5 V, V_OUT= 5.0 V

380

Peak Current Limit

I_SWBSTPEAK

• At SWBSTIN, V_IN= 3.6 V

-

1800

-

V_SWBSTOS-

mV

ms

Start-up Overshoot, IL = 0 mA

500

START

Turn-on Time

t_ON-SWBST

• Enable to 90% of V_OUTIL = 0

-

2.0

-

Switching Frequency

f_SWBST

2.0

MHz

mV

Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs

• Maximum transient Amplitude

V_SWBS

TRANSIENT

-

300

500

Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs

• Maximum transient Amplitude

V_SWBS

mV

µs

TRANSIENT

Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs

• Time to settle 80% of transient

V_SWBS

TRANSIENT

Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs

• Time to settle 80% of transient

V_SWBS

ms

TRANSIENT

-

20

-

Efficiency, IL = IL_MAX

65

80

%

Bias Current Consumption

• PFM or Auto mode

I_SWBSTBIAS

I_LEAK-SWBST

Notes:

µA

-

35

-

NMOS Off Leakage

µA

• SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 0

1.0

6.0

55. V_INis the low side of the inductor that is connected to BP.

7.5.6

Linear Regulators (LDOs)

This section describes the linear regulators provided. For convenience, these regulators are named to indicate their typical or

possible applications, but the supplies are not limited to these uses and may be applied to any loads within the specified regulator

capabilities.

A low power standby mode controlled by STANDBY is provided for the regulators with an external pass device in which the bias

current is aggressively reduced. This mode is useful for deep sleep operation, where certain supplies cannot be disabled, but

active regulation can be tolerated with lesser parametric requirements. The output drive capability and performance are limited

in this mode.

All regulators use the main bandgap as reference. The main bandgap is bypassed with a capacitor at REFCORE. The bandgap

and the rest of the core circuitry are supplied from VCORE. The performance of the regulators is directly dependent on the

performance of VCOREDIG and the bandgap. No external DC loading is allowed on VCOREDIG or REFCORE. VCOREDIG is

kept powered as long as there is a valid supply and/or coin cell.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

62

Functional Block Description

7.5.6.1

General Features

The following applies to all linear regulators, unless otherwise specified.

• Specifications are for an ambient temperature of –40 to 85 °C.

• Advised bypass capacitor is the Murata GRM155R60G225ME95, which comes in a 0402 case.

• In general, parametric performance specifications assume the use of low ESR X5R/X7R ceramic capacitors with 20%

accuracy and 15% temperature spread, for a worst case stack up of 35% from the nominal value. Use of other types with wider

temperature variation may require a larger room-temperature nominal capacitance value to meet performance specs over

temperature. In addition, capacitor derating as a function of DC bias voltage requires special attention. Finally, minimum

bypass capacitor guidelines are provided for stability and transient performance. Larger values may be applied; performance

metrics may be altered and generally improved, but should be confirmed in system applications.

• Regulators which require a minimum output capacitor ESR (those with external PNPs) can avoid an external resistor if ESR

is assured with capacitor specifications or board level trace resistance.

• The output voltage tolerance specified for each of the linear regulators include process variation, temperature range, static

line regulation, and static load regulation.

• The PSRR of the regulators is measured with the perturbating signal at the input of the regulator. The power management IC

is supplied separately from the input of the regulator and does not contain the perturbated signal. During measurements, care

must be taken not to reach the drop out of the regulator under test.

• In the Low Power mode, the output performance is degraded. Only those parameters listed in the Low Power mode section

are guaranteed. In this mode, the output current is limited to much lower currents than in the active mode.

• Regulator performance is degraded in the extended input voltage range. This means that the supply still behaves as a

regulator, and will try to hold up the output voltage by turning the pass device fully on. As a result, the bias current will increase

and all performance parameters will be heavily degraded, such as PSRR and load regulation.

• Note that the minimum operating range specifications in some cases may be conflicting, due to numerous set point and biasing

options, as well as the potential to run BP into one of the software or hardware shutdown thresholds. The specifications are

general guidelines that should be interpreted with some care in such cases.

• When a regulator gets disabled, the output will be pulled towards ground by an internal pull-down. The pull-down is also

activated when RESETb goes low.

• 32 kHz spur levels are specified for fully loaded conditions.

• Short-circuit protection (SCP) is included on certain LDOs (see the SCP section later in this section). Exceeding the SCP

threshold will disable the regulator and generate a system interrupt. The output voltage will not sag below the specified voltage

with the rated current being drawn. For the lower current LDOs without SCP, they are less accessible to the user environment

and essentially self-limiting.

• The power tree of a given application must be scrubbed for critical use cases to ensure consistency and robustness in the

power strategy.

7.5.6.2

LDO Regulator Control

The regulators with embedded pass devices (VPLL, VGEN1, and VUSB) have an adaptive biasing scheme thus, there are no

distinct operating modes such as a Normal mode and a Low Power mode. Therefore, no specific control is required to put these

regulators in a Low Power mode.

The external pass regulator (VDAC) can also operate in a normal and low power mode. However, since a load current detection

cannot be performed for this regulator, the transition between both modes is not automatic and is controlled by setting the

corresponding mode bits for the operational behavior desired.

The regulators VUSB2, and VGEN2 can be configured for using the internal pass device or external pass device as explained in

Supplies. For both configurations, the transition between both modes is controlled by setting the VxMODE bit for the specific

regulator. Therefore, depending on the configuration selected, the automatic Low Power mode determines availability.

The regulators can be disabled and the general purpose outputs can be forced low when going into Standby (note that the

Standby response timing can be altered with the STBYDLY function, as described in the previous section). Each regulator has

an associated SPI bit for this. When the bit is not set, STANDBY is of no influence. The actual operating mode of the regulators

as a function of STANDBY is not reflected through SPI. In other words, the SPI will read back what is programmed, not the actual

state.

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63

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Functional Block Description

Table 51. LDO Regulator Control (external pass device LDOs)

VxEN

VxMODE

VxSTBY STANDBY⁽⁵⁶⁾

Regulator Vx

0

1

X

0

1

X

0

1

X

0

1

X

0

Off

On

Low Power

On

1

Off

1

Low Power

Notes

56. STANDBY refers to a Standby event as described earlier

For regulators with internal pass devices, the previous table can be simplified by elimination of the VxMODE column.

Table 52. LDO Regulator Control (internal pass device LDOs)

VxEN

VxSTBY

STANDBY ⁽⁵⁷⁾

Regulator Vx

0

1

X

0

1

X

0

1

Off

On

Off

Notes

57. STANDBY refers to a Standby event as described earlier

7.5.6.3

Transient Response Waveforms

The transient load and line response are specified with the waveforms as depicted in Figure 18. Note that where the transient

load response refers to the overshoot only, so excluding the DC shift itself, the transient line response refers to the sum of both

overshoot and DC shift. This is also valid for the mode transition response.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

64

Functional Block Description

Imax

Iload

0mA

Vnom + 0.8V

Vin

Vnom + 0.3V

1us

10us

Iload for Transient Load Response

Vin for Transient Line Response

IL = 0mA

IL = Imax

Overshoot

Vout

Overshoot

Vout for Transient Load Response

Active Mode

Low Power Mode

Active Mode

Overshoot

Vout

Mode

Transition

Time

Overshoot

IL < ILmax

IL < ILmaxlp

IL < ILmax

V

Mode Transition Response (V

, V

, and V

)

OUT

GEN2

USB2

DAC

Vout for Mode Transition Response (VGEN1/2/3, VVIDEO, VCAM, VSD)

Figure 18. Transient Waveforms

7.5.6.4

Short-circuit Protection

The higher current LDOs, and those most accessible in product applications, include short-circuit detection and protection

(VDAC, VUSB, VUSB2, VGEN1, and VGEN2). The short-circuit protection (SCP) system includes debounced fault condition

detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product

damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its VxEN bit, while at the same time, an

interrupt SCPI will be generated to flag the fault to the system processor. The SCPI interrupt is maskable through the SCPM

mask bit.

The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, then not only is no interrupt generated, but also

the regulators will not automatically be disabled upon a short-circuit detection. However, the built-in current limiter will continue

to limit the output current of the regulator. Note that by default, the REGSCPEN bit is not set, so at startup, none of the regulators

in an overload condition are disabled.

7.5.6.5

VPLL

VPLL is provided for isolated biasing of the application processors PLLs for clock generation, in support of protocol and peripheral

needs. Depending on the application and power requirements, this supply may be considered for sharing with other loads, but

noise injection must be avoided and filtering added, if necessary to ensure suitable PLL performance. The VPLL regulator has a

dedicated input supply pin.

MC34708

Analog Integrated Circuit Device Data

65

Freescale Semiconductor

Functional Block Description

VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail such as from SW5 for the two lower set points

of each regulator VPLL[1:0] = [00], [01]. In addition, when the two upper set points (VPLL[1:0] = [10],[11]) are used, the VINPLL

inputs can be connected to either BP or a 2.2 V nominal external switched mode power supply rail, to improve power dissipation.

Table 53. VPLL Voltage Control

Parameter Value

Function

ILoad max

Input Supply

VPLL[1:0]

00

output = 1.2 V

50 mA

BP or 1.8 V

01 output = 1.25 V

10 output = 1.50 V

BP or External switch

11

output = 1.8 V

Table 54. VPLL Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

GENERAL

V_INPLL

Characteristic

Min

Typ

Max

Unit Notes

Operating Input Voltage Range

V

• VPLL all settings, BP biased

UVDET

1.75

-

4.5

• VPLL [1:0] = 00, 01 (SW5 = 1.8 V)

• VPLL, [1:0] = 10, 11, External Switch

1.8

2.2

2.15

Operating current Load range

I_PLL

-

50

mA

V

VPLL ACTIVE MODE – DC

V_PLL

Output Voltage V_OUT

V_NOM

– 0.05

V_NOM

+ 0.05

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

Load Regulation

V_PLL-LOPP

V_PLL-LIPP

I_PLL-Q

mV/mA

mV

• 1.0 mA < IL < IL_MAXFor any V_INMIN< V_IN< V_INMAX

-

0.35

5.0

-

Line Regulation

• V_INMIN< V_IN< V_INMAXFor any IL_MIN< IL < IL_MAX

Quiescent Current

µA

• V_INMIN< V_IN< V_INMAXIL = 0

8.0

VPLL ACTIVE MODE – AC

PSRR, IL = 75% of IL_MAX, 20 Hz to 20 kHz

VPLL_PSRR

dB

• V_IN= UVDET

35

50

40

60

-

• V_IN= V_NOM+ 1.0 V, > UVDET

Output Noise Density, V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 1.0 kHz

VPLL_NOISE

-

20

-

dB/dec

• > 1.0 kHz – 1.0 MHz

2.5

V/Hz

Turn-on Time

t_ON-VPLL

µs

ms

%

• Enable to 90% of end value V_IN= V_INMIN, V_INMAXIL = 0

-

0.05

-

120

10

Turn-off Time

t_OFF-VPLL

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAX, IL = 0

Start-up Overshoot

VPLL_OS-

START

• V_IN= V_INMIN, V_INMAXIL = 0

1.0

2.0

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

66

Functional Block Description

Table 54. VPLL Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

50

Max

70

Unit Notes

Transient Load Response

• V_IN= V_INMIN, V_INMAX

V_PLL-LO

mV

TRANSIENT

-

Transient Line Response

• IL = 75% of IL_MAX

V_PLL-LI

mV

TRANSIENT

5.0

8.0

7.5.6.6

VREFDDR

VREFDDR is an internal PMOS half supply Voltage Follower. The output voltage is at one half the input voltage. It’s typical

application is as the V for DDR memories. A filtered resistor divider is utilized to create a low frequency pole. This divider then

REF

utilizes a voltage follower to drive the load.

Table 55. VREFDDR Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

GENERAL

V_REFFDDRIN

I_REFDDR

Operating Input Voltage Range V_INMINto V_INMAX

Operating Current Load Range IL_MINto IL_MAX

1.2

0.0

-

1.8

10

V

mA

VREFDDR ACTIVE MODE – DC

Output Voltage V_OUT

V_REFDDR

V

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

0.6

V_IN/2

0.9

2.0

-

(58)

%

Output Voltage tolerance

V_REFDDRTOL

• V_INMIN< V_IN< V_INMAXIL = 1.0 mA

-2.0

-

Load Regulation

V_REFDDR

mV/mA

µA

LOPP

• 1.0 mA < IL < IL_MAXFor any V_INMIN< V_IN< V_INMAX

-

5.0

8.0

Quiescent Current

I_REFDDRQ

• V_INMIN< V_IN< V_INMAXIL = 0

-

VREFDDR ACTIVE MODE – AC

Turn-on Time

t_ON-VREFDDR

µs

ms

%

• Enable to 90% of end value V_IN= V_INMIN, V_INMAXIL = 0

-

100

10

2.0

-

Turn-off Time

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAX, IL = 0

t_OFF-

VREFDDR

0.05

-

Start-up Overshoot

V_REFDDROS

• V_IN= V_INMIN, V_INMAXIL = 0

-

1.0

5.0

Transient Load Response

• V_IN= V_INMIN, V_INMAX

V_REFDDRL

mV

TRANSIENT

Notes

58. guaranteed at 25 °C only

MC34708

Analog Integrated Circuit Device Data

67

Freescale Semiconductor

Functional Block Description

7.5.6.7

VUSB2

VUSB2 has an internal PMOS pass FET which will support loads up to 65 mA. To support load currents an external PNP is

provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at high loads and large differentials

between BP and output settings. For lower current requirements, an integrated PMOS pass FET is included. The input pin for

the integrated PMOS option is shared with the base current drive pin for the PNP option. The external PNP configuration must

be committed as a hardwired board level implementation. The recommended PNP device is the ON Semiconductor™

NSS12100XV6T1G, which is capable of handling up to 250 mW of continuous dissipation, at minimum footprint and 75 °C of

ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP device is ON Semiconductor

NSS12100UW3TCG. For stability reasons, a small minimum ESR may be required.

A short-circuit condition will shut down the VUSB2 regulator and generate an interrupt for SCPI.

The nominal output voltage of this regulator is SPI configurable, and can be 2.5 V, 2.6 V, 2.75 V, or 3.0 V. The output current

when working with the internal pass FET is 65 mA, and could be up to 350 mA when working with an external PNP.

Table 56. VUSB2 Voltage Control

ILoad max

Output

Voltage

Parameter Value

VUSB2CONFIG=0 VUSB2CONFIG=1

Internal Pass FET

External PNP

VUSB2[1:0] 00

2.5 V

2.6 V

65 mA

350 mA

01

10

11

2.75 V

3.00 V

Table 57. VUSB2 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

GENERAL

V_USB2IN

Characteristic

Min

Typ

Max

Unit Notes

V_NOM

0.25

+

-

4.5

V

Operating Input Voltage Range V_INMINto V_INMAX

Operating Current Load Range IL_MINto IL_MAX

• Internal pass FET

I_USB2

mA

0.0

-

65

• External PNP Not exceeding PNP max power

350

Extended Input Voltage Range

V_USB2IN

V

• Performance may be out of specification

UVDET

-

4.5

Minimum Bypass Capacitor Value

• Internal pass device

CO_VUSB2

µF

0.65

1.1

2.2

-

• External pass device

Bypass Capacitor ESR

• 10 kHz – 1.0 MHz

ESR_VUSB2

m

20

-

100

VUSB2 ACTIVE MODE - DC

Output Voltage V_OUT

V_USB2

V

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

V_NOM- 3%

V_NOM

0.25

V_NOM+ 3%

Load Regulation

V_USB2LOPP

mV/mA

• 1.0 mA < IL < IL_MAXFor any V_INMIN< V_IN< V_INMAX

-

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

68

Functional Block Description

Table 57. VUSB2 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

8.0

-

Max

Unit Notes

Line Regulation

V_USB2LIPP

mV

• V_INMIN< V_IN< V_INMAXFor any IL_MIN< IL < IL_MAX

-

VUSB2_SCTH

mA

µA

Short-circuit Protection threshold

IL_MAX

+20%

• V_INMIN< V_IN< V_INMAXShort-circuit V_OUTto GND

Active Mode Quiescent Current, V_INMIN< V_IN< V_INMAX

• IL = 0, Internal PMOS configuration

I_USB2Q

-

25

30

-

• V_INMIN< V_IN< V_INMAXIL = 0, External PNP configuration

VUSB2 LOW POWER MODE - DC

Output Voltage V_OUT

V_USB2

V

• V_INMIN< V_IN< V_INMAXIL_MINLP< IL < IL_MAXLP

V_NOM- 3%

0.0

V_NOM

-

V_NOM+ 3%

3.0

Current Load Range IL_MINLPto IL_MAXLP

I_USB2

mA

µA

Low Power Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_USB2Q

-

8.0

10.5

VUSB2 ACTIVE MODE - AC

PSRR, IL = 75% of IL_MAX20 Hz to 20 kHz

VUSB2_PSRR

dB

• V_IN= V_INMIN+ 100 mV

• V_IN= V_NOM+ 1.0 V

35

50

40

60

-

Output Noise Density, V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 1.0 kHz

VUSB

2_NOISE

-

20

-

dB/dec

• > 1.0 kHz – 1.0 MHz

1.0

V/Hz

Turn-on Time

t_ON-VUSB2

ms

%

• Enable to 90% of end value V_IN= V_INMIN, V_INMAXIL = 0

-

0.05

-

1.0

10

Turn-off Time

t_OFF-VUSB2

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAXIL = 0

Start-up Overshoot

VUSB2_OS-

START

• V_IN= V_INMIN, V_INMAXIL = 0

1.0

2.0

Transient Load Response, V_IN= V_INMIN, V_INMAX

• VUSB2=01, 10, 11

x

VUSB2_LO

TRANSIENT

-

1.0

50

2.0

70

%

• VUSB2=00

mV

Transient Line Response

• IL = 75% of IL_MAX

VUSB2_LI

mV

µs

TRANSIENT

-

5.0

-

8.0

Mode Transition Time

t_MOD-VUSB2

• From low power to active and from active to low power

_IN= V_INMIN, V_INMAXIL = IL_MAXLP

100

V

Mode Transition Response

VUSB_MODE

%

RES

• From low power to active and from active to low power

-

1.0

2.0

V_IN= V_INMIN, V_INMAXIL = IL_MAXLP

MC34708

Analog Integrated Circuit Device Data

69

Freescale Semiconductor

Functional Block Description

7.5.6.8

VDAC

The primary applications of this power supply is the TV-DAC. However, these supplies could also be used for other peripherals

if one of these functions is not required. Low Power modes and programmable standby options can be used to optimize power

efficiency during deep sleep modes.

An external PNP is utilized for VDAC to avoid excess on-chip power dissipation at high loads and large differentials between BP

and output settings. For stability reasons, a small minimum ESR may be required. In the Low Power mode for VDAC, an internal

bypass path is used instead of the external PNP. External PNP devices must always be connected to the BP line in the

application. The recommended PNP device is the ON Semiconductor NSS12100XV6T1G, which is capable of handling up to

250 mW of continuous dissipation at minimum footprint and 75 °C of ambient. For use cases where up to 500 mW of dissipation

is required, the recommended PNP device is ON Semiconductor NSS12100UW3TCG. For stability reasons, a small minimum

ESR may be required.

A short-circuit condition will shut down the VDAC regulator and generate an interrupt for SCPI.

The nominal output voltage of this regulator is SPI configurable, and can be 2.5 V, 2.6 V, 2.7 V, or 2.775 V. The maximum output

current along with an external PNP, is 250 mA.

Table 58. VDAC Voltage Control

Parameter

Value

Output Voltage

ILoad max

VDAC

00

01

10

11

2.500 V

2.600 V

2.700 V

2.775 V

250 mA

Table 59. VDAC Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

BUS

A

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

GENERAL

V_DACIN

Characteristic

Min

Typ

Max

Unit Notes

V_NOM

0.25

+

V

Operating Input Voltage Range V_INMINto V_INMAX

-

4.5

Operating Current Load Range IL_MINto IL_MAX

• Not exceeding PNP max power

I_DAC

mA

0.0

-

250

4.5

Extended Input Voltage Range

V_DACIN

V

• Performance may be out of specification

UVDET

VDAC ACTIVE MODE – DC

Output Voltage V_OUT

V_DAC

V

mV/mA

mV

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

V_NOM– 3%

V_NOM

0.20

5.0

V_NOM+ 3%

Load Regulation

V_DACLOPP

V_DACLIPP

VDAC_SCTH

• 1.0 mA < IL < IL_MAXFor any V_INMIN< V_IN< V_INMAX

-

Line Regulation

• V_INMIN< V_IN< V_INMAXFor any IL_MIN< IL < IL_MAX

mA

Short-circuit Protection threshold

IL_MAX

+20%

-

• V_INMIN< V_IN< V_INMAXShort-circuit V_OUTto GND

Active Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_DACQ

µA

-

30

-

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

70

Functional Block Description

Table 59. VDAC Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol Characteristic

Min

Typ

Max

Unit Notes

VDAC LOW POWER MODE – DC - VDACMODE=1

Output Voltage V_OUT

V_DAC

V

• V_INMIN< V_IN< V_INMAXIL_MINLP< IL < IL_MAXLP

V_NOM– 3%

0.0

V_NOM

-

V_NOM+ 3%

3.0

Current Load Range IL_MINLPto IL_MAXLP

I_DAC

mA

µA

Low Power Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_DACQ

-

8.0

-

VDAC ACTIVE MODE – AC

PSRR - IL = 75% of IL_MAX20 Hz to 20 kHz

VDAC_PSRR

dB

• V_IN= V_INMIN+ 100 mV

• V_IN= V_NOM+ 1.0 V

35

50

40

60

-

Output Noise Density, V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 1.0 kHz

VDAC_NOISE

V/Hz

-

-115

-126

-132

• > 1.0 kHz – 10 kHz

• > 10 kHz – 1.0 MHz

Spurs

VDAC_SPURS

dB

ms

• 32.768 kHz and harmonics

-

-120

1.0

Turn-on Time

t_ON-VDAC

• Enable to 90% of end value V_IN= V_INMIN, V_INMAXIL = 0

Turn-off Time

t_OFF-VDAC

ms

%

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAX, IL = 0

0.05

-

10

2.0

8.0

100

2.0

Start-up Overshoot

VDAC_OS-

START

• V_IN= V_INMIN, V_INMAXIL = 0

-

1.0

5.0

-

Transient Load Response

• V_IN= V_INMIN, V_INMAX

VDAC_LO

%

TRANSIENT

Transient Line Response

• IL = 75% of IL_MAX

V_DACLI

mV

µs

%

TRANSIENT

Mode Transition Time

t_MODE-VDAC

• From low power to active V_IN= V_INMIN, V_INMAXIL = IL_MAXLP

Mode Transition Response

VDAC_MODE

RES

• From low power to active and from active to low power

1.0

V_IN= V_INMIN, V_INMAXIL = IL_MAXLP

7.5.6.9

VGEN1, VGEN2

General purpose LDOs, VGEN1, and VGEN2, are provided for expansion of the power tree to support peripheral devices, which

could include EMMC cards, WLAN, BT, GPS, or other functional modules. These regulators include programmable set points for

system flexibility. VGEN1 has an internal PMOS pass FET, and is powered from the SW5 buck for an efficiency advantage and

reduced power dissipation in the pass devices. VGEN2 is powered directly from the battery.

VGEN2 has an internal PMOS pass FET, which will support loads up to 50 mA. For higher current capability, drive for an external

PNP is provided. The external PNP is offered to avoid excess on-chip power dissipation at high loads and large differentials

between BP and output settings. The input pin for the integrated PMOS option is shared with the base current drive pin for the

PNP option. The external PNP device is always connected to the BP line in the application. The recommended PNP device is

MC34708

Analog Integrated Circuit Device Data

71

Freescale Semiconductor

Functional Block Description

the ON Semiconductor NSS12100XV6T1G which is capable of handling up to 250 mW of continuous dissipation at minimum

footprint and 75 °C of ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP device is

the ON Semiconductor NSS12100UW3TCG. For stability, a small minimum ESR may be required.

A short-circuit condition will shut down the VGEN1 and VGEN2 regulators, and generate an interrupt for SCPI.

Table 60. VGEN1 Control Register Bit Assignments

Parameter

Value

Output Voltage

ILoad max

VGEN1[2:0]

000

001

010

011

100

101

110

111

1.2000

1.2500

1.3000

1.3500

1.4000

1.4500

1.5000

1.5500

250 mA

The nominal output voltage of VGEN1 is SPI configurable, and can be 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V, 1.45 V, 1.5 V, or

1.55 V.

The nominal output voltage of VGEN2 is SPI configurable, and can be 2.5 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 3.15 V, or 3.3 V.

The output current when working with the internal pass FET is 50 mA, and could be up to 250 mA when working with an external

PNP.

Table 61. VGEN2 Control Register Bit Assignments

ILoad max

Output

Voltage

Parameter Value

VGEN2CONFIG=0 VGEN2CONFIG=1

Internal Pass FET

External PNP

VGEN2[2:0]

000

001

010

011

100

101

110

111

2.50

2.70

2.80

2.90

3.00

3.10

3.15

3.30

50 mA

250 mA

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

72

Functional Block Description

Table 62. VGEN1 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

GENERAL

V_GEN1IN

Characteristic

Min

Typ

Max

Unit Notes

Operating Input Voltage Range V_INMINto V_INMAX

• All settings

V

1.75

0.0

1.8

-

1.85

250

Operating Current Load Range IL_MINto IL_MAX

• Not exceeding PNP max power

I_GEN1

mA

VGEN1 ACTIVE MODE – DC

Output Voltage V_OUT

V_GEN1

V

mV/mA

mV

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

V_NOM– 3%

V_NOM

0.25

5.0

V_NOM+ 3%

Load Regulation

V_GEN1LOPP

V_GEN1LIPP

VGEN1_SCTH

• 1.0 mA < IL < IL_MAXFor any V_INMIN< V_IN< V_INMAX

-

Line Regulation

• V_INMIN< V_IN< V_INMAXFor any IL_MIN< IL < IL_MAX

mA

Short-circuit Protection threshold

IL_MAX

+20%

-

• V_INMIN< V_IN< V_INMAXShort-circuit V_OUTto GND

Active Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_GEN1Q

µA

V

-

12

-

VGEN1 LOW POWER MODE - DC

Output Voltage V_OUT

V_GEN1

• V_INMIN< V_IN< V_INMAXIL_MINLP< IL < IL_MAXLP

V_NOM- 3%

0.0

V_NOM

-

V_NOM+ 3%

3.0

Current Load Range IL_MINLPto IL_MAXLP

I_GEN1

mA

µA

Low Power Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_GEN1Q

-

12

-

VGEN1 ACTIVE MODE - AC

PSRR

VGEN1_PSRR

dB

• IL = 75% of IL_MAX20 Hz to 20 kHz VGEN1[2:0] = 000-101

50

37

60

-

• IL = 75% of ILMAX 20 Hz to 20 kHz VGEN1[2:0] = 110-111

Output Noise Density, V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 1.0 kHz

VGEN

1_NOISE

V/Hz

-

-115

-126

-132

• > 1.0 kHz – 10 kHz

• > 10 kHz – 1.0 MHz

Spurs

VGEN

1_SPURS

dB

ms

• 32.768 kHz and harmonics

-

-100

1.0

Turn-on Time

t_ON-VGEN1

• Enable to 90% of end value V_IN= V_INMIN, V_INMAX, IL = 0

Turn-off Time

t_OFF-VGEN1

ms

%

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAX, IL = 0

0.01

-

10

Start-up Overshoot

VGEN1_OS-

START

• V_IN= V_INMIN, V_INMAX, IL = 0

1.0

2.0

MC34708

Analog Integrated Circuit Device Data

73

Freescale Semiconductor

Functional Block Description

Table 62. VGEN1 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

BUS

A

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

1.0

5.0

-

Max

2.0

Unit Notes

Transient Load Response

• V_IN= V_INMIN, V_INMAX

VGEN1_LO

%

TRANSIENT

-

Transient Line Response

• IL = 75% of IL_MAX

V_GEN1LI

mV

µs

TRANSIENT

8.0

Mode Transition Time

t_MODE-VGEN1

• From low power to active and from active to low power

_IN= V_INMIN, V_INMAXIL = IL_MAXLP

100

V

Mode Transition Response

VGEN

%

1_MODERES

• From low power to active and from active to low power

-

1.0

2.0

V_IN= V_INMIN, V_INMAXIL = IL_MAXLP

Table 63. VGEN2 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

VGEN2

Characteristic

Min

Typ

Max

Unit Notes

V_GEN2IN

V

Operating Input Voltage Range V_INMINto V_INMAX

• All settings, BP biased

V_NOM

+0.25

-

4.5

Operating Current Load Range IL_MIto IL_MAX

• Internal Pass FET

I_GEN2

mA

0.0

-

50

250

4.5

Operating Current Load Range IL_MINto IL_MAX

• External PNP, Not exceeding PNP max power

I_GEN2

Extended Input Voltage Range

V_GEN2IN

mV/mA

• BP Biased, Performance may out of specification for output levels

VGEN2 [2:0] = 010 to 111

UVDET

Minimum Bypass Capacitor Value

CO_VGEN2

µs

• Used as a condition for all other parameters

1.1

20

2.2

-

Bypass Capacitor ESR

• 10 kHz – 1.0 MHz

ESR_VGEN2

m

100

VGEN2 ACTIVE MODE - DC

Output Voltage V_OUT

V_GEN2

V

mV/mA

mV

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MAX

V_NOM- 3%

V_NOM

0.20

8.0

V_NOM+ 3%

Load Regulation

V_GEN2LOPP

V_GEN2LIPP

VGEN2_SCTH

• 1.0 mA < IL < IL_MAX, For any V_INMIN< V_IN< V_INMAX

-

Line Regulation

• V_INMIN< V_IN< V_INMAXFor any IL_MIN< IL < IL_MAX

mA

Short-circuit Protection threshold

ILmax

+20%

-

• V_INMIN< V_IN< V_INMAXShort-circuit V_OUTto GND

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

74

Functional Block Description

Table 63. VGEN2 Electrical Specification

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Active Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

Min

Typ

Max

Unit Notes

I_GEN2Q

µA

-

30

-

VGEN2 LOW POWER MODE - DC - VGEN2MODE=1

Output Voltage V_OUT

V_GEN2

V

• V_INMIN< V_IN< V_INMAXIL_MINLP< IL < IL_MAXLP

V_NOM- 3%

0.0

V_NOM

-

V_NOM+ 3%

3.0

Current Load Range IL_MINLPto IL_MAXLP

I_GEN2

mA

µA

Low Power Mode Quiescent Current

• V_INMIN< V_IN< V_INMAXIL = 0

I_GEN2Q

-

8.0

-

VGEN2 ACTIVE MODE - AC

PSRR - IL = 75% of ILmax, 20 Hz to 20 kHz

VGEN2_PSRR

dB

• V_IN= V_INMIN+ 100 mV

• V_IN= V_NOM+ 1.0 V

35

55

40

60

-

Output Noise Density - V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 1.0 kHz

VGEN

2_NOISE

V/Hz

-

-115

-126

-132

• > 1.0 kHz – 10 kHz

• > 10 kHz – 1.0 MHz

Turn-on Time

t_ON-VGEN22

ms

%

• Enable to 90% of end value V_IN= V_INMIN, V_INMAX, IL = 0

-

1.0

10

Turn-off Time

t_OFF-VGEN2

• Disable to 10% of initial value V_IN= V_INMIN, V_INMAX, IL = 0

0.05

-

Start-up Overshoot

VGEN2_OS-

START

• V_IN= V_INMIN, V_INMAXIL = 0

-

1.0

5.0

-

2.0

8.0

100

2.0

Transient Load Response

• V_IN= V_INMIN, V_INMAX

VGEN2_LO

%

TRANSIENT

Transient Line Response

• IL = 75% of IL_MAX

V_GEN2LI

mV

µs

%

TRANSIENT

Mode Transition Time

t_MODE-VGEN2

• From low power to active V_IN= V_INMIN, V_INMAX, IL = IL_MAXLP

Mode Transition Response

VGEN

2_MODERES

• From low power to active and from active to low power

1.0

V_IN= V_INMIN, V_INMAX, IL = IL_MAXLP

MC34708

Analog Integrated Circuit Device Data

75

Freescale Semiconductor

Functional Block Description

7.6

Battery Management

The MC34708 supports power path management, which allows power to the system even in the absence of the battery, or in the

case of a deeply discharged battery. The charger supports charging from a USB host or a wall charger.

The charger interface provides switching operations via an integrated DAC at programmable current levels. It incorporates a

standalone trickle charge mode, in case of a dead battery, with a dual LED indicator driver. Over-voltage, short-circuit, and under-

voltage detectors are included, as well as charger detection and removal. The charger includes the necessary circuitry to allow

for USB charging. The battery management system also provides a battery presence detector and an A to D converter that serves

for measuring the charge current, battery, and other supply voltages, as well as for measuring the battery thermistor and die

temperature. The charger has two charge paths, a main and an aux charge path. Finally, a system is included for monitoring the

current drawn from, or charged into the main battery, for support of a Coulomb Counter function.

The battery management interface contains two charge paths. This gives flexibility in the application and allows the USB charge

path to be separate or combined with a standard wall charger. The MC34708 supports power path management, which permits

the system to be supplied without a battery present (in factory mode only), or a deeply discharged battery with the M

present.

FET

BATT

7.6.1

Functional Block Diagram

The charger line up is depicted in Figure 19.

Figure 19. Charger Line Up

The charger is a buck switching charger, operating at 2.0 MHz. Transistors M

and M

are used to isolate the charger from

AUX

VBUS

over-voltage conditions. GOTG is used to disable the V

path for over-voltage conditions and in OTG mode, or when a audio

BUS

accessory is attached. The USB charge path will take precedence over the aux charge path. G

will enable M

, in the cases

AUX

where a USB charger is not present and the V

is within the valid threshold window. To support power path management and

AUX

allow the system to be powered without a battery or in a dead battery case, M

needs to be populated. In case of a dead

BATT

battery, the transistor M

is made non-conducting and the internal trickle charge current charges the battery. If the battery is

BATT

sufficiently charged, the transistor M

is made conducting, which connects the battery to the application just as in during

BATT

normal operation without a charger. In cases applications where M

is replaced by a short, the GBAT pin must be grounded.

BATT

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

76

Functional Block Description

System power up with a Dead battery operation is not supported in this case, and the PMIC will trickle to the LOWBATT threshold

and then the system will power up. V

and V

are used to sense when the V

and AUX charge path are within range to

BUS

AUX

BUS

charge, and as an internal supply to power up internal detectors and circuitry in a dead battery case.

7.6.2

Buck Charger Operation

The charger buck takes its feedback from two sources, depending on the state of the battery:

• M present and V is less than the LOWBATT threshold. M will be opened and BP will be set to the VCHRCV[5:0]

BATT

settings (set to 3.6 by default) to supply the system loads. The feedback for the buck charger is taken from a conventional

internal resistor divider connected at the BP pin. This supports dead battery operation and allows the system to operate if the

battery does not exist or is being trickle charged through a separate path.

• For batteries above LOWBATT[1:0] threshold, BP tracks the battery voltage level V

. If M

is present, M will be

BATT

closed when the MC34708 detects when the BP voltage is at the same potential as the V

node. When the V

node is

BATT

below this threshold and M

is present, the feedback is taken from the BP node. When the M

is closed, the feedback

BATT

is taken from the BATT node. If M

is not populated, then the feedback node will always be taken from the BATT node.

BATT

The buck regulator core implements PWM in normal operation and auto-PFM modes PWM-PS mode during soft start. The

charger buck needs to be able to support 100% duty operation for cases when the input falls close to the output voltage. In this

mode, the high side PMOS is switched fully on, and the low side NMOS switch is disabled. The regulator will stay in 100% (or

close to it) duty-cycle mode until either BP rises above the CHRCV[5:0], under which case BP is clamped to a maximum of

CHRCV[5:0], or when the loop feedback demands a lower duty cycle. While in 100% duty cycle mode, the output current limit is

still operational. The CHRRCV is the point at which the battery charger enters the constant voltage mode from the constant

current mode. This is set to 3.6 V by default.

The buck charger can be disabled by software by setting the CHREN=0. It defaults to 1 on power up and is reset by RESETB,

so every time the PMIC goes into an off mode, the charger is re enabled. The CHRGEN signal disables linear and buck charging.

Table 64. Buck Charger Constant Voltage Settings

Buck Charge

Output Voltage (V)

Buck Charge

Output Voltage (V)

CHRCV[5:0]

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

3.50

3.52

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

4.00

4.02

4.04

4.06

4.08

4.10

4.12

4.14

4.16

4.18

4.20

4.22

4.24

4.26

4.28

4.30

4.32

4.34

4.36

3.54

3.56

3.58

3.60 (default)

3.62

3.64

3.66

3.68

3.70

3.72

3.74

3.76

3.78

3.80

3.82

3.84

3.86

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

77

Functional Block Description

Table 64. Buck Charger Constant Voltage Settings

Buck Charge

Output Voltage (V)

Buck Charge

Output Voltage (V)

CHRCV[5:0]

010011

010100

010101

010110

3.88

3.90

3.92

3.94

101100

101101

101110

101111

4.38

4.40

4.42

4.44

The control loop will monitor the voltage drop across the M

and the M

to limit the input current. This current input

AUXSW

VBUSSW

current limit is set automatically/manually by the input current limit, as detailed in Mini/Micro USB Switch. When the VBUS

connection is not in input current regulation mode, and the MANUAL S/W is 1, the USB current limit USBCHR[1:0] is set

automatically by detecting the charger connected connection and can select between 100 mA, 500 mA, and 950 mA current

limits (set by the USBCHR[1:0]). The AUX current limit can be set manually by setting the AUXILIM[2:0] bits and setting the

AUXWEAKEN =0. Changing the AUXWEAKEN=0 also disables the WKAUXDET interrupt. If AUXWEAKEN=1, then

WKAUXDET interrupt will be enabled, and the AUX input current will be configured in auto input current regulation mode. The

input current limit can be set to 1.5 A on both the USB, and AUX charge path by setting the ILIM_1P5 SPI bit = 1. When it is set

to a one, the USBCHR[1:0] and AUXILIM[1:0] settings are ignored. The ILIM_1P5 bit defaults to 0 on reset. The buck input current

limit does not apply to the trickle current. The VBUS input current can be overridden by setting the MANUAL S/W =0 and setting

the MUSBCHR[1:0] bits appropriately refer to Mini/Micro USB Switch for more details.

Table 65. Buck Input Current Limit Settings

Input Current Limit

ILIM_1P5 USBCHR[1:0] AUXILIM[2:0]

(mA)

1

0

XX

11

10

XXX

111

110

101

100

011

010

001

000

NA

1500

950

500

400

300

250

200

150

01

00

100

0 (off)

The charge constant current is programmable by SPI through CHRCC[3:0] bits in steps of 50 mA, from 250 mA to 1550 mA. The

constant charge current is set to 550 mA by default.

Table 66. Buck Charger Constant Current Limit Settings

Buck Charger Constant

Current Limit (mA)

Buck Charger Constant

Current Limit (mA)

CHRCC[3:0]

0000

0001

0010

0011

0100

0101

250

350

1000

1001

1010

1011

1100

1101

1050

1150

1250

1350

1450

1550

450

550 (default)

650

750

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

78

Functional Block Description

Table 66. Buck Charger Constant Current Limit Settings

Buck Charger Constant

Current Limit (mA)

Buck Charger Constant

CHRCC[3:0]

Current Limit (mA)

0110

0111

850

950

1110

1111

1550

Table 67. Buck Charger Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit

Notes

Buck Charger

f_CHRG

Operating Frequency

Quiescent Current

-

2.0

-

MHz

mA

I_CHRGQ

• PWM mode not switching

Charger Input

5.0

V_BUSIN

/

V

V_AUXIN

• VBUSVIN/AUXVIN

4.05

-

5.25

6.8

20

• Protection threshold VBUSVIN/AUXVIN

• Absolute max input VBUS/VIN (not operating)

-

6.5

16

Charger Restart Threshold

CHRG_RE

%

-

95.6

-

START-TH

• BATT relative to CHRGCV[5:0]

(59)

CHRCV Output Accuracy

CHR_CVACC

CHR_OVPTH

I_CHRINLIM

-1.0

-

1.0

-

%

Charger Over-voltage Protection Threshold

15

Charger Input Current Limit (using the USB input)

mA

• 100 mA

• 500 mA

• 950 mA

-

93

100

500

-

475

925

(59)

I_OUTACC

Output Current Accuracy

• CHRCC 250 – 600 mA

• CHRCC 600 – 1000 mA

• CHRCC 1000 –1550 mA

• Resuscitation

-15

-

15

%

-10

10

-5.0

-

5.0

-

12

70

-

mA

• TRICKLE1

• TRICKLE2

•TRICKLSEL = VCOREDIG

•TRICKLSEL = Floating

325

550

Notes

59. Battery charger works from BATTEMPL[1:0] (default 0 °C) to BATTTEMPH[1:0] (default 46 °C). Max range is from 0 to 60 °C.

7.6.3

Over-voltage Protection

In order to protect the application, the voltage at the VBUSVIN, and VAUX pins are monitored. When the above is 6.5 V typical,

the external pass FETs will be disabled.

For the VBUS charge path, it means opening M

. In the AUX path, it means opening M

while M

is closed. In the

BATT

VBUS

AUX path, it means opening M

. The corresponding interrupt VBUSOVP or AUXOVP is generated. When a V

over-voltage

AUX

BUS

is detected, the internal circuitry of the USB block is disconnected. The battery is also monitored for over-voltage conditions, and

the battery is protected by disabling the charger and setting the interrupt BATTOVP. In order to ensure immediate protection, the

control of M

, M

, and M

occurs real-time, asynchronously to the charger state machine.

VBUS

AUX

BATT

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

79

Functional Block Description

The interrupt for the over-voltage conditions on the battery is debounced by a programmable debounce period. VBUS and AUX

interrupts are debounced by SUP_OVP_DB[1:0]. When the over-voltage condition disappears for longer than the programmed

debounce time, charging will resume and previously programmed SPI settings will be reloaded. When a BATTOVP, AUXOVP,

or VBUSOVP interrupt is set, charging will not resume until the processor clears the interrupt.

Table 68. Over-voltage Debounce Time SUP_OVP_DB[1:0]

SUP_OVP_DB[1:0]

Debounce Time

00

01

10

11

0 (default 1.0)

2 RTC clock cycles

4 RTC clock cycles

8 RTC clock cycles (default 2.0)

Table 69. Over-voltage Debounce Time OVDB[1:0]

OVPDB[1:0]

Debounce Time

00

01

10

11

0 (default 2.0

2 RTC clock cycles

4 RTC clock cycles

8 RTC clock cycles (default 1.0)

7.6.4

Thermal Fold back

In order to protect the PMIC from overheating while charging, hardware based automatic thermal fold back is implemented. The

thermal fold back option is enabled by default (THFB_EN=1), but can be disabled by setting the SPI bit THFB_EN=0. The thermal

fold back is operational only when the buck input current limit is set to 1.5 Amps (ILIM_1P5 =1). With THFB_EN = 0 or

ILIM_1P5 = 0, firmware will still receive the interrupts when crossing the thresholds but it will be up to the software to fold back

the input current limit manually. The thermal fold back will monitor the die temperature to determine when to decrease the buck

current limit. There are four thresholds which the PMIC will fold back the input current limit as seen in Table 70. These are 110 C

(THERM110), 120 °C (THERM 120), 125 °C (THERM125), and 130 °C (THERM130C). The THERM1xx thresholds are

debounced by the SPI bits DIE_TEMP_DB[1:0], which are programmable from 100 s to 4.0 ms (1.0 ms by default). When the

die temperature crosses these thresholds the corresponding sense bit will change and an interrupt will be generated to notify the

software that the hardware is reaching its thermal limit. THFB_DLY[1:0] (defaults to 10 ms) sets the delay between the interrupt

being sent to the processor and the time that the PMIC takes action by folding back the buck input current limit to prevent the die

from heating up. For example with THFB_EN=1, ILIM_1P5 =1 and THFB_MODE = 0, if the die heats up to 115 °C, the

THERM110S bit will change state from a zero to a one, the THERM110C interrupt will be set, and the buck input current limit will

be set to 950 mA. Should the die continue to heat up to 123 °C then the THERM120S bit will be set and the THERM120 interrupt

will be generated and the buck current limit will be set to 500 mA. When the die temperature is greater than 130 °C the charger

will be disabled. The THFB_MODE bit allows the firmware to select two preset thermal fold back options when the die

temperature reaches the specified range.

Table 70. Thermal Fold Back Settings

Buck Input Current Limit (mA)

Condition (°C)

THERM110S

THERM120S

THERM125S

THERM130S

THFB_MODE = 0 THFB_MODE = 1

1500

950

500

300

Off

1500

950

500

Off

Die Temp< 110

110 < Die Temp < 120

120 < Die Temp < 125

125 < Die Temp < 130

130 < Die Temp

140

0

1

0

1

0

1

0

1

Thermal Shutdown

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

80

Functional Block Description

Table 71. Die Temp Debounce Settings

DIE_TEMP_DB [1:0]

Time

Units

00

01

0.100

1.0

ms

10

2.5

11 (default)

4.0

Table 72. Thermal Fold Back Delay Settings

THFB_DLY [1:0]

Time

Units

00

01

0

5

ms

10 (default)

11

10

15

7.6.5

Charge Source Input Thresholds

The VBUS and VAUX pins are monitored to detect when a valid charger is inserted. The PMIC will detect that a valid charger is

attached, when the VBUS voltage transitions above the setpoint, which is defaulted to 4.35 V. When above this threshold for

longer than the debounce period (VBUSDB[1:0]), the USBDET interrupt is generated and USBDETS is set to a one. When the

VBUS input falls below the VBUSTL[2:0] threshold, the USBDET interrupt is generated immediately without any debounce and

the USBDETS bit is low.

The MC34708 will detect a valid aux charger is attached when the VAUX voltage transitions above the VAUXTH[2:0] setpoint,

(default is 4.35 V). When above this threshold for longer than the debounce period by VAUXDB[1:0], the AUXDET interrupt is

generated and AUXDETS is set to a one. When the input falls below the AUXTL[2:0], the AUXDET interrupt is generated

immediately without any debounce and the AUXDETS bit is low.

Table 73. VBUS, VAUX High/low Threshold

VBUSTH[2:0]

VAUXTH[2:0]

VBUSWEAK[2:0]

VAUXWEAK[2:0]

VBUSTL[2:0]

VAUXTL[2:0]

Voltage

000

001

010

011

100

101

110

111

4.05

4.15

000 (default)

001

4.200

4.275

4.350

4.450

4.525

4.600

4.675

4.750

000

001

010

011

100

101

110

111

3.55

3.65

4.25

010

3.75

4.35 (default)

4.45

011

3.85 (default)

3.95

100

4.55

101

4.05

4.65

110

4.15

4.75

111

4.25

If input current regulation is enabled, when the VBUS voltage drops below the weak VBUSWEAK[2:0] threshold, the charger state

machine will enter input current regulation (due to a weak USB supply), and will decrease the input current limit one step below

its present value. If the USB voltage does not recover (rise back above VBUSWEAK[2:0]), the current limit will be reduced again.

Once the input current limit is at the minimum value (100 mA), if the supply still does not recover, the charger will be shut off and

the WKVBUSDET interrupt will be asserted. If this happens in less than 2.0 ms, the pending VINREGMINT interrupt will be

cancelled, and only the WKVBUSDET interrupt will be asserted. This functionality is enabled by default on power up by the

VBUSWEAKEN SPI bit high (default). The weak VBUS functionality can be disabled by setting the VBUSWEAKEN = 0. When

the following conditions exist: MBATT is present, the charger is capable of supplying 500 mA, the system is ON, the battery is

MC34708

Analog Integrated Circuit Device Data

81

Freescale Semiconductor

Functional Block Description

bellow 3.4 V, and the input current limit drops to less than 250 mA then, the PMIC will power down the rails. The PMIC will trickle

charge the battery and prohibit the system to power on until the battery reaches the 3.4 V threshold.

The AUX charge input regulation algorithm is different than the USB charge path. The AUX input regulation is enabled by setting

the AUXWEAKEN bit high. It can be disabled by setting the AUXWEAKEN bit low. If the AUXWEAKEN bit is set high, the AUX

charge path will continuously try to regulate the VAUX input to keep it between the VAUXWEAK[2:0] and the VAUXH[2:0]

thresholds. After the trickle charge has completed, the charger will turn on the buck at its lowest input current setting (100 mA),

and then slowly ramp up the current limit every 100 ms. If the VAUX voltage stays above the VAUXTH[2:0] threshold, the charger

will continue to ramp the buck input current limit up to the next setpoint. If the VAUX voltage crosses below the VAUXTH[2:0] and

stays above the VAUXWEAK[2:0] threshold, then the state machine will hold the current setpoint. If the VAUX threshold rises

above the VAUXH[2:0] threshold, the charger will continue increasing the input current limit. Should the VAUX cross below the

VAUXTWEAK[2:0] setpoint, the state machine will rapidly decrease the input current in 120 s steps. Once the input current limit

is at the minimum value (100 mA), if the supply still does not recover, the charger will be shut off and the WKAUXDET interrupt

will be asserted. When the following conditions exist: MBATT is present, the charger is capable of supplying >=500 mA, the

system is ON, the battery is bellow 3.4 V and the input current limit drops to less than 250 mA then, the PMIC will power down

the rails. The PMIC will trickle charge the battery and prohibit the system to power on, until the battery reaches the 3.4 V

threshold.

The VBUS and VAUX detectors are debounced by the VBUSDB[1:0] and VAUXDB[1:0] SPI bits defined in Table 74. These

debounce periods do not apply to input regulation modes.

Table 74. VBUS, VAUX Debounce Times

VBUSDB[1:0]

Debounce Time (ms)

VAUXDB[1:0]

00

01

10

11

0

10

20

30

7.6.6

Trickle Charge Settings

In cases of a deeply discharged battery, the battery will be charged via an internal trickle charge. An internal current source

between VBUSBIN/VAUXVIN and ITRIC provides small currents to the battery, when trickle charging a dead battery for the

resuscitation and I

modes. The I

mode will depend on how the TRICKLESEL pin is configured, as shown in

TRICKLE1

TRICKLE2

Table 75 and Table 76. If TRICKLESEL is grounded, the I

current will use the internal trickle charge path. If the

TRICKLE2

TRICKLESEL is tied to VCOREDIG or floating, then the buck charger will be enabled in constant current mode for I

.

TRICKLE2

I

is only valid for configurations where the M

FET is not present.

TRICKLE2

BATT

Trickle must auto recover from fault states when the fault no longer exists. The only exception is when the precharge timer has

expired (CHRTIMEEXP), then the trickle charge should stop and the CHRGLEDR should flash.

Table 75. Trickle Charger Settings

Parameter

BATT

Internal Trickle Charger

I_RESUSITATION

I_TRICKLE1

BATT<1.5 V

12 mA (linear)

70 mA (linear)

1.5 V<BATT <VBAT_TRKL

VBAT_TRKL <BATT<LOWBATT

I_TRICKLE2

Programmable via TRICKLESEL

When charging from a USB source, the mini-USB will automatically detect which charger is attached and will set the buck current

limit. If the mini-USB detects that a standard USB host is attached, it will set the USB buck input current limit USBCHRG[1:0] to

100 mA. The charger will transition from trickle1 to trickle 2 at the VBAT_TRKL[1:0] setpoint, as long as the M

FET is not

BATT

detected. If the M

FET is detected, then the trickle2 mode is not allowed, and the charger will charge at the trickle1 current

BATT

up to 3.4 V. If a standard USB host is detected and the TRICKLESEL pin is not grounded, the buck will turn on, but the USBCHRG

will limit the input current to 100 mA, to stay within the USB specification. Once the system boots up, it can negotiate for the

500 mA increased current, See Auto Detection of Charger.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

82

Functional Block Description

With the AUXWEAKEN bit set high, the charger will always go into current regulation mode. When trickle charging from an aux

path, the charger will always go into input current regulation mode. When transitioned from I

to I

, the state

TRICKLE1

TRICKE2

machine will ensure that the VAUX voltage is between the VAUXTH and VAUXWEAK thresholds. If it is, I

will be

TRICKLE2

maintained. If V

drops below the V

threshold, the trickle charger will decrease to the trickle1 setpoint. If an M

AUX

AUXWEAK BATT

FET is detected, trickle2 is not allowed and the state machine will continue trickle charging at the trickle1 setting.

With AUXWEAKEN set low, the input current regulation mode is disabled. The input current limit can be set manually as

described in Charger Input Current Limit Setting.

Table 76. Tricke2 Charger Current

TRICKLESEL pin

Trickle Charger Current (mA)

Mode

Ground

VCOREDIG

Floating

70 (linear)

Trickle1

Trickle2

325 (buck mode)

550 (buck mode)

The SPI bits VBAT_TRKL[1:0] set the trickle 1 to trickle 2 transition threshold, where the trickle current changes from trickle 1 to

the trickle 2 current set by the TRICKLESEL pin. This is only valid in configurations where the M FET is not detected. In

BATT

applications where the M

FET is present, the battery will continue to charge at the 70 mA rate until the battery reaches 3.4 V.

BATT

Table 77. VBAT_TRKL Voltage Setpoint (Dedicated charger)

VBAT_TRKL

Trickle1 to Trickle2 Voltage Threshold (V)

00

01

10

11

2.8

2.9

3.0 (default)

3.1

In the case of a dedicated charger, the trickle2 to constant current charge mode is based on the LOWBATT setpoint. When the

battery transitions from L to H (3.1 V, 3.2 V, 3.3 V, or 3.4 V), the buck charger will turn on and go into constant current mode.

Should the battery transition below the H to L threshold (3.0 V, 3.1 V, 3.2 V, or 3.3 V), the charger will revert to the trickle 2 charge

setpoint.

Table 78. LOWBATT Threshold

L to H transition (Power on)

LOWBATT

H to L transition (Low battery detect)

LOWBATT

LOWBATT[1:0]

00

01

3.1

3.2

3.3

3.4

3.0

3.1

3.2

3.3

10

11 (default)

7.6.7

Battery Thermistor Check Circuitry

A battery pack may be equipped with a thermistor, whose resistance decreases over temperature (NTC). In order to read the

thermistor value, it is biased from the NTCREF pin through a pull-up resistor (R ). The thermistor check circuit compares the

PU

voltage at BPTHERM with two programmed thresholds, BATTTEMPL[1:0] and BATTTEMPH[1:0]. In addition, the BPTHERM is

sent to the ADC on channel 7 to allow the software to readout the exact temperature of the battery. Charging is allowed when

the thermistor is within the range.

MC34708

Analog Integrated Circuit Device Data

83

Freescale Semiconductor

Functional Block Description

Table 79. Battery Thermistor Temp ranges

BATTTEMPH[1:0]

Temp (°C)

BATTTEMPL[1:0]

Temp (°C)

00

01

10

11

45 (default)

00

01

10

11

0 (default)

50

55

60

5

10

15

By default, the battery thermistor value is taken into account for charging the battery. Upon detection of a supply at VBUS/VAUX,

the core circuitry powers up. As soon as VCOREDIG is ready, the NTCREF is biased up to VCOREDIG, independent of the state

of the THERM SPI bit. The NTCREF is biased up whenever a battery is detected, the SPI THERM is set, or the charger is

detected (USB or AUX). The resulting voltage at BPTHERM is compared to the corresponding temperature thresholds,

BATTTEMPH and BATTTEMPL. If the voltage at BPTHERM is within range, the charging will behave as previously described.

However, if out of range, the charger state machine will go to a wait state, pause the pre-charge timers, and no current will be

sourced to the battery. When the temperature comes back in range, charging is continued again. The actual behavior depends

on the configuration the charger circuitry at the moment the temperature range is exceeded. The BPTHERM is optimize for a

24 kohm pull-up resistor to NTCREF, and the recommended NTC thermistor from Murata NCP15WB473F03RC or equivalent.

In applications where battery packs without a thermistor may be used, BATTTEMPH[1:0] and BATTTEMPL[1:0] should be left

as the default value and bias the BPTHERM to 0.991 V, in order to get within the temperature window.

7.6.8

Charge LEDs Indicators

Since normal LED control via the SPI bus is not always possible in the standalone operation (when the processor is off), two

current sinks are provided at the CHRGLEDR, and CHRGLEDG pins for LEDs connected to the LEDVDD and BP nodes,

respectively.

The CHRGLEDR will be activated when standalone charging is started and will remain under control of the state machine. When

charging is complete, the CHRGLEDR is disabled and the CHRGLEDG is activated. Software can take control over the charging

LEDs, even in standalone mode, by setting the CHRGLEDOVRD=1. When CHRGLEDOVRD=1, the CHRGLEDs are totally

controlled by software, so the state machine no longer has control. With CHRGLEDOVRD=0 (disabled), software cannot force

the LEDs on, but can still set the current.

Table 80. Charge LED Driver Control

CHRGLEDxEN

CHRGLEDx

CHRGLEDOVRD

0 (default)

Auto

On

0

1

0

Off

“x” represents for R, and G

The charging LED drivers CHRGLEDR, and CHRLEDG are independent current sink channels. Each driver channel features

programmable current levels via CHRGLEDx[1:0], as well as programmable PWM duty cycle settings with CHRGLEDxDC[5:0].

By a combination of level and PWM settings, each channel provides flexible LED intensity control. By driving LEDs of different

colors, color mixing can be achieved.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

84

Functional Block Description

Table 81. Charge LED Drivers Current Programming

CHRGLEDx[1:0]

CHRGLEDx Current Level (mA)

00

3.4

6.6 (default)

9.8

01

10

11

12.5

“x” represents for R, and G

Table 82. Charge LED Drivers Duty Cycle Programming

CHRGLEDxDC[5:0]

Duty Cycle

000000

0/32, Off

000001

1/32

…

010000

16/32

…

011111

…

31/32

1xxxxx

32/32, Continuously On

“x” represents R, and G

The charging LED drivers include ramp up and ramp down patterns implemented in hardware. Ramping is enabled for each of

the drivers using the corresponding CHRGLEDxRAMP bits, only when the repetition rate is 256 Hz.

The ramp itself is generated by increasing or decreasing the PWM duty cycle with a 1/32 step every 1/64 seconds. The ramp

time is therefore a function of the initial set PWM cycle and the final PWM cycle. As an example, starting from 0/32 and going to

32/32 will take 500 ms, while going to from 8/32 to 16/32 takes 125 ms.

Note that the ramp function is executed upon every change in PWM cycle setting. If a PWM change is programmed via the SPI

when CHRGLEDxRAMP=0, the change is immediate rather than spread out over a PWM sweep.

For color mixing and to guarantee a constant color, the color mixing should be obtained by the current level setting, so the

intensity is set through the PWM duty cycle.

In addition, programmable blink rates are provided. Blinking is obtained by lowering the PWM repetition rate of each of the drivers

through CHRGLEDxPER[1:0], while the on period is determined by the duty cycle setting. To avoid high frequency spur coupling

in the application, the switching edges of the output drivers are softened.

Table 83. Charge LED Drivers Period Control

CHRGLEDxPER[1:0]

Repetition Rate

Units

00

01

10

11

256

8

Hz

1

1/2

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

85

Functional Block Description

Table 84. Charge LED Modes in Standalone Mode

Repetition

Rate (Hz)

Duty

cycle

Current

(mA)

LED Mode

Color

Ramp

Charger off

Charging

Both off

1.0

Off

6.0

Off

Red on

32/32

steady state

Charging

fault

1.0

16/32

32/32

6.0

Off

Red flashing

Charge

Green on

complete steady state

Table 85. Charge LED Driver Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

Charge LED Driver

Absolute Accuracy

Matching - At 1.0 V, 12 nA

-

30

4.0

1.0

%

Leakage - CHRGLAEDxDC [5:0]=000000

A

7.6.9

Coulomb Counter

As indicated previously, the current in and out of the battery can be read out through the general purpose ADC as a voltage drop

over the R1 sense resistor. Together with battery voltage reading, the battery capacity can be estimated. A more accurate battery

capacity estimation can be obtained by using the integrated Coulomb Counter.

The Coulomb Counter (or CC) monitors the current flowing in/out of the battery by integrating the voltage drop across the battery

current sense resistor R1, followed by an A to D conversion. The result of the A to D conversion is used to increase/decrease

the contents of a counter that can be read out by software. This function will require a 10F output capacitor to perform a first

order filtering of the signal across R1. Due to the sampling of the A to D converter and the filtering applied, the longer the software

waits before retrieving the information from the CC, the higher the accuracy. The capacitor will be connected between the CFP

and CFM pins. See Figure 20.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

86

Functional Block Description

From

Charger

Path

ITRIC

SPI BITS

RESETB

BATTISNSP

BATTISNSCCP

CFP

CF

Coulomb

Counter

R1

CCOUT

20mOhm 10uF

CFN

BATTISNSCCN

BATTISNSN

BATT

CHRGFB

RTC

References

Figure 20. Coulomb Counter Block Diagram (Recommended)

To improve the CC reading/offset error a second 20 mOhm resistor can be used as shown in Figure 21.

From

Charger

Path

BATTISNSP

ITRIC

SPI BITS

RESETB

R1

20mOhm

BATTISNSN

BATTISNSCCP

CFP

CF

Coulomb

Counter

R2

CCOUT

20mOhm 10uF

CFN

BATTISNSCCN

BATT

CHRGFB

References

RTC

Figure 21. Coulomb Counter Block diagram (For improved CC readings)

The CC results are available in the 2’s complement CCOUT [15:0] counter. This counter is preferably reflecting 0.1 Coulomb per

LSB. As a reminder, 1 Coulomb is the equivalent of 1 Ampere during 1 second, so a current of 20 mA during 1 hour is equivalent

to 72 C. The 1-bit A to D output must first be decimated and converted to 16-bit resolution. The decimation filter is implemented

with an up/down counter and its bandwidth and gain are controlled by setting the ONEC[14:0] bits. The CCOUT[15:0] counter is

then increased or decreased by 1 with every ONEC[14:0] counts up or down of the decimation filter A to D converter. For

example, ONEC[14:0]= 0x0111 HEX = 273 DEC yields 0.1 C count per LSB of CCOUT[15:0] with R1=20 mOhm.

The coulomb counter resolution can be programmed to 100, 200, 500, or 1000 mC/LSB. By setting the CCRES[1:0] SPI bits, as

shown in Table 86. The CCRES[1:0] is set to 00 by default, so the CC resolution is 100 mC/LSB.

MC34708

Analog Integrated Circuit Device Data

87

Freescale Semiconductor

Functional Block Description

Table 86. Coulomb Counter Resolution

CCOUT

Resolution

mC/LSB

CCRES[1:0]

Dynamic Range Dynamic Range

(Coulombs)

(mA-Hrs)

00 (default)

100

200

+/- 3276.8

+/- 6553.6

+/- 16348.0

+/- 32768.0

+/- 910.2

+/- 1820.4

+/- 4551.1

+/- 9102.2

01

10

11

500

1000

The CC can be reset by setting the RSTCC bit. This will reset the digital blocks of the CC and will clear the CCOUT[15:0] counter.

The RSTCC bit is automatically cleared at the end of the reset period, which may take up to 40s. The CC is started by setting

the STARTCC bit. The CC is disabled by setting this bit low again. This will not reset the CC settings nor its counters, so when

restarting the CC with STARTCC, the count will continue.

While the CC is running it can be calibrated. An analog and a digital offset calibration is available.

The digital portion of the CC is by default permanently corrected for offset and gain errors. This function can be disabled by setting

the CCCALDB bit. However this is not recomended.

The CCCALA bit is set to calibrate the analog portion of the CC. This will disconnect the inputs of the CC from the sense resistor

and will internally short them together. The CCOUT[15:0] counter will accumulate the analog error over time. The calibration

period can be freely chosen by the implementer and depends on the accuracy required. By reading out the contents of the

CCOUT[15:0] and taking into account the calibration period, software can now calculate the error and account for it. Once the

calibration period has finished, the CCCALA bit should be cleared again.

One optional feature is to apply a dithering to the A to D converter, to avoid any error in the measurement due to repetitive events.

To enable dithering, the CCDITHER bit should be set. To make this feature operational, the digital calibration should remain

enabled, so the CCCALDB bit should not be set.

The CC is also used to measure battery charging current when the charger is in Constant Voltage mode, near the end of the

charging cycle. The measured charging current is compared to a programmable threshold to determine when an End of Charge

is reached. A charge complete signal is sent to the charger to indicate completion of the charging cycle.

When the CC is being used to determine the End of Charge, the SPI control bits STARTCC and RSTCC are overridden by

internal logic, to ensure CC is enabled and operating normally. This eliminates any possibility of missing the End of Charge event,

or of falsely declaring an End of Charge prematurely. Note that the ONEC value, CCRES value, and other SPI register values,

can still be actively changed during an End of Charge detection mode. This allows the application software to use a high

resolution setting, such as 100 mC/LSB and a short integration period for rapid End of Charge detection, even though a lower

resolution setting might have been used for Coulomb counting during normal system operation. If the user chooses different

ONEC and CCRES settings for an End of Charge detection vs. normal operation, the system fuel gauge software simply needs

to properly account for the different scale (resolution) of the CCOUT values in each mode, to maintain an accurate count of the

battery state of charge.

To be sure the contents of the CCOUT[15:0] are valid, a CCFAULT bit is available. CCFAULT will be set ‘1’ if the CCOUT counter

has a hardware overflow or underflow. Content is no longer valid, means the bit gets set when a fault condition occurs and stays

latched until cleared in software by writing a ‘1’ to the CCFAULT register. There is no interrupt associated to this bit. The following

fault conditions are covered.

Counter roll over: CCOUT[15:0]=0x8000 HEX

This occurs when the contents of CCOUT[15:0] go from a negative to a positive value or vice versa. Software may incorrectly

interpret the battery charge by this change in polarity. When CCOUT[15:0] becomes equal to 0x8000 HEX, the CCFAULT is set.

The counter stays counting so its contents can still be exploited.

In addition to the CCOUT[15:0] value and CCFAULT status bit discussed earlier, another output for the Coulomb counter digital

control logic is BATTCURRENT[11:0].

The BATTCURRENT value is a read-only value proportional to the current flowing through the sense resistor, which is the

average battery current during the INTEGTIME[1:0] measurement period. The INTEGTIME[1:0] bits select one of four different

integration periods for measuring battery current with the Coulomb counter: 4, 8, 16, or 32 seconds. The longer the integration

time period, the more accurate the battery current measurement, but longer integration times give less frequent updates.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

88

Functional Block Description

BATTCURRENT can be read through the SPI interface from the ACC2 register, and its value is converted to mA using the scale

factors in Table 87.

Table 87. BATTCURRENT Resolution

BATTCURRENT

CCRES[1:0]

INTEGTIME[1 :0]

Resolution in mA/LSB

00 (100 mC/LSB)

(default)

00 (4.0 sec)

25

01 (8.0 sec)

(default)

12.5

10 (16 sec)

11 (32 sec)

00 (4.0 sec)

01 (8.0 sec)

10 (16 sec)

11 (32 sec)

00 (4.0 sec)

01 (8.0 sec)

10 (16 sec)

11 (32 sec)

00 (4.0 sec)

01 (8.0 sec)

10 (16 sec)

11 (32 sec)

6.25

3.125

50

01 (200 mC/LSB)

10 (500 mC/LSB)

11 (1000 mC/LSB)

25

12.5

6.25

100

50

25

12.5

200

100

50

25

Table 88. Coulomb Counter Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V

= -5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

BUS

A

noted reflect the approximate parameter means at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

COULOMB COUNTER

Sense resistor R1

CCrsense

I_CC-RANGE

I_CC-ON

m

mA

A

• Placed in Battery path of Charger system

-

20

-

Sensed current

• Through R1

1.0

3000

On consumption

• CC active

-

10

-

Resolution

CC

C

RESOLUTION

• 1LSB Increment in CCOUT [15:0] with ONEC [14:0] = 1

366.2

7.6.10 Charger Operation

MC34708

Analog Integrated Circuit Device Data

89

Freescale Semiconductor

Functional Block Description

7.6.10.1 Auto Detection of Charger

The MC34708 will auto detect the type of the external power source and select one of two battery charge current levels, according

to the type. The MC34708 is capable of detecting the following types of accessories: USB host, dedicated charger, USB charger, 

A/V charger, and 5-wire type 1 or 2 chargers.

When a USB host is detected, the buck input current limit will be set to 100 mA. When the application turns on and negotiates

for the increased current, the input current limit can be increased by setting MUSBCHRG[1:0]= 10, along with setting the Manual

SW_B low.

When a 5-wire type (1 or 2), or an A/V charger is selected, the buck input current limit will be set to 500 mA.

When a USB charger or a dedicated charger is attached, the buck input current limit will be set to 950 mA by default. Software

can program the ILIM_1P5 SPI bit to increase the buck input limit to 1500 mA, if a USB charger is attached.

7.6.10.2 Standalone Charging

A standalone charge mode of operation is provided to minimize software interaction. It also allows for a completely discharged

battery to be revived without processor control. This is especially important when charging from a USB host, or when in single

path configuration (M

replaced by short, GBAT grounded).

BATT

Since the default voltage and charge current setting of the buck regulator may not be the optimum choice for a given application,

these values can be reprogrammed through the SPI by setting the CHRCC [3:0] and CHRCV[5:0] bits. The buck input current

limit can also be manually set by the MUSBCHRG[1:0] SPI bits and setting the Manual SW_B SPI bit low. See the Serial

Interfaces section for more information.

A USB host is only capable of supplying a 100 mA load current until the host has negotiated for the increased current. A system

is not capable of operating on 100 mA of current. Upon connecting a USB host with a dead battery, the input current limit is set

to 100 mA, the resuscitation trickle cycle is started, and the trickle current set to 12 mA, until the battery voltage reaches 1.5 V.

When the battery is between 1.5 V and VBAT_TRKL, the trickle current is set to 70 mA. With M

not present, the charger will

BATT

charge at the I

set point, from VBAT_TRKL to the LOWBATT threshold charger will charge at the I

setpoint.

TRICKLE2

When the battery voltage rises above the LOWBATT threshold, a power up sequence is automatically initiated. If the M

FET

BATT

is present the I

setpoint will be maintained up to the 3.4 V, at which point a power up sequence is initiated. When the

TRIKLE1

application turns on and successfully negotiates for the increased current, the input current limit can be increased by setting the

MUSBCHRG[1:0]= 10, along with setting the Manual SW_B low.

Upon connecting a dedicated charger, USB charger, a 5-wire type (1 or 2), or an A/V charger, to the USB charge path with a

dead battery, the behavior will be different for applications with an M

FET present and for those without an M

FET.

BATT

With M

present, the application will be powered with the buck charger input current limit set to either 500 mA (a 5-wire type

BATT

(1 or 2), or an A/V charger) or 950 mA (dedicated charger or USB charger), as determined by the mini-USB interface. The buck

will regulate the BP voltage to 3.6 V. MBATT will be open and the internal trickle charge current source will be enabled, set to

12 mA (resuscitation), up to 1.5 V. After it reaches 1.5 V, it will be set to the trickle1 setting of 70 mA, up to 3.4 V. Once the battery

is greater 3.4V, the MBATT FET will be closed and the battery will be connected to BP. The buck charger will take control of the

charging the battery in constant current mode via the CHRCC[3:0] bits, which will default to 550 mA.

With M

replaced with a short (GBAT grounded), the battery, and therefore BP, is below the LOW

[1:0] threshold. This

BATT

will be detected and the internal trickle path will be used to precharge the battery. The internal trickle will be set to 12 mA

(resuscitation), up to the 1.5 V level. Once the battery reaches 1.5 V level, the trickle current will transition to the trickle1 setting

of 70 mA, up to the VBAT_TRKL[1:0] setpoint. When the battery reaches the VBAT_TRKL threshold, the internal trickle charge

will transition to the trickle2 current set by TRICKLESEL. After the battery is charged to the LOWBATT[1:0] threshold, a turn on

event is generated and the buck charger will take control of the charging the battery in constant current mode, via the CHRCC[3:0]

bits, which default to 550 mA.

Upon connecting an aux charger to the aux charge path the application with a dead the behavior will be different for applications

with a M

FET present and for those without a M

FET.

BATT

With M

present, the charger will hold off enabling the system until the aux input current threshold has reached 500 mA

BATT

AUXILIM[2:0]. Once it reaches this limit the buck will regulate the BP voltage to 3.6 V. M

will be open and the internal trickle

BATT

charge current source will be enabled, set to 12 mA (resuscitation) up to 1.5 V, after it reaches 1.5 V, it will be set to the trickle1

setting of 70 mA up to the VBAT_TRKL[1:0] setpoint. Once the battery exceeds 3.4 V, the M FET will be closed and the

BATT

battery will be connected to BP. The buck charger will take control of the charging the battery in constant current mode via the

CHRCC[3:0] bits, which will default to 550 mA. If the aux input current limit does obtain the 500 mA limit, then the system will stay

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

90

Functional Block Description

off and the battery will continue to trickle charge until the battery has recovered to the 3.4 V threshold, and then the PMIC will

power on.

With M

replaced by a short (GBAT grounded), the battery, and therefore BP, is below the LOWBATT[1:0] threshold, this will

BATT

be detected and the internal trickle path will be used to precharge the battery. The input current limit is set to 100 mA, when the

VAUX voltage transitions above the VAUXTH threshold and the trickle cycle is started, the trickle current resuscitation current is

set to 12 mA (resuscitation), until the battery voltage reaches 1.5 V. When the battery is between 1.5 V and VBAT_TRKL, the

trickle1 current is set to 70 mA. When the battery voltage reaches the VBAT_TRKL threshold, the trickle current will be increased

to the I

current. If VAUX drops below the VAUXWEAK threshold, the trickle charger will decrease to the trickle1 setpoint.

TRICKLE2

The battery will charge to the LOWBATT threshold and the application will turn on.

The Precharge timer is set by the PRETMR pin, as shown in Table 89. The precharge will timeout and stop charging. If it did not

succeed in raising the battery to the LOWBATT[1:0] threshold, the interrupt CHRTIMEEXP will be generated. The precharge

timer applies to the total time it takes the battery to recover from the dead battery condition (caused by a resuscitation to trickle1

to trickle2).

Table 89. Precharge Timer Settings

PRETMR pin

Trickle Precharge Timer (Hrs)

Ground

VCOREDIG

Floating

4.5

5.5

6.5

The charging circuit will stop charging and generate an interrupt once the battery is fully charged. Clearing the CHRCMPLT

interrupt will immediately start a new charge cycle. To prevent this from immediately starting a new charge cycle, the charger

should be disabled by setting the CHREN = 0. If the CHRCMPLT interrupt is left asserted and the battery discharges below the

95.4% of the CHRGCV threshold, the charger will restart. To turn the charger buck off, the CHREN bit must be cleared. The

charge complete is detected by the charge current dropping below the charge current termination threshold CHRITERM[2:0].

The MC34708 uses the coulomb counter to determine the end of charge.

The hardware end of charge termination is enabled by the CHRITERMEN set to a 1. The hardware end of charge termination

can be disabled by setting the CHRITERMEN to a 0. With CHRITERMEN set to 0, it is up to the software to determine the end

of charge. The buck charger can be enabled or disabled at the end of charge by setting the SPI bit EOC_BUCK_EN. With

EOC_BUCK_EN =1, when the battery reaches end of charge, the buck will be enabled. With EOC_BUCK_EN =0, the buck will

be disabled when the battery reaches end of charge. Additional flexibility allows the battery to be connected or disconnected

where the M

FET is present. This allows the charger to be disconnected from the battery, to prevent the battery from float

BATT

charging (overcharging). When BATT_ISO_EN is set to a one, it takes priority over the EOC_BUCK_EN bit. With

BATT_IOS_EN =1, the M FET is opened when the charger detects an end of charge completion. The system will be powered

BATT

via the buck charger, regardless the state of EOC_BUCK_EN. To close the M

BATT_ISO_EN should be set to a 0.

FET during an end of charge, the

BATT

Table 90. End of Charge Operating Mode

BAT_ISO_EN EOC_BUCK_EN

Operating Mode

Buck off in charge complete. If

M_BATTdetected, it will be closed

0 (default)

Buck on in charge complete. If

0

1

0

1

M_BATTdetected, it will be closed

Buck on in charge complete. If

M_BATTdetected, it will be opened

Buck on in charge complete. If

M_BATTdetected, it will be opened

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

91

Functional Block Description

Table 91. Charge Termination Current Settings

CHRITERM[2:0]

Charger Termination Current (mA)

000

001

010

011

100

101

110

111

50

100

150

200

250

300

350

400

The charger will turn off the CHRGLEDR LED and illuminate the CHRGLEDG LED when the battery charging is complete. The

red charge LED CHRGLEDR will be on as long as the charger is charging. During a battery over-temperature, the CHRGLEDR

LED will continue to stay on. In the following fault conditions, USBOVP, AUXOVP, BATTOVP, CHRTIMEXP, WKVBUSDET, and

WKAUXDET, the CHRGLEDR LED will blink at the 1.0 Hz rate. Software can take control over the CHRGLEDs by setting the

CHRGOVRD bit.

During the constant current/constant voltage charge mode, the charge timer is running (CHRTMR). If the CHRTMR expires

before the CHRITERM limit is reached, the charging will be stopped and the CHRTIMEEXP interrupt generated. The charge timer

is programmable by the CHRTMR[3:0] SPI bits. It defaults to 12 hours on power up.

Table 92. Charger Timer Settings

Charge Time

(Hrs)

Charge Time

(Hrs)

CHRGTMR [3:0]

0000 (default)

0001

1

2

3

4

5

6

7

8

1000

1001

1010

1011

1100

1101

1110

1111

9

10

11

12

13

14

15

16

0010

0011

0100

0101

0110

0111

The detection of the transistor M

placed versus M

not placed is reflected through the CHRGSSS MBATTSNS bit. A logic

BATT

1 indicates M

is detected. If M

not placed, the GBAT pin must be left grounded.

BATT

The charging circuit will stop charging if the die temperature of the IC exceeds the thermal protection shutdown threshold. To re-

enable the charger, a turn on event is required.

7.6.10.3 Factory Mode

In factory mode, power is provided to the application with no battery present. This is only available on the USB charge path. It is

not a situation which should occur in the field. The factory mode is differentiated from a USB Host by and in addition to USBDET,

a UID being pulled to ground via a 64.9 k resistor, see Mini/Micro USB Switch.

With M

present, the application will be powered with the buck charger input current limit set to a typical 950 mA, and the

BATT

constant current charge setting to 950 mA. If the ILIM_1P5 SPI bit is set, the constant current charger current setting will be set

to 1500 mA, as will the input current limit. The transistor M is opened (non conducting) to separate BP from BATT, and the

BATT

internal trickle charge current source is not enabled. All the charger timers are disabled.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

92

Functional Block Description

With M

replaced by short, GBAT is grounded. The application powers up and the buck input current limit is set to 950 mA,

BATT

the constant current setting. All the charger timers are disabled. If the ILIM_1P5 SPI bit is set, the constant current charger current

setting will be set to 1500 mA, as will the input current limit.

In factory mode, input current regulation and thermal fold back regulation will be disabled. The input mode regulation interrupts

and the thermal fold back will assert, when the condition exists (if enabled and unmasked). With these interrupts, the processor

can take action to reduce the system current.

7.7

Analog to Digital Converter

The ADC core is a 10 bit converter. The ADC core and logic run at an internally generated frequency of approximately 1.33 MHz.

The ADC is supplied from VCORE. The ADC core has an integrated auto calibration circuit which reduces the offset and gain

errors.

7.7.1

Input Selector

The ADC has 16 input channels. Table 93 gives an overview of the characteristics of each of these channels.

Table 93. ADC Inputs

Channel

Signal read

Battery Voltage (BATTISNSN)

Battery Current (BATTISNSN-BATTISNSP)

Application Supply (BPSNS)

Die temperature

Input Level

Scaling

Scaled Version

0

1

0 – 4.8 V

-80 mV – +80 mV ⁽⁶⁰⁾

0 to 4.8 V

-40 – 150 °C

0 – 10 V

/2

x15

/2

0 – 2.4 V

-1.2 to +1.2 V

0 – 2.4 V

1.2 – 2.4 V

0 – 2.4 V

Reserved

0 – 2.4 V

2

3

Aux Charger Voltage (VAUX)

USB Voltage (VBUS)

Reserved

4

x0.24

x0.4

5

0 – 6.0 V

6

Reserved

0 – 2.4 V

Reserved

x1

Battery Thermistor (BPTHERM)

Coincell Voltage

7

8

0 – 3.6 V

X2/3

x1

ADIN9

9

0 – 2.4 V

ADIN10

10

11

12

13

14

15

0 – 2.4 V

x1

ADIN11

0 – 2.4 V

x1

ADIN12/TSX1

0 – 2.4 V

x1/x2

ADIN13/TSX2

0 – 2.4 V

ADIN14/TSY1

0 – 2.4 V

ADIN15/TSY2

0 – 2.4 V

Notes

60. Equivalent to -4.0 A to +4.0 A of current with a 20 mOhm sense resistor

Some of the internal signals are first scaled to adapt the signal range to the input range of the ADC. The battery current is

indirectly read out by the voltage drop over the resistor in the charge path and battery path respectively. For details on scaling,

see Dedicated Readings.

Table 94. ADC Input Specification

Parameter

Condition

Min Typ Max Units

Source Impedance

No bypass capacitor at input

-

5.0

30

kOhm

Bypass capacitor at input 10 nF

MC34708

Analog Integrated Circuit Device Data

93

Freescale Semiconductor

Functional Block Description

When considerately exceeding the maximum input of the ADC at the scaled or unscaled inputs, the reading result will return a

full scale. It has to be noted however, that this full scale does not necessarily yield a 1022 DEC reading due to the offsets and

calibration applied. The same applies for when going below the minimum input where the corresponding 0000 DEC reading may

not be returned.

7.7.2

Control

The ADC parameters are programmed by the processor via the SPI. When a reading sequence is finished, an interrupt

ADCDONEI is generated. The interrupt can be masked with the ADCDONEM bit.

The ADC is automatically calibrated every time the PMIC is powered on.

The ADC is enabled by setting ADEN bit high. The ADC can start a series of conversions through SPI programming by setting

the ADSTART bit. If the ADEN bit is low, the ADC will be disabled and in low power mode. The ADC is automatically calibrated

every time PMIC is powered.

The conversions will begin after a small analog synchronization of up to 30 microseconds, plus a programmable delay from 0

(default) up to 600 S, by programming the bits ADDLY1[3:0]. The ADDLY2[3:0] controls the delay between each of the

conversions from 0 to 600 S. ADDLY3[3:0] controls the delay after the final conversion, and is only valid when ADCONT is high.

ADDLY1, 2, and 3 are set to 0 by default.

Table 95. ADDLYx[3:0]

ADDLYx[3:0]

Delay in s

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

40

80

120

160

200

240

280

320

360

400

440

480

520

560

600

There is a max of 8 conversions that will take place when the ADC is started. The register ADSELx[3:0] selects the channel which

the ADC will read and store in the ADRESULTx register. The ADC will always start at the channel indicated in ADSEL0, and read

up to and including the channel set by the ADSTOP[2:0] bits. For example, when ADSTOP[2:0] = 010, it will request the ADC to

read channels indicated in ADSEL0, ADSEL1, and ADSEL2. When ADSTOP[2:0] = 111, all eight channels programmed by the

value in ADSEL0-7 will be read. When the ADCONT bit is set high, it allows the ADC to continuously loop and read the channels

from address 0 to the stop address programmed in ADSTOP. By default, the ADCONT is set low (disabled). In the continuous

mode, the ADHOLD bit will allow the software to hold the ADC sequencer from updating the results register while the ADC results

are read. Once the sequence of A/D conversions is complete, the ADRESULTx results are stored in 4 SPI registers (ADC 4 -

ADC 7).

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

94

Functional Block Description

7.7.3

Dedicated Readings

7.7.3.1

Channel 0 Battery Voltage

The battery voltage is read at the BATTISNSN pin on channel 0. The battery voltage is first scaled as V(BATT)/2 to fit the input

range of the ADC.

Table 96. Battery Voltage Reading Coding

Conversion Code

Voltage at Input ADC in V Voltage at BATTISNSN in V

ADRESULTx[9:0]

1 111 111 111

1 000 010 100

0 000 000 000

2.400

1.250

0.000

4.800

2.500

0.000

7.7.3.2

Channel 1 Battery Current

Battery current is only valid after a battery voltage reading. The current flowing into and out of the battery can be read via the

ADC by monitoring the voltage drop over the sense resistor between BATTISNSN and BATTISNSP.

The voltage difference between BATTISNSN and BATTISNSP is amplified to fit the ADC input range as V(BATTISNSP -

BATTISNSN)*15. Since battery current can flow in both directions, the conversion is read out in 2’s complement. Positive

readings correspond to the current flowing into the battery, and negative readings to the current flowing out of the battery.

Table 97. Battery Current Reading Coding

Conversion

Code ADRESULTx [9:0]

Voltage at input

ADC in mV

Current through

20 mOhm in mA

BATTISNSN–BATTISNSP in mV

Current Flow

0 111 111 111

0 000 000 001

0 000 000 000

1 111 111 111

1 000 000 000

1200.00

2.346

0

80

0.156

0

4000

7.813

0

To battery

-

-2.346

-1200.00

-0.156

-80

7.813

4000

From battery

The value of the sense resistor used determines the accuracy of the result, as well as the available conversion range. Note that

excessively high values can impact the operating life of the device due to extra voltage drop across the sense resistor.

7.7.3.3

Channel 2 Application Supply

The application supply voltage is read at the BP pin on channel 2. The battery voltage is first scaled as V(BP)/2 to fit the input

range of the ADC.

Table 98. Application Supply Voltage Reading Coding

Conversion Code

Voltage at Input ADC in V

Voltage at BP in V

ADRESULTx[9:0]

1 111 111 111

1 000 010 101

0 000 000 000

2.400

1.250

0.000

4.800

2.500

0.000

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

95

Functional Block Description

7.7.3.4

Channel 3 Die Temperature

The relation between the read out code and temperature is given in Table 99.

Table 99. Die Temperature Voltage Reading

Parameter

Min

Typ

Max

Unit

Die Temperature Read Out Code at 25 °C

Slope temperature change per LSB

Slope error

-

680

+0.426

-

Decimal

°C/LSB

%

5.0

The Actual Die Temperature is obtained as follows: Die Temp = 25 + 0.426 * (ADC Code - 680)

7.7.3.5

Channel 4 AUX Charger Voltage

The aux charger voltage is measured at the VAUX pin on channel 4. The aux charger voltage is first scaled in order to fit the input

range of the ADC by multiplying by 0.24.

7.7.3.6

Channel 5 VBUS Voltage

The VBUS voltage is measured at the VBUS pin on channel 5. The VBUS voltage is first scaled in order to fit the input range of

the ADC by multiplying by 0.4.

7.7.3.7

Channel 6 Reserved

Channel 6 is reserved.

7.7.3.8

Channel 7 Battery Thermistor

Channel 7 is used to read out the battery pack thermistor. The thermistor is biased to NTCREF (1.5 V) with an external pull-up.

The THERM SPI bit must be set high to enable the NTCREF voltage. To save current when the thermistor reading is not required,

the bias can be disabled by setting the THERM SPI bit low. A resistor divider network should assure the resulting voltage falls

within the ADC input range, especially when the thermistor check function is used. See Serial Interfaces.

When an application is on and supplied by the charger, a battery removal can be detected by a battery thermistor presence check.

When the thermistor terminal becomes high-impedance, the battery is considered removed. This detection function is available

at the BPTHERM input and can be enabled by setting the BATTDETEN bit. The voltage at BPTHERM is compared to the

NTCREF voltage, and when the voltage exceeds the battery removal detect threshold, the sense bit BATTDETBS is set high,

and after a debounce period the BATTDETBI interrupt is generated.

Table 100. Battery Removal Detect Specification

Parameter

Condition

Min

Typ

Max

Units

Battery Removal

Detect Threshold

31/32 *

NTCREF

V

-

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

96

Functional Block Description

7.7.3.9

Channel 8 Coin Cell Voltage

The voltage of the coin cell connected to the LICELL pin can be read on channel 8. Since the voltage range of the coin cell

exceeds the input voltage range of the ADC, the LICELL voltage is scaled as V(LICELL)*2/3. See .

Table 101. Coin Cell Voltage Reading Coding

Conversion Code

Voltage at ADC input (V) Voltage at LICELL (V)

ADRESULTx[9:0]

1 111 111 110

1 000 000 000

0 000 000 000

2.400

1.200

0.000

3.6

1.8

0

7.7.3.10 Channel 9-11 ADIN9-ADIN11

There are 3 general purpose analog input channels that can be measured through the ADIN9-ADIN11 pins.

7.7.3.11 Channel 12-15 ADIN12-ADIN15

If the touch screen is not used, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose inputs. They are

respectively mapped on ADC channels 12, 13, 14, and 15.

7.7.4

Touch Screen Interface

The touch screen interface provides all circuitry required for the readout of a 4-wire resistive touch screen. The touch screen X

plate is connected to TSX1 and TSX2, while the Y plate is connected to TSY1 and TSY2. A local supply TSREF will serve as a

reference. Several readout possibilities are offered.

If the touchscreen is not used, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose inputs. They are

respectively mapped on ADC channels 12, 13, 14, and 15.

Touch Screen Pen detection bias can be enabled via the TSPENDETEN bit in the AD0 register. When this bit is enabled and a

pen touch is detected, the TSPENDET bit in the Interrupt Status 0 register is set and the INT pin is asserted - unless the interrupt

is masked. Pen detection is only active when TSEN is low.

The reference for the touch screen (Touch Bias) is TSREF and is powered from VCORE. During touch screen operation, TSREF

is a dedicated regulator. No loads other than the touch screen should be connected here. When the ADC performs non touch

screen conversions, the ADC does not rely on TSREF and the reference is disabled.

The readouts are designed such that the on chip switch resistances are of no influence on the overall readout. The readout

scheme does not account for contact resistances, as present in the touch screen connectors. The touch screen readings will

have to be calibrated by the user or the factory, where one has to point with a stylus to the opposite corners of the screen. When

reading the X-coordinate, the 10-bit ADC reading represents a 10-bit coordinate, with ‘0’ for a coordinate equal to X-, and full

scale ‘1023’ when equal to X+. When reading the Y-coordinate, the 10-bit ADC reading represents a 10-bit coordinate, with ‘0’

for a coordinate equal to Y-, and full scale ‘1023’ when equal to Y+. When reading contact resistance, the 10-bit ADC reading

represents the voltage drop over the contact resistance created by the known current source, multiplied by 2.

The X-coordinate is determined by applying TSREF over the TSX1 and TSX2 pins, while performing a high-impedance reading

on the Y-plate through TSY1. The Y-coordinate is determined by applying TSREF between TSY1 and TSY2, while reading the

TSX1 pin. The contact resistance is measured by applying a known current into the TSY1 pin of the touch screen and through

the TSX2 pin, which is grounded. The voltage difference between the two remaining terminals TSY2 and TSX1 is measured by

the ADC, and equals the voltage across the contact resistance. Measuring the contact resistance helps determine if the touch

screen is touched with a finger or a stylus.

The TSSELx[1:0] allows the application processor to select its own reading sequence. The TSSELx[1:0] determines what is read

during the touch screen reading sequence, as shown in Table 102. The Touchscreen will always start at TSSEL0 and read up

to and including the channel set by TSSEL at the TSSTOP[2:0] bits. For example when TSSTOP[2:0] = 010, it will request the

ADC to read channels indicated in TSSEL0, TSSEL1, and TSSEL2. When TSSTOP[2:0] = 111, all eight addresses will be read.

MC34708

Analog Integrated Circuit Device Data

97

Freescale Semiconductor

Functional Block Description

Table 102. Touch Screen Action Select

TSSELx[1:0]

Signals Sampled

00

01

10

11

Dummy to discharge TSREF cap

X plate

Y –plate

Contact

The touch screen readings can be repeated, as in the following example readout sequence, to reduce the interrupt rate and to

allow for easier noise rejection. The dummy conversion inserted between the different readings allows the references in the

system to be pre-biased for the change in touch screen plate polarity. It will read out as ‘0’.

A touchscreen reading will take precedence over an ADC sequence. If an ADC reading is triggered during a touchscreen event,

the ADC sequence will be overwritten by the Touchscreen data.

The first Touch screen conversion can be delayed from 0 (default) to 600 s by programming the TSDLY1[3:0] bits. The

TSDLY2[3:0] controls the delay between each of the touch screen conversions from 0 to 600 s. TSDLY[2:0] sets the delay after

the last address is converted. TSDLY1, 2, and 3 are set to 0 by default.

Table 103. TSDLYx[3:0]

TSDLYx[3:0]

Delay in uS

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

40

80

120

160

200

240

280

320

360

400

440

480

520

560

600

To perform a touch screen reading, the processor must do the following:

• Enable the touch screen with TSEN

• Select the touch screen sequence by programming the TSSEL0-TSSEL7 SPI bits.

• Program the TSSTOP[2:0]

• Program the delay between the conversion via the TSDLY1 and TSDLY2 settings.

• Trigger the ADC via the TSSTART SPI bit

• Wait for an interrupt indicating the conversion is done TSDONEI

• And then read out the data in the ADRESULTx registers

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

98

Functional Block Description

7.7.5

ADC Specifications

Table 104. ADC Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol Characteristic

Min

Typ

Max

Unit Notes

ADC

Conversion Current

-

1.0

-

mA

V

Converter Core Input Range

V_ADCIN

• Single ended voltage readings

• Differential readings

0.0

-

2.4

1.2

-1.2

Conversion Time per channel

Integral Non-linearity

Differential Non-linearity

Zero Scale Error (Offset)

Full Scale Error (Gain)

Drift over temperature

Turn on/off time

t_CONVERT

-

10

3.0

1.0

5.0

10

1.0

31

s

LSB

s

t_ON-OFF-ADC

Source Impedance

Z_SOURCE

k

• No bypass capacitor at input

• Bypass capacitor at input 10 nF

-

5.0

30

BATTERY CURRENT READING⁽⁶¹⁾

Amplifier Gain

19

-2.0

-

20

-

21

2.0

-

Amplifier Offset

mV

Sense Resistor

20

m

DIE TEMPERATURE VOLTAGE READING

Die Temperature Read Out Code at 25 °C

-

680

0.426

-

Decimal

°C/LSB

%

Slope temperature change per LSB

Slope error

5.0

-

V_BATTREMTH

31/32 *

NTCREF

V

Battery Removal Detect Threshold

Notes

61. Amplifier Bias Current accounted for in overall ADC current drain

MC34708

Analog Integrated Circuit Device Data

99

Freescale Semiconductor

Functional Block Description

7.8

Auxiliary Circuits

7.8.1

General Purpose I/Os

The MC34708 contains 4 configurable GPIO input/outputs for general purpose use. When configured as outputs, they can be

configured as open-drain (OD) or CMOS (push-pull outputs). These GPIOs are low voltage capable (1.2 or 1.8 V). In open drain

configuration these outputs can only be pulled up to 2.5 V maximum.

Each individual GPIO has a dedicated 16-bit control register. Table 105 provides detailed bit descriptions.

Table 105. GPIOLVx Control

SPI Bit

Description

DIR

GPIOLVx direction

0: Input (default)

1: Output

DIN

DOUT

Input state of the GPIOLVx pin

0: Input low

1: Input High

Output state of GPIOLVx pin

0: Output Low

1: Output High

HYS

Hysteresis

0: CMOS in

1: Hysteresis (default)

DBNC[1:0]

GPIOLVx input debounce time

00: no debounce (default)

01: 10 ms debounce

10: 20 ms debounce

11: 30 mS debounce

INT[1:0]

GPIOLVx interrupt control

00: None (default)

01: Falling edge

10: Rising edge

11: Both edges

PKE

ODE

DSE

PUE

Pad keep enable

0: Off (default)

1: On

Open drain enable

0: CMOS (default)

1: OD

Drive strength enable

0: 4.0 mA (default)

1: 8.0 mA

Pull-up/down enable

0: pull-up/down off

1: pull-up/down on (default)

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

100

Functional Block Description

Table 105. GPIOLVx Control

SPI Bit

Description

PUS[1:0]

Pull-up/Pull-down enable

00: 10 K active pull-down

01: 10 K active pull-up

10: 100 K active pull-down

11: 100 K active pull-up (default)

SRE[1:0]

Slew rate enable

00: slow (default)

01: normal

10: fast

11: very fast

x= 0, 1, 2, or 3

7.8.2

PWM Outputs

There are two PWM outputs on the MC34708 PWM1 and PWM2 and which are controlled by the PWMxDUTY and

PWMxCLKDIV registers shown in Table 106.The base clock will be the 2.0 MHz divided by 32.

Table 106. PWMx Duty Cycle Programming

PWMxDC[5:0](⁽⁶²⁾

)

Duty Cycle

000000

000001

…

0/32, Off (default)

1/32

…

010000

…

16/32

…

31/32

011111

1xxxxx

32/32, Continuously On

Notes

62. “x” represent 1 and 2

32.768 kHz Crystal Oscillator RTC Block Description and Application Information

Table 107. PWMx Clock Divider Programming

PWMxCLKDIV[5:0](⁽⁶³⁾

)

Duty Cycle

000000

000001

…

Base Clock

Base Clock / 2

…

001111

…

Base Clock / 16

…

111111

Base Clock / 64

Notes

63. “x” represent 1 and 2

MC34708

Analog Integrated Circuit Device Data

101

Freescale Semiconductor

Functional Block Description

7.8.3

Mini/Micro USB Switch

The MC34708 is able to multiplex the 5 pins to support UART and high-speed USB2.0 data communications, a mono/stereo-

audio/microphone headset, or other accessories. To identify what accessory is plugged into the Mini or Micro-USB connector,

the MC34708 supports various detection mechanisms, including the VBUS detection and ID detection. A highly accurate 5-bit

ADC is offered to distinguish the 32 levels of ID resistance, and to identify the button pressed in a cord remote control, while an

Audio Type 1 cable is attached. After identifying the accessory attached, the MC34708 configures itself to support the accessory

2

and interrupts a host via the INT pin. The processor can evaluate what caused the interrupt via the SPI/I C bus. The MC34708

is also able to identify some non-supported accessories, such as video cables, phone-powered devices, etc.

GND

To/From

Mini-USB

Connector

ID

Detect

ID

VBUS

GOTG

MVBUS

MPD

VBUSVIN

VBUS

Detect

M0

M1

VUSB

Regulator

MOTG

VINUSB

VUSB

SWBST (5.0 V boosted supply)

3.3 V USB Analog supply

VINUSB2

VUSB2

BP

VUSB2

Regulator

2.5V USB Analog supply

TXD

RXD

DP

To/from

Mini-USB

Connector

UART

Switches

DM

To/From

Application

Processor

D+

D-

USB

Switches

SPKR

To/From

Audio IC

SPKRL

Audio

Switches

MIC

VBUS

Figure 22. USB Interface

7.8.3.1

Supplies

The MC34708 provides the regulators required to power the PHY in the i.MX50, i.MX51, and i.MX53 processors, which are

VUSB2 (detailed Serial Interfaces), and VUSB. The IC also provides the 5.0 V supply for USB OTG operation. The MC34708 is

capable of identifying the type of the external power source, and selecting one of two battery charge current levels, according to

the type. Refer to Serial Interfaces.

The VUSB regulator is used to supply 3.3 V to the external USB PHY. The input to the VUSB regulator can be supplied from the

VBUS wire of the cable when supplied by a host (PC or Hub), or by the SWBST voltage via the VINUSB pin. The VUSB regulator

is powered from the SWBST boost supply to ensure OTG current sourcing compliance through the normal discharge range of

the main battery. The VUSBSEL SPI bit is used to make the selection between a host or OTG mode operation.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

102

Functional Block Description

Table 108. VUSB Input Source Control ⁽⁶⁴⁾

Parameter

Value

Function

Powered by Host: VBUS powers VUSB regulator (switch M0 closed and M1 open)

0

1

V_USBSEL

OTG mode: SWBST internally switched to supply the VUSB regulator (switch M1 closed, M0 open), and

SWBST will drive VBUS from the VINUSB pin as long as SPI bit OTGEN is set = 1.

Notes

64. VUSBSEL = 1 and OTGEN = 1 only close the switch between the VINUSB and VBUS pins, but do not enable the SWBST boost

regulator (which should be enabled with SWBSTEN = 1)

The VUSB regulator defaults to ON when PUMS4:1 = [0100], and is supplied by the SWBST output. As shown in Figure 22 above

this means that the M0 and MOTG switches are open, while the M1 switch is closed.

When PUMS4:1 is not equal to [0100], the VUSB regulator can not be enabled unless 5.0 V is present on the VBUS pin. If VBUS

is detected during a cold start, then the VUSB regulator will be enabled and powered ON in the sequence shown in Serial

Interfaces, and it will default to be supplied by the VBUS pin. This means that switch M0 is closed and switch M1 and MOTG in

Figure 22 are open. If VBUS is not detected at cold start, then the VUSB regulator cannot be enabled. If VBUS is detected later,

the VUSB regulator will be enabled automatically be enabled and supplied from the VBUS pin. The VUSBEN SPI bit is initialized

at startup, based on the PUMS4:1 configuration. With PUMS4:1 not equal to [0100], the VUSBEN SPI bit will default to a one on

power up and will reset to a 1, when either RESETB is valid or VBUS is invalid. This allows the VUSBEN regulator to be enabled

automatically if the VUSB regulator was disabled by software. With PUMS4:1 equal to [0100], the VUSBEN bit will be enabled in

the power up sequence.

The MC34708 also supports USB OTG mode by supplying 5.0 V to the VBUS pin. The OTGEN SPI bit along with the VUSBSEL

SPI bit, control switching the SWBST to drive VBUS in OTG mode. When OTGEN = 1 and VUSBSEL = 1, SWBST will be driving

the VBUS (switch M1 and MOTG are closed, and the M0 switch is open). In OTG mode, the MVBUS switch should be opened

and the MPD switch closed to isolate the charge input from VBUS. When OTG mode is disabled, the switch (MOTG) from

VINUSB to VBUS will be open.

In OTG mode, the VUSB regulator is enabled by setting the VUSBEN SPI bit to a one. When SWBST is supplying the VBUS pin

(OTG Mode), it will generate a USBDET interrupt. The USBDET interrupt while in OTG mode should not be interpreted as being

powered by the host by software.

Table 109. VUSB/OTG Switch Configuration

Mode

VUSB powered from VBUS pin

VUSB powered from VINUSB pin

Invalid option

OTGEN VUSBSEL Switches Enabled (Closed) Switches Disabled (Open)

0

1

0

1

0

1

M0

M1

M1, MOTG

M0, MOTG

OTG Mode (VUSB powered from VINUSB pin and SWBST

M1, MOTG

M0, MVBUS, MPD

Since VBUS is shared with the charger input at the board level (see Serial Interfaces), the VBUS node must be able to withstand

the same high voltages as the charger. The VUSB regulator is disabled and switches M0 and MOTG are opened in over-voltage

conditions.

MC34708

Analog Integrated Circuit Device Data

103

Freescale Semiconductor

Functional Block Description

Table 110. VUSB Electrical Characteristics

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

BUS

A

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

VUSB REGULATOR

Operating Input Voltage Range V_INMINto V_INMAX

• Supplied by VBUS

V_USBIN

V

4.4

-

5.0

-

5.25

5.75

• Supplied by SWBST

Operating Current Load Range IL_MINto IL_MAX

Bypass Capacitor Value Range

I_USB

0.0

-

100

-

mA

F



CO_VUSB

ESR_VUSB

0.65

2.2

Bypass Capacitor ESR

• 10 kHz - 1.0 MHz

0.0

-

0.1

VUSB ACTIVE MODE - DC

Output Voltage V_OUT

V_USB

V

mV/mA

mV

• V_INMIN< V_IN< V_INMAXIL_MIN< IL < IL_MA

V_NOM- 4%

3.3

V_NOM+ 4%

Load Regulation

V_USBLOPP

V_USBLIPP

V_USBSCTH

t_OFF-VUSB

• 0 < IL < IL_MAXfrom DM / DP, For any V_INMIN< V_IN< V_INMAX

-

1.0

-

20

-

Line Regulation

• V_INMIN< V_IN< V_INMAX, For any IL_MIN< IL < IL_MAX

-

Short-circuit Protection threshold

mA

• V_INMIN< V_IN< V_INMAX, Short-circuit V_OUTto ground

I_MAX+20%

Turn-off Time

sec

• Disable to 0.8 V, per USB OTG specification parameter

VA_SESS_VLD V_IN= V_INMIN, V_INMAXIL = 0

-

1.3

VUSB ACTIVE MODE - AC

PSRR - IL = 75% of IL_MAX20 Hz to 20 kHz

VUSB_PSRR

dB

• V_IN= V_INMIN+ 100 mV

35

40

-

Output Noise - V_IN= V_INMINIL = 75% of IL_MAX

• 100 Hz – 50 kHz

VUSB_NOISE

V/Hz

-

1.0

0.2

• > 50 kHz – 1.0 MHz

7.8.3.2

Accessory Identification

The PC34708 monitors both the ID pin and the VBUS pin. When an accessory attachment is detected, the accessory

identification state machine will enter Active mode to start the identification flow. The ID detection state machine will determine

what ID resistor is attached and the Power Supply Type Identification or PSTI circuit will determine what type of power supply is

connected.

An identification conclusion is made when the identification flow is finished. The corresponding bit in the USB Device Type/Status

register is set to indicate the device type, and the ATTACH bit in the USB Interrupt Status register is set to inform the baseband.

If the attached accessory can't be identified, the Unknown_Atta bit in the USB Interrupt Status register is set.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

104

Functional Block Description

There are three types of accessories that the MC34708 will automatically detect.

1. Recognized and supported. The following accessories are identified and configured automatically: USB port, dedicated

charger, USB charger, A/V charger, 5-wire type 1 and type 2 chargers, UART, Audio Type 1 cable, TTY accessory, USB

jig cables, and UART jig cables.

2. Recognized but not supported. The following accessories can be identified but are not supported by the MC34708 PMIC:

A/V cables, Phone-Powered Devices, and Audio Type 2 cables.

3. Not recognized accessories. All accessories that are not recognized are identified as unknown accessories.

Reset

Yes

VBUS_DET?

No

Active

Detection

Delay

(Identification

Flow)

Yes

ID_FLOAT?

No

Standby

DP  0.6V

No

ID_DET_EN

D?

Yes

R_ID< 100?

Yes

DM > 0.8V

ADC = 00000

No

Yes

No

Start ADC to

measure R_ID

No

Video cable?

R_ID= 75?

DM < 0.4V?

Yes

USB-OTG

No

A/V_CHG = 1

R_ID= Video

cable?

Yes

No

ID_FLOAT?

USB host

ID_FLOAT

DM  0.6V

No

Video

cable

No

UART jig

cable w/

boot option

Yes R_ID= UART

jig w/ boot?

ID_DET_EN

D?

Dedicated

Charger

No

DP < 0.4V?

Yes

No

ID_DET_EN

D?

Audio

Type 1

Yes R_ID= Audio

No

Yes

Type 1 ?

UART jig

cable w/o

boot option

R_ID= UART

jig w/o boot?

Yes

No

USB

Charger

R_ID

=

Yes

TTY

Converter

Yes

R_ID= TTY

Converter?

440k?

USB jig

cable w/

No

R_ID= USB

jig w/ Boot?

Yes

No

boot option

Phone

Powered

Device

No

R_ID

=

No

102k?

R_ID

=

5-Wire

Charger

UART

Cable

Yes R_ID= UART

USB jig

cable w/o

boot option

200k?

No

Cable?

R_ID= USB

Yes

jig w/o Boot?

No

Audio

Type2

Cable

R_ID= Audio

Type2

Cable?

No

Yes

No

Unknown

No

Stuck Key

Process

Yes

R_ID= remote

key?

Figure 23. Identification Flow State Diagram

7.8.3.3

Id Identification

A comparator monitors the ID pin impedance to ground. When a resistor less than 1.0 M is connected between the ID line and

the ground, the ID_FLOATS bit in the Interrupt Sense 0 register will be set to 0. When the resistor is removed, the ID_FLOATS

bit will be set to 1. A falling edge of this bit starts the identification flow, and a rising edge starts the detachment detection flow.

The ID_DET_END signal is used to indicate the end of the identification.

After the ID_FLOATS bit is set to 0, the identification flow is started, and an ADC_EN signal is set to enable an ADC conversion.

A 5-bit ID ADC is used to measure the ID resistance. The ADC is also used to identify what button is pressed in a cord remote

control when the attached accessory is an Audio Type 1 cable.

When the conversion completes, an ADC_STATUS bit is set and the ADC result value is sent to the ADC Manual SW/Result

register. The ADC_EN signal is cleared automatically after the conversion finishes.

If the ID resistance is below 2.0 k, the ADC Result is set to 00000. If the ID line is floating, the ADC Result is set to 11111.

MC34708

Analog Integrated Circuit Device Data

105

Freescale Semiconductor

Functional Block Description

7.8.3.4

Stuck Key Identification

When the ADC conversion is finished and the ADC result is found to be a value corresponding to a remote control key of Audio

Type 1 cable, a stuck key process flow will be initiated to determine whether a remote control key is stuck and to inform the

baseband of the stuck key status.

Figure 24 shows the stuck key process flow. If the stuck key is detected to be released within 1.5 s, the flow will return to re-start

the ID identification flow. Otherwise, a Stuck_Key Interrupt is set. When the key is released, a Stuck_Key_RCV Interrupt is

generated, and the identification flow is re-started to determine the ID resistance of the attached cable.

Figure 24. Stuck Key Process Flow Diagram

7.8.3.5

Power Supply Type Identification

The PSTI (Power Supply Type Identification) circuit is used in Active mode to identify the type of the connected power supply.

The PSTI circuit first detects whether the DP and DM pins are shorted. If the DP and DM pins are found to be shorted, the PSTI

circuit will continue to determine whether DP and DM pins are a forward short or reverse short. The detection result, together

with the ID detection result, is used to determine what powered accessory is connected.

The PSTI circuit is shown in Figure 25. Its operation is described as follows.

When the MC34708 detects that the VBUS_DET bit is set, the PSTI identification flow starts.

1. Wait for a Detection Delay t (programmable in the USB Time Delay register).

D

2. During t , check to see whether ID_FLOAT = 0. If yes, then wait for the ID_DET_END to be set and check whether the

D

attached accessory is an A/V cable.

3. If the result is an A/V cable, set the A/V_CHG and ATTACH interrupt bits, as well as the A/V bit in USB Device Type/Status

register, to inform the baseband and finish the identification flow. If not, go to step 4.

4. Enable the PSTI (PSTI_EN set to '1') at t1. When PSTI_EN rises, the SW1 switch is turned on to drive the VDAT_SRC

data source voltage to DP line. In the meantime, the SW2 switch is turned on so the IDAT_SINK current source sinks a

current from the DM line. At t2, the PSTI starts to compare the DM line voltage with references VDAT_REF and VCR_REF.

If the DM line voltage stays above VDAT_REF, but below VCR_REF for 20 ms continuously before t4, which means that

the DP and DM pins are shorted, the DP/DM_short signal is set to '1' at t3. Go to step 5. If the DP and DM are not shorted,

the VBUS detection completes at t4 and the VBUS_DET_END is set to '1'. The state machine will go to step 6 to

determine the type of accessory, based on the DM voltage.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

106

Functional Block Description

5. The state machine checks if the ID pin is floating. If the ID pin is not floating at t3, the PSTI circuit turns off SW1 and SW2,

and the VBUS detection completes. The VBUS_DET_END is set to '1' and the state machine goes to step 6. If the ID pin

is floating at t3, the PSTI circuit turns off SW1 and SW2, and then turns on SW3 and SW4 to force VDAT_SRC to the DM

pin. If the DP pin is between the two thresholds VDAT_REF and VCR_REF for 20 ms continuously before t6, it means that

the DP and DM pins are a reverse short.The DP/DM_reverse_short is set to '1' at t5, the SW3 and SW4 are turned off,

VBUS_DET_END is set to '1', and the state machine goes to step 6. If DP and DM are not a reverse short, the VBUS

detection completes at t6, SW3 and SW4 are turned off, the VBUS_DET_END is set to '1', and the state machine goes to

step 6.

6. The state machine decides on the attached accessory, based on the ID identification, and the VBUS identification results.

Figure 25. Power Supply Type Identification Circuit Block Diagram

Figure 26. Operating Waveforms for the PSTI Circuit

MC34708

Analog Integrated Circuit Device Data

107

Freescale Semiconductor

Functional Block Description

Table 111. Timing Delays for PSTI Circuit

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

BUS

A

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

Switching Delay

ms

t_D

t1 - t0 (t_Din Default Value is TD = 0100)

-

100

200

300

400

500

...

-

• TD = 0000

• TD = 0001

• TD = 0010

• TD = 0011

• TD = 0100

• ...

-

...

-

...

-

• TD = 1111

1600

t2 - t1

t_SW

20

-

ms

t3 - t2

t4 - t1

t6 - t3

100

The MC34708 contains registers which hold control and status information. The register map and the description of each register

can be found in the SPI/I2C Register Map section. The details of some important control bits are described as follows.

7.8.3.6

Control Functions

7.8.3.6.1

Timing of the Switching Action (WAIT BIT)

If the WAIT bit is '1' when the Attach interrupt bit is set, the MC34708 waits for a WAIT time before turning on the switches. The

WAIT time is programmed by the Switching Wait bits in the Timing Set 2 register. If the WAIT bit is '0' when the Attach interrupt

is generated, then the MC34708 will not turn on the switches until the WAIT bit is set to '1' by the SPI. Both cases are shown in

Figure 27.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

108

Functional Block Description

Figure 27. Operating Waveforms of the Wait Bit

7.8.3.6.2

Automatic Switching OR Manual Switching (Switch_open & Manual S/W Bits)

When a supported accessory is identified, the default behavior of the MC34708 automatically turns on the corresponding signal

switches. The user can also choose to turn on optional signal switches manually. Switch turn on is controlled by the Manual 

S/W bit and the Switch_Open bits in the USB Manual SW/Result and USB Control/Device mode registers respectively.

If the Switch_Open bit is '0', the audio, UART, and USB switches are off.

If Manual S/W = 1, which is its reset value, the switches to be turned on and the outputs of the JIG and BOOT pins are determined

automatically by the Device Mode register, which is the identification result. If Manual S/W = 0, the switches to be turned on are

determined by the values of the USB Manual SW/Result register. The relationship between the values of the USB Manual SW/

Result register and the switches to be turned on is found in SPI/I2C Register Map section.

The values of the Switch_Open and Manual S/W bits will not affect the identification flow and the timing of the signal switching

action of the MC34708. The difference between Manual S/W = 1 and Manual S/W = 0 is what switches are turned on. In both

cases, no switches are turned on in Standby mode. If the Manual S/W bit is changed from '1' to '0' while an accessory is attached,

the already automatically turned on switches will be turned off, and the switches selected manually will be turned on. However,

writing the Manual S/W bit back to '1' in Active mode will not change the switches and outputs status. Setting the

Switch_Open = 1, sets the switches according to the Manual S/W bit.

Raw Data (Raw Data Bit)

The RAW DATA bit functions only when the accessory is Audio Type 1, which supports the remote control key. The RAW DATA

bit determines whether to report the ID pin resistance change to the baseband when any key is pressed. When RAW DATA = 1,

the ADC is enabled only when an ID line event is detected, such as when a key is pressed. In this case, the interrupt bits KP,

LKP, or LKR, and the corresponding button bits in Button 1 and Button 2 registers, will be set accordingly. Detailed behavior

information when RAW DATA = 1 can be found in Audio Type 1 Operation Mode.

Audio Device Type 1 - Audio with or without the Remote Control. When RAW DATA = 0, the ADC is enabled periodically to

calculate the ID line resistance. Any change of ADC Result will set the ADC_Change interrupt bit to inform the baseband. The

baseband can read the ADC result via the SPI. The KP, LKP, or LKR, and the button bits, will not set when RAW DATA = 0. The

period of ADC conversion is determined by the Device Wake-up bits in the USB Timing register. All other behaviors of Audio

MC34708

Analog Integrated Circuit Device Data

109

Freescale Semiconductor

Functional Block Description

Type 1 and other accessories will not be affected by the RAW DATA bit. LKR and the button bits will not set when RAW DATA = 0.

The period of ADC conversion is determined by the Device Wake-up bits in the Timing Set 1 register. All other behaviors of Audio

Type 1 and other accessories will not be affected by the RAW DATA bit.

7.8.3.7

Analog and Digital Switches

The signal switches in the MC34708 are shown in Figure 28. These switches are controlled by the identification result when the

Manual S/W = 1, and by the Manual SW/Result register, when the Manual S/W = 0 is in Active mode. The Switch_Open bit

overrides the switch configuration. When the Switch_Open bit is 0, all switches are turned off. The switches for the SPK_L and

SPK_R are capable of passing signals of 1.5 V, referencing to the GND pin voltage. The SPK_L and SPK_R pins are pulled

down to GND via a 100 k resistor respectively, as shown in Figure 28. When the switches are configured automatically by the

identification result, the configuration of the switches vs. the device type is shown in Table 112.

When detachment of an accessory is detected, the MC34708 will return to Standby mode. In Standby mode, regardless of the

Manual S/W = 1 or Manual S/W = 0 state, all signal switches and are off in the Standby mode. The OUT-to-ground FET is turned

on whenever the FET_ON bit is '0'.

DP

DM

RxD

TxD

SW1

SW2

SW3

D+

D-

SW6

SW7

SW4

SPK_R

SPK_L

SW5

VBUS

MIC

GOTG

MVBUS

M0

M1

VUSB

LDO

MOTG

VBUSVIN

MPD

VINUSB

Figure 28. Analog and Digital Switches

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

110

Functional Block Description

Table 112. Switch Configuration When Controlled by the Device Type Register

Device Type

Audio

USB

UART

USB CHG

Dedicated CHG

On SW#

Off SW

4, 5, 7, MPD

MOTG, MVBUS, M0

5WT1 CHG

3, 6, MVBUS

MPD ⁽⁶⁵⁾

1, 2

3, 6, MVBUS

MPD ⁽⁶⁵⁾

MVBUS

MPD ⁽⁶⁵⁾

TTY

(65)

Device Type

5WT2 CHG

JIG_USB_ON

JIG_USB_OFF

JIG_UART_ON

JIG_UART

On SW#

Off SW

MVBUS

3, 6, MVBUS

MPD ⁽⁶⁵⁾

3, 6

4, 5, 7, MPD

MPD ⁽⁶⁵⁾

MOTG, MVBUS, M0

(65)

Notes

65. Switches M0, M1, and MOTG are controlled by software by the OTGEN and VUSBSEL bits.

7.8.3.8

Audio Type 1 Operation Mode

Audio Type 1 accessories have the same interface shown in Figure 29, either stereo or mono, with or without a remote control,

or with or without a microphone. When a device, such as a microphone is not connected to the accessory, the corresponding pin

in the mini-USB connector will be left floating. With the normal operation setting of the control bits, the accessory is identified as

an Audio Type 1 device, the analog switches SW4 and SW7 for SPK_R to DP, SPK_L to DM, and SW5 for VBUS to MIC are

turned on, the MPD switch is turned on, and the MOTG, MVBUS, and M0 switches are turned off, to isolate the VBUS pin.

The MC34708 supports the remote control key for an Audio Type 1 device. If the RAW DATA = 0, the ADC is turned on

periodically to monitor the ID line change caused by the key press. The period is programmed by the Device Wake-up bits. If the

ADC Result changes, the ADC_Change bit in the USB Interrupt Sense register is set to inform the baseband. If the RAW

DATA = 1, a comparator is enabled to monitor the key press. The timing of the key press when RAW DATA= 1 is shown in

Figure 30. If a key is pressed for a time less than 20 ms, the MC34708 ignores it. If the key is still pressed after 20 ms, the

MC34708 starts a timer to count the time during which the key is kept pressed. There are three conditions according to the press

time: Error key press, short key press, and long key press.

1. Error key press: if the key press time is less than TKP, the Error bit in the USB Button register and the short key press bit

KP in USB Interrupt Sense register are set to indicate that an error happens. The Error bit is reset to '0' when the USB

Button register is read or the next key press happens. The KP bit is cleared when the Interrupt 1 register is read.

2. Short key press: if the key press time is between TKP and TLKP, the KP bit and the corresponding button bit in USB

Button are set to inform the baseband. If the ADC result is not one of the ADC values of the 13 buttons, the Unknown bit in

the Button 2 register is set. The INT pin is driven high when the key is released and returns to low when the interrupt

register is read. The KP bit is cleared when the USB Interrupt Sense register is read.

3. Long key press: if the key press time is longer than TLKP, the long key press bit LKP in the USB Interrupt Sense register,

and the corresponding button bit, are set to inform the baseband. If the ADC Result is not one of the ADC values of the 13

buttons, the Unknown bit in the USB Button register is set. When the key is released, the long key release bit LKR in the

Interrupt 2 register is set to interrupt the baseband again.

MC34708

Analog Integrated Circuit Device Data

111

Freescale Semiconductor

Functional Block Description

Figure 29. Audio Accessory with Remote Control and Microphone

Figure 30. Operation of the Headset with Remote Control and Microphone

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

112

Functional Block Description

T_KP

T_LKP

20ms

Key

Press

Error

KP

Button Register read

INT

Interrupt Status 0 Register KP bit written to a one

KP

Interrupt Status 0 Register KP bit written to a one

INT

LKP

LKR

INT

ADC

Time

Interrupt Status 0 Register

LKR bit written to a one

Interrupt Status0 Register

LKP bit written to a one

Figure 31. Remote Control Key Press Timing

The ID detection circuit continues to be ON for detaching detection in the Active mode, and samples the ID line every interval

programmed by the device wake-up bits in the USB Timing register. When the ID_FLOAT rising edge is detected, the Detach bit

in the USB Interrupt Sense register is set to inform the host the accessory is detached. The MC34708 then enters Standby mode.

7.8.3.9

JiG Cable USB and UART

The JIG cable is used for test and development and has an ID resistance to differentiate it from a regular USB cable. The Jig

cable has 2 ID resistance values to resemble a USB JIG type1/2, and 2 ID resistance values to resemble a UART JIG type1/2

cable.

7.8.3.9.1

USB JIG Cable 1 or 2

Under normal operation, setting the control bits when the identified accessory is a USB JIG 1 or 2 cable, both the DPLUS to DP,

the DMINUS to DM switches are switched on, the MVBUS switch is ON, and the MPD switch is off.

When SW_HOLD = 0, the switching action of DPLUS to DP, and the DMINUS to DM switches are controlled by the WAIT bit. If

WAIT = 1, the signal switches will be turned ON after a WAIT. If WAIT = 0, the signal switches won't be turned on until the WAIT

2

bit is set to '1' by the SPI/I C. When SW_HOLD = 1, regardless of what the WAIT is set to, '0' or '1', the signal switches are turned

on, once the USB JIG cable is identified.

The ID detector and the VBUS detector both monitor the detachment of the USB JIG cable. The ID detection circuit continues to

be ON for detachment detection in the Active mode. When the ID_FLOAT is set, the Detach bit in the Interrupt Status 0 register

is set to inform the host. When the USBDETS is set to '0', which means either the VBUS power is removed or the cable is

detached, the Detach bit is also set to inform the host. The mini USB interface moves to the Standby mode. If the Detach bit is

set, due to the removing only the VBUS or the ID resistance, and the cable is not detached completely, the identification flow will

MC34708

Analog Integrated Circuit Device Data

113

Freescale Semiconductor

Functional Block Description

be triggered again. The ID_FLOAT bit or USBDETS bit still indicate that an accessory is connected when the mini USB interface

moves to the Standby mode. All the signal switches are turned off

7.8.3.9.2

UART JIG Cable 1 or 2

Under normal operation, setting the control bits when the identified accessory is a UART JIG cable 1 or 2, both the RxD to DP

and the TxD to DM switches are switched on.

When SW_HOLD = 0, the switching action of RxD to DP, and the TxD to DM switches, are controlled by the WAIT bit. If WAIT = 1,

the signal switches will be turned on after a WAIT time. If WAIT = 0, the signal switches won't be turned on until the WAIT bit is

2

set to '1' by the SPI/I C. When SW_HOLD = 1, regardless of what the WAIT is set to, '0' or '1', the signal switches are turned on,

once the UART JIG cable is identified.

The ID detection comparator continues to be ON for detachment detection in the Active mode. When the ID_FLOAT is set, the

Detach bit in the Interrupt Status 0 register is set to inform the host that the accessory is detached. The mini USB interface then

enters the Standby mode.

7.8.3.10 TTY Operation Mode

A TTY converter is a type of audio accessory. It has its own ID resistance. When a TTY converter is attached, this sets the TTY

bit in the USB Device Type register and the Attach interrupt bit in the Interrupt Status 0 register. During normal operation, when

setting the control bits, the automatic switch configuration of the TTY converter, is similar to that of an Audio Type 1 accessory.

The SPK_R to DP switch, and MIC to VBUS switch are turned on, but the SPK_L to DM switch can only be turned on when

TTY_SKPL bit in USB Control register is manually set to 1. In addition, the MPD switch is also turned on, the MOTG, MVBUS,

and M0 switches are turned off to isolate the VBUS pin.The TTY accessory doesn’t support the remote control key. The Power

Save mode operation and the detachment detection are the same as those of the Audio Type 1 device.

7.8.3.11 UART Operation Mode

During normal operation, when setting the control bits, when the identified accessory is a UART cable, both the RxD and the TxD

switches are switched on (see Figure 32).

The ID detection comparator continues to be ON for detachment detection in the Active mode. When the ID_FLOAT is set, the

Detach bit in the USB interrupt Sense register, is set to inform the host that the accessory is detached. The MC34708 USB

detection then enters Standby mode.

Baseband

VBUSVIN

MP D

GOTG

MVBUS

UART

Cable

UART

Interface

VBUS

Det

VBUS

RxD

TxD

DP

D+

D-

UART

DM

ID

ADC

ID Det

`

GND

SHLD

Figure 32. UART Operation

7.8.3.12 USB Host (PC or HUB) Operation Mode

When the attached accessory is a USB host or hub, the ID pin floats. During normal operation, when setting the control bits, both

the D PLUS to DP and the D MINUS to DM switches are switched on (see Figure 33), and the MVBUS is turned on to allow the

charger to start. The mini USB interface sets the charger input current limit and sets the bit USB in the USB Device type register.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

114

Functional Block Description

When SW_HOLD = 0, the switching action of D+ to DP and the D- to DM switches, are controlled by the WAIT bit. If WAIT = 1,

the signal switches will be turned on after a WAIT time. If WAIT = 0, the signal switches won't be turned on until the WAIT bit is

set to '1' by the SPI. When SW_HOLD = 1, regardless of what the WAIT is set to, '0' or '1', the signal switches are turned on once

the USB host is identified.

After the DPLUS to DP and the DMINUS to DM switches are turned on, the baseband can pull the DPLUS signal high to start

the USB attaching sequence.

The detachment is detected by the falling edge of the USBDETS signal. When the USBDETS falls, the Detach bit is set to inform

the baseband. The MC34708 USB detection then enters the Standby mode.

Baseband

VBUSIN

MP D

GOTG

MVBUS

USB

Cable

USB

Host

VBUS

Det

VBUS

5V

DPLUS

DP

D+

D-

USB Xcvr

DMINUS

DM

ID

ADC

ID Det

GND

SHLD

Figure 33. USB Operation

7.8.3.13 USB charger or Dedicated Charger Operation Mode

When the attached accessory is a USB Charger or Dedicated Charger, the MC34708 turns on the MVBUS to allow the charger

to start, sets the charger input current limit by setting the USBCHRG [1:0] = 11 (950 mA), and sets the bit USB Charge or the

Dedicated CHG in the USB Device type register. During normal operation when setting of the control bits, the D PLUS and D

MINUS switches are turned on for the USB Charger, but not for the Dedicated Charger.

The VBUS detector is used to monitor the detachment of the charger. The falling edge of USBDETS is an indication of charger

detachment. Unplugging the mini-USB connector and unplugging the ac side, both lead to the same detachment conclusion. The

Detach bit is set to inform the host. The MC34708 USB detection then enters the Standby mode.

7.8.3.14 5-Wire Charger or A/V Charger Mode

When the attached accessory is a 5-Wire Charger or A/V Charger, the MC34708 turns on the MVBUS switch, to allow the charger

to start, configures the input current limit to the charger (500 mA), and sets the appropriate device type 5.0 W CHG or A/V in the

USB device type register.

The VBUS detector is used to monitor the detachment of the charger. The falling edge of USBDETS is an indication of the charger

detachment. Both unplugging the mini-USB connector and unplugging the ac side lead to the same detachment conclusion. The

Detach bit is set to inform the host. Then the MC34708 USB detection enters the Standby mode.

7.8.3.15 Charger Input Current Limit Setting

When the Manual SW_B bit is set to 1, the MC34708 automatically detects what device is attached, and configures the charger

input current by setting the USBCHGRG[1:0] signals (these are internal signals and not SPI bits). There is an option of overriding

the automatic detection thresholds, by setting the SPI bit Manual SW_B low, and then the charger input current limit can be

programmed via the MUSBCHRG[1:0] SPI bits in the USB Control register.

MC34708

Analog Integrated Circuit Device Data

115

Freescale Semiconductor

Functional Block Description

Table 113. Charger Input Current Limit Settings

USBCHRG[1:0] (Internal Signal)

MUSBCHRG[1:0]

Charger input

Current Limit (mA)

Device type detected in

Auto mode

00

01

10

11

Disable Charger

100

500

950

USB Host

5-Wire, AV charger, USB JIG

USB Charger, Dedicated

charger, Factory mode

7.8.3.16 Unknown Accessory Operation Mode

When an unknown accessory is attached, the ID_FLOAT bit is cleared or the USBDETS bit is set to '1'. Only the Unknown_Atta

bit is set to interrupt the baseband. The Attach bit is not set to distinguish the unknown accessory from the known accessory. No

other actions are taken. If an unknown powered accessory is attached, the switch MVBUS is turned on during the identification

process, and the switch MVBUS will be turned off immediately when the accessory is identified as an unknown accessory.

The falling edge of the USBDETS or the rising edge of the ID_FLOAT signals can trigger the detachment detection. The Detach

bit is set to inform the detachment of the unknown accessory. The USB detection then enters the Standby mode.

7.8.3.17 Software Reset

The USB detection supports a software reset, which is realized by writing the Reset bit in the USB Control register to 1. The

consequence of the software reset is the same as the hardware reset. All register bits reset by the Mini-USB will be reset.

Table 114. ID Detection Thresholds

UID Pin External

UID Pin Voltage ⁽⁶⁶⁾

0.18 * VCORE < UID < 0.77 * VCORE

0 < UID < 0.12 * VCORE

IDFLOATS IDGNDS IDFACTORYS

Accessory

Connection

Non-USB accessory is attached (per

CEA-936-A spec)

0

1

0

1

0

1

Resistor to Ground

A type plug (USB default slave) is

attached (per CEA-936-A spec)

Grounded

Floating

B type plug (USB Host, OTG default

master or no device) is attached.

0.89 * VCORE < UID < VCORE

3.6 V < UID (1)

Voltage Applied

Notes

Factory mode

66. UID maximum voltage is 5.25 V

7.8.3.18 ID Resistance Value Assignment

The ID resistors used are standard 1% resistors. Table 115 lists the complete 32 ID resistor assignment. Those with the Assigned

Functions filled are ones that are already used with special functions. The ones reserved can be assigned to other functions.

Table 115. ID Resistance Assignment

Item#

ADC Result

ID Resistance K

Assignment

0

1

2

3

4

00000

00001

00010

00011

00100

<1.9

2.0

Reserved

S0

S1

S2

S3

2.604

3.208

4.014

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

116

Functional Block Description

Table 115. ID Resistance Assignment

Item#

ADC Result

ID Resistance K

Assignment

5

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

4.820

6.03

8.03

10.03

12.03

14.46

17.26

20.5

24.07

28.7

34.0

40.2

49.9

64.9

80.6

102

S4

S5

6

7

S6

8

S7

9

S8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

S9

S10

S11

S12

UART JIG Cable 2

UART JIG Cable 1

USB JIG Cable 2

USB JIG Cable 1

Factory Mode

Audio Type 2

PPD

121

Reserved

UART

150

200

5W Type 1

Reserved

A/V

255

301

365

442

5W Type 2

Reserved

TTY

523

619

1000

-

Audio Type 1

ID float

The remote control architecture is illustrated in Figure 34. The recommended resistors for the remote control resistor network are

given in Table 116.

ID

R₁

R₂

R₁₃

R₃

…...

R₁₄

SEND/END

HOLD

/

GND

Figure 34. Remote Control Architecture

MC34708

Analog Integrated Circuit Device Data

117

Freescale Semiconductor

Functional Block Description

Table 116. ID Remote Control Values

Resistor

Standard Value K

ID Resistance

R1

R2

2.0

0.604

0.806

1.21

2.0

2.604

3.208

4.014

4.82

R3

R4

R5

R6

6.03

R7

8.03

R8

2.0

10.03

12.03

14.46

17.26

20.5

R9

2.0

R10

R11

R12

R13

R14

2.43

2.8

3.24

3.57

590/976

24.07

614/1000

7.8.3.19 USB Interface Electrical Specifications

Table 117. USB Interface Electrical Characteristics

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Power Input

I_DM

Characteristic

Min

Typ

Max

Unit Notes

Detection Module Quiescent Current

A

• In Standby mode

-

2

3

• When accessory is attached & INT_MASK = ‘1’

125

550

850

160

650

1000

• In Active mode (V_DD< V_BUS

)

VBUS Supply Quiescent Current

• In VBUS Power mode

I_VBUS

mA

-

1.5

1.2

0.5

• In Active mode - Dedicated Charger

• In Active mode - Audio or TTY

Accessory Detect Switch

SPK_L and SPK_R Switches



• On resistance (20 Hz to 470 kHz)

• Matching between channels

R_{SPK_ON}

R_{SPK_ONMCT}

R_{SPK_ONFLT}

-

30

3.0

0.3



• On resistance flatness (from -1.2 to 1.2 V)

D+ and D- Switches

R_{USB_ON}

R_{USB_ONMCT}

-

5.0

0.1

8.0

1.0

0.4

• On resistance (0.0 Hz to 240 MHz)

• Matching between channels

• On resistance flatness (from 0.0 to 3.3 V)

R_{USB_ONFLT}

0.02

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

118

Functional Block Description

Table 117. USB Interface Electrical Characteristics

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

RxD and TxD Switches

• On resistance



R_{UART_ON}

R_{UART_ONFLT}

-

60

• On resistance flatness (from 0.0 to 3.3 V)

6.0

MIC Switches



• On resistance (at 1.5 V MIC bias voltage)

R_{MIC_ON}

-

75

150

-

Pull-Down Resistors between SPK_L or SPK_R Pins to GND

R_{PD_AUDIO}

100

k

Signal Voltage Range

• MIC

V

-

1.5

3.6

• SPK_L, SPK_R

• D+, D-, RxD, TxD

-1.5

-0.3

PSRR - From BP (100 mVrms) to DP/DM Pins

V_{A_PSRR}

dB

%

• 20 Hz to 20 kHz with 32/16  load.

-

-60

0.05

-50

Total Harmonic Distortions

T_HD

• 20 Hz to 20 kHz with 32/16  load.

Crosstalk between Two Channels

V_{A_CT}

dB

• 20 Hz to 20 kHz with 32/16  load.

Off Channel Isolation

• Less than 1.0 MHz

V_{A_ISO}

-100

Power Supply Type Identification

Data Source Voltage

V_{DAT_SRC}

V

• Loaded by 0~200 μA

0.5

0.0

0.3

0.8

0.6

-

0.7

200

0.4

1.0

Data Source Current

Data Detect Voltage

Car Kit Detect Voltage

I_{DAT_SRC}

V_{DAT_REF}

V_{CR_REF}

I_{DAT_SINK}

μA

V

0.35

0.9

V

Data Sink Current

μA

• DM pin is biased between 0.15 to 3.0 V

65

-

100

8.0

135

-

DP, DM Pin Capacitance

C_DP/DM

R_DP/DM

pF

DP, DM Pin Impedance

M

• All switches are off (Switch_Open = 0)

-

50

-

ID Detection

ID FLOAT Threshold

• Detection threshold

V_FLOAT

V

-

2.3

20

-

t_{ID_FLOAT}ID FLOAT Detection Deglitch Time

ms

IID

Pull-up Current Source

μA

• When ADC Result is 1xxxx

• When ADC Result is 0xxxx

1.9

2.0

32

2.1

30.4

33.6

Video Cable Detection

• Detection current

I_VCBL

1.0

1.2

50

1.4

mA

mV

• Detection voltage low threshold

• Detection voltage high threshold

V_{VCBL_L}

V_{VCBL_H}

-

118

MC34708

Analog Integrated Circuit Device Data

119

Freescale Semiconductor

Functional Block Description

Table 117. USB Interface Electrical Characteristics

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

BUS

A

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

t_VCBL

Video Cable Detection Time (Video Cable Detection Current Source On

Time)

ms

-

20

-

t_{RMTCON_DG}Key Press Comparator Debounce Time

ms

-

20

-

7.9

Serial Interfaces

The IC contains a number of programmable registers for control and communication. The majority of registers are accessed

2

through a SPI interface in a typical application. The same register set may alternatively be accessed with an I C interface that is

2

muxed on SPI pins. Table 118 describes the muxed pin options for the SPI and I C interfaces; further details for each interface

mode follow.

Table 118. SPI / I²C Bus Configuration

Pin Name

SPI Mode Functionality

Configuration ⁽⁶⁷⁾, Chip Select

I²C Mode Functionality

Configuration ⁽⁶⁸⁾

CS

CLK

SPI Clock

SCL: I²C bus clock

MISO

MOSI

Notes

Master In, Slave Out (data output)

Master Out, Slave In (data input)

SDA: Bi-directional serial data line

A0 Address Selection ⁽⁶⁹⁾

67. CS held low at Cold Start, configures the interface for SPI mode; once activated, CS functions as the SPI Chip Select.

68. CS tied to VCOREDIG at Cold Start, configures the interface for I²C mode; the pin is not used in I²C mode, other than for configuration.

69. In I²C mode, the MOSI pin is hardwired to ground, or VCOREDIG is used to select between two possible addresses.

7.9.1

SPI Interface

The IC contains a SPI interface port which allows access by a processor to the register set. Via these registers the resources of

the IC can be controlled. The registers also provide status information about how the IC is operating, as well as information on

external signals.

2

Because the SPI interface pins can be reconfigured for reuse as an I C interface, a configuration protocol mandates that the CS

pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin). The state of CS is latched in during

2

the initialization phase of a Cold Start sequence, ensuring that the I C bus is configured before the interface is activated. With

the CS pin held low during startup (as would be the case if connected to the CS driver of an unpowered processor due to the

integrated pull down), then the bus configuration will be latched for SPI mode.

The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The

addressable register map spans 64 registers of 24 data bits each. The map is not fully populated, but it follows the legacy

conventions for bit positions corresponding to common functionality with previous generation FSL products.

7.9.1.1

SPI Interface Description

For a SPI read, the first bit sent to the IC must be a zero indicating a SPI read cycle. Next, the six bit address is sent MSB first.

This is followed by one dead bit to allow for more address decode time. The MC34708 will clock the above bits in on the rising

edge of the SPI clock. Then the 24 data bits are driven out on the MISO pin on the falling edge of the SPI clock so the master

can clock them in on the rising edge of the SPI clock.

For each MOSI SPI transfer, first a one is written to the write/read_b bit if this SPI transfer is to be a write. A zero is written to the

write/read_b bit if this is to be a read command. If a zero is written, then any data sent after the address bits are ignored and the

internal contents of the field addressed do not change when the 32nd CLK is sent.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

120

Functional Block Description

For a SPI write the first bit sent to the MC34708 must be a one indicating a SPI write cycle. Next the six bit address is sent MSB

first. This is followed by one dead bit to allow for more address decode time. Then the data is sent MSB first. The SPI data is

written to the SPI register whose address was sent at the start of the SPI cycle on the falling edge of the 32nd SPI clock.

Additionally, whenever a SPI write cycle is taking place the SPI read data is shifted out for the same address as for the write

cycle. Next the 6-bit address is written, MSB first. Finally, data bits are written, MSB first. Once all the data bits are written then

the data is transferred into the actual registers on the falling edge of the 32nd CLK.

The CS polarity is active high. The CS line must remain high during the entire SPI transfer. For a write sequence it is possible for

the written data to be corrupted, if after the falling edge of the 32nd clock the CS goes low before it's required time. CS can go

low before this point and the SPI transaction will be ignored, but after that point the write process is started and cannot be stopped

because the write strobe pulse is already being generated and CS going low may cause a runt pulse that may or may not be wide

enough to clock all 24 data bits properly. To start a new SPI transfer, the CS line must be toggled low and then pulled high again.

The MISO line will be tri-stated while CS is low.

The register map includes bits that are read/write, read only, read/write “1” to clear (i.e., Interrupts), and clear on read, reserved,

and unused. Refer to the SPI/I2C Register Map and the individual subcircuit descriptions to determine the read/write capability

of each bit. All unused SPI bits in each register must be written to as zeroes. A SPI read back of the address field and unused

bits are returned as zeroes. To read a field of data, the MISO pin will output the data field pointed to by the 6 address bits loaded

at the beginning of the SPI sequence.

CS

CLK

MOSI

MISO

Write_En

Address5

Addr ess 4

Address3

Address2

Address 1

Address 0

“Dead Bit”

Data 23

Data 22

Data 1

Data 0

Figure 35. SPI Transfer Protocol Single Read/Write Access

CS

Preamble

First Address

Preamble Another Address

24 Bits Data

MOSI

MISO

24 Bits Data

Figure 36. SPI Transfer Protocol Multiple Read/Write Access

MC34708

Analog Integrated Circuit Device Data

121

Freescale Semiconductor

Functional Block Description

7.9.1.2

SPI Timing Requirements

The following diagram and table summarize the SPI timing requirements. The SPI input and output levels are set via the SPIVCC

pin, by connecting it to the desired supply. This would typically be tied to SW5 and programmed for 1.80 V. The strength of the

MISO driver is programmable through the SPIDRV [1:0] bits. See Thermal Protection Thresholds for detailed SPI electrical

characteristics.

T

clkper

CS

T

cl khigh

sellow

T

se lhl d

selsu

clklow

CLK

T

wrtsu

T

wrthld

MOSI

MISO

T

rddis

rdsu

T

rdhld

rden

Figure 37. SPI Interface Timing Diagram

Table 119. SPI Interface Timing Specifications⁽⁷⁰⁾

Parameter

Description

T min (ns)

Time CS has to be high before the first rising edge of CLK

Time CS has to remain high after the last falling edge of CLK

Time CS has to remain low between two transfers

t_SELSU

t_SELHLD

t_SELLOW

t_CLKPER

t_CLKHIGH

t_CLKLOW

t_WRTSU

t_WRTHLD

t_RDSU

15

Clock period of CLK

38

Part of the clock period where CLK has to remain high

Part of the clock period where CLK has to remain low

Time MOSI has to be stable before the next rising edge of CLK

Time MOSI has to remain stable after the rising edge of CLK

Time MISO will be stable before the next rising edge of CLK

Time MISO will remain stable after the falling edge of CLK

Time MISO needs to become active after the rising edge of CS

Time MISO needs to become inactive after the falling edge of CS

15

4.0

t_RDHLD

t_RDEN

t_RDDIS

Notes

70. This table reflects a maximum SPI clock frequency of 26 MHz.

MC34708

Analog Integrated Circuit Device Data

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122

Functional Block Description

7.9.2

I²C Interface

2

7.9.2.1

I C Configuration

2

When configured for I C mode, the interface may be used to access the complete register map previously described for SPI

access. Since SPI configuration is more typical, references within this document will generally refer to the common register set

2

as a “SPI map” and bits as “SPI bits”; however, it should be understood that access reverts to I C mode when configured as such.

2

The SPI pins CLK and MISO are reused for the SCL and SDA lines respectively. Selection of I C mode for the interface is

configured by hard-wiring the CS pin to VCOREDIG on the application board. The state of CS is latched in during the initialization

2

phase of a Cold Start sequence, so the I CS bit is defined for bus configuration before the interface is activated. The pull-down

2

on CS will be deactivated if the high state is detected (indicating I C mode).

2

In I C mode, the MISO pin is connected to the bus as an open drain driver, and the logic level is set by an external pull-up. The

2

part can function only as an I C slave device, not as a host.

2

7.9.2.2

I C Device ID

2

I C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for

bus conflict avoidance, pin programmable selection is provided to allow configuration for the address LSB(s). This product

supports 7-bit addressing only; support is not provided for 10-bit or general Call addressing.

2

Because the MOSI pin is not utilized for I C communication, it is reassigned for pin programmable address selection by

2

hardwiring to VCOREDIG or GND at the board level when configured for I C mode. MOSI will act as Bit 0 of the address. The

2

I C address assigned to FSL PM ICs (shared amongst our portfolio) is given as follows:

00010-A1-A0, the A1 and A0 bits are allowed to be configured for either 1 or 0. The A1 address bit is internally hardwired as a

“0”, leaving the LSB A0 for board level configuration. The designated address then is defined as: 000100-A0.

2

7.9.2.3

I C Operation

2

The I C mode of the interface is implemented generally following the Fast Mode definition which supports up to 400 kbits/s

operation. (Exceptions to the standard are noted to be 7-bit only addressing, and no support for general Call addressing) Timing

diagrams, electrical specifications, and further details on this bus standard, is available on the internet, by typing 

2

“I C specification” in the web search string field.

2

Standard I C protocol utilizes bytes of 8 bits, with an acknowledge bit (ACK) required between each byte. However, the number

of bytes per transfer is unrestricted. The register map is organized in 24 bit registers which corresponds to the 24 bit words

2

supported by the SPI protocol of this product. To ensure that I C operation mimics SPI transactions in behavior of a complete 24

bit word being written in one transaction, software is expected to perform write transactions to the device in 3-byte sequences,

beginning with the MSB. Internally, data latching will be gated by the acknowledge at the completion of writing the third

consecutive byte.

2

Failure to complete a 3-byte write sequence will abort the I C transaction and the register will retain its previous value. This could

be due to a premature STOP command from the master, for example.

2

I C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and

3-bytes will be sent out unless a STOP command or NACK is received prior to completion.

The following examples show how to write and read data to the IC. The host initiates and terminates all communication. The host

sends a master command packet after driving the start condition. The device will respond to the host if the master command

packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK

to transmissions from the host. If at any time a NAK is received, the host should terminate the current transaction and retry the

transaction.

MC34708

Analog Integrated Circuit Device Data

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Freescale Semiconductor

Functional Block Description

Packet

Type

Device

Address

Register Address

7

0

7

0

Host SDA

(to MISO)

Continuation

START

0

R / W

A

C

K

A

C

K

Slave SDA

(from MISO)

Host can

also drive

another

Start instead

of Stop

Packet

Type

Master Driven Data

( byte 2 )

Master Driven Data

( byte 1)

Master Driven Data

( byte 0 )

23

16

15

8

7

0

Host SDA

(to MISO)

STOP

A

C

K

A

C

K

A

C

K

Slave SDA

(from MISO)

Figure 38. I²C 3-byte Write Example

Packet

Type

Device

Address

Register Address

Device Address

23

16

0

15

0

8

7

0

Host SDA

(to MISO)

Continuation

START

0

START

1

R /W

A

C

K

A

C

K

A

Slave SDA

(from MISO)

C

K

Host can also

drive another

Start instead of

Stop

AP Lite Driven Data

( byte 2)

AP Lite Driven Data

( byte 1 )

APLite Driven Data

( byte 0)

Packet

Type

A

C

K

A

C

K

Host SDA

(to MISO)

NA

CK

STOP

23

16

15

8

7

0

Slave SDA

(from MISO)

Figure 39. I²C 3-byte Read Example

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

124

Functional Block Description

7.9.3

SPI/I²C Specification

Table 120. SPI/I²C Electrical Characteristics

Characteristics noted under conditions BP = 3.6 V, V

= 5.0 V, -40 C  T  85 C, unless otherwise noted. Typical values

A

BUS

at BP = 3.6 V and T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SPI Interface Logic IO

Input Low CS

V_INCSLO

V_INCSHI

V_INMOSILO

0.0

1.1

0.0

-

0.4

V

Input High CS

SPIVCC+0.3

0.3*SPIVCC

/

Input Low, MOSI, CLK

V_INCLKLO

V_INMOSIHI

/

V

Input High, MOSI, CLK

0.7*SPIVCC

-

SPIVCC+0.3

V_INCLKHI

V_MISOLO

Output Low MISO, INT

/

V_INTLO

• Output sink 100 A

0.0

SPIVCC-0.2

1.75

-

0.2

SPIVCC

3.6

Output High MISO, INT

V_MISOHI

V_INTHI

/

V

• Output source 100 A

SPIVCC Operating Range

V_CC-SPI

t_MISOET

V

MISO Rise and Fall Time, CL = 50 pF, SPIVCC = 1.8 V

• SPIDRV [1:0] = 00

ns

-

6.0

2.5

3.0

2.0

-

• SPIDRV [1:0] = 01 (default)

• SPIDRV [1:0] = 10

• SPIDRV [1:0] = 11

7.10 Configuration Registers

7.10.1 Register Set structure

The general structure of the register set is given in the following table. Expanded bit descriptions are included in the following

functional sections for application guidance. For brevity’s sake, references are occasionally made herein to the register set as

2

the “SPI map” or “SPI bits”, but note that bit access is also possible through the I C interface option so such references are

implied as generically applicable to the register set accessible by either interface.

Table 121. Register Set

Register

0

1

2

3

4

5

6

7

8

Interrupt Status 0

Interrupt Mask 0

16

17

18

19

20

21

22

23

24

Memory A

Memory B

32

33

34

35

36

37

38

39

40

Regulator Mode 0

GPIOLV0 Control

GPIOLV1 Control

GPIOLV2 Control

GPIOLV3 Control

USB Timing

48

49

50

51

52

53

ADC5

ADC6

Interrupt Sense 0

Interrupt Status 1

Interrupt Mask 1

Memory C

ADC7

Memory C

Battery Profile

Charger Debounce

Charger Source

RTC Time

Interrupt Sense 1

Power Up Mode Sense

Identification

RTC Alarm

RTC Day

USB Button

54 Charger LED Control

RTC Day Alarm

Regulator 1 A/B Voltage

USB Control

55

56

PWM Control

Unused

Regulator Fault Sense

USB Device Type

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Analog Integrated Circuit Device Data

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Functional Block Description

Table 121. Register Set

Register

9

ACC 0

ACC 1

25

26

27

28

29

30

31

Regulator 2 & 3 Voltage

Regulator 4 A/B Voltage

Regulator 5 Voltage

Regulator 1 & 2 Mode

Regulator 3, 4 and 5 Mode

Regulator Setting 0

41

42

43

44

45

46

47

Unused

ADC 0

ADC 1

ADC 2

ADC 3

ADC4

57

58

59

60

61

62

63

Unused

10

11

12

13

14

15

ACC 2

Unused

Power Control 0

Power Control 1

Power Control 2

SWBST Control

7.10.2 Specific Registers

7.10.2.1 IC and Version Identification

The IC and other version details can be read via the identification bits. These are hardwired on the chip and described in

Table 122.

Table 122. IC Revision Bit Assignment

Identifier

Value

Purpose

Represents the full mask revision

XXX

Pass 1.0 = 001

Pass 1.1 = 001

Pass 2.0 = 010

Pass 2.1 = 010

Pass 2.3 = 010

FULL_LAYER_REV[2:0]

Represents the full mask revision

Pass 1.0 = 001

XXX

000

Pass 1.1 = 001

METAL_LAYER_REV[2:0]

Pass 2.0 = 010

Pass 2.1 = 001

Pass 2.3 = 011

Represents the full mask revision

Pass 1.0 = 001

Pass 1.1 = 001

FIN[2:0]

Pass 2.0 = 010

Pass 2.1 = 010

Pass 2.3 = 000

Represents the full mask revision

Pass 1.0 = 001

Pass 1.1 = 001

FAB[2:0]

Pass 2.0 = 010

Pass 2.1 = 000

Pass 2.3 = 000

7.10.2.2 Embedded Memory

There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[23:0],

MEMB[23:0], MEMC[23:0], and MEMD[23:0] is maintained by the coin cell when the main battery is deeply discharged, removed,

or contact-bounced (i.e., during a power cut). The contents of the embedded memory are reset by RTCPORB. A known pattern

can be maintained in these registers to validate confidence in the RTC contents when power is restored after a power cut event.

Alternatively, the banks can be used for any system need for bit retention with coin cell backup.

MC34708

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126

Functional Block Description

7.10.3 SPI/I²C Register Map

The complete SPI bitmap is given in Figures 40 to 43, with one register per row for a general overview.

Figure 40. SPI Bitmap Overview (Part 1A)

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

127

Functional Block Description

Figure 41. SPI Bitmap Overview (Part 1B)

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

128

Functional Block Description

Figure 42. SPI Bitmap Overview (Part 1C)

MC34708

Analog Integrated Circuit Device Data

129

Freescale Semiconductor

Functional Block Description

Figure 43. SPI Bitmap Overview (Part 1D)

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130

Functional Block Description

7.10.4 SPI Register’s Bit Description

Table 123. Register 0, Interrupt Status 0

Name

Bit # R/W

Reset

Default

Description

ADCDONEI

TSDONEI

TSPENDET

USBDET

AUXDET

USBOVP

AUXOVP

CHRTIMEEXP

BATTOTP

BATTOVP

CHRCMPL

WKVBUSDET

WKAUXDET

LOWBATT

VBUSREGMI

ATTACH

0

1

2

3

4

5

6

7

8

9

RW1C

RESETB

OFFB

0

ADC has finished requested conversions

Touchscreen has finished requested conversions

Touch screen pen detection

USB detect

OFFB

Auxiliary charger detect

RESETB

USB over-voltage detection

Aux charger over-voltage detection

Charge timer expired

Battery over-temperature

Battery over-voltage

10 RW1C

11 RW1C

12 RW1C

13 RW1C

14 RW1C

Charge complete detection

Weak VBUS detection

Weak Aux detection

Low battery threshold warning

VBUS regulation mode

15 RW1C MUSBRSTB

16 RW1C MUSBRSTB

17 RW1C MUSBRSTB

18 RW1C MUSBRSTB

19 RW1C MUSBRSTB

1: accessory attached

DETACH

KP

1: accessory detached

1: remote controller key is pressed

1: remote controller long key is pressed

1: remote controller long key is released

1: an unknown accessory is attached

1: ADC Result has changed when the RAW DATA = 0

1: Stuck key is detected

LKP

LKR

UNKNOWN_ATTA 20 RW1C MUSBRSTB

ADC_CHANGE

STUCK_KEY

21 RW1C MUSBRSTB

22 RW1C MUSBRSTB

STUCK_KEY_RCV 23 RW1C MUSBRSTB

1: Stuck key is recovered

Table 124. Interrupt Mask 0

Name

Bit # R/W Reset Default

Description

ADCDONEM

TSDONEM

0

1

2

3

4

5

6

7

8

R/W RESETB

R/W OFFB

R/W RESETB

1

ADCDONEI mask bit

TSDONEI mask bit

TSPENDETM

USBDETM

Touch screen pen detect mask bit

USBDET mask bit

AUXDETM

Aux charger detect mask bit

USBOVP mask bit

USBOVPM

AUXOVPM

AUXOVP mask bit

CHRTIMEEXPM

BATTOTPM

CHRTIMEEXP mask bit

BATTOTP mask bit

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Analog Integrated Circuit Device Data

Freescale Semiconductor

131

Functional Block Description

Table 124. Interrupt Mask 0

Name

Bit # R/W Reset Default

R/W RESETB

Description

BATTOVPM

CHRCMPLM

WKVBUSDETM

WKAUXDETM

LOWBATTM

VBUSREGMIM

ATTACH_M

9

1

BATTOVP mask bit

CHRCMPL mask bit

CHGCURRI mask bit

BPONI mask bit

10 R/W RESETB

11 R/W RESETB

12 R/W RESETB

13 R/W RESETB

14 R/W RESETB

15 R/W RESETB

16 R/W RESETB

17 R/W RESETB

18 R/W RESETB

19 R/W RESETB

20 R/W RESETB

21 R/W RESETB

22 R/W RESETB

LOBATLI mask bit

LOBATHI mask bit

DETACH mask bit

KP mask bit

DETACH_M

KP_M

LKP mask bit

LKP_M

LKR mask bit

LKR_M

DETACH mask bit

UNKNOWN_ATTA mask bit

UKNOWN_ATTA_M

ADC_CHANGE_M

STUCK_KEY_M

VBUS power supply type identification completed mask

ID resistance detection finished mask

For future use

STUCK_KEY_RCV_M 23 R/W RESETB

Table 125. Register 2, Interrupt Sense 0

Name

Bit # R/W

Reset

Default

Description

Unused

0

1

R

0

S

0

S

0

S

Not available

Unused

2

Not available

USBDETS

AUXDETS

USBOVPS

AUXOVPS

Unused

3

NONE

USBDET sense bit

AUXDET sense bit

USBOVP sense bit

AUXOVP sense bit

Not available

4

5

6

7

BATTOTPS

BATTOVPS

Unused

8

BATTOTP sense bit

BATTOVP sense bit

Not available

9

10

11

12

13

14

15

16

17

18

19

Unused

Not available

Unused

Not available

Unused

Not available

Unused

Not available

Unused

Not available

Unused

Not available

VBUS_DET_ENDS

ID_DET_ENDS

ID_FLOATS

MUSBRSTB

NONE

VBUS power supply type identification completed sense bit

ID resistance detection finished sense bit

ID float sense bit

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Analog Integrated Circuit Device Data

Freescale Semiconductor

132

Functional Block Description

Table 125. Register 2, Interrupt Sense 0

Name

Bit # R/W

Reset

Default

Description

ID_GNDS

20

R

MUSBRSTB

0

ID ground sense bit

0: no

1: yes

MUSB_ADC_STATUS 21

R

NONE

X

Mini USB ADC conversion status

1: ADC conversion completed

0: ADC conversion in progress

Unused

22

23

R

0

Not available

Table 126. Register 3, Interrupt Status 1

Name

Bit # R/W

Reset

Default

Description

1HZI

TODAI

0

1

2

3

4

5

6

7

8

9

RW1C RTCPORB

R

0

1

0

1.0 Hz time tick

Time of day alarm

Unused

PWRON1I

PWRON2I

WDIRESETI

SYSRSTI

RTCRSTI

PCI

RW1C

OFFB

PWRON1 event

PWRON2 event

RW1C RTCPORB

WDI system reset event

PWRON system reset event

RTC reset event

RW1C

OFFB

Power cut event

WARMI

RW1C RTCPORB

Warm start event

MEMHLDI

THERM110

10 RW1C RTCPORB

11 RW1C RESETB

Memory hold event

110 °C thermal threshold

120 °C thermal threshold

125 °C thermal threshold

130 °C thermal threshold

Clock source change

Short-circuit protection trip detection

GPIOLV1 interrupt

THERM120 12 RW1C RESETB

THERM125 13 RW1C RESETB

THERM130 14 RW1C RESETB

CLKI

15 RW1C RESETB

16 RW1C RESETB

17 RW1C RESETB

18 RW1C RESETB

19 RW1C RESETB

20 RW1C RESETB

SCPI

GPIOLV1I

GPIOLV2I

GPIOLV3I

GPIOLV4I

Unused

GPIOLV2 interrupt

GPIOLV3 interrupt

GPIOLV4 interrupt

21

R

Not available

BATTDETBI 22 RW1C

OFFB

Battery removal detect

Not available

Unused

23

R

RESETB

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Analog Integrated Circuit Device Data

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133

Functional Block Description

Table 127. Register 4, Interrupt Mask 1

Name

Bit # R/W

Reset

Default

Description

1HZM

TODAM

0

1

2

3

4

5

6

7

8

9

R/W RTCPORB

R

1

0

1

1HZI mask bit

TODAI mask bit

Unused

PWRON1M

PWRON2M

WDIRESETM

SYSRSTM

RTCRSTM

PCM

R/W

OFFB

PWRON1 mask bit

PWRON2 mask bit

WDIRESETI mask bit

SYSRSTI mask bit

RTCRSTI mask bit

PCI mask bit

R/W RTCPORB

R/W

OFFB

WARMM

R/W RTCPORB

WARMI mask bit

MEMHLDM

10 R/W RTCPORB

MEMHLDI mask bit

THERM110 mask bit

THERM120 mask bit

THERM125 mask bit

THERM130 mask bit

CLKI mask bit

THERM110M 11 R/W

THERM120M 12 R/W

THERM125M 13 R/W

THERM130M 14 R/W

RESETB

CLKM

15 R/W

16 R/W

17 R/W

18 R/W

19 R/W

20 R/W

SCPM

Short-circuit protection trip mask bit

GPIOLV1 interrupt mask bit

GPIOLV2 interrupt mask bit

GPIOLV3 interrupt mask bit

GPIOLV4 interrupt mask bit

Not available

GPIOLV1M

GPIOLV2M

GPIOLV3M

GPIOLV4M

Unused

21

R

BATTDETBM 22 R/W

Unused 23

OFFB

Battery detect removal mask bit

Not available

R

Table 128. Register 5, Interrupt Sense 1

Name

Bit # R/W Reset Default

Description

Unused

0

1

R

0

S

0

Not available

Unused

2

Not available

PWRON1S

PWRON2S

Unused

3

NONE

PWRON1I sense bit

PWRON2I sense bit

Not available

4

5

Unused

6

Not available

Unused

7

Not available

Unused

8

Not available

Unused

9

Not available

Unused

10

Not available

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

134

Functional Block Description

Table 128. Register 5, Interrupt Sense 1

Name

Bit # R/W Reset Default

Description

THERM110S

THERM120S

THERM125S

THERM130S

CLKS

11

12

13

14

15

16

17

18

19

20

21

22

23

R

NONE

S

0

S

0

THERM110 sense bit

THERM120 sense bit

THERM125 sense bit

THERM130 sense bit

CLKI sense bit

Unused

Not available

Unused

Not available

Unused

Not available

Unused

Not available

Unused

Not available

Unused

Not available

BATTDETBS

Unused

NONE

Battery removal detect sense bit

Not available

Table 129. Register 6, Power Up Mode Sense

Name

Bit #

R/W

Reset

Default

Description

ICTESTS

PUMS1S

PUMS2S

PUMS3S

PUMS4S

PUMS5S

Unused

0

1

R

NONE

S

L

0

L

0

ICTEST sense state

PUMS1 state

PUMS2 state

PUMS3 state

PUMS4 state

PUMS5 state

Not available

Mbatt detect sense

Not available

2

3

4

5

6

Unused

7

Unused

8

MBATDETS⁽⁷¹⁾

Unused

9

NONE

10

11

12

13

14

15

16

17

18

19

20

21

Unused

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Analog Integrated Circuit Device Data

Freescale Semiconductor

135

Functional Block Description

Table 129. Register 6, Power Up Mode Sense

Name

Bit #

R/W

Reset

Default

Description

Unused

22

23

0

Not available

Notes

71. MBATDETS will latch an updated sense value when the charger is enabled.

Table 130. Register 7, Identification

Name

Bit # R/W

Reset

Default

Description

METAL_LAYER_REV0

METAL_LAYER_REV1

METAL_LAYER_REV2

0

1

2

R

NONE

X

Metal Layer version

Pass 1.0 = 000

Pass 1.1 = 001

Pass 2.0 = 000

Pass 2.1 = 001

Pass 2.3 = 011

FULL_LAYER_REV0

FULL_LAYER REV1

FULL_LAYER REV2

3

4

5

R

NONE

X

Full Layer version

Pass 1.0 = 001

Pass 1.1 = 001

Pass 2.0 = 010

Pass 2.1 = 010

Pass 2.3 = 010

FIN0

FIN1

FIN2

6

7

8

R

NONE

X

FIN version

Pass 1.0 = 000

Pass 1.1 = 001, 010, 011

Pass 2.0 = 000

Pass 2.1 = 010

Pass 2.3 = 000

FAB0

FAB1

FAB2

9

R

NONE

X

FAB version

Pass 1.0 = 000

Pass 1.1 = 000

Pass 2.0 = 000

Pass 2.1 = 000

Pass 2.3 = 000

10

11

Unused

12

13

14

15

16

17

18

R

0

Not available

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

136

Functional Block Description

Table 130. Register 7, Identification

Name

Bit # R/W

Reset

Default

Description

PAGE0

PAGE1

PAGE2

PAGE3

PAGE4

19

20

21

22

23

R/W DIGRESETB

0

SPI Page

Table 131. Register 8, Regulator Fault Sense

Name

Bit #

R/W

Reset

Default

Description

SW1FAULT

Reserved

0

1

R

NONE

S

0

SW1 fault detection

Reserved

SW2FAULT

SW3FAULT

SW4AFAULT

SW4BFAULT

SW5FAULT

SWBSTFAULT

VUSBFAULT

VUSB2FAULT

VDACFAULT

VGEN1FAULT

VGEN2FAULT

Unused

2

S

0

SW2 fault detection

SW3 fault detection

SW4A fault detection

SW4B fault detection

SW5 fault detection

SWBST fault detection

VUSB fault detection

VUSB2 fault detection

VDAC fault detection

VGEN1 fault detection

VGEN2 fault detection

Not available

3

4

5

6

7

8

9

10

11

12

13-22

23

RESCGPEN

R/W RESETB

0

Regulator short-circuit protect enable

Table 132. Register 9, ACC 0

Name

Bit #

R/W

Reset

Default

Description

STARTCC

RSTCC

0

1

2

3

4

5

6

7

R/W

RWC

R/W

R

DIGRESETB

0

1

0

1=Run, 0=Stop

1=Reset, self clearing

CCDITHER

CCCALDB

CCCALA

1=ACC Dithering enabled, 0=ACC Dithering disabled

1=Disable Digital Offset Cancellation

1=Enable Analog Offset Calibration Mode

EOC integration period

INTEGTIME0

INTEGTIME1

CCFAULT

1=CCOUT contents no longer valid

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

137

Functional Block Description

Table 132. Register 9, ACC 0

Name

Bit #

R/W

Reset

Default

Description

CCOUT0

CCOUT1

CCOUT2

CCOUT3

CCOUT4

CCOUT5

CCOUT6

CCOUT7

CCOUT8

CCOUT9

CCOUT10

CCOUT11

CCOUT12

CCOUT13

CCOUT14

CCOUT15

8

R

RTCPORB

0

Accumulated Coulomb Counter Output

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Table 133. Register 10, ACC 1

Name

Bit # R/W

Reset

Default

Description

ONEC0

ONEC1

ONEC2

ONEC3

ONEC4

ONEC5

ONEC6

ONEC7

ONEC8

ONEC9

ONEC10

ONEC11

ONEC12

ONEC13

ONEC14

Spare

0

1

R/W

R

DIGRESETB

0

1

0

1

0

1

0

Coulomb Counter One C Setting

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Not available

Spare

R

Spare

R

Spare

R

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

138

Functional Block Description

Table 133. Register 10, ACC 1

Name

Bit # R/W

Reset

Default

Description

Spare

19

20

21

22

23

R

0

Not available

Spare

R

CCRES0

CCRES1

R/W

DIGRESETB

Coulomb Counter Resolution (mC/LSB)00 = 100

01 = 200

10 = 500

11 = 1000

Table 134. Register 11, ACC 2

Name

Bit # R/W

Reset

Default

Description

BATTCURRENT1

BATTCURRENT2

BATTCURRENT3

BATTCURRENT4

BATTCURRENT5

BATTCURRENT6

BATTCURRENT7

BATTCURRENT8

BATTCURRENT9

BATTCURRENT10

BATTCURRENT11

Spare

0

1

R

DIGRESETB

0

EOC I_BATTcurrent

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

R/W DIGRESETB

Not available

Spare

Table 135. Register 12, Unused

Name

Bit #

R/W

Reset

Default

Description

Unused

23-0

R

0

Not available

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

139

Functional Block Description

Table 136. Register 13, Power Control 0

Name

Bit #

R/W

Reset

Default

Description

PCEN

PCCOUNTEN

WARMEN

0

1

2

3

4

5

6

7

8

9

R/W

R

RTCPORB

RESETB

0

1

0

Power cut enable

Power cut counter enable

Warm start enable

USEROFFSPI

DRM

SPI command for entering user off modes

Keeps VSRTC and CLK32KMCU on for all states

Keeps the CLK32KMCU active during user off

Enables the CLK32KMCU

RTCPORB ⁽⁷²⁾

RTCPORB

USEROFFCLK

CLK32KMCUEN

Unused

Not available

Unused

R

Not available

PCUTEXPB

R/W

RTCPORB

PCUTEXPB=1 at a startup event indicates that PCUT timer did not

expire (assuming it was set to 1 after booting)

Unused

10

11

12

13

14

15

16

17

18

19

20

21

22

23

R

0

Not available

Unused

R

Not available

Unused

R

Not available

Unused

R

Not available

Unused

R

Not available

Unused

R

Not available

Unused

R

Not available

Unused

R

Not available

BATTDETEN

VCOIN0

VCOIN1

VCOIN2

COINCHEN

R/W

RTCPORB

Enables battery detect function

Coin cell charger voltage setting

Coin cell charger enable

Notes:

72. Reset by RTCPORB but not during a GLBRST (global reset)

Table 137. Register 14, Power Control 1

Name

Bit # R/W

Reset

Default

Description

PCT0

PCT1

PCT2

PCT3

PCT4

PCT5

PCT6

PCT7

0

1

2

3

4

5

6

7

R/W

RTCPORB

0

Power cut timer

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

140

Functional Block Description

Table 137. Register 14, Power Control 1

Name

Bit # R/W

Reset

Default

Description

PCCOUNT0

PCCOUNT1

PCCOUNT2

PCCOUNT3

PCMAXCNT0

PCMAXCNT1

PCMAXCNT2

PCMAXCNT3

Unused

8

R/W

R

RTCPORB

0

Power cut counter

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Maximum allowed number of power cuts

Not available

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Table 138. Register 15, Power Control 2

Name

Bit #

R/W

Reset

Default

Description

RESTARTEN

PWRON1RSTEN

PWRON2RSTEN

Unused

0

1

R/W

R

RTCPORB

0

1

0

1

0

1

0

Enables automatic restart after a system reset

Enables system reset on PWRON1 pin

Enables system reset on PWRON2 pin

Not available

2

3

PWRON1DBNC0

PWRON1DBNC1

PWRON2DBNC0

PWRON2DBNC1

GLBRSTTMR0

GLBRSTTMR1

STANDBYINV

Unused

4

R/W

R

RTCPORB

Sets debounce time on PWRON1 pin

5

6

Sets debounce time on PWRON2 pin

Sets Global reset time

7

8

9

10

11

12

13

14

15

16

17

18

If set then STANDBY is interpreted as active low

Not available

WDIRESET

R/W

R

RESETB

RTCPORB

Enables system reset through WDI

SPI drive strength

SPIDRV0

SPIDRV1

Unused

Not available

Unused

R

CLK32KDRV0

CLK32KDRV1

R/W

RTCPORB

CLK32K and CLK32KMCU drive strength (master control bits)

MC34708

Analog Integrated Circuit Device Data

141

Freescale Semiconductor

Functional Block Description

Table 138. Register 15, Power Control 2

Name

Bit #

R/W

Reset

Default

Description

Unused

19

20

21

R

0

Not available

ON_STBY_LP

R/W

RESETB

On Standby Low Power Mode

0 = Low power mode disabled

1 =Low power mode enabled

STBYDLY0

STBYDLY1

22

23

R/W

RESETB

1

0

Standby delay control

Table 139. Register 16, Memory A

Name

Bit # R/W

Reset

Default

Description

MEMA0

MEMA1

MEMA2

MEMA3

MEMA4

MEMA5

MEMA6

MEMA7

MEMA8

MEMA9

MEMA10

MEMA11

MEMA12

MEMA13

MEMA14

MEMA15

MEMA16

MEMA17

MEMA18

MEMA19

MEMA20

MEMA21

MEMA22

MEMA23

0

1

R/W

RTCPORB

0

Backup memory A

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

142

Functional Block Description

Table 140. Register 17, Memory B

Name

Bit #

R/W

Reset

Default

Description

MEMB0

MEMB1

MEMB2

MEMB3

MEMB4

MEMB5

MEMB6

MEMB7

MEMB8

MEMB9

MEMB10

MEMB11

MEMB12

MEMB13

MEMB14

MEMB15

MEMB16

MEMB17

MEMB18

MEMB19

MEMB20

MEMB21

MEMB22

MEMB23

0

1

R/W

RTCPORB

0

Backup memory B

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

MC34708

Analog Integrated Circuit Device Data

143

Freescale Semiconductor

Functional Block Description

Table 141. Register 18, Memory C

Name

Bit # R/W

Reset

Default

Description

MEMC0

MEMC1

MEMC2

MEMC3

MEMC4

MEMC5

MEMC6

MEMC7

MEMC8

MEMC9

MEMC10

MEMC11

MEMC12

MEMC13

MEMC14

MEMC15

MEMC16

MEMC17

MEMC18

MEMC19

MEMC20

MEMC21

MEMC22

MEMC23

0

1

R/W

RTCPORB

0

Backup memory C

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

144

Functional Block Description

Table 142. Register 19, Memory D

Name

Bit #

R/W

Reset

Default

Description

MEMD0

MEMD1

MEMD2

MEMD3

MEMD4

MEMD5

MEMD6

MEMD7

MEMD8

MEMD9

MEMD10

MEMD11

MEMD12

MEMD13

MEMD14

MEMD15

MEMD16

MEMD17

MEMD18

MEMD19

MEMD20

MEMD21

MEMD22

MEMD23

0

1

R/W

RTCPORB

0

Backup memory D

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

145

Functional Block Description

Table 143. Register 20, RTC Time

Name

Bit # R/W

Reset

Default

Description

TOD0

TOD1

0

1

R/W

RTCPORB ⁽⁷³⁾

0

Time of day counter

TOD2

2

TOD3

3

TOD4

4

TOD5

5

TOD6

6

TOD7

7

TOD8

8

TOD9

9

TOD10

10

11

12

13

14

15

16

17

18

19

20

21

22

23

TOD11

TOD12

TOD13

TOD14

TOD15

TOD16

RTCCAL0

RTCCAL1

RTCCAL2

RTCCAL3

RTCCAL4

RTCCALMODE0

RTCCALMODE1

RTC calibration count

RTC calibration mode

Notes

73. Reset by RTCPORB but not during a GLBRST (global reset)

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

146

Functional Block Description

Table 144. Register 21, RTC Alarm

Name

Bit #

R/W

Reset

Default

Description

TODA0

TODA1

TODA2

TODA3

TODA4

TODA5

TODA6

TODA7

TODA8

TODA9

TODA10

TODA11

TODA12

TODA13

TODA14

TODA15

TODA16

Unused

RTCDIS

0

1

R/W

R

RTCPORB ⁽⁷⁴⁾

1

0

Time of day alarm

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

Disable RTC

R

R/W

RTCPORB ⁽⁷⁴⁾

Notes

74. Reset by RTCPORB but not during a GLBRST (global reset)

MC34708

Analog Integrated Circuit Device Data

147

Freescale Semiconductor

Functional Block Description

Table 145. Register 22, RTC Day

Name

Bit #

R/W

Reset

Default

Description

DAY0

DAY1

0

1

R/W

R

RTCPORB ⁽⁷⁵⁾

0

Day counter

DAY2

2

DAY3

3

DAY4

4

DAY5

5

DAY6

6

DAY7

7

DAY8

8

DAY9

9

DAY10

DAY11

DAY12

DAY13

DAY14

Unused

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

R

Notes

75. Reset by RTCPORB but not during a GLBRST (global reset)

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

148

Functional Block Description

Table 146. Register 23, RTC Day Alarm

Name

Bit #

R/W

Reset

Default

Description

DAYA0

DAYA1

DAYA2

DAYA3

DAYA4

DAYA5

DAYA6

DAYA7

DAYA8

DAYA9

DAYA10

DAYA11

DAYA12

DAYA13

DAYA14

Unused

0

1

R/W

R

RTCPORB ⁽⁷⁶⁾

1

0

Day alarm

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

R

Notes

76. Reset by RTCPORB but not during a GLBRST (global reset)

Table 147. Register 24, Regulator 1A/B Voltage

Name

Bit #

R/W

Reset

Default

Description

SW1 setting in normal mode

SW1A0

SW1A1

SW1A2

SW1A3

SW1A4

SW1A5

0

1

2

3

4

5

R/WM NONE

*

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

149

Functional Block Description

Table 147. Register 24, Regulator 1A/B Voltage

Name

Bit #

R/W

Reset

Default

Description

SW1ASTBY0

SW1ASTBY1

SW1ASTBY2

SW1ASTBY3

SW1ASTBY4

SW1ASTBY5

Reserved

6

R/WM NONE

*

SW1 setting in Standby mode

7

R/WM NONE

8

R/WM NONE

9

R/WM NONE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

R/WM NONE

R

Not available

Reserved

Table 148. Register 25, Regulator 2 & 3 Voltage

Name

Bit #

R/W

Reset

Default

Description

SW20

SW21

0

1

R/WM NONE

*

SW2 setting in normal mode

SW22

2

SW23

3

SW24

4

SW25

5

SW2STBY0

SW2STBY1

SW2STBY2

SW2STBY3

SW2STBY4

SW2STBY5

SW30

6

SW2 setting in Standby mode

7

8

9

10

11

12

13

14

15

16

SW3 setting in normal mode

SW31

SW32

SW33

SW34

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

150

Functional Block Description

Table 148. Register 25, Regulator 2 & 3 Voltage

Name

Bit #

R/W

Reset

Default

Description

Unused

17

18

19

20

21

22

23

R

0

*

Not available

SW3STBY0

SW3STBY1

SW3STBY2

SW3STBY3

SW3STBY4

Unused

R/WM NONE

R

SW3 setting in standby mode

*

0

Not available

Table 149. Register 26, REgulator 4A/B

Name

Bit #

R/W

Reset

Default

Description

SW4A0

SW4A1

0

1

R/WM

NONE

*

SW4A setting in normal mode

SW4A2

2

SW4A3

3

SW4A4

4

SW4ASTBY0

SW4ASTBY1

SW4ASTBY2

SW4ASTBY3

SW4ASTBY4

SW4AHI0

SW4AHI1

SW4B0

5

SW4A setting in Standby mode

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

SW4A high setting

SW4B setting in normal mode

SW4B1

SW4B2

SW4B3

SW4B4

R/WM RESETB

SW4BSTBY0

SW4BSTBY1

SW4BSTBY2

SW4BSTBY3

SW4BSTBY4

SW4BHI0

SW4BHI1

SW4B setting in Standby mode

SW4B high setting

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

151

Functional Block Description

Table 150. Register 27, REgulator 5 Voltage

Name

Bit #

R/W

Reset

Default

Description

SW50

SW51

0

1

R/WM NONE

*

SW4 setting in normal mode

R/WM NONE

SW52

2

R/WM NONE

*

SW53

3

R/WM NONE

*

SW54

4

R/WM NONE

*

Unused

SW5STBY0

SW5STBY1

SW5STBY2

SW5STBY3

SW5STBY4

Unused

5

R

*

Not available

6

R

*

7

R

*

Not available

8

R

*

Not available

9

R

*

Not available

10

11

12

13

14

15

16

17

18

19

20

21

22

23

R/WM NONE

*

SW5 setting in Standby mode

R/WM NONE

*

R/WM NONE

*

R/WM NONE

*

R/WM NONE

*

R

0

Not available

Table 151. Register 28, Regulators 1 & 2 Operating Mode

Name

Bit #

R/W

Reset

Default

Description

SW1AMODE0

SW1AMODE1

SW1AMODE2

SW1AMODE3

SW1AMHMODE

SW1AUOMODE

SW1DVSSPEED0

SW1DVSSPEED1

Unused

0

1

R/W

R

RESETB

OFFB

0

1

0

1

0

1

0

SW1A operating mode

2

3

4

SW1A Memory Hold mode

SW1A User Off mode

SW1 DVS1 speed

5

OFFB

6

RESETB

7

8

Not available

Unused

9

R

Unused

10

R

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

152

Functional Block Description

Table 151. Register 28, Regulators 1 & 2 Operating Mode

Name

Bit #

R/W

Reset

Default

Description

Unused

11

12

13

14

15

16

17

18

19

20

21

22

23

R

0

1

0

1

0

1

0

1

0

Not available

R

Unused

R

SW2MODE0⁽⁷⁷⁾

SW2MODE1⁽⁷⁷⁾

SW2MODE2⁽⁷⁷⁾

SW2MODE3⁽⁷⁷⁾

SW2MHMODE

SW2UOMODE

SW2DVSSPEED0

SW2DVSSPEED1

PLLEN

R/W

RESETB

OFFB

SW2 operating mode

SW2 Memory Hold mode

SW2 User Off mode

SW2 DVS1 speed

OFFB

RESETB

PLL enable

PLLX

PLL multiplication factor

Notes

77. SWxMODE[3:0] bits will be reset to their default values by the startup sequencer, based on PUMS settings. An enabled switch will

default to APSKIP mode for both Normal and Standby operation.

Table 152. Register 29, Regulators 3, 4, and 5 Operating Mode

Name

Bit #

R/W

Reset

Default

Description

SW3MODE0

SW3MODE1

0

1

R/W

RESETB

OFFB

0

1

0

1

0

1

0

1

0

1

0

1

0

SW3 operating mode

SW3MODE2

2

SW3MODE3

3

SW3MHMODE

SW3UOMODE

SW4AMODE0

SW4AMODE1

SW4AMODE2

SW4AMODE3

SW4AMHMODE

SW4AUOMODE

SW4BMODE0

SW4BMODE1

SW4BMODE2

SW4BMODE3

SW4BMHMODE

SW4BUOMODE

4

SW3 Memory Hold mode

SW3 User Off mode

5

OFFB

6

RESETB

OFFB

SW4A operating mode

7

8

9

10

11

12

13

14

15

16

17

SW4A Memory Hold mode

SW4A User Off mode

SW4B operating mode

OFFB

RESETB

OFFB

SW4B Memory Hold mode

SW4B User Off mode

OFFB

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

153

Functional Block Description

Table 152. Register 29, Regulators 3, 4, and 5 Operating Mode

SW5MODE0⁽⁷⁸⁾

SW5MODE1⁽⁷⁸⁾

SW5MODE2⁽⁷⁸⁾

SW5MODE3⁽⁷⁸⁾

SW5MHMODE

SW5UOMODE

18

19

20

21

22

23

R/W

RESETB

OFFB

0

1

0

1

0

SW5 operating mode

SW5 Memory Hold mode

SW5 User Off mode

OFFB

Notes

78. SWxMODE[3:0] bits will be reset to their default values by the startup sequencer, based on PUMS settings. An enabled regulator will

default to APSKIP mode for both Normal and Standby operation.

Table 153. Register 30, Regulator Setting 0

Name

Bit #

R/W

Reset

Default

Description

VGEN10

VGEN11

VGEN12

Unused

VDAC0

VDAC1

VGEN20

VGEN21

VGEN22

VPLL0

0

1

R/WM

R

RESETB

*

VGEN1 setting

2

*

3

0

*

Not available

VDAC setting

4

R/WM

R

RESETB

5

*

6

*

VGEN2 setting

7

*

8

*

9

*

VPLL setting

VPLL1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

*

VUSB20

VUSB21

Unused

*

VUSB2 setting

*

0

Not available

R

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

154

Functional Block Description

Table 154. Register 31, SWBST Control

Name

Bit #

R/W

Reset

Default

Description

SWBST0

SWBST1

SWBSTMODE0

SWBSTMODE1

Spare

0

1

R/W

R

NONE

*

SWBST setting

NONE

*

2

RESETB

0

1

0

1

0

SWBST mode

3

4

Not available

SWBSTSTBYMODE0

SWBSTSTBYMODE1

Spare

5

SWBST standby mode

6

7

Not available

Unused

8

Unused

9

R

Unused

10

11

12

13

14

15

16

17

18

19

20

21

22

23

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Unused

R

Table 155. Register 32, Regulator Mode 0

Name

Bit #

R/W

Reset

Default

Description

VGEN1EN

VGEN1STBY

VUSBSEL

VUSBEN

0

1

R/W

R

NONE

RESETB

NONE

*

0

*

VGEN1 enable

VGEN1 controlled by standby

Slave or Host configuration for VBUS

VUSB enable (PUMS4:1=[0100]). Also reset to 1 by invalid VBUS

VDAC enable

2

3

RESETB

NONE

1

*

VDACEN

4

VDACSTBY

VDACMODE

Unused

5

RESETB

0

*

VDAC controlled by standby

VDAC operating mode

6

7

Not available

Unused

8

R

Not available

Unused

9

R

Not available

VREFDDREN

10

R/W

NONE

VREFDDR enable

MC34708

Analog Integrated Circuit Device Data

155

Freescale Semiconductor

Functional Block Description

Table 155. Register 32, Regulator Mode 0

Name

Bit #

R/W

Reset

Default

Description

VGEN2CONFIG

11

R/W

NONE

*

PUMS5 Tied to ground = 0: VGEN2 with external PNP

PUMS5 Tied to VCROREDIG =1:VGEN2 internal PMOS

VGEN2EN

VGEN2STBY

VGEN2MODE

VPLLEN

12

13

14

15

16

17

R/W

NONE

RESETB

NONE

*

0

*

VGEN2 enable

VGEN2 controlled by standby

VGEN2 operating mode

VPLL enable

VPLLSTBY

RESETB

NONE

0

*

VPLL controlled by standby

VUSB2CONFIG

PUMS5 Tied to ground = 0: VUSB2 with external PNP

PUMS5 Tied to VCROREDIG =1:VUSB2 internal PMOS

VUSB2EN

VUSB2STBY

VUSB2MODE

Unused

18

19

20

21

22

23

R/W

R

NONE

*

VUSB2 enable

VUSB2 controlled by standby

VUSB2 operating mode

Not available

RESETB

0

Unused

R

Not available

Unused

R

Not available

Table 156. Register 33, GPIOLV0 Control

Name

Bit #

R/W

Reset

Default

Description

DIR

0

R/W RESETB

0

GPIOLV0 direction

0: Input

1: Output

DIN

DOUT

HYS

1

2

3

0

1

Input state of GPIOLV0 pin

0: Input low

1: Input High

Output state of GPIOLV0 pin

0: Output Low

1: Output High

Hysteresis

0: CMOS in

1: Hysteresis

DBNC0

DBNC1

4

5

R/W RESETB

0

GPIOLV0 input debounce time

00: no debounce

01: 10 ms debounce

10: 20 ms debounce

11: 30 mS debounce

INT0

INT1

6

7

R/W RESETB

0

GPIOLV0 interrupt control

00: None

01: Falling edge

10: Rising edge

11: Both edges

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

156

Functional Block Description

Table 156. Register 33, GPIOLV0 Control

Name

Bit #

R/W

Reset

Default

Description

PKE

8

R/W RESETB

0

Pad keep enable

0: Off

1: On

ODE

DSE

9

0

1

Open drain enable

0: CMOS

1: OD

10

11

12

Drive strength enable

0: 4.0 mA

1: 8.0 mA

PUE

Pull-up/down enable

0: pull-up/down off

1: pull-up/down on (default)

PUS0

Pull-up/Pull-down select

00: 10 K pull-down

01: 100 K pull-down

10: 10 K pull-up

11: 100 K pull-up

PUS1

SRE0

SRE1

13

14

15

R/W RESETB

1

0

(1.0 default 10)

Slew rate enable

00: slow (default)

01: normal

10: fast

11: very fast

Unused

16

17

18

19

20

21

22

23

R

0

Not available

Table 157. Register 34, GPIOLV1 Control

Name

Bit #

R/W

Reset

Default

Description

DIR

0

R/W

RESETB

0

GPIOLV1directon

0: Input

1: Output

DIN

1

R/W

RESETB

0

Input state of GPIOLV1 pin

0: Input low

1: Input High

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

157

Functional Block Description

Table 157. Register 34, GPIOLV1 Control

Name

Bit #

R/W

Reset

Default

Description

DOUT

2

R/W

RESETB

0

Output state of GPIOLV1 pin

0: Output Low

1: Output High

HYS

3

R/W

RESETB

1

Hysteresis

0: CMOS in

1: Hysteresis

DBNC0

DBNC1

4

5

R/W

RESETB

0

GPIOLV1 input debounce time

00: no debounce

01: 10 ms debounce

10: 20 ms debounce

11: 30 mS debounce

INT0

INT1

6

7

R/W

RESETB

0

GPIOLV1 interrupt control

00: None

01: Falling edge

10: Rising edge

11: Both edges

PKE

ODE

DSE

PUE

PUS0

8

R/W

RESETB

0

1

Pad keep enable

0: Off

1: On

9

Open drain enable

0: CMOS

1: OD

10

11

12

Drive strength enable

0: 4.0 mA

1: 8.0 mA

Pull-up/down enable

0: pull-up/down off

1: pull-up/down on (default)

Pull-up/Pull-down select

00: 10 K pull-down

01: 100 K pull-down

10: 10 K pull-up

11: 100 K pull-up

PUS1

SRE0

SRE1

13

14

15

R/W

RESETB

1

0

(1.0 default 10)

Slew rate enable

00: slow (default)

01: normal

10: fast

11: very fast

Unused

16

17

18

19

R

0

Not available

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

158

Functional Block Description

Table 157. Register 34, GPIOLV1 Control

Name

Bit #

R/W

Reset

Default

Description

Unused

20

21

22

23

R

0

Not available

Table 158. Register 35, GPIOLV2 Control

Name

Bit #

R/W

Reset

Default

Description

DIR

0

R/W

RESETB

0

GPIOLV2 direction

0: Input

1: Output

DIN

DOUT

HYS

1

2

3

R/W

RESETB

0

1

Input state of GPIOLV2 pin

0: Input low

1: Input High

Output state of GPIOLV2 pin

0: Output Low

1: Output High

Hysteresis

0: CMOS in

1: Hysteresis

DBNC0

DBNC1

4

5

R/W

RESETB

0

GPIOLV2 input debounce time

00: no debounce

01: 10 ms debounce

10: 20 ms debounce

11: 30 mS debounce

INT0

INT1

6

7

R/W

RESETB

0

GPIOLV2 interrupt control

00: None

01: Falling edge

10: Rising edge

11: Both edges

PKE

ODE

DSE

PUE

8

9

R/W

RESETB

0

1

Pad keep enable

0: Off

1: On

Open drain enable

0: CMOS

1: OD

10

11

Drive strength enable

0: 4.0 mA

1: 8.0 mA

Pull-up/down enable

0: pull-up/down off

1: pull-up/down on (default)

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

159

Functional Block Description

Table 158. Register 35, GPIOLV2 Control

Name

Bit #

R/W

Reset

Default

Description

PUS0

12

R/W

RESETB

1

Pull-up/Pull-down select

00: 10 K pull-down

01: 100 K pull-down

10: 10 K pull-up

11: 100 K pull-up

PUS1

SRE0

SRE1

13

14

15

R/W

RESETB

1

0

(1.0 default = 10)

Slew rate enable

00: slow (default)

01: normal

10: fast

11: very fast

Unused

16

17

18

19

20

21

22

23

R

0

Not available

Table 159. Register 36, GPIOLV3 Control

Name

Bit #

R/W

Reset

Default

Description

DIR

0

R/W

RESETB

0

GPIOLV3 direction

0: Input

1: Output

DIN

DOUT

HYS

1

2

3

R/W

RESETB

0

1

Input state of GPIOLV3 pin

0: Input low

1: Input High

Output state of GPIOLV3 pin

0: Output Low

1: Output High

Hysteresis

0: CMOS in

1: Hysteresis

DBNC0

DBNC1

4

5

R/W

RESETB

0

GPIOLV3 input debounce time

00: no debounce

01: 10 ms debounce

10: 20 ms debounce

11: 30 mS debounce

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

160

Functional Block Description

Table 159. Register 36, GPIOLV3 Control

Name

Bit #

R/W

Reset

Default

Description

INT0

INT1

6

7

R/W

RESETB

0

GPIOLV3 interrupt control

00: None

01: Falling edge

10: Rising edge

11: Both edges

PKE

ODE

DSE

PUE

8

9

R/W

RESETB

0

1

Pad keep enable

0: Off

1: On

Open drain enable

0: CMOS

1: OD

10

11

Drive strength enable

0: 4.0 mA

1: 8.0 mA

Pull-up/down enable

0: pull-up/down off

1: pull-up/down on (default)

PUS0

PUS1

12

13

R/W

RESETB

1

Pull-up/Pull-down select

00: 10 K pull-down

01: 100 K pull-down

10: 10 K pull-up

11: 100 K pull-up

(1.0 default = 10)

SRE0

SRE1

14

15

R/W

RESETB

0

Slew rate enable

00: slow (default)

01: normal

10: fast

11: very fast

Unused

16

17

18

19

20

21

22

23

R

0

Not available

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

161

Functional Block Description

Table 160. Register 37, USB timing

Name

Bit # R/W

Reset

Default

Description

DEVICE_WAKE_UP[3:0]

0

1

2

3

R/W MUSBRSTB

0

The periodical sampling time of the ID line in the Power-Save mode and

Standby mode; the periodical time of ADC conversion of the resistance

at ID pin when RAW DATA = 0.

0000: 50 ms

0001: 100 ms

0010: 150 ms

0011: 200 ms

0100: 300 ms

KEYPRESS[3:0]

LONG_KEYPRESS[3:0]

SWITCHING_WAIT

TD

4

5

6

7

R/W MUSBRSTB

0

Normal key press duration

0000: 100 ms

0001: 200 ms

0010: 300 ms

...

8

9

R/W MUSBRSTB

0

Long key press duration

0000: 300 ms

0001: 400 ms

0010: 500 ms

...

10

11

12

13

14

15

R/W MUSBRSTB

0

Waiting time before switching the analog or digital switches:

0000: 10 ms

0001: 30 ms

0010: 50 ms

...

16

17

18

19

R/W MUSBRSTB

0

1

0

Time delay to start the powered accessory identification flow after

detecting the bus voltage

0000: 100 ms

0001: 200 ms

0010: 300 ms

0011: 400 ms

0100: 500 ms

...

1111:1600 ms

The time for no activity in the switches before entering the Power Save

mode automatically for Audio Type 1 or TTY device

0000: 1 s

0001: 2 s

...

1001:10s

...

1111:16 s

Unused

20

21

R

0

Not available

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

162

Functional Block Description

Table 160. Register 37, USB timing

Name

Bit # R/W

Reset

Default

Description

Unused

22

23

R

0

Not available

READVALID

MUSBRSTB

Read data valid

0: Data not valid

1: Data valid

Table 161. Register 38, USB Button

Name

Bit #

R/W

Reset

Default

Description

Send_End

S1

0

1

R/C

R

MUSBRSTB

0

1: the Send_End button is pressed

1: button 1 is pressed

1: button 2 is pressed

1: button 3 is pressed

1: button 4 is pressed

1: button 5 is pressed

1: button 6 is pressed

1: button 7 is pressed

1: button 8 is pressed

1: button 9 is pressed

1: button 10 is pressed

1: button 11 is pressed

1: button 12 is pressed

1: button error occurred

1: an unknown button is pressed

Not available

S2

2

S3

3

S4

4

S5

5

S6

6

S7

7

S8

8

S9

9

S10

10

11

12

13

14

15

16

17

18

19

20

21

22

23

S11

S12

ERROR

UNKNOWN

Unused

R

Not available

R

Not available

R

Not available

R

Not available

R

Not available

R

Not available

R

Not available

R

Not available

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

163

Functional Block Description

Table 162. Register 39, USB Control

Name

Bit #

R/W

Reset

Default

Description

Wait

0

R/W MUSBRSTB

1

Wait or not to wait for the command from the baseband before turning on the

analog or digital switches for attached accessory

0: Wait until this bit is changed to 1. Turn on the switches immediately when

this bit is changed to 1.

1: Wait for only the time programmed by the Switching Wait bits in Timing Set

2 register before turning on the switches.

Manual S/W

RAWDATA

1

2

R/W MUSBRSTB

1

Manual or automatic switching of the switches

0: manual: the switches are controlled by the Manual S/W registers.

1: auto: the switches are controlled by the Device Type registers

Interrupt behavior selection

0: Enable the ADC conversion periodically and report the ADC Result changes

on ID pin to the host.

1: Enable the key press monitor circuit to detect the ID pin status changes and

report the key press events to the host.

SWITCH_OPEN

3

R/W MUSBRSTB

1

Switch connection selection

0: Open all switches

1: Switch selection according to the Manual S/W bit.

RESET

4

5

RWM MUSBRSTB

R/W MUSBRSTB

0

Soft reset. When written to 1, the IC is reset. Once the reset is complete, the

RST bit is set and the RESET bit is cleared automatically.

1: to soft-reset the IC

TTY_SPKL

SPK_L to DM switch control

0: Turn off the SPK_L to DM switch

1: Turn on the SPK_L to DM switch for TTY

RST

6

7

R/C

MUSBRSTB

This bit indicates if a chip reset has occurred. This bit will be cleared once

being read.

0: no.

1: Yes.

ACTIVE

R/W MUSBRSTB

Indicate either the device is in Active mode

0: Standby

1: Active

CLK_RST

VOTGEN

8

9

R/C

R/W

R

MUSBRST

RESETB

1

0

Not available

Enables the OTG switch and the GOTG switch

Not available

Unused

10

11

MUSBCHARG

R/W MUSBRSTB

Manual override for USB buck charger input current limit. With

MUSBCHARG=1. the MUSBCHRG[1:0] SPI bits have control over the buck

charger input current limit.

SWHOLD

12

1

Switch Hold

0: Run state machine and allow detection of accessory

1: Holds off state machine until baseband comes up

MUSBCHRG0

MUSBCHRG1

13

14

R/W MUSBRSTB

0

Controls the buck charger input current limit when Manual S/W = 0

[00] = Buck disabled

[01] = 100 mA

[10] = 500 mA

[11] = 950 mA

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

164

Functional Block Description

Table 162. Register 39, USB Control

Name

Bit #

R/W

Reset

Default

Description

VBUS

SWITCHING0

15

R/W MUSBRSTB

0

VBUS line switching configuration when Manual S/W = 0

00: open all switches MVBUS, MPD, MOTG, M0

01: MVBUS switch closed, MPD switch open

VBUS

16

0

SWITCHING1

10: VBUS connects to MIC. M0, MOTG, MVBUS switches open, MPD switch

closed

Others: open all switches connected to the VBUS line

DP

17

18

19

R/W MUSBRSTB

0

DP line switching configuration when Manual S/W = 0

000: open all switches

SWITCHING0

001: DP connected to D+, DM connected to D-

010: DP connected to SPK_R, DM connected to SPK_L

011: DP connected to RxD, DM connected to TxD

Others: open all switches connected to the DP pin and DM pin

DP

SWITCHING1

DP

SWITCHING2

DM

20

21

22

R/W MUSBRSTB

0

DM line switching configuration when Manual S/W = 0

000: open all switches

SWITCHING0

001: DP connected to D+, DM connected to D-

010: DP connected to SPK_R, DM connected to SPK_L

011: DP connected to RxD, DM connected to TxD

Others: open all switches connected to the DP pin and DM pin

DM

SWITCHING1

DM

SWITCHING2

READVALID

23

R

MUSBRSTB

0

Read data valid

0: Data not valid

1: Data valid

Table 163. Register 40, USB Device Type

Name

Bit #

R/W

Reset

Default

Description

Audio Type 1

Audio Type 2

USB

0

1

R

MUSBRSTB

0

1: An audio type 1 accessory is attached

1: An audio type 2 accessory is attached

1: A USB host is attached

2

UART

3

1: A UART cable is attached

5W CHG

4

1: A 5-wire charger (type 1 or 2) is attached

1: A USB charger is attached

USB CHG

DEDICATED CHG

USB OTG

PPD

5

6

1: A dedicated charger is attached

1: A USB OTG accessory is attached

1: A phone powered device is attached

1: A TTY converter is attached

7

8

TTY

9

A/V

10

11

12

13

14

15

16

17

1: An audio/video cable is attached

1: An audio/video charger is attached

1: A USB jig cable 1 is attached

1: A USB jig cable 2is attached

AVCHRG

USBJIG1

USBJIG2

UARTJIG1

UARTJIG2

ID_FACTORY

UNK_DEVICE

1: A UART jig cable 1is attached

1: A UART jig cable 2 is attached

1: A factory cable is attached

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

165

Functional Block Description

Table 163. Register 40, USB Device Type

Name

Bit #

R/W

Reset

Default

Description

Unused

18

19

20

21

22

23

R

0

Not available

ADCIDRESULT0

ADCIDRESULT1

ADCIDRESULT2

ADCIDRESULT3

ADCIDRESULT4

MUSBRSTB

ADC result value of the resistance at ID pin

Table 164. Register 41, Unused

Name

Bit #

R/W

Reset

Default

Description

Unused

0-23

R

0

Not available

Table 165. Register 42, Unused

Name

Bit #

R/W

Default

Description

Unused

0-23

R

0

Not available

Table 166. Register 43, ADC 0

Name

Bit #

R/W

Reset

Default

Description

ADEN

0

1

2

R/W

DIGRESETB

0

Enables ADC from the low power mode

ADSTART

ADCONT

Request a start of the ADC Reading Sequencer

Run ADC reads continuously when high or one time when low. Note that the

TSSTART request will have higher priority

ADHOLD

ADSTOP0

ADSTOP1

ADSTOP2

Spare

3

4

5

6

7

8

R/W

DIGRESETB

0

Hold the ADC reading Sequencer while saved ADC results are read from SPI

Channel Selection to stop when complete. Always start at 000 and read up to and

including this channel value.

Not available

THERM

0: NTCREF not forced on

1: Force NTCREF on

Spare

9

R/W

DIGRESETB

0

Not available

10

11

12

13

14

15

Spare

Not available

TSEN

Enable the Touch screen from low power mode.

Request a start of the ADC Reading Sequencer for Touch screen readings.

Run ADC reads of Touch screen continuously when high or one time when low.

TSSTART

TSCONT

TSHOLD

Hold the ADC reading Sequencer while saved Touch screen results are read from

SPI

TSSTOP0

TSSTOP1

TSSTOP2

16

17

18

R/W

DIGRESETB

0

Just like the ADSTOP above, but for the Touchscreen read programming. This will

allow independent code for ADC Sequence readings and touchscreen ADC

Sequence readings.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

166

Functional Block Description

Table 166. Register 43, ADC 0

Name

Bit #

R/W

Reset

Default

Description

Spare

19

20

R/W

DIGRESETB

0

Not available

TSPENDET

EN

Enable the Touchscreen Pen Detection. Note that TSEN must be off for Pen

Detection.

Spare

21

22

23

R/W

DIGRESETB

0

Not available

Table 167. Register 44, ADC 1

Name

Bit #

R/W

Reset

Default

Description

ADDLY10

ADDLY11

ADDLY12

ADDLY13

ADDLY20

ADDLY21

ADDLY22

ADDLY23

ADDLY30

ADDLY31

ADDLY32

ADDLY33

TSDLY10

TSDLY11

TSDLY12

TSDLY13

TSDLY20

TSDLY21

TSDLY23

TSDLY30

TSDLY31

TSDLY33

0

1

R/W DIGRESETB

0

This will allow delay before the ADC readings.

2

3

4

This will allow delay between each of ADC readings in a set.

5

6

7

8

This will allow delay after the set of ADC readings. This delay is only valid between

subsequent wrap around reading sequences with ADCONT

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

This will allow delay before the ADC Touch screen readings. This is like the ADDLY1,

but allows independent programming of touchscreen readings from general purpose

ADC readings to prevent code replacement in the system.

This will allow delay between each of ADC Touch screen readings in a set. This is

like the ADDLY2, but allows independent programming of touchscreen readings

from general purpose ADC readings to prevent code replacement in the system.

This will allow delay after the set of ADC Touch screen readings. This delay is only

valid between subsequent wrap around reading sequences with TSCONT mode.

This is like the ADDLY3, but allows independent programming of touchscreen

readings from general purpose ADC readings to prevent code replacement in the

system.

MC34708

Analog Integrated Circuit Device Data

167

Freescale Semiconductor

Functional Block Description

Table 168. Register 45, ADC 2

Name

Bit #

R/W

Reset

Default

Description

ADSEL00

ADSEL01

ADSEL02

ADSEL03

ADSEL10

ADSEL11

ADSEL12

ADSEL13

ADSEL20

ADSEL21

ADSEL22

ADSEL23

ADSEL30

ADSEL31

ADSEL32

ADSEL33

ADSEL40

ADSEL41

ADSEL42

ADSEL43

ADSEL50

ADSEL51

ADSEL52

ADSEL53

0

1

R/W

DIGRESETB

0

Channel Selection to place in ADRESULT0

Channel Selection to place in ADRESULT1

Channel Selection to place in ADRESULT2

Channel Selection to place in ADRESULT3

Channel Selection to place in ADRESULT4

Channel Selection to place in ADRESULT5

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Table 169. Register 46, ADC 3

Name

Bit # R/W

Reset

Default

Description

ADSEL60

ADSEL61

ADSEL62

ADSEL63

ADSEL70

ADSEL71

ADSEL72

ADSEL73

TSSEL00

TSSEL01

0

1

2

3

4

5

6

7

8

9

R/W DIGRESETB

0

Channel Selection to place in ADRESULT6

Channel Selection to place in ADRESULT7

Touchscreen Selection to place in ADRESULT0.

Select the action for the Touchscreen; 00 = dummy to discharge TSREF capacitance,

01 = to read X-plate, 10 = to read Y-plate, and 11 = to read Contact.

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

168

Functional Block Description

Table 169. Register 46, ADC 3

Name

Bit # R/W

Reset

Default

Description

TSSEL10

TSSEL11

TSSEL20

TSSEL21

TSSEL30

TSSEL31

TSSEL40

TSSEL41

TSSEL50

TSSEL51

TSSEL60

TSSEL61

TSSEL70

TSSEL71

10

11

12

13

14

15

16

17

18

19

20

21

22

23

R/W DIGRESETB

0

Touchscreen Selection to place in ADRESULT1.

See TSSEL0 for modes.

Touchscreen Selection to place in ADRESULT2.

See TSSEL0 for modes.

Touchscreen Selection to place in ADRESULT3.

See TSSEL0 for modes.

Touchscreen Selection to place in ADRESULT4.

See TSSEL0 for modes.

Touchscreen Selection to place in ADRESULT5.

See TSSEL0 for modes.

Touchscreen Selection to place in ADRESULT6.

See TSSEL0 for modes.

Touchscreen Selection to place in ADRESULT7.

See TSSEL0 for modes.

Table 170. Register 47, ADC 4

Name

Bit # R/W

Reset

Default

Description

Unused

0

1

R

0

Not available

Unused

ADRESULT00

ADRESULT01

ADRESULT02

ADRESULT03

ADRESULT04

ADRESULT05

ADRESULT06

ADRESULT07

ADRESULT08

ADRESULT09

Unused

2

DIGRESETB

ADC Result for ADSEL0

3

4

5

6

7

8

9

10

11

12

13

Not available

Unused

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

169

Functional Block Description

Table 170. Register 47, ADC 4

Name

Bit # R/W

Reset

Default

Description

ADRESULT10

ADRESULT11

ADRESULT12

ADRESULT13

ADRESULT14

ADRESULT15

ADRESULT16

ADRESULT17

ADRESULT18

ADRESULT19

14

15

16

17

18

19

20

21

22

23

R

DIGRESETB

0

ADC Result for ADSEL1

Table 171. Register 48, ADC5

Name

Bit # R/W

Reset

Default

Description

Unused

0

1

R

0

Not available

Unused

ADRESULT20

ADRESULT21

ADRESULT22

ADRESULT23

ADRESULT24

ADRESULT25

ADRESULT26

ADRESULT27

ADRESULT28

ADRESULT29

Unused

2

DIGRESETB

ADC Result for ADSEL2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

Unused

ADRESULT30

ADRESULT31

ADRESULT32

ADRESULT33

ADRESULT34

ADRESULT35

ADRESULT36

ADRESULT37

ADRESULT38

ADRESULT39

DIGRESETB

ADC Result for ADSEL3

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

170

Functional Block Description

Table 172. Register 49, ADC6

Name

Bit # R/W

Reset

Default

Description

Unused

0

1

R

0

Not available

Unused

ADRESULT40

ADRESULT41

ADRESULT42

ADRESULT43

ADRESULT44

ADRESULT45

ADRESULT46

ADRESULT47

ADRESULT48

ADRESULT49

Unused

2

DIGRESETB

ADC Result for ADSEL4

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

Unused

ADRESULT50

ADRESULT51

ADRESULT52

ADRESULT53

ADRESULT54

ADRESULT55

ADRESULT56

ADRESULT57

ADRESULT58

ADRESULT59

DIGRESETB

ADC Result for ADSEL5

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

171

Functional Block Description

Table 173. Register 50, ADC7

Name

Bit # R/W

Reset

Default

Description

Unused

0

1

R

0

Not available

Unused

ADRESULT60

ADRESULT61

ADRESULT62

ADRESULT63

ADRESULT64

ADRESULT65

ADRESULT66

ADRESULT67

ADRESULT68

ADRESULT69

Unused

2

DIGRESETB

ADC Result for ADSEL6

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Not available

Unused

ADRESULT70

ADRESULT71

ADRESULT72

ADRESULT73

ADRESULT74

ADRESULT75

ADRESULT76

ADRESULT77

ADRESULT78

ADRESULT79

DIGRESETB

ADC Result for ADSEL7

Table 174. Register 51, Battery Profile

Name

Bit # R/W

Reset

Default

Description

VBAT_TRKL0

VBAT_TRKL1

0

1

R/W RTCPORB

0

1

Trickle1 to Trickle2 change over threshold

00: 2.8 V

01: 2.9 V

10: 3.0 V

11: 3.1 V

CHRITERMEN

CHREN

2

3

4

5

R/W RTCPORB

1

Charger Current termination enable

Charger enable

LOWBATT0

LOWBATT1

Turn on detection threshold and low battery warning threshold

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

172

Functional Block Description

Table 174. Register 51, Battery Profile

Name

Bit # R/W

Reset

Default

Description

CHRCV0

CHRCV1

6

7

8

9

R/W RTCPORB

R/M RTCPORB

R/W RTCPORB

1

0

1

0

Constant Voltage Setting

CHRCV2

CHRCV3

CHRCV4

10 R/W RTCPORB

11 R/W RTCPORB

12 R/W RTCPORB

13 R/W RTCPORB

14 R/W RTCPORB

15 R/W RTCPORB

16 R/W RTCPORB

17 R/W RTCPORB

18 R/W RTCPORB

19 R/W RTCPORB

20 R/W RTCPORB

21 R/W RTCPORB

22 R/W RTCPORB

23 R/W RTCPORB

CHRCV5

CHRCC0

CHRCC1

Charge Current

CHRCC2

CHRCC3

CHRITERM0

CHRITERM1

CHRITERM2

BATTEMPL0

BATTEMPL1

BATTEMPH0

BATTEMPH1

FLOAT_CHARGE

Charger Current termination threshold

Battery charging temp low

Battery charging temp high

Buck enabled at EOC end of charge

1=Buck Enabled 0=Buck disabled

Table 175. Register 52, Charger Debounce

Name

Bit # R/W

Reset

Default

Description

BATTDETDB0

BATTDETDB1

VBATTDB0

VBUSDB0

0

1

2

3

4

5

6

7

8

9

R/W RESETB

R/M RESETB

R/W RESETB

1

0

1

0

Battery detect debounce

Battery voltage debounce

VBUS debounce

VBUSDB1

VAUXDB0

VAUX debounce

VUSXDB1

OVPDB0

Battery voltage over-voltage debounce

OVPDB1

CHRGLEDOVRD

AUXILIM0

10 R/W RESETB

11 R/W RESETB

12 R/W RESETB

13 R/W RESETB

14 R/W RESETB

15 R/W RESETB

Charger LED override

AUX input current limit

AUXILIM1

AUXILIM2

SUP_OVP_DB0

VBUS or Aux supply over-voltage debounce

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

173

Functional Block Description

Table 175. Register 52, Charger Debounce

Name

Bit # R/W

Reset

Default

Description

DIE_TEMP_DB0

DIE_TEMP_DB1

THFB_DLY0

THFB_DLY1

ILIM_1P5

16 R/W RESETB

17 R/W RESETB

18 R/W RESETB

19 R/W RESETB

20 R/W RESETB

1

0

1

0

Die Temp Comparator Debounce

Interrupt/Regulation Delay

1.5 A USB/AUX Charger

0=OFF 1=ON

THFB_EN

THFB_MODE

BATT_ISO_EN

21 R/W RESETB

22 R/W RESETB

23 R/W RESETB

1

0

Thermal Foldback Enable

0=OFF 1=ON

Thermal Feedback LOW/High Temp Range Select

0=LOW 1=HIGH

Mbatt Open/Closed during EOC

1=OPEN 0=CLOSED

Table 176. Register 53, Charger Source

Name

Bit # R/W

Reset

Default

Description

VBUSTL0

VBUSTL1

0

1

2

3

4

5

6

7

8

9

R/W RESETB

R/M RESETB

R/W RESETB

1

0

1

0

1

0

1

0

1

VBUS threshold low

VBUSTL2

VBUSTH0

VBUS threshold high

Weak VBUS threshold

AUX threshold low

VBUSTH1

VBUSTH2

VBUSWEAK0

VBUSWEAK1

VBUSWEAK2

AUXTL0

AUXTL1

10 R/W RESETB

11 R/W RESETB

12 R/W RESETB

13 R/W RESETB

14 R/W RESETB

15 R/W RESETB

16 R/W RESETB

17 R/W RESETB

18 R/W RESETB

19 R/W RESETB

20 R/W RESETB

21 R/W RESETB

22 R/W RESETB

23 R/W RESETB

AUXTL2

AUXTH0

AUX threshold high

Weak Aux threshold

AUXTH1

AUXTH2

AUXWEAK0

AUXWEAK1

AUXWEAK2

CHRTIMER0

CHRTIMER1

CHRTIMER2

CHRTIMER3

AUXWEAKEN

VBUSWEAKEN

Enable weak AUX

Enable weak VBUS

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

174

Functional Block Description

Table 177. Register 54, Charger LED Control

Name

Bit # R/W

Reset

Default

Description

CHRGLEDRPER0

CHRGLEDRPER1

CHRGLEDRRAMP

CHRGLEDRDC0

CHRGLEDRDC1

CHRGLEDRDC2

CHRGLEDRDC3

CHRGLEDRDC4

CHRGLEDRDC5

CHRGLEDR0

0

1

2

3

4

5

6

7

8

9

R/W RESETB

0

1

0

1

0

Charger LED red repetition period

Charger LED red channel driver ramp enable

Charger LED red channel driver duty cycle

Charger LED red driver current setting

CHRGLEDR1

10 R/W RESETB

11 R/W RESETB

12 R/W RESETB

13 R/W RESETB

14 R/W RESETB

15 R/W RESETB

16 R/W RESETB

17 R/W RESETB

18 R/W RESETB

19 R/W RESETB

20 R/W RESETB

21 R/W RESETB

22 R/W RESETB

23 R/W RESETB

CHRGLEDREN

CHRGLEDGPER0

CHRGLEDGPER1

CHRGLEDGRAMP

CHRGLEDGDC0

CHRGLEDGDC1

CHRGLEDGDC2

CHRGLEDGDC3

CHRGLEDGDC4

CHRGLEDGDC5

CHRGLEDG0

Charger LED red enable

Charger LED green repetition period

Charger LED green channel driver ramp enable

Charger LED green channel driver duty cycle

Charger LED green driver current setting

Charger LED green enable

CHRGLEDG1

CHRGLEDGEN

Table 178. Register 55, PWM Control

Name

Bit # R/W

Reset

Default

Description

PWM1DUTY0

PWM1DUTY1

PWM1DUTY2

PWM1DUTY3

PWM1DUTY4

PWM1DUTY5

0

1

2

3

4

5

R/W RESETB

0

PWM1 Duty Cycle

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

175

Functional Block Description

Table 178. Register 55, PWM Control

Name

Bit # R/W

Reset

Default

Description

PWMCLKDIV0

PWM1CLKDIV1

PWM1CLKDIV2

PWM1CLKDIV3

PWM1CLKDIV4

PWM1CLKDIV5

PWM2DUTY0

PWM2DUTY1

PWM2DUTY2

PWM2DUTY3

PWM2DUTY4

PWM2DUTY5

PWM2CLKDIV0

PWM2CLKDIV1

PWM2CLKDIV2

PWM2CLKDIV3

PWM2CLKDIV4

PWM2CLKDIV5

6

7

8

9

R/W RESETB

0

PWM1 Clock Divide Setting

10 R/W RESETB

11 R/W RESETB

12 R/W RESETB

13 R/W RESETB

14 R/W RESETB

15 R/W RESETB

16 R/W RESETB

17 R/W RESETB

18 R/W RESETB

19 R/W RESETB

20 R/W RESETB

21 R/W RESETB

22 R/W RESETB

23 R/W RESETB

PWM2 Duty Cycle

PWM2 Clock Divide Setting

Table 179. Register 56, Unused

Name

Bit #

R/W

Reset

Default

Description

Unused

0-23

R

0

Not available

Table 180. Register 57, Unused

Name

Bit #

R/W

Default

Description

Unused

0-23

R

0

Not available

Table 181. Register 58, Unused

Name

Bit #

R/W

Default

Description

Unused

0-23

R

0

Not available

Table 182. Register 59, Unused

Name

Bit #

R/W

Default

Description

Unused

0-23

R

0

Not available

Table 183. Register 60, Unused

Name

Bit #

R/W

Default

Description

Unused

0-23

R

0

Not available

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

176

Functional Block Description

Table 184. Register 61, Unused

Name

Bit #

R/W

Reset

Default

Description

Unused

0-23

R

0

Not available

Table 185. Register 62, Unused

Name

Bit #

R/W

Default

Description

Unused

0-23

R

0

Not available

Table 186. Register 63, Unused

Name

Bit #

R/W

Default

Description

Unused

0-23

R

0

Not available

MC34708

Analog Integrated Circuit Device Data

177

Freescale Semiconductor

Typical Applications

8

Typical Applications

The following diagram gives a typical application diagram of the MC34708 PMIC together with its functional components. For

details on component references and additional components such as filters, refer to the individual sections.

8.1

Application Diagram

Tied to

BATTISNSCC

VBUS

(Charger input)

Aux charge input

M1

L1

2.2u

BP

R1

20m

M3

M2

C1

C69

C4

10u

C67

10n

1

10u

C2

C68

10n

10u

BP

D1

D9

D2

R73

To GND,

VCOREDIG,

Float

SW1 Output

2 x22u

C5

4.7u

L2

1.0u

BP

SW1IN

SW1ALX

GNDSW1A

SW1FB

O/P

Drive

Switching Charger

Interface and Control, Protection,

Trickle Generation

Battery Interface &

Protection

C6/C7

SW1

Dual Phase

GP

2000 mA

Buck

SW1CFG

SW1VSSSNS

VCOREDIG

To AP

LICELL, UID, Die Temp, GPO4

D8

Voltage

Current

/

GNDADC

SW1BLX

GNDSW1B

O/P

Drive

Sensing &

Translation

R18

100K

10 Bit GP

A/D Result

ADC

ADIN9

DVS

CONTROL

SW1PWGD

General Purpose ADC Inputs:

i.e., PA thermistor, Light Sensor, Etc.

ADIN10

ADIN11

SW2 Output

C11

C10

4.7u

BP

L4

A/D

Control

1.0u

SW2IN

SW2LX

GNDSW2

SW2FB

SW2PWGD

22u

MUX

O/P

Drive

SW2

ADIN12/TSX1

ADIN13/TSX2

ADIN14/TSY1

ADIN15/TSY2

TSREF

D10

R19

100K

LP

Touch

Screen

Interface

`

1000 mA

To AP

BP

Buck

Touch

Screen

Interface

SW3 Output

10u

C13

4.7u

L5

1.0u

Die Temp &

Thermal Warning

Detection

SW3IN

C54

C14

To Interrupt

Section

SW3

INT MEM

500 mA

Buck

O/P

Drive

SW3LX

GNDSW3

SW3FB

To battery

Thermistor

D11

2.2u

BPTHERM

NTCREF

C16

4.7u

SW4A Output

C17 10u

L6

1.0u

BP

R11 24K

SW4AIN

SW4ALX

GNDSW4A

SW4FBA

O/P

Drive

BATTISNSCCP

D12

(needs to be separate routes from

BATTISNSP and BATTISNN)

SW4

Dual Phase

DDR

1000 mA

Buck

BATTISNSCCN

CFP

Coulomb

Counter

CCOUT

SW4CFG

C53

To SPI

SW4B Output

C20 10u

C19

4.7u

L7

1.0u

Package Pin Legend

10uF

BP

SW4BIN

CFN

SW4BLX

GNDSW4B

SW4BFB

O/P

Drive

Output Pin

Input Pin

D13

SPIVCC

Shift Register

Bi-directional Pin

SW5

SW5 Output

C23 22u

C22

4.7u

L8

1.0u

CS

SPI

Interface

+

Muxed

I2C

Optional

Interface

SW5IN

CLK

SW5

I/O

1000 mA

Buck

O/P

Drive

SW5LX

GNDSW5

SW5FB

SPI

D14

MOSI

MISO

To Enables & Control

Registers

BP

C25

4.7u

L9

2.2u

GNDSPI

Shift Register

SWBSTIN

SWBSTLX

SWBSTFB

SWBST

Output

(Boost)

BP

D3

O/P

Drive

SWBST

380 mA

Boost

C56

VALWAYS

VCORE

1u

GNDSWBST

C26

10u

C50

MC34708

1u

C51

VCOREDIG

VDDLP

Reference

Generation

1u

SW4B

C57

100n

C52

SPI Control

VINREFDDR

VHALF

C55

100n

100pF

C49

VCOREREF

GNDCORE

GNDREF

VREFDDR

10mA

100n

VREFDDR

1u

C28

SPKR

SPKL

MIC

C30

2.2u

VINPLL

VPLL

BP

VPLL

50 mA

Pass

FET

To/From

Audio IC

BP

VUSB2DRV

VUSB2

TXD

RXD

Q1

Pass

FET

VUSB2

350mA

VBUS/ID

Detectors, Host

Auto detection

C29

2.2u

BP

To/From

AP

DPLUS

DMINUS

VDACDRV

VDAC

250mA

Q3

UART Switches

Audio Switches

C36

2.2u

DP

DM

To

Trimmed

Circuits

SPI

Trim-In-Package

Control

Logic

To/From

USB Cable

C38

SW5

VINGEN1

VGEN1

250mA

Pass

FET

GNDUSB

UID

2.2u

VBUS

BP

Startup

Sequencer

Decode

Trim?

OVP

Control

Logic

VGEN2DRV

VGEN2

PUMSx

Q5

PLL

Switchers

Pass

FET

VGEN2

250mA

VINUSB

VUSB

Monitor

Timer

SWBST

C47

C41

2.2u

VUSB

Regulator

RTC

Calibration

+

32 KHz

Internal

Osc

LDOVDD

BP

2.2u

SPI Result

Registers

Interrupt

Inputs

Enables &

Control

32 KHz

Buffers

Best

of

Supply

GNDREG1

GNDREG2

GNDREF1

GNDREF2

BP

LCELL

Switch

LICELL

C46

Coin Cell

Battery

PWM

Outputs

32 KHz

Crystal

Osc

GPIO Control

Li Cell

Charger

Core Control Logic, Timers, & Interrupts

100n

VSRTC

R4

R20 R3

C43

0.1u

To/From

AP

To AP

To Peripherals

To GND, or

VCOREDIG

18p

15p

C45

C44

Y1

32.768 KHz

Crystal

On/Off

Button

Reset

button

Figure 44. MC34708 Typical Application Schematic

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

178

Typical Applications

8.2

Bill of Material

The following table provides a complete list of the recommended components on a full featured system using the MC34708

Device. Critical components such as inductors, transistors, and diodes are provided with a recommended part number, but

equivalent components may be used.

Table 187. MC34708 Bill of Material ⁽⁷⁹⁾

Item

Quantity Component

Description

MC34708

Vendor

Comments

Freescale

PMIC

1

Charger/Battery Interface

10 F

TDK

Battery Filter

2

3

1

2

1

C1

R1, R2

M3

20 mOhm

Battery Sense

PMOS NTHS2101P

10 F

On Semi

GBAT

4

BP/ buck charging cap

Charger Buck inductor

5

C2

2.2 H LPS3015-222ML

FDMA510PZ

10 nF

Coilcraft

Fairchild

6

L1

VBUS Over-voltage protection

VBUS 10 nF input cap

7

M2

8

C67

M1

FDMA510PZ

2.2 F 20 V

Fairchild

Infineon

VAUX Over-voltage protection

VAUX charge input cap

9

11

12

13

14

15

16

17

18

C4

10 nF

VAUX 10 nF input cap

C68

D9

Diode BAS3010-03LRH

1.0 nF

Schottky for charger snubber

1.0 nF For charger snubber (DNP)

10 Ohm for snubber (DNP)

C69

R73

D2

10 Ohm

Green Charge LED

Red Charge LED

24 k Batt thermistor PU

D1

NTC Thermistor PU

-

Miscellaneous

1.0 F

VALWAYS

VSRTC

19

20

21

22

23

24

25

26

27

28

29

1

C56

C43

C50

C51

C52

C49

C53

C46

Y1

100 nF

1.0 F

VCORE

1.0 F

VCOREDIG

VDDLP

100 pF

100 nF

VREFCORE

Coulomb Counter

Coin cell

10 F

100 nF

Crystal 32.768 kHz CC7

18 pF

Oscillator

C44

C45

18 pF

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

179

Typical Applications

Table 187. MC34708 Bill of Material ⁽⁷⁹⁾

Description Vendor

Item

30

Quantity Component

Comments

100 k

RESETB, RESETBMCU Pull-ups

2

1

R3, R4

R20

SDWNB Pull-up

31

Boost

2.2 H LPS3015-222ML

Diode BAS52

4.7 F 16 V

Coilcraft

Infineon

Boost Inductor

32

33

1

L9

D3

Boost diode

Boost Output Capacitor

Boost Input Capacitor

34

C26

C25

4.7 F

35

SW1

36

1.0 H VLS201612ET-1R0N TDK

1.0 H VLS252010ET-1R0N TDK

Buck 1 Inductor (I_MAX< 1.6 Amps)

2

0

2

1

Optional dual phase Inductor (I_MAX 2.0 Amps)

Taiyo Yuden Optional single Phase inductor (I_MAX< 1.6 Amps)

37

L2, L3

1.0 H BRL3225T1ROM

1.0 uH LPS4012-102NL

22 F

38

Coilcraft

Optional single phase inductor (I_MAX 2.0 Amps)

Buck 1 Output Capacitor

39

40

C6, C7

C5

4.7 F

Buck 1 Input Capacitor

41

Diode BAS3010-03LRH

Infineon

SW1LX diode

42

D8

SW2

43

1.0 H VLS252010ET-1R0N TDK

Buck 2 Inductor

1

L4

22 F

Buck 2 Output Capacitor

Buck 2 Input Capacitor

SW2LX diode

44

C11

C10

D10

4.7 F

45

Diode BAS3010-03LRH

Infineon

46

SW3

47

1.0 H VLS201612ET-1R0N TDK

Buck 3 Inductor

1

L5

10 F

Buck 3 Output Capacitor

Buck 3 Input Capacitor

SW3LX diode

48

C14

C13

D11

4.7 F

49

Diode BAS3010-03LRH

Infineon

50

SW4A

51

1.0 H VLS201612ET-1R0N TDK

Buck 4A Inductor

1

0

1

L6

1.0 H VLS252010ET-1R0N TDK

Optional Inductor

52

10 F

Buck 4A Output Capacitor

Buck 4A Input Capacitor

SW4ALX diode

53

C17

C16

D12

4.7 F

54

Diode BAS3010-03LRH

Infineon

55

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

180

Typical Applications

Table 187. MC34708 Bill of Material ⁽⁷⁹⁾

Description Vendor

Item

Quantity Component

Comments

SW4B

1.0 H VLS201612ET-1R0N TDK

Buck 4B Inductor

Optional Inductor

56

57

1

0

1

L7

-

1.0 H VLS25010ET-1R0N TDK

10 F

Buck 4B Output Capacitor

Buck 4B Input Capacitor

SW4BLX diode

58

C20

C19

D13

4.0 F

59

Diode BAS3010-03LRH

Infineon

60

SW5

61

1.0 H VLS252010ET-1R0N TDK

Buck 5 Inductor

1

L8

22 F

Buck 5 Output Capacitor

Buck 5 Input Capacitor

SW5LX diode

62

C23

C22

D14

4.7 F

63

Diode BAS3010-03LRH

Infineon

64

VPLL

65

2.2 F

VPLL

1

C30

VREFDDR

66

100 nF

VHALF 0.1 uF caps

VREFDDR

1

C57

C28

1.0 F

67

VDAC

68

PNP NSS12100UW3

On Semi

VDAC PNP

VVDAC

1

Q3

2.2 F

69

C36

VUSB2

70

PNP NSS12100UW3

VUSB2 PNP

VUSB2

1

Q1

2.2 F

71

C29

VUSB

72

2.2 F

4.7 F

VUSB

1

C47

C38

VGEN1

73

VGEN1

VGEN2

74

PNP NSS12100UW3

On Semi

VGEN2 PNP

VGEN2

1

Q5

2.2 F

75

C41

Notes

79. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings

or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their

application.

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Typical Applications

8.3

MC34708 Layout Guidelines

8.3.1

General board recommendations

1. It is recommended to use an 8 layer board stack-up arranged as follows:

• High current signal

• GND

• Signal

• Power

• Signal

• GND

• High current signal

2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area.

3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.

8.3.2

Component Placement

Sense resistors should be placed as Close to the IC as possible. Route the high current path flowing from VBATT to BATTISNSN

as thick and as short as possible to reduce power losses.

8.3.3

General Routing Requirements

1. Some recommended things to keep in mind for manufacturability:

• Via in pads require a 4.5 mil Minimum annular ring. Pad must be 9.0 mils larger than the hole

• Max copper thickness for lines less than 5.0 mils wide is 0.6 oz copper

• Minimum allowed spacing between line and hole pad is 3.5 mils

• Minimum allowed spacing between line and line is 3.0 mils

2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from

power, clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins.

3. Shield feedback traces of the switching regulators and keep them as short as possible (trace them on the bottom so the

ground and power planes shield these traces).

4. Sense pins must be directly connected to the 0.02 Ohm sense resistor R1 (BATTISNSN and BATTISNSP).

5. Avoid coupling trace between important signal/low noise supplies (like VREFCORE, VCORE, VCOREDIG) from any

switching node (i.e. SW1ALXx, SW2LXx, SW3LXx, SW4ALX, SW4BLX, SW5LXx, SWBSTLXx, and CHRGLXx).

6. Make sure that all components related to an specific block are referenced to the corresponding ground, e.g. all

components related to the SW1 converter must referenced to GNDSW1A1 and GNDSW1A2.

7. The LEDVDD trace must be orthogonal from the CHRGLXx traces.

8.3.4

Parallel Routing Requirements

2

1. SPI/I C signal routing:

• CLK is the fastest signal of the system, so it must be given special care. Here are some tips for routing the communication

signals:

• To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to

shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole

signal trace length.

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182

Typical Applications

Figure 45. Recommended Shielding for Critical Signals.

• These signals can be placed on an outer layer of the board to reduce their capacitance in respect to the ground plane.

• The crystal connected to the XTAL1 and XTAL2 pins must not have a ground plane directly below.

• The following are clock signals: CLK, CLK32K, CLK32KMCU, XTAL1, and XTAL2. These signals must not run parallel to

each other, or in the same routing layer. If it is necessary to run clock signals parallel to each other, or parallel to any other

signal, then follow a MAX PARALLEL rule as follows:

• Up to 1 inch parallel length – 25 mil minimum separation

• Up to 2 inch parallel length – 50 mil minimum separation

• Up to 3 inch parallel length – 100 mil minimum separation

• Up to 4 inch parallel length – 250 mil minimum separation

• Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good

practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.

2. The traces BATTISNSN and BATTISNSP that go to the R1 resistor must run in parallel.

8.3.5

Differential Routing

1. DP and DM traces should be routed as 90 ohm differential signals.

2. DPLUS and DMINUS traces should be routed as 90 ohm differential signals.

8.3.6

Switching Regulator Layout Recommendations

1. Per design, the MC34708 is designed to operate with only 1 input bulk capacitor. However, it is recommended to add a

high frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor should be in the

range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.

2. Make high-current ripple traces low inductance (short, high W/L ratio).

3. Make high-current traces wide or copper islands.

4. Make high-current traces SYMETRICAL for dual–phase regulators (SW1, SW4).

BP

SWxIN

Cin

SWx Output

Cin_hf

L

SWx LX

Co ut

GNDSWx

SWxFB

Figure 46. Generic Buck Regulator Architecture

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Typical Applications

Figure 47. Recommended Layout for Switching Regulators.

8.4

Thermal Considerations

8.4.1

Rating Data

The thermal rating data of the packages has been simulated with the results listed in Table 5.

Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol R

or θJA (Theta-JA)

θJA

strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. R

or θJMA (Theta-

θJMA

JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced

convection on both 1s and 2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly used.

The JEDEC standards can be consulted at http://www.jedec.org/

8.4.2

Estimation of Junction Temperature

An estimation of the chip junction temperature TJ can be obtained from the equation

T = T + (R

x P )

D

J

A

θJA

with

T = Ambient temperature for the package in °C

A

R_= Junction to ambient thermal resistance in °C/W

JA

P = Power dissipation in the package in W

D

The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal

performance. Unfortunately, there are two values in common usage: the value determined on a single layer board R

and the

θJA

value obtained on a four layer board R

. Actual application PCBs show a performance close to the simulated four layer board

θJMA

value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the

device.

At a known board temperature, the junction temperature TJ is estimated using the following equation

T = T + (R

x P ) with

D

J

B

θJB

T = Board temperature at the package perimeter in °C

B

R

= Junction to board thermal resistance in °C/W

θJB

P = Power dissipation in the package in W

D

When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.

See Functional Block Description for more details on thermal management.

MC34708

Analog Integrated Circuit Device Data

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184

Packaging

9

Packaging

The MC34708 is offered in two pin compatible 206 pin MAPBGA packages, an 8.0x8.0 mm, 0.5 mm pitch package, and a

13x13 mm, 0.8 mm pitch package.

9.1

Package Mechanical Dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to

www.freescale.com and perform a keyword search for the drawing’s document number.

Table 188. Package Drawing Information

Package

Suffix

Package Outline Drawing Number

98ASB42344B

98ASA00299D

206-pin MAPBGA (8 x 8), 0.5 mm

206-pin MAPBGA (13 x 13), 0.8 mm

VK

VM

Dimensions shown are provided for reference ONLY (For Layout and Design, refer to the Package Outline Drawing listed in the

following figures).

MC34708

Analog Integrated Circuit Device Data

185

Freescale Semiconductor

Packaging

Figure 48. 8 x 8 Package Mechanical Dimension

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

186

Packaging

Figure 49. 13 x 13 Package Mechanical Dimension

MC34708

Analog Integrated Circuit Device Data

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Freescale Semiconductor

Reference Section

10 Reference Section

Table 189. MC34708 Reference Documents

Reference

Description

MC34708FS

MC34708ER

Fact Sheet

Errata

MC34708

Analog Integrated Circuit Device Data

Freescale Semiconductor

188

Revision History

11 Revision History

REVISION

6.0

DATE

DESCRIPTION OF CHANGES

•

Initial release

7/2011

10/2011

•

Corrected the two pins SW2PWGD and SDWNB, and associated drawings.

Changed Charge LED Driver Electrical Specifications, VPLL Matching from 3.0 to 4.0%

Changed VPLL Electrical Specification, t_ON-VPLLfrom 100 to 120 s

Changed SWBST Electrical Specifications, I_{LEAK_SWBST}from 5.0 to 6.0 A

Added Max limit to Charger Input Current Limit (using the USB input)

Added note ⁽⁵⁸⁾to V_REFDDR

Changed R_{USB ON}value to 5.0 typ, 8.0 max

Set MIC bias to 1.5 V, and changed ON resistance values to 75 typ and 150 max.

Added Efficiency values for all Buck Converter

7.0

Added diodes to the LX pin on SW1, SW2, SW3, SW4A, SW4B, and SW5.

Updated schematics to reflect the LX pin diodes on SW1, SW2, SW3, SW4A, SW4B, and SW5, and

removed the 10 F VBUSVIN input capacitor.

MC34708

Analog Integrated Circuit Device Data

189

Freescale Semiconductor

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Information in this document is provided solely to enable system and

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MC34708

Rev. 7.0

10/2011


型号：	PC34708VK
厂家：	NXP
描述：	1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA206, 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, MO-275CCCE-1, MAPBGA-206
文件：	总190页 (文件大小：6323K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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