PCA85176H/Q900/1_技术文档

PCA85176

Automotive LCD driver for low multiplex rates

Rev. 5 — 11 July 2013

Product data sheet

1. General description

The PCA85176 is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)¹with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily

cascaded for larger LCD applications. The PCA85176 is compatible with most

microcontrollers and communicates via the two-line bidirectional I²C-bus. Communication

overheads are minimized by a display RAM with auto-incremented addressing, by

hardware subaddressing, and by display memory switching (static and duplex drive

modes).

2. Features and benefits

 AEC-Q100 compliant for automotive applications

 Single chip LCD controller and driver

 Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

 Selectable display bias configuration: static, ¹⁄₂, or ¹⁄₃

 Internal LCD bias generation with voltage-follower buffers

 40 segment drives:

 Up to 20 7-segment numeric characters

 Up to 10 14-segment alphanumeric characters

 Any graphics of up to 160 elements

 40  4-bit RAM for display data storage

 Auto-incremented display data loading across device subaddress boundaries

 Display memory bank switching in static and duplex drive modes

 Versatile blinking modes

 Independent supplies possible for LCD and logic voltages

 Wide power supply range: from 1.8 V to 5.5 V

 Wide logic LCD supply range:

 From 2.5 V for low-threshold LCDs

 Up to 8.0 V for guest-host LCDs and high-threshold twisted nematic LCDs

 Low power consumption

 Extended temperature range up to 95 C

 400 kHz I²C-bus interface

 May be cascaded for large LCD applications (up to 2560 elements possible)

 No external components required

 Manufactured in silicon gate CMOS process

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.

PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCA85176H

PCA85176T

TQFP64

plastic thin quad flat package, 64 leads; SOT357-1

body 10  10  1.0 mm

TSSOP56

plastic thin shrink small outline package, SOT364-1

56 leads; body width 6.1 mm

3.1 Ordering options

Table 2.

Ordering options

Type number

Sales item (12NC)

Orderable part number

IC

Delivery form

revision

PCA85176H/Q900/1

PCA85176T/Q900/1

935290065518

935290076118

PCA85176H/Q900/1,5

PCA85176T/Q900/1,1

1

tape and reel, 13 inch, dry pack

tape and reel, 13 inch

4. Marking

Table 3.

Marking codes

Type number

Marking code

PCA85176H

PCA85176T

PCA85176H/Q900/1

PCA85176T/Q900/1

PCA85176

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NXP Semiconductors

Automotive LCD driver for low multiplex rates

5. Block diagram

BP0 BP2 BP1 BP3

S0 to S39

40

V

LCD

BACKPLANE

OUTPUTS

DISPLAY SEGMENT

OUTPUTS

LCD

VOLTAGE

SELECTOR

DISPLAY

REGISTER

DISPLAY

CONTROLLER

OUTPUT BANK SELECT

AND BLINK CONTROL

LCD BIAS

GENERATOR

V

SS

CLK

CLOCK SELECT

AND TIMING

BLINKER

TIMEBASE

PCA85176

DISPLAY RAM

SYNC

POWER-ON

RESET

COMMAND

DECODER

WRITE DATA

CONTROL

DATA POINTER AND

AUTO INCREMENT

OSC

OSCILLATOR

V

DD

SCL

SDA

2

INPUT

FILTERS

I C-BUS

SUBADDRESS

COUNTER

CONTROLLER

SA0

A0

A1

A2

013aaa048

Fig 1. Block diagram of PCA85176

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

n.c.

S34

S35

S36

S37

S38

S39

n.c.

S17

S16

S15

S14

S13

S12

S11

S10

S9

3

4

5

6

7

8

PCA85176H

9

n.c.

10

11

12

13

14

15

16

SDA

SCL

SYNC

CLK

S8

S7

S6

V

S5

DD

OSC

A0

S4

n.c.

013aaa049

Top view. For mechanical details, see Figure 29.

Fig 2. Pinning diagram for TQFP64 (PCA85176H)

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

BP2

BP1

BP3

S0

BP0

2

V

LCD

V

SS

3

4

SA0

A2

5

S1

6

S2

A1

7

S3

A0

8

S4

OSC

9

S5

V

DD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

S6

CLK

SYNC

SCL

SDA

S39

S38

S37

S36

S35

S34

S33

S32

S31

S30

S29

S28

S27

S26

S25

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

PCA85176T

013aaa050

Top view. For mechanical details, see Figure 30.

Fig 3. Pinning diagram for TSSOP56 (PCA85176T)

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

6.2 Pin description

Table 4.

Symbol

Pin description

Description

TQFP64

TSSOP56

Type

(PCA85176H)

(PCA85176T)

SDA

SCL

10

44

input/output I²C-bus serial data line

11

45

input

input/output clock line

I²C-bus serial clock

CLK

13

47

V_DD

14

48

supply

supply voltage

SYNC

OSC

A0 to A2

SA0

12

46

input/output cascade synchronization

15

49

input

internal oscillator enable

16 to 18

19

50 to 52

53

input

subaddress inputs

input

I²C-bus address input

ground supply voltage

LCD supply voltage

V_SS

20

54

supply

output

V_LCD

21

55

BP0, BP2, 25 to 28

BP1, BP3

56, 1, 2, 3

LCD backplane outputs

S0 to S39 29 to 32, 34 to 47,

49 to 64, 2 to 7

4 to 43

-

output

-

LCD segment outputs

n.c.

1, 8, 9, 22 to 24,

33, 48

not connected; do not

connect and do not use as

feed through

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Product data sheet

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

7. Functional description

The PCA85176 is a versatile peripheral device designed to interface between any

microcontroller to a wide variety of LCD segment or dot matrix displays. It can directly

drive any static or multiplexed LCD containing up to four backplanes and up to

40 segments.

7.1 Commands of PCA85176

The commands available to the PCA85176 are defined in Table 5.

Table 5.

Definition of PCA85176 commands

Bit position labeled as - is not used.

Command

Bit

Operation Code

Reference

7

6

1

0

1

5

4

3

2

1

0

mode-set

C

0

-

E

B

M[1:0]

Table 7

Table 8

Table 9

Table 10

Table 11

load-data-pointer

device-select

bank-select

blink-select

P[5:0]

1

0

1

0

1

0

A[2:0]

0

I

O

AB

BF[1:0]

All available commands carry a continuation bit C in their most significant bit position as

shown in Figure 22. When this bit is set logic 1, it indicates that the next byte of the

transfer to arrive will also represent a command. If this bit is set logic 0, it indicates that

the command byte is the last in the transfer. Further bytes will be regarded as display data

(see Table 6).

Table 6.

C bit description

Bit

Symbol Value

Description

continue bit

7

C

0

last control byte in the transfer; next byte will be regarded

as display data

1

control bytes continue; next byte will be a command too

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

7.1.1 Command: mode-set

The mode-set command allows configuring the multiplex mode, the bias levels and

enabling or disabling the display.

Table 7.

Mode-set command bit description

Bit

Symbol Value

Description

7

C

-

0, 1

10

-

see Table 6

6 to 5

fixed value

4

3

-

unused

E

display status^[1]

disabled (blank)^[3]

enabled

0^[2]

1

2

B

LCD bias configuration^[4]

¹⁄₃bias

¹⁄₂bias

0^[2]

1

1 to 0

M[1:0]

LCD drive mode selection

static; BP0

01

10

1:2 multiplex; BP0, BP1

1:3 multiplex; BP0, BP1, BP2

1:4 multiplex; BP0, BP1, BP2, BP3

11

00^[2]

[1] The possibility to disable the display allows implementation of blinking under external control.

[2] Default value.

[3] The display is disabled by setting all backplane and segment outputs to V_LCD

.

[4] Not applicable for static drive mode.

7.1.2 Command: load-data-pointer

The load-data-pointer command defines the display RAM address where the following

display data will be sent to.

Table 8.

Load-data-pointer command bit description

See Section 7.6.1.

Bit

7

Symbol Value

Description

see Table 6

fixed value

C

0, 1

0

6

-

5 to 0

P[5:0]

000000^[1]to 6 bit binary value, 0 to 39; transferred to the data pointer to

100111 define one of forty display RAM addresses

[1] Default value.

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

7.1.3 Command: device-select

The device-select command allows defining the subaddress counter value.

Table 9.

Device-select command bit description

See Section 7.6.2.

Bit

Symbol Value

Description

see Table 6

fixed value

7

C

0, 1

6 to 3

2 to 0

-

1100

A[2:0]

000^[1]to 111 3 bit binary value, 0 to 7; transferred to the subaddress

counter to define one of eight hardware subaddresses

[1] Default value.

7.1.4 Command: bank-select

The bank-select command controls where data is written to RAM and where it is displayed

from.

Table 10. Bank-select command bit description

See Section 7.6.5.

Bit

Symbol Value

Description

Static

1:2 multiplex^[1]

7

C

-

0, 1

see Table 6

fixed value

6 to 2

1

11110

I

input bank selection; storage of arriving display data

0^[2]

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

0

O

output bank selection; retrieval of LCD display data

0^[2]

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

[2] Default value.

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

7.1.5 Command: blink-select

The blink-select command allows configuring the blink mode and the blink frequency.

Table 11. Blink-select command bit description

See Section 7.1.5.1.

Bit

7

Symbol Value

Description

C

0, 1

see Table 6

6 to 3

2

-

1110

fixed value

AB

blink mode selection

0^[1]

1

normal blinking^[2]

alternate RAM bank blinking^[3]

1 to 0

BF[1:0]

blink frequency selection

00^[1]

01

off

1

10

2

11

3

[1] Default value.

[2] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

7.1.5.1 Blinking

The display blinking capabilities of the PCA85176 are very versatile. The whole display

can blink at frequencies selected by the blink-select command (see Table 11). The blink

frequencies are derived from the clock frequency. The ratio between the clock and blink

frequencies depends on the blink mode selected (see Table 12).

An additional feature is for an arbitrary selection of LCD elements to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. By means of the output bank selector, the displayed RAM

banks are exchanged with alternate RAM banks at the blink frequency. This mode can

also be specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of

LCD elements can blink by selectively changing the display RAM data at fixed time

intervals.

The entire display can blink at a frequency other than the nominal blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 7).

Table 12. Blink frequencies

Blink mode

Blink frequency^[1]

off

1

-

f_clk

---------

f_blink

=

768

f_clk

------------

2

1536

f_clk

------------

3

3072

[1] The blink frequency is proportional to the clock frequency (f_clk). For the range of the clock frequency see

Table 20.

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PCA85176

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Automotive LCD driver for low multiplex rates

7.2 Power-On Reset (POR)

At power-on the PCA85176 resets to the following starting conditions:

• All backplane and segment outputs are set to V_LCD

• The selected drive mode is: 1:4 multiplex with ¹⁄₃bias

• Blinking is switched off

• Input and output bank selectors are reset

• The I²C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• The display is disabled (bit E = 0, see Table 7)

Remark: Do not transfer data on the I²C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.3 Possible display configurations

The possible display configurations of the PCA85176 depend on the number of active

backplane outputs required. A selection of display configurations is shown in Table 13. All

of these configurations can be implemented in the typical system shown in Figure 5.

dot matrix

7-segment with dot

14-segment with dot and accent

013aaa312

Fig 4. Example of displays suitable for PCA85176

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NXP Semiconductors

Automotive LCD driver for low multiplex rates

Table 13. Selection of possible display configurations

Number of

Backplanes

Icons

Digits/Characters

7-segment^[1]

Dot matrix/

Elements

14-segment^[2]

4

3

2

1

160

120

80

20

15

10

5

10

7

160 (4  40)

120 (3  40)

80 (2  40)

40 (1  40)

5

40

2

[1] 7 segment display has 8 elements including the decimal point.

[2] 14 segment display has 16 elements including decimal point and accent dot.

V

DD

t

r

R ≤

2C

B

V

DD

LCD

40 segment drives

4 backplanes

SDA

SCL

OSC

HOST

MICRO-

PROCESSOR/

MICRO-

LCD PANEL

PCA85176

(up to 160

elements)

CONTROLLER

A0 A1 A2 SA0

V

SS

013aaa051

V

SS

The resistance of the power lines must be kept to a minimum.

Fig 5. Typical system configuration

The host microcontroller maintains the 2-line I²C-bus communication channel with the

PCA85176. The internal oscillator is enabled by connecting pin OSC to pin V_SS. The

appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.

The only other connections required to complete the system are the power supplies (V_DD

,

V

_SS, and V_LCD) and the LCD panel chosen for the application.

7.3.1 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of three

impedances connected between V_LCDand V_SS. The center impedance is bypassed by

switch if the ¹⁄₂bias voltage level for the 1:2 multiplex drive mode configuration is

selected.

7.3.2 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

7.3.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

V

_LCDand the resulting discrimination ratios (D) are given in Table 14.

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Automotive LCD driver for low multiplex rates

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across

a segment. It can be thought of as a measurement of contrast.

Table 14. Biasing characteristics

LCD drive

mode

Number of:

LCD bias

configuration

V_offRMSV_onRMS

------------------------ ----------------------- D = ------------------------

V_LCDV_LCDV_offRMS

V_onRMS

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1



1

⁄

1:2 multiplex

1:3 multiplex

1:4 multiplex

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

2

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th(off)), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode a suitable choice is V_LCD> 3V_th(off)

.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 1:

a²+ 2a + n

n  1 + a²

V_onRMS

=

-----------------------------

(1)

V

LCD

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 2:

a²– 2a + n

n  1 + a²

V_offRMS

=

-----------------------------

(2)

(3)

V

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 3:

a²+ 2a + n

V_onRMS

----------------------

D =

=

---------------------------

a²– 2a + n

V_offRMS

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PCA85176

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Automotive LCD driver for low multiplex rates

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V_LCD

• 1:4 multiplex (¹⁄₂bias): V_LCD

=

6  V_offRMS= 2.449V_offRMS

4  3

---------------------

= 2.309V_offRMS

3

These compare with V_LCD= 3V_offRMSwhen ¹⁄₃bias is used.

It should be noted that V_LCDis sometimes referred as the LCD operating voltage.

7.3.3.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependent on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_th(off)) and the other at 90 % relative transmission (at V_th(on)), see

Figure 6. For a good contrast performance, the following rules should be followed:

V

_onRMS V_thon

_offRMS V_thoff

(4)

(5)

V

_on(RMS)and V_off(RMS)are properties of the display driver and are affected by the selection

of a, n (see Equation 1 to Equation 3) and the V_LCDvoltage.

V_th(off)and V_th(on)are properties of the LCD liquid and can be provided by the module

manufacturer. V_th(off)is sometimes just named V_th. V_th(on)is sometimes named saturation

voltage V_sat

.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

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PCA85176

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Automotive LCD driver for low multiplex rates

100 %

90 %

10 %

V

[V]

RMS

V

th(off)

V

th(on)

OFF

SEGMENT

GREY

SEGMENT

ON

SEGMENT

013aaa494

Fig 6. Electro-optical characteristic: relative transmission curve of the liquid

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PCA85176

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Automotive LCD driver for low multiplex rates

7.3.4 LCD drive mode waveforms

7.3.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD. The

backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Figure 7.

T

fr

LCD segments

V

LCD

BP0

Sn

V

SS

state 1

(on)

state 2

(off)

V

LCD

V

SS

V

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

0 V

state 1

−V

LCD

V

LCD

state 2

0 V

−V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa207

V_state1(t) = V_Sn(t)  V_BP0(t).

_on(RMS)= V_LCD

V

.

V_state2(t) = V_{(Sn + 1)}(t)  V_BP0(t).

V_off(RMS)= 0 V.

Fig 7. Static drive mode waveforms

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Automotive LCD driver for low multiplex rates

7.3.4.2 1:2 Multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCA85176 allows the use of ¹⁄₂bias or ¹⁄₃bias in this mode as shown in Figure 8 and

Figure 9.

T

fr

V

LCD

LCD segments

V

/2

BP0

BP1

Sn

LCD

SS

state 1

V

LCD

state 2

V

/2

LCD

SS

V

LCD

V

SS

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

/2

LCD

0 V

−V

state 1

/2

LCD

−V

LCD

V

LCD

/2

LCD

0 V

state 2

−V

/2

LCD

−V

(b) Resultant waveforms

at LCD segment.

013aaa208

V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.791V_LCD

.

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.354V_LCD

.

Fig 8. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

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T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

Sn

V

/3

LCD

SS

state 1

V

LCD

state 2

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/3

LCD

V

/3

LCD

0 V

−V

state 1

/3

LCD

−2V

−V

/3

LCD

V

LCD

2V

/3

LCD

V

/3

LCD

0 V

−V

state 2

/3

LCD

−2V

−V

/3

LCD

(b) Resultant waveforms

at LCD segment.

013aaa209

V_state1(t) = V_Sn(t)  V_BP0(t).

_on(RMS)= 0.745V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.333V_LCD

V

.

Fig 9. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

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7.3.4.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as

shown in Figure 10.

T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

BP2

Sn

V

/3

LCD

SS

state 1

state 2

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+2

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V /3

LCD

V

/3

LCD

state 1

0 V

−V

/3

LCD

−2V

−V

/3

LCD

V

LCD

2V /3

LCD

V

/3

LCD

state 2

0 V

−V

/3

LCD

−2V

−V

/3

LCD

(b) Resultant waveforms

at LCD segment.

013aaa210

V_state1(t) = V_Sn(t)  V_BP0(t).

_on(RMS)= 0.638V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.333V_LCD

V

.

Fig 10. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

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7.3.4.4 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as

shown in Figure 11.

T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

BP2

V

/3

LCD

SS

state 1

state 2

V

LCD

2V

LCD

/3

V

/3

LCD

SS

V

LCD

2V

LCD

/3

V

/3

LCD

SS

V

LCD

2V

/3

LCD

BP3

Sn

V

/3

LCD

SS

V

LCD

2V

LCD

/3

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+2

Sn+3

V

/3

LCD

SS

V

LCD

2V

LCD

/3

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

LCD

/3

V

/3

LCD

state 1

0 V

-V

/3

LCD

-2V

/3

LCD

-V

LCD

V

LCD

2V

LCD

/3

V

/3

LCD

0 V

-V

state 2

/3

LCD

-2V

/3

LCD

-V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa211

V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.577V_LCD

.

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 11. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias

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7.4 Oscillator

7.4.1 Internal clock

The internal logic of the PCA85176 and its LCD drive signals are timed either by its

internal oscillator or by an external clock. The internal oscillator is enabled by connecting

pin OSC to pin V_SS. If the internal oscillator is used, the output from pin CLK can be used

as the clock signal for several PCA85176 in the system that are connected in cascade.

7.4.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to V_DD. The LCD

frame frequency is determined by the clock frequency (f_clk).

Remark: A clock signal must always be supplied to the device; removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.4.3 Timing

The PCA85176 timing controls the internal data flow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. In cascaded

applications, the correct timing relationship between each PCA85176 in the system is

maintained by the synchronization signal at pin SYNC. The timing also generates the LCD

frame frequency signal. The frame frequency signal is a fixed division of the clock

f_clk

-------

=

frequency from either the internal or an external clock: f_fr

24

7.5 Backplane and segment outputs

7.5.1 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required, the

unused outputs can be left open-circuit.

• In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities

• In 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 all carry the

same signals and may also be paired to increase the drive capabilities

• In static drive mode the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements

7.5.2 Segment outputs

The LCD drive section includes 40 segment outputs S0 to S39 which should be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display register. When

less than 40 segment outputs are required, the unused segment outputs should be left

open-circuit.

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7.6 Display RAM

The display RAM is a static 40  4-bit RAM which stores LCD data.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bitmap, Figure 12, shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the

segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,

second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1,

BP2, and BP3 respectively.

display RAM addresses (columns)/segment outputs (S)

0

1

2

3

4

35 36 37 38 39

0

1

2

3

display RAM bits

(rows)/

backplane outputs

(BP)

mbe525

The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs; and between the bits in a RAM row and the backplane outputs.

Fig 12. Display RAM bitmap

When display data is transmitted to the PCA85176, the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and depending on the current multiplex drive mode the bits are stored singularly,

in pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment

display showing all drive modes is given in Figure 13; the RAM filling organization

depicted applies equally to other LCD types.

• In static drive mode the eight transmitted data bits are placed into row 0 as one byte

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and 1 as two successive 4-bit RAM words

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address, but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted (see Section 7.6.3)

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, 1, 2, and 3 as two successive 4-bit RAM words

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7.6.1 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 8). Following this command, an

arriving data byte is stored at the display RAM address indicated by the data pointer. The

filling order is shown in Figure 13.

After each byte is stored, the content of the data pointer is automatically incremented by a

value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I²C-bus data access terminates early then the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.6.2 Subaddress counter

The storage of display data is determined by the contents of the subaddress counter.

Storage is allowed only when the content of the subaddress counter match with the

hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined

by the device-select command (see Table 9). If the content of the subaddress counter and

the hardware subaddress do not match then data storage is inhibited but the data pointer

is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overflows.

The storage arrangements described lead to extremely efficient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCA85176 occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character.

The hardware subaddress must not be changed while the device is being accessed on the

I²C-bus interface.

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7.6.3 RAM writing in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 15 (see Figure 13 as

well).

Table 15. Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1

a0

-

b7

b6

b5

-

b4

b3

b2

-

b1

b0

-

c7

c6

c5

-

c4

c3

c2

-

c1

c0

-

d7

d6

d5

-

:

-

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 16.

Table 16. Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1/b7 b4

a0/b6 b3

b1/c7 c4

b0/c6 c3

c1/d7 d4

c0/d6 d3

d1/e7 e4

d0/e6 e3

:

b5

-

b2

-

c5

-

c2

-

d5

-

d2

-

e5

-

e2

-

In the case described in Table 16 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a

combination of writing and rewriting the RAM like follows:

• In the first write to the RAM, bits a7 to a0 are written

• The data-pointer (see Section 7.6.1 on page 24) has to be set to the address of bit a1

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7

and b6

• The data-pointer has to be set to the address of bit b1

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and

c6

Depending on the method of writing to the RAM (standard or entire filling by rewriting),

some elements remain unused or can be used, but it has to be considered in the module

layout process as well as in the driver software design.

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7.6.4 Writing over the RAM address boundary

In all multiplex drive modes, depending on the setting of the data pointer, it is possible to

fill the RAM over the RAM address boundary. If the PCA85176 is part of a cascade the

additional bits fall into the next device that also generates the acknowledge signal. If the

PCA85176 is a single device or the last device in a cascade the additional bits will be

discarded and no acknowledge signal will be generated.

7.6.5 Bank selection

7.6.5.1 Output bank selector

The output bank selector (see Table 10 on page 9) selects one of the four rows per display

RAM address for transfer to the display register. The actual row selected depends on the

particular LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, followed by the

contents of row 1, row 2, and then row 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

7.6.5.2 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded by using the bank-select

command (see Table 10). The input bank selector functions independently to the output

bank selector.

7.6.5.3 RAM bank switching

The PCA85176 includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. A bank can be thought of as one RAM row or a collection of RAM rows (see

Figure 14). The RAM bank switching gives the provision for preparing display information

in an alternative bank and to be able to switch to it once it is complete.

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Fig 14. RAM banks in static and multiplex driving mode 1:2

There are two banks; bank 0 and bank 1. Figure 14 shows the location of these banks

relative to the RAM map. Input and output banks can be set independently from one

another with the Bank-select command (see Table 10 on page 9). Figure 15 shows the

concept.

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Fig 15. Bank selection

In the static drive mode, the bank-select command may request the contents of row 2 to

be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the

contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

In Figure 16 an example is shown for 1:2 multiplex drive mode where the displayed data is

read from the first two rows of the memory (bank 0), while the transmitted data is stored in

the second two rows of the memory (bank 1).

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Fig 16. Example of the Bank-select command with multiplex drive mode 1:2

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8. Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 17).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 17. Bit transfer

8.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P.

The START and STOP conditions are illustrated in Figure 18.

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Fig 18. Definition of START and STOP conditions

8.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 19.

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MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

mga807

Fig 19. System configuration

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration)

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition

Acknowledgement on the I²C-bus is illustrated in Figure 20.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from

master

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 20. Acknowledgement of the I²C-bus

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8.5 I²C-bus controller

The PCA85176 acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCA85176 are

the acknowledge signals of the selected devices. Device selection depends on the

I²C-bus slave address, on the transferred command data and on the hardware

subaddress.

In single device applications, the hardware subaddress inputs A0, A1, and A2 are

normally tied to V_SSwhich defines the hardware subaddress 0. In multiple device

applications A0, A1, and A2 are tied to V_SSor V_DDusing a binary coding scheme, so that

no two devices with a common I²C-bus slave address have the same hardware

subaddress.

8.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

8.7 I²C-bus protocol

Two I²C-bus slave addresses (0111 000 and 0111 001) are used to address the

PCA85176. The entire I²C-bus slave address byte is shown in Table 17.

Table 17. I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

1

0

SA0

The PCA85176 is a write-only device and will not respond to a read access, therefore bit 0

should always be logic 0. Bit 1 of the slave address byte that a PCA85176 will respond to,

is defined by the level tied to its SA0 input (V_SSfor logic 0 and V_DDfor logic 1).

Having two reserved slave addresses allows the following on the same I²C-bus:

• Up to 16 PCA85176 for very large LCD applications

• The use of two types of LCD multiplex drive modes

The I²C-bus protocol is shown in Figure 21. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of the two possible

PCA85176 slave addresses available. All PCA85176 whose SA0 inputs correspond to

bit 0 of the slave address respond by asserting an acknowledge in parallel. This I²C-bus

transfer is ignored by all PCA85176 whose SA0 inputs are set to the alternative level.

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NXP Semiconductors

Automotive LCD driver for low multiplex rates

acknowledge

by A0, A1 and A2

selected

acknowledge by

all addressed

PCA85176s

R/W

0

PCA85176 only

slave address

S

A

0

1

0

A

C

COMMAND

A

DISPLAY DATA

A

P

S

1 byte

n ≥ 1 byte(s)

n ≥ 0 byte(s)

update data pointers

and if necessary,

subaddress counter

013aaa053

Fig 21. I²C-bus protocol

After an acknowledgement, one or more command bytes follow that define the status of

each addressed PCA85176.

The last command byte sent is identified by resetting its most significant bit, continuation

bit C (see Figure 22). The command bytes are also acknowledged by all addressed

PCA85176 on the bus.

MSB

LSB

C

REST OF OPCODE

msa833

Fig 22. Format of command byte

After the last command byte, one or more display data bytes may follow. Display data

bytes are stored in the display RAM at the address specified by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data directed to the intended PCA85176 device.

An acknowledgement after each byte is asserted only by the PCA85176 that are

addressed via address lines A0, A1, and A2. After the last display byte, the I²C-bus

master asserts a STOP condition (P). Alternately a START may be asserted to restart an

I²C-bus access.

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Product data sheet

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

9. Internal circuitry

V

DD

SA0

CLK

V

SS

DD

SS

SCL

V

SS

DD

V

SS

OSC

V

SS

DD

SDA

SYNC

V

SS

DD

A0, A1 A2

V

SS

LCD

BP0, BP1,

BP2, BP3

V

SS

V

LCD

S0 to S39

V

SS

mdb076

Fig 23. Device protection circuits

PCA85176

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Product data sheet

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PCA85176

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Automotive LCD driver for low multiplex rates

10. Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

11. Limiting values

Table 18. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

0.5

Max

+6.5

+9.0

+6.5

Unit

V

V_DD

V_LCD

V_I

supply voltage

LCD supply voltage

input voltage

V

on each of the pins CLK,

SDA, SCL, SYNC, SA0,

OSC, A0 to A2

V

V_O

output voltage

on each of the pins S0 to

S39, BP0 to BP3

0.5

+9.0

V

I_I

input current

output current

supply current

10

50

-

+10

+50

400

100

2000

mA

mW

V

I_O

I_DD

I_DD(LCD)LCD supply current

I_SS

ground supply current

total power dissipation

output power

P_tot

P_o

-

[1]

V_ESD

electrostatic discharge

voltage

HBM

-

CDM

[2]

[3]

[4]

TQFP64 (PCA85176H)

TSSOP56 (PCA85176T)

-

1000

1500

200

V

-

V

I_lu

latch-up current

-

mA

C

T_stg

T_amb

storage temperature

ambient temperature

55

40

+150

+95

operating device

[1] Pass level; Human Body Model (HBM), according to Ref. 7 “JESD22-A114”

[2] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”

[3] Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (T_amb(max)).

[4] According to the store and transport requirements (see Ref. 13 “UM10569”) the devices have to be stored

at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

12. Static characteristics

Table 19. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 8.0 V; T_amb= 40 C to +95 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

LCD supply voltage

supply current

V_LCD 6.5 V

V_LCD> 6.5 V

V_DD< 2.5 V

1.8

2.5

-

5.5

6.5

8.0

7

V

-

V

V_LCD

-

V

V_DD 2.5 V

-

V

[1][2]

[1]

I_DD

f_clk(ext)= 1536 Hz

3.5

2.7

A

V_DD= 3.0 V;

T_amb= 25 C

-

I_DD(LCD)

LCD supply current

f_clk(ext)= 1536 Hz

-

18

13

25

-

A

V_LCD= 3.0 V;

T_amb= 25 C

Logic^[3]

V_P(POR)

V_IL

power-on reset supply voltage

LOW-level input voltage

1.0

1.3

-

1.6

V

on pins CLK, SYNC,

OSC, A0 to A2, SA0,

SCL, SDA

V_SS

0.3V_DD

[4][5]

V_IH

HIGH-level input voltage

LOW-level output current

on pins CLK, SYNC,

OSC, A0 to A2, SA0,

SCL, SDA

0.7V_DD

-

V_DD

V

I_OL

output sink current;

V_OL= 0.4 V; V_DD= 5 V

on pins CLK and SYNC

on pin SDA

1

3

1

-

mA

I_OH(CLK)

I_L

HIGH-level output current on pin CLK output source current;

V_OH= 4.6 V; V_DD= 5 V

leakage current

V_I= V_DDor V_SS

;

1

-

+1

A

on pins CLK, SCL, SDA,

A0 to A2 and SA0

I_L(OSC)

C_I

leakage current on pin OSC

input capacitance

V_I= V_DD

1

-

+1

7

A

[6]

-

pF

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

Table 19. Static characteristics …continued

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 8.0 V; T_amb= 40 C to +95 C; unless otherwise specified.

Symbol

LCD outputs

V_O

Parameter

Conditions

Min

Typ

Max

Unit

output voltage variation

output resistance

on pins BP0 to BP3 and

S0 to S39

100

-

+100

mV

[7]

R_O

V_LCD= 5 V

on pins BP0 to BP3

on pins S0 to S39

-

1.5

6.0

-

k

[1] LCD outputs are open-circuit; inputs at V_SSor V_DD; external clock with 50 % duty factor; I²C-bus inactive.

[2] For typical values, see Figure 24.

[3] The I²C-bus interface of the PCA85176 is 5 V tolerant.

[4] When tested, I²C pins SCL and SDA have no diode to V_DDand may be driven to the V_Ilimiting values given in Table 18 (see Figure 23

as well).

[5] Propagation delay of driver between clock (CLK) and LCD driving signals.

[6] Periodically sampled, not 100 % tested.

[7] Outputs measured one at a time.

001aal523

5

I

DD

(μA)

4

3

2

1

0

2

3

4

5

6

V

DD

(V)

T_amb= 30 C; 1:4 multiplex drive mode; V_LCD= 6.5 V; f_clk(ext)= 1.536 kHz; all RAM written with

logic 1; no display connected; I²C-bus inactive.

Fig 24. Typical I_DDwith respect to V_DD

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

13. Dynamic characteristics

Table 20. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 8.0 V; T_amb= 40 C to +95 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock

[1]

f_clk(int)

internal clock frequency

PCA85176H

PCA85176T

1440

1920

960

1970

2640

-

2640

3600

4800

Hz

f_clk(ext)

f_fr

external clock frequency

frame frequency

internal clock

PCA85176H

PCA85176T

external clock

60

80

40

60

82

110

150

200

-

Hz

s

110

-

t_clk(H)

t_clk(L)

HIGH-level clock time

LOW-level clock time

-

Synchronization

t_{PD(SYNC_N)}SYNC propagation delay

-

30

-

ns

s

t_{SYNC_NL}

t_PD(drv)

I²C-bus^[3]

Pin SCL

f_SCL

SYNC LOW time

1

-

[2]

driver propagation delay

V_LCD= 5 V

-

30

SCL clock frequency

-

400

kHz

s

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

1.3

0.6

-

t_HIGH

s

Pin SDA

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

100

0

-

ns

Pins SCL and SDA

t_BUF

bus free time between a STOP and

1.3

-

s

START condition

t_SU;STO

t_HD;STA

t_SU;STA

set-up time for STOP condition

hold time (repeated) START condition

0.6

-

s

set-up time for a repeated START

condition

t_r

rise time of both SDA and SCL signals f_SCL= 400 kHz

f_SCL< 125 kHz

-

0.3

1.0

0.3

400

50

s

pF

ns

t_f

fall time of both SDA and SCL signals

capacitive load for each bus line

C_b

t_w(spike)

spike pulse width

on the I²C-bus

[1] Typical output duty factor: 50 % measured at the CLK output pin.

[2] Not tested in production.

[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

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Product data sheet

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

1 / f

clk

t

clk(L)

clk(H)

0.7 V

0.3 V

DD

CLK

0.7 V

0.3 V

DD

SYNC

t

PD(SYNC_N)

t

SYNC_NL

10 %

80 %

10 %

BPn, Sn

t

013aaa298

PD(drv)

Fig 25. Driver timing waveforms

SDA

t

f

BUF

LOW

SCL

SDA

t

HD;STA

t

SU;DAT

r

HD;DAT

t

HIGH

t

SU;STA

t

SU;STO

mga728

Fig 26. I²C-bus timing waveforms

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PCA85176

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Automotive LCD driver for low multiplex rates

14. Application information

14.1 Cascaded operation

Large display configurations of up to 16 PCA85176 can be recognized on the same

I²C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable

I²C-bus slave address (SA0).

Table 21. Addressing cascaded PCA85176

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2

1

8

9

10

11

12

13

14

15

When cascaded PCA85176 are synchronized, they can share the backplane signals from

one of the devices in the cascade. The other PCA85176 of the cascade contribute

additional segment outputs, but their backplane outputs are left open-circuit

(see Figure 27).

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Product data sheet

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PCA85176

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Automotive LCD driver for low multiplex rates

V

LCD

DD

SDA

SCL

40 segment drives

PCA85176

SYNC

CLK

(2)

BP0 to BP3

OSC

(open-circuit)

A0 A1 A2 SA0

V

SS

LCD PANEL

V

LCD

V

t

r

DD

≤

R

2C

V

LCD

b

DD

40 segment drives

SDA

SCL

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SYNC

CLK

4 backplanes

BP0 to BP3

PCA85176

(1)

OSC

A0 A1 A2 SA0

V

SS

V

SS

013aaa052

(1) Is master (OSC connected to V_SS).

(2) Is slave (OSC connected to V_DD).

Fig 27. Cascaded PCA85176 configuration

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCA85176. Synchronization is guaranteed after a power-on reset. The only time that

SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments or by defining a multiplex drive mode when PCA85176

with different SA0 levels are cascaded).

SYNC is organized as an input/output pin. The output selection is realized as an

open-drain driver with an internal pull-up resistor. A PCA85176 asserts the SYNC line at

the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the first PCA85176 to assert

SYNC. The timing relationship between the backplane waveforms and the SYNC signal

for the various drive modes of the PCA85176 are shown in Figure 28.

The PCA85176 can always be cascaded with other devices of the same type or

conditionally with other devices of the same family. This allows optimal drive selection for

a given number of pixels to display. Figure 25 and Figure 28 show the timing of the

synchronization signals.

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Product data sheet

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

In a cascaded configuration only one PCA85176 master must be used as clock source. All

other PCA85176 in the cascade must be configured as slave such that they receive the

clock from the master.

If an external clock source is used, all PCA85176 in the cascade must be configured such

as to receive the clock from that external source (pin OSC connected to V_DD). Thereby it

must be ensured that the clock tree is designed such that on all PCA85176 the clock

propagation delay from the clock source to all PCA85176 in the cascade is as equal as

possible since otherwise synchronization artefacts may occur.

In mixed cascading configurations, care has to be taken that the specifications of the

individual cascaded devices are met at all times.

1

T

=

fr

f

fr

BP0

SYNC

(a) static drive mode.

BP0

(1/2 bias)

BP0

(1/3 bias)

SYNC

(b) 1:2 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(c) 1:3 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(d) 1:4 multiplex drive mode.

mgl755

Fig 28. Synchronization of the cascade for the various PCA85176 drive modes

PCA85176

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Product data sheet

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PCA85176

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Automotive LCD driver for low multiplex rates

15. Test information

15.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

PCA85176

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Product data sheet

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PCA85176

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Automotive LCD driver for low multiplex rates

16. Package outline

TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm

SOT357-1

y

X

A

48

33

Z

49

32

E

e

H

E

(A )

3

A

2

A

1

w M

p

θ

pin 1 index

b

L

p

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.05

0.05 0.95

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.2

mm

0.25

0.5

1

0.2 0.08 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

02-03-14

SOT357-1

137E10

MS-026

Fig 29. Package outline SOT357-1 (TQFP64) of PCA85176H

PCA85176

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PCA85176

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Automotive LCD driver for low multiplex rates

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

E

D

A

X

c

H

v

M

A

y

E

Z

56

29

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

28

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Fig 30. Package outline SOT364-1 (TSSOP56) of PCA85176T

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17. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

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18. Packing information

18.1 Tape and reel information

TOP VIEW

P0

Ø D0

W

B0

A0

K0

P1

direction of feed

Ø D1

Original dimensions are in mm.

Figure not drawn to scale.

013aaa699

Fig 31. Tape and reel details for PCA85176

Table 22. Carrier tape dimensions of PCA85176

Symbol

Description

Value

Unit

SOT357-1 (TQFP64) of PCA85176H

Compartments

A0

B0

K0

P1

D1

pocket width in x direction

pocket width in y direction

pocket depth

12.6 to 13

1.5 to 1.7

16

mm

pocket hole pitch

pocket hole diameter

1.5

Overall dimensions

W

tape width

24

1.5

4

mm

D0

P0

sprocket hole diameter

sprocket hole pitch

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Table 22. Carrier tape dimensions of PCA85176 …continued

Symbol Description

Value

Unit

SOT364-1 (TSSOP56) of PCA85176T

Compartments

A0

B0

K0

P1

D1

pocket width in x direction

pocket width in y direction

pocket depth

8.65 to 8.9

14.4 to 15.8

1.5 to 1.8

12

mm

pocket hole pitch

pocket hole diameter

1.5 to 2.05

Overall dimensions

W

tape width

24

mm

D0

P0

sprocket hole diameter

sprocket hole pitch

1.5 to 1.55

4

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19. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

19.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

19.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

19.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

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PCA85176

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Automotive LCD driver for low multiplex rates

19.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 32) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 23 and 24

Table 23. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 24. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 32.

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Product data sheet

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PCA85176

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 32. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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20. Footprint information

Footprint information for reflow soldering of TQFP64 package

SOT357-1

Hx

Gx

(0.125)

P2

P1

Hy Gy

By

Ay

C

D2 (8×)

D1

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ax

Ay

Bx

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 13.300 13.300 10.300 10.300 1.500 0.280 0.400 10.500 10.500 13.550 13.550

sot357-1_fr

Fig 33. Footprint information for reflow soldering of SOT357-1 (TQFP64) of PCA85176H

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Automotive LCD driver for low multiplex rates

Footprint information for reflow soldering of TSSOP56 package

SOT364-1

Hx

Gx

P2

(0.125)

Hy Gy

By Ay

C

D2 (4x)

P1

D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

0.500 0.560 8.900 6.100 1.400 0.280 0.400 14.270 7.000 16.600 9.150

sot364-1_fr

Fig 34. Footprint information for reflow soldering of SOT364-1 (TSSOP56) of PCA85176T

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Automotive LCD driver for low multiplex rates

21. Abbreviations

Table 25. Abbreviations

Acronym

AEC

CMOS

CDM

DC

Description

Automotive Electronics Council

Complementary Metal-Oxide Semiconductor

Charged Device Model

Direct Current

HBM

I²C

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

LCD

LSB

Liquid Crystal Display

Least Significant Bit

MSB

MSL

PCB

POR

RAM

RC

Most Significant Bit

Moisture Sensitivity Level

Printed-Circuit Board

Power-On Reset

Random Access Memory

Resistance and Capacitance

Root Mean Square

RMS

SCL

SDA

SMD

Serial CLock line

Serial DAta Line

Surface-Mount Device

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Automotive LCD driver for low multiplex rates

22. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN10853 — ESD and EMC sensitivity of IC

[3] AN11267 — EMC and system level ESD design guidelines for LCD drivers

[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[8] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[9] JESD78 — IC Latch-Up Test

[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[11] SNV-FA-01-02 — Marking Formats Integrated Circuits

[12] UM10204 — I²C-bus specification and user manual

[13] UM10569 — Store and transport requirements

23. Revision history

Table 26. Revision history

Document ID

PCA85176 v.5

Modifications:

PCA85176 v.4

PCA85176 v.3

PCA85176 v.2

PCA85176 v.1

Release date

20130711

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCA85176 v.4

• Adjusted values for V_DDand V_LCDin Table 19

20130610

20120905

20110627

20100414

Product data sheet

-

PCA85176 v.3

PCA85176 v.2

PCA85176 v.1

-

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Automotive LCD driver for low multiplex rates

24. Legal information

24.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

24.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

24.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

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Product data sheet

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PCA85176

NXP Semiconductors

Automotive LCD driver for low multiplex rates

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

24.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

25. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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Automotive LCD driver for low multiplex rates

26. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 5. Definition of PCA85176 commands . . . . . . . . . .7

Table 6. C bit description . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 7. Mode-set command bit description . . . . . . . . . .8

Table 8. Load-data-pointer command bit description . . . .8

Table 9. Device-select command bit description . . . . . . .9

Table 10. Bank-select command bit description . . . . . . . .9

Table 11. Blink-select command bit description . . . . . . . .10

Table 12. Blink frequencies . . . . . . . . . . . . . . . . . . . . . . .10

Table 13. Selection of possible display configurations . . .12

Table 14. Biasing characteristics . . . . . . . . . . . . . . . . . . .13

Table 15. Standard RAM filling in 1:3 multiplex

drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 16. Entire RAM filling by rewriting in 1:3

multiplex drive mode. . . . . . . . . . . . . . . . . . . . .25

Table 17. I²C slave address byte . . . . . . . . . . . . . . . . . . .31

Table 18. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 19. Static characteristics . . . . . . . . . . . . . . . . . . . .35

Table 20. Dynamic characteristics . . . . . . . . . . . . . . . . . .37

Table 21. Addressing cascaded PCA85176 . . . . . . . . . .39

Table 22. Carrier tape dimensions of PCA85176 . . . . . .46

Table 23. SnPb eutectic process (from J-STD-020D) . . .49

Table 24. Lead-free process (from J-STD-020D) . . . . . .49

Table 25. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 26. Revision history . . . . . . . . . . . . . . . . . . . . . . . .54

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PCA85176

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Automotive LCD driver for low multiplex rates

27. Figures

Fig 1. Block diagram of PCA85176 . . . . . . . . . . . . . . . . .3

Fig 2. Pinning diagram for TQFP64 (PCA85176H) . . . . .4

Fig 3. Pinning diagram for TSSOP56 (PCA85176T) . . . .5

Fig 4. Example of displays suitable for PCA85176 . . . .11

Fig 5. Typical system configuration . . . . . . . . . . . . . . . .12

Fig 6. Electro-optical characteristic: relative transmission

curve of the liquid. . . . . . . . . . . . . . . . . . . . . . . . .15

Fig 7. Static drive mode waveforms. . . . . . . . . . . . . . . .16

Fig 8. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₂bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Fig 9. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Fig 10. Waveforms for the 1:3 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 11. Waveforms for the 1:4 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 12. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .22

Fig 13. Relationship between LCD layout, drive mode,

display RAM filling order, and display data

transmitted over the I²C-bus . . . . . . . . . . . . . . . .23

Fig 14. RAM banks in static and multiplex

driving mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 15. Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 16. Example of the Bank-select command with

multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .28

Fig 17. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Fig 18. Definition of START and STOP conditions. . . . . .29

Fig 19. System configuration . . . . . . . . . . . . . . . . . . . . . .30

Fig 20. Acknowledgement of the I²C-bus . . . . . . . . . . . .30

Fig 21. I²C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .32

Fig 22. Format of command byte. . . . . . . . . . . . . . . . . . .32

Fig 23. Device protection circuits. . . . . . . . . . . . . . . . . . .33

Fig 24. Typical I_DDwith respect to V_DD. . . . . . . . . . . . . .36

Fig 25. Driver timing waveforms . . . . . . . . . . . . . . . . . . .38

Fig 26. I²C-bus timing waveforms . . . . . . . . . . . . . . . . . .38

Fig 27. Cascaded PCA85176 configuration. . . . . . . . . . .40

Fig 28. Synchronization of the cascade for the various

PCA85176 drive modes. . . . . . . . . . . . . . . . . . . .41

Fig 29. Package outline SOT357-1 (TQFP64)

of PCA85176H. . . . . . . . . . . . . . . . . . . . . . . . . . .43

Fig 30. Package outline SOT364-1 (TSSOP56)

of PCA85176T . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Fig 31. Tape and reel details for PCA85176 . . . . . . . . . .46

Fig 32. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Fig 33. Footprint information for reflow soldering

of SOT357-1 (TQFP64) of PCA85176H . . . . . . .51

Fig 34. Footprint information for reflow soldering

of SOT364-1 (TSSOP56) of PCA85176T . . . . . .52

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Automotive LCD driver for low multiplex rates

28. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.2

8.3

8.4

8.5

8.6

8.7

START and STOP conditions. . . . . . . . . . . . . 29

System configuration . . . . . . . . . . . . . . . . . . . 29

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 30

I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 31

Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 31

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

3.1

4

5

9

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 33

Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34

Static characteristics . . . . . . . . . . . . . . . . . . . 35

Dynamic characteristics. . . . . . . . . . . . . . . . . 37

Application information . . . . . . . . . . . . . . . . . 39

Cascaded operation. . . . . . . . . . . . . . . . . . . . 39

Test information . . . . . . . . . . . . . . . . . . . . . . . 42

Quality information. . . . . . . . . . . . . . . . . . . . . 42

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 43

Handling information . . . . . . . . . . . . . . . . . . . 45

Packing information . . . . . . . . . . . . . . . . . . . . 46

Tape and reel information . . . . . . . . . . . . . . . 46

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

10

11

12

7

7.1

Functional description . . . . . . . . . . . . . . . . . . . 7

Commands of PCA85176. . . . . . . . . . . . . . . . . 7

Command: mode-set . . . . . . . . . . . . . . . . . . . . 8

Command: load-data-pointer . . . . . . . . . . . . . . 8

Command: device-select . . . . . . . . . . . . . . . . . 9

Command: bank-select. . . . . . . . . . . . . . . . . . . 9

Command: blink-select. . . . . . . . . . . . . . . . . . 10

Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 11

Possible display configurations . . . . . . . . . . . 11

LCD bias generator . . . . . . . . . . . . . . . . . . . . 12

Display register. . . . . . . . . . . . . . . . . . . . . . . . 12

LCD voltage selector . . . . . . . . . . . . . . . . . . . 12

Electro-optical performance . . . . . . . . . . . . . . 14

LCD drive mode waveforms . . . . . . . . . . . . . . 16

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 16

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 17

1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 19

1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 20

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 21

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 21

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Backplane and segment outputs . . . . . . . . . . 21

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 21

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 21

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 22

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Subaddress counter . . . . . . . . . . . . . . . . . . . . 24

RAM writing in 1:3 multiplex drive mode. . . . . 25

Writing over the RAM address boundary . . . . 26

Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 26

Output bank selector . . . . . . . . . . . . . . . . . . . 26

Input bank selector . . . . . . . . . . . . . . . . . . . . . 26

RAM bank switching. . . . . . . . . . . . . . . . . . . . 26

13

14

14.1

15

15.1

16

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.5.1

7.2

17

18

18.1

7.3

7.3.1

7.3.2

7.3.3

7.3.3.1

7.3.4

7.3.4.1

7.3.4.2

7.3.4.3

7.3.4.4

7.4

7.4.1

7.4.2

7.4.3

7.5

7.5.1

7.5.2

7.6

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.5.1

7.6.5.2

7.6.5.3

19

Soldering of SMD packages. . . . . . . . . . . . . . 48

Introduction to soldering. . . . . . . . . . . . . . . . . 48

Wave and reflow soldering. . . . . . . . . . . . . . . 48

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 48

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 49

19.1

19.2

19.3

19.4

20

21

22

23

Footprint information . . . . . . . . . . . . . . . . . . . 51

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 53

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Revision history . . . . . . . . . . . . . . . . . . . . . . . 54

24

Legal information . . . . . . . . . . . . . . . . . . . . . . 55

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 55

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 56

24.1

24.2

24.3

24.4

25

26

27

28

Contact information . . . . . . . . . . . . . . . . . . . . 56

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8

Characteristics of the I²C-bus . . . . . . . . . . . . 29

8.1

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 11 July 2013

Document identifier: PCA85176


型号：	PCA85176H/Q900/1
厂家：	NXP
描述：	LIQUID CRYSTAL DISPLAY DRIVER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT357-1, TQFP-64 驱动接口集成电路
文件：	总59页 (文件大小：542K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA85176H/Q900/1 [NXP]

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