PCA85232U/2DA/Q1,0_技术文档

PCA85232

LCD driver for low multiplex rates

Rev. 4 — 8 April 2015

Product data sheet

1. General description

The PCA85232 is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)¹with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 160 segments. It can easily

be cascaded for larger LCD applications. The PCA85232 is compatible with most

microcontrollers and communicates via the two-line bidirectional I²C-bus. Communication

overheads are minimized by a display RAM with auto-incremental addressing, by

hardware subaddressing, and by display memory switching (static and duplex drive

modes).

For a selection of NXP LCD segment drivers, see Table 29 on page 56.

2. Features and benefits

 AEC-Q100 compliant for automotive applications

 Single-chip LCD controller and driver for up to 640 elements

 Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

 160 segment drives:

 Up to 80 7-segment numeric characters

 Up to 40 14-segment alphanumeric characters

 Any graphics of up to 640 elements

 May be cascaded for large LCD applications (up to 5120 elements possible)

 160  4-bit RAM for display data storage

 Software programmable frame frequency in the range of 117 Hz to 176 Hz; factory

calibrated

 Wide LCD supply range: from 1.8 V for low threshold LCDs and up to 8.0 V for

guest-host LCDs and high threshold (automobile) twisted nematic LCDs

 Internal LCD bias generation with voltage-follower buffers

 Selectable display bias configuration: static, ¹⁄₂, or ¹⁄₃

 Wide power supply range: from 1.8 V to 5.5 V

 LCD and logic supplies may be separated

 Low power consumption, typical: I_DD= 4 A, I_DD(LCD)= 65 A

 400 kHz I²C-bus interface

 Auto-incremental display data loading across device subaddress boundaries

 Versatile blinking modes

 Compatible with Chip-On-Glass (COG) technology

 No external components required

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19 on page 58.

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

 Two sets of backplane outputs for optimal COG configurations of the application

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCA85232U

bare die

197 bumps; 6.5  1.16  0.40 mm

PCA85232U

3.1 Ordering options

Table 2.

Ordering options

Product type number Orderable part number Sales item

(12NC)

Delivery form

IC

revision

PCA85232U/2DA/Q1

PCA85232U/2DA/Q1,0 935291553026 chips with bumps in tray

1

4. Marking

Table 3.

Marking codes

Product type number

Marking code

PCA85232U

PC85132/232-1

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

5. Block diagram

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Fig 1. Block diagram of PCA85232

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

6.2 Pin description

Table 4.

Pin description

Input or input/output pins must always be at a defined level (V_SSor V_DD) unless otherwise specified.

Symbol

SDAACK^[1]

SDA^[1]

SCL

Description

1 to 3

4 to 6

7 to 9

10

I²C-bus acknowledge output

I²C-bus serial data input

I²C-bus serial clock input

clock input and output

CLK

V_DD

11 to 13

14

supply voltage

SYNC

cascade synchronization input and output

selection of internal or external clock

OSC

15

T1, T2, and T3

16, 17, and 18 to 20 dedicated testing pins; to be tied to V_SSin

application mode

A0 and A1

SA0

21, 22

subaddress inputs

23

I²C-bus slave address input

ground supply voltage

LCD supply voltage

[2]

V_SS

24 to 26

27 to 29

30, 31

V_LCD

BP2 and BP0

S0 to S79

LCD backplane outputs

LCD segment outputs

LCD backplane outputs

LCD segment outputs

LCD backplane outputs

32 to 111

112 to 115

116 to 195

196, 197

BP0, BP2, BP1, and BP3

S80 to S159

BP3 and BP1

[1] For most applications SDA and SDAACK are shorted together (see Section 14.3 on page 44).

[2] The substrate (rear side of the die) is connected to V_SSand should be electrically isolated.

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

7. Functional description

The PCA85232 is a versatile peripheral device designed to interface between any

microcontroller to a wide variety of LCD segment or dot matrix displays. It can directly

drive any static or multiplexed LCD containing up to four backplanes and up to

160 segments.

7.1 Commands of PCA85232

The commands available to the PCA85232 are defined in Table 5.

Table 5.

Definition of PCA85232 commands

Operation code

Command

Reference

Bit

7

1

0

1

6

1

0

1

5

0

1

4

0

1

0

3

2

1

0

mode-set

E

B

M[1:0]

Table 6

Table 7

Table 8

Table 9

Table 10

Table 11

Table 12

load-data-pointer-MSB

load-data-pointer-LSB

device-select

bank-select

blink-select

P[7:4]

P[3:0]

0

1

0

1

0

A[1:0]

I

0

O

AB

BF[1:0]

frequency-ctrl

F[2:0]

7.1.1 Command: mode-set

The mode-set command allows configuring the multiplex mode, the bias levels and

enabling or disabling the display.

Table 6.

Bit

Mode-set - command bit description

Symbol

Value

Description

7 to 4

3

-

1100

fixed value

E

display status^[1]

disabled (blank)^[3]

enabled

0^[2]

1

2

B

LCD bias configuration^[4]

¹⁄₃bias

¹⁄₂bias

0^[2]

1

1 to 0

M[1:0]

LCD drive mode selection

static; BP0

01

10

1:2 multiplex; BP0, BP1

1:3 multiplex; BP0, BP1, BP2

1:4 multiplex; BP0, BP1, BP2, BP3

11

00^[2]

[1] The possibility to disable the display allows implementation of blinking under external control. The enable

bit determines also whether the internal clock signal is available at the CLK pin (see Section 7.1.6.2 on

page 9).

[2] Default value.

[3] The display is disabled by setting all backplane and segment outputs to V_LCD

.

[4] Not applicable for static drive mode.

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

7.1.2 Command: load-data-pointer

The load-data-pointer command defines the display RAM address where the following

display data will be sent to.

Table 7.

Load-data-pointer-MSB - command bit description

See Section 7.5.1 on page 24.

Bit

Symbol

-

Value

Description

7 to 4

3 to 0

0000

0000^[1]to

1001

fixed value

P[7:4]

defines the first 4 (most significant) bits of the

data-pointer

the data-pointer indicates one of the 160 display RAM

addresses

[1] Default value.

Table 8.

Load-data-pointer-LSB - command bit description

See Section 7.5.1 on page 24.

Bit

Symbol

-

Value

Description

7 to 4

3 to 0

0100

0000^[1]to

1111

fixed value

P[3:0]

defines the last 4 (least significant) bits of the

data-pointer

the data-pointer indicates one of the 160 display RAM

addresses

[1] Default value.

7.1.3 Command: device-select

The device-select command allows defining the subaddress counter value.

Table 9.

Device-select - command bit description

See Section 7.5.2 on page 24.

Bit

Symbol

-

Value

Description

7 to 2

1 to 0

111000

00^[1]to 11

fixed value

A[1:0]

defines one of four hardware subaddresses

(see Table 23 on page 44)

[1] Default value.

7.1.4 Command: bank-select

The bank-select command controls where data is written to RAM and where it is displayed

from.

Table 10. Bank-select - command bit description

See Section 7.5.4 on page 25.

Bit

Symbol Value

Description

Static

1:2 multiplex^[1]

7 to 2

1

-

I

111110

fixed value

input bank selection; storage of arriving display data

0^[2]

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

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PCA85232

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LCD driver for low multiplex rates

Table 10. Bank-select - command bit description …continued

See Section 7.5.4 on page 25.

Bit

Symbol Value

Description

Static

1:2 multiplex^[1]

0

O

output bank selection; retrieval of LCD display data

0^[2]

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

[2] Default value.

7.1.5 Command: blink-select

The blink-select command allows configuring the blink mode and the blink frequency.

Table 11. Blink-select - command bit description

See Section 7.1.6.6 on page 10.

Bit

7 to 3

2

Symbol Value

Description

-

11110

fixed value

AB

blink mode selection

0^[1]

1

normal blinking^[2]

alternate RAM bank blinking^[3]

1 to 0

BF[1:0]

blink frequency selection

00^[1]

01

off

1

10

2

11

3

[1] Default value.

[2] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

7.1.6 Clock frequency and timing

The timing of the PCA85232 organizes the internal data flow of the device. The timing

includes the transfer of display data from the display RAM to the display segment outputs

and therefore the frame frequency.

7.1.6.1 Clock source selection

The PCA85232 can be configured to use either the built-in oscillator or an external clock

as clock source:

Internal clock — To enable the internal oscillator, pin OSC has to be connected to V_SS

Pin CLK then becomes an output. For further information on the internal clock, see

Section 7.1.6.2.

.

External clock — To enable the use of an external clock, pin OSC has to be connected to

V_DD. Pin CLK then becomes an input for the external clock frequency f_clk(ext). For further

information on the external clock, see Section 7.1.6.3.

Figure 3 illustrates the frequency generation of the PCA85232.

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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Remark: A clock signal must always be supplied to the device. Removing the clock may

freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.1.6.2 Internal clock

If the internal oscillator is used, the timing of the PCA85232 is derived from the built-in

oscillator by a pre-scaler which can be configured with the frequency-ctrl command (see

Table 12).

The internal oscillator is calibrated within an accuracy of 5.1 % (at V_DD= 5.0 V;

T_amb= 30 C).

The frequency-ctrl command determines the division factor between the oscillator

frequency f_oscand the internal clock frequency f_clk(int). If the internal oscillator is used, the

frame frequency is derived from the internal clock frequency f_clk(int)by the fixed division

shown in Equation 1 on page 9.

If the display is enabled (see bit E in Table 6), f_clk(int)on pin CLK provides the clock signal

for cascaded LCD drivers in the system. For further information about cascading, see

Section 14.4 on page 44. The value range of f_oscis specified in Table 22 on page 38.

7.1.6.3 External clock

If the external clock source is selected, the timing frequency of the PCA85232 is the

external clock frequency. In this case, the frequency-ctrl command has no influence on

the clock frequency nor the frame frequency. The frame frequency is derived from the

external clock frequency f_clk(ext)by the fixed division as shown in Equation 1.

7.1.6.4 Frame frequency

Sourced by the internal oscillator or an external clock, the frame frequency is derived from

the clock frequency f_clkby Equation 1.

f_clk

f_fr

=

(1)

-------

24

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

7.1.6.5 Command: frequency-ctrl

Table 12. Frequency-ctrl - command bit description

Bit

Symbol

Value

Description

Equation

Nominal

clock

Nominal

frame

frequency^[1]frequency^[1]

7 to 4

-

11101

000

fixed value

3 to 0 F[2:0]

defines the division factor

2800 Hz

3027 Hz

3294 Hz

117 Hz

126 Hz

137 Hz

64

80

-----

f_clkint

=

 f_osc

001

64

-----

74

010

64

-----

68

011^[2], 111

100

3500 Hz

3733 Hz

146 Hz

156 Hz

f_clkint= f_osc

64

-----

f_clkint

=

 f_osc

60

101

110

4000 Hz

4226 Hz

167 Hz

176 Hz

64

-----

56

64

-----

53

[1] Calculated with the oscillator frequency of f_osc= 3.500 Hz. The frame frequency is derived from the internal

clock frequency by Equation 1.

[2] Default value.

7.1.6.6 Blinking

The display blinking capabilities of the PCA85232 are very versatile. The whole display

can blink at frequencies selected by the blink-select command (see Table 11). The blink

frequencies are derived from the clock frequency (f_clk). The ratios between the clock and

blink frequencies depend on the blink mode in which the device is operating (see

Table 13).

Table 13. Blink frequencies

Assuming that f_clk= 3.500 kHz.

Blink mode

Operating mode ratio

Blink frequency

blinking off

off

1

-

~4.56 Hz

f_clk

f_blink

=

--------

768

2

3

~2.28 Hz

~1.14 Hz

f_clk

-----------

1536

f_clk

-----------

3072

An additional feature is for an arbitrary selection of LCD elements to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads: With the output bank selector, the displayed RAM banks are

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

exchanged (see Section 7.5.4 on page 25) with alternate RAM banks at the blink

frequency. This mode can also be specified by the blink-select command (see Table 11 on

page 8).

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD elements can blink selectively by changing the display RAM data at fixed time

intervals.

The entire display can blink at a frequency other than the nominal blinking frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 6).

7.2 Power-On Reset (POR)

At power-on, the PCA85232 resets to the following starting conditions:

• All backplane and segment outputs are set to V_LCD

• The selected drive mode is 1:4 multiplex with ¹⁄₃bias

• Blinking is switched off

• Input and output bank selectors are reset

• The I²C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• The display is disabled (bit E = 0, see Table 6 on page 6)

• If internal oscillator is selected (pin OSC connected to V_SS), then there is no clock

signal on pin CLK

Remark: Do not transfer data on the I²C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.3 Possible display configurations

The display configurations possible with the PCA85232 depend on the required number of

active backplane outputs. A selection of display configurations is given in Table 14.

All of the display configurations given in Table 14 can be implemented in a typical system

as shown in Figure 5.

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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Table 14. Selection of possible display configurations

Number of

Backplanes

Icons

Digits/Characters

Dot matrix/

Elements

7-segment

14-segment

4

3

2

1

640

480

320

160

80

60

40

20

40

30

20

10

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Fig 5. Typical system configuration

The host microcontroller maintains the 2-line I²C-bus communication channel with the

PCA85232.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to V_SS. The only other connections required to complete the system are the

power supplies (V_DD, V_SS, and V_LCD) and the LCD panel selected for the application.

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Product data sheet

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PCA85232

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LCD driver for low multiplex rates

7.3.1 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of three

impedances connected between pins V_LCDand V_SS. The center impedance is bypassed

by switch if the ¹⁄₂bias voltage level for the 1:2 multiplex drive mode configuration is

selected.

7.3.2 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

7.3.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command. The biasing configurations that apply to the preferred modes of

operation, together with the biasing characteristics as functions of V_LCDand the resulting

discrimination ratios (D) are given in Table 15.

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across

a segment. It can be thought of as a measurement of contrast.

Table 15. Biasing characteristics

LCD drive

mode

Number of:

LCD bias

configuration

V_offRMSV_onRMS

------------------------ ----------------------- D = ------------------------

V_LCDV_LCDV_offRMS

V_onRMS

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1



1

⁄

1:2 multiplex

1:3 multiplex

1:4 multiplex

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

2

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th(off)), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode, a suitable choice is V_LCD> 3V_th(off)

.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 2:

a²+ 2a + n

n  1 + a²

V_onRMS

=

-----------------------------

(2)

V

LCD

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

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Product data sheet

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LCD driver for low multiplex rates

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 3:

a²– 2a + n

n  1 + a²

V_offRMS

=

-----------------------------

(3)

(4)

V

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 4:

a²+ 2a + n

V_onRMS

D =

=

---------------------------

----------------------

a²– 2a + n

V_offRMS

Using Equation 4, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V_LCD

• 1:4 multiplex (¹⁄₂bias): V_LCD

=

6  V_offRMS= 2.449V_offRMS

4  3

---------------------

= 2.309V_offRMS

3

These compare with V_LCD= 3V_offRMSwhen ¹⁄₃bias is used.

_LCDis sometimes referred as the LCD operating voltage.

V

7.3.3.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependent on the LCD liquid used. The

RMS voltages, at which a pixel is switched on or off, determine the transmissibility of the

pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_th(off)) and the other at 90 % relative transmission (at V_th(on)), see

Figure 6. For a good contrast performance, the following rules should be followed:

V

_onRMS V_thon

_offRMS V_thoff

(5)

(6)

V

_on(RMS)and V_off(RMS)are properties of the display driver and are affected by the selection

of a (see Equation 2), n (see Equation 4), and the V_LCDvoltage.

V_th(off)and V_th(on)are properties of the LCD liquid and can be provided by the module

manufacturer. V_th(off)is sometimes named V_th. V_th(on)is sometimes named saturation

voltage V_sat

.

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LCD driver for low multiplex rates

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

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PCA85232

NXP Semiconductors

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7.3.4 LCD drive mode waveforms

7.3.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD.

Backplane and segment drive waveforms for this mode are shown in Figure 7.

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= V_LCD

_state2(t) = V_(Sn+1)(t)  V_BP0(t).

V_off(RMS)= 0 V.

.

V

Fig 7. Static drive mode waveforms

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7.3.4.2 1:2 multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCA85232 allows the use of ¹⁄₂bias or ¹⁄₃bias in this mode as shown in Figure 8 and

Figure 9.

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.791V_LCD

.

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.354V_LCD

.

Fig 8. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

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PCA85232

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LCD driver for low multiplex rates

7

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.745V_LCD

.

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 9. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

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7.3.4.3 1:3 multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as

shown in Figure 10.

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.638V_LCD

.

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V_off(RMS)= 0.333V_LCD

.

Fig 10. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

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7.3.4.4 1:4 multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as

shown in Figure 11.

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V_state1(t) = V_Sn(t)  V_BP0(t).

_on(RMS)= 0.577V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

V_off(RMS)= 0.333V_LCD

V

.

Fig 11. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias

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7.4 Backplane and segment outputs

7.4.1 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated in accordance with the selected LCD drive mode.

• In the 1:4 multiplex drive mode BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required, the unused outputs can be left

open-circuit.

• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same

signals and may also be paired to increase the drive capabilities.

• In static drive mode, the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

The pins for the four backplanes BP0 to BP3 are available on both pin bars of the chip. In

applications, it is possible to use either the pins for the backplanes

• on the top pin bar

• on the bottom pin bar

• or both of them to increase the driving strength of the device.

When using all backplanes available they may be connected to the respective sibling

(BP0 on the top pin bar with BP0 on the bottom pin bar, and so on).

7.4.2 Segment outputs

The LCD drive section includes 160 segment outputs (S0 to S159) which must be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data resident in the display register.

When less than 160 segment outputs are required, the unused segment outputs must be

left open-circuit.

7.5 Display RAM

The display RAM is a static 160  4 bit RAM which stores LCD data. There is a one-to-one

correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

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The display RAM bitmap, Figure 12, shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 159 which correspond with the

segment outputs S0 to S159. In multiplexed LCD applications the segment data of the

first, second, third, and fourth row of the display RAM are time-multiplexed with BP0,

BP1, BP2, and BP3 respectively.

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The display RAM bitmap shows the direct relationship between the display RAM addresses and

the segment outputs; and between the bits in a RAM word and the backplane outputs.

Fig 12. Display RAM bitmap

When display data is transmitted to the PCA85232, the received display bytes are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and does not wait for the acknowledge cycle as with the commands. Depending

on the current multiplex drive mode, data is stored singularly, in pairs, triples, or

quadruples. To illustrate the filling order, an example of a 7-segment numeric display

showing all drive modes is given in Figure 13. The RAM filling organization depicted

applies equally to other LCD types.

The following applies to Figure 13:

• In static drive mode the eight transmitted data bits are placed in row 0 as 1 byte.

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into

row 0 and 1 as four successive 2-bit RAM words.

• In 1:3 multiplex drive mode the 8 bits are placed in triples into row 0, 1, and 2 as 3

successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not

recommended to use this bit in a display because of the difficult addressing. This last

bit may, if necessary, be controlled by an additional transfer to this address but care

should be taken to avoid overwriting adjacent data because always full bytes are

transmitted (see Section 7.5.3 on page 24).

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples

into row 0, 1, 2, and 3 as 2 successive 4-bit RAM words.

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7.5.1 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 7 on page 7 and Table 8 on

page 7). Following this command, an arriving data byte is stored at the display RAM

address indicated by the data pointer. The filling order is shown in Figure 13.

After each byte is stored, the content of the data pointer is automatically incremented by a

value dependent on the selected LCD drive mode:

• In static drive mode by eight

• In 1:2 multiplex drive mode by four

• In 1:3 multiplex drive mode by three

• In 1:4 multiplex drive mode by two

If an I²C-bus data access is terminated early, then the state of the data pointer is

unknown. The data pointer should be re-written before further RAM accesses.

7.5.2 Subaddress counter

The storage of display data is conditioned by the content of the subaddress counter.

Storage is allowed only when the content of the subaddress counter matches with the

hardware subaddress applied to A0 and A1. The subaddress counter value is defined by

the device-select command (see Table 9 on page 7). If the content of the subaddress

counter and the hardware subaddress do not match then data storage is inhibited but the

data pointer is incremented as if data storage had taken place. The subaddress counter is

also incremented when the data pointer overflows.

The storage arrangements described lead to extremely efficient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCA85232 occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character.

The hardware subaddress must not be changed while the device is being accessed on the

I²C-bus interface.

7.5.3 RAM writing in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 16 (see Figure 13 as

well).

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Table 16. Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

outputs (BPn)

0

1

2

3

a7

a6

a5

-

a4

a3

a2

-

a1

a0

-

b7

b6

b5

-

b4

b3

b2

-

b1

b0

-

c7

c6

c5

-

c4

c3

c2

-

c1

c0

-

d7

d6

d5

-

:

-

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 17.

Table 17. Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.

Display RAM

bits (rows)/

backplane

Display RAM addresses (columns)/segment outputs (Sn)

0

1

2

3

4

5

6

7

8

9

:

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0

1

2

3

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a6

a5

-

a4

a3

a2

-

a1/b7 b4

a0/b6 b3

b1/c7 c4

b0/c6 c3

c1/d7 d4

c0/d6 d3

d1/e7 e4

d0/e6 e3

:

b5

-

b2

-

c5

-

c2

-

d5

-

d2

-

e5

-

e2

-

In the case described in Table 17 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8, and so on, have to be connected to elements on the display. This can be

achieved by a combination of writing and rewriting the RAM like follows:

• In the first write to the RAM, bits a7 to a0 are written

• The data-pointer (see Section 7.1.2 on page 7) has to be set to the address of bit a1

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7

and b6

• The data-pointer has to be set to the address of bit b1

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and

c6

Depending on the method of writing to the RAM (standard or entire filling by rewriting),

some elements remain unused or can be used, but it has to be considered in the module

layout process as well as in the driver software design.

7.5.4 Bank selection

7.5.4.1 Output bank selector

The output bank selector (see Table 10 on page 7) selects one of the four rows per display

RAM address for transfer to the display register. The actual row selected depends on the

particular LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, followed by the

contents of row 1, row 2, and then row 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

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• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

7.5.4.2 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded by using the bank-select

command (see Table 10). The input bank selector functions independently to the output

bank selector.

7.5.4.3 RAM bank switching

The PCA85232 includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. A bank can be thought of as one RAM row or a collection of RAM rows (see

Figure 14). The RAM bank switching gives the provision for preparing display information

in an alternative bank and to be able to switch to it once it is complete.

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There are two banks; bank 0 and bank 1. Figure 14 shows the location of these banks

relative to the RAM map. Input and output banks can be set independently from one

another with the Bank-select command (see Table 10 on page 7). Figure 15 shows the

concept.

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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In the static drive mode, the bank-select command may request the contents of row 2 to

be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the

contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it once it is assembled.

In Figure 16 an example is shown for 1:2 multiplex drive mode where the displayed data is

read from the first two rows of the memory (bank 0), while the transmitted data is stored in

the second two rows of the memory (bank 1).

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Fig 16. Example of the Bank-select command with multiplex drive mode 1:2

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8. Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

By connecting pin SDAACK to pin SDA on the PCA85232, the SDA line becomes fully

I²C-bus compatible. In COG applications where the track resistance from the SDAACK

pin to the system SDA line can be significant, possibly a voltage divider is generated by

the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a

consequence, it may be possible that the acknowledge generated by the PCA85232

cannot be interpreted as logic 0 by the master. In COG applications where the

acknowledge cycle is required, it is therefore necessary to minimize the track resistance

from the SDAACK pin to the system SDA line to guarantee a valid LOW level (see

Section 14.2 on page 42).

By separating the acknowledge output from the serial data line (having the SDAACK open

circuit) design efforts to generate a valid acknowledge level can be avoided. However, in

that case the I²C-bus master has to be set up in such a way that it ignores the

acknowledge cycle.²

The following definition assumes that SDA and SDAACK are connected and refers to the

pair as SDA.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

are interpreted as a control signal (see Figure 17).

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Fig 17. Bit transfer

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change

of the data line, while the clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP

condition (P). The START and STOP conditions are shown in Figure 18.

2. For further information, please consider the NXP application note: Ref. 1 “AN10170”.

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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Fig 18. Definition of START and STOP conditions

8.2 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is shown in Figure 19.

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Fig 19. System configuration

8.3 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is shown in Figure 20.

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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Fig 20. Acknowledgement on the I²C-bus

8.4 I²C-bus controller

The PCA85232 acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCA85232 is

the acknowledge signal. Device selection depends on the I²C-bus slave address, on the

transferred command data, and on the hardware subaddress.

In single device applications, the hardware subaddress inputs A0 and A1 are normally tied

to V_SSwhich defines the hardware subaddress 0. In multiple device applications

A0 and A1 are tied to V_SSor V_DDin accordance with a binary coding scheme. No two

devices with a common I²C-bus slave address must have the same hardware

subaddress.

8.5 Input filters

To enhance noise immunity in electrical adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

8.6 I²C-bus protocol

Two I²C-bus slave addresses (0111 000 and 0111 001) are reserved for the

PCA85232.The entire I²C-bus slave address byte is shown in Table 18.

Table 18. I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

1

0

SA0

The PCA85232 is a write-only device and does not respond to a read access, therefore

bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCA85232 responds

to, is defined by the level tied to its SA0 input (V_SSfor logic 0 and V_DDfor logic 1).

Having two reserved slave addresses allows the following on the same I²C-bus:

• Up to 8 PCA85232 on the same I²C-bus for very large LCD applications

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Product data sheet

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PCA85232

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LCD driver for low multiplex rates

• The use of two types of LCD multiplex drive modes on the same I²C-bus

The I²C-bus protocol is shown in Figure 21. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of two possible PCA85232

slave addresses available. All PCA85232 with the corresponding SA0 level acknowledge

in parallel to the slave address, but all PCA85232 with the alternative SA0 level ignore the

whole I²C-bus transfer.

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Fig 21. I²C-bus protocol

After acknowledgement, a control byte follows which defines if the next byte is RAM or

command information.

Table 19. Control byte description

Bit

Symbol Value

Description

7

CO

continue bit

0

last control byte

control bytes continue

register selection

command register

data register

1

6

RS

0

1

5 to 0

-

not relevant

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Fig 22. Control byte format

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

In this way, it is possible to configure the device and then fill the display RAM with little

overhead.

The command bytes and control bytes are also acknowledged by all addressed

PCA85232 connected to the bus.

The display bytes are stored in the display RAM at the address specified by the data

pointer and the subaddress counter; see Section 7.5.1 and Section 7.5.2.

The acknowledgement after each byte is made only by the (A0 and A1) addressed

PCA85232. After the last (display) byte, the I²C-bus master issues a STOP condition (P).

Alternatively a repeated START may be asserted to restart an I²C-bus access.

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

9. Internal circuitry

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Fig 23. Device protection diagram

10. Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

Semiconductors are light sensitive. Exposure to light sources can cause the IC to

malfunction. The IC must be protected against light. The protection must be applied to all

sides of the IC.

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

11. Limiting values

Table 20. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol Parameter

Conditions

Min

0.5

50

0.5

50

0.5

Max

+6.5

+50

Unit

V

V_DD

I_DD

supply voltage

supply current

mA

V

V_LCD

LCD supply voltage

+9.0

+50

I_DD(LCD)LCD supply current

mA

V

V_i

input voltage

on pins CLK, SYNC,

SA0, OSC, SDA, SCL,

A0, A1, T1, T2, and T3

+6.5

I_I

input current

10

+10

mA

V

V_O

output voltage

on pins S0 to S159 and 0.5

+9.0

BP0 to BP3

on pins SDAACK,

CLK, SYNC

0.5

+6.5

V

I_O

output current

10

+10

mA

mW

V

I_SS

ground supply current

total power dissipation

power dissipation per output

50

+50

P_tot

P/out

V_ESD

-

400

-

100

[2]

[3]

[4]

[5]

electrostatic discharge

voltage

HBM

MM

-

4500

300

200

-

V

I_lu

latch-up current

-

mA

C

T_stg

T_amb

storage temperature

ambient temperature

65

40

+150

+95

operating device

C

[1] Stresses above these values listed may cause permanent damage to the device.

[2] Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.

[3] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.

[4] Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature (T_amb(max)).

[5] According to the store and transport requirements (see Ref. 11 “UM10569”) the devices have to be stored

at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

12. Static characteristics

Table 21. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 1.8 V to 8.0 V; T_amb= 40 C to +95 C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

1.8

-

5.5

8.0

30

80

60

80

V

V_LCD

I_DD

LCD supply voltage

supply current

1.8

V

[1][2][3]

[1][3]

f_clk(ext)= 3.500 kHz

-

A

with internal oscillator running

f_clk(ext)= 3.500 kHz

[1][2][4]

[1][4]

I_DD(LCD)LCD supply current

with internal oscillator running

Logic^[5]

V_I

input voltage

on pins SDA and SCL

all other input pins

0.5

-

+5.5

V

0.5

V_DD+ 0.5 V

V_IH

V_IL

V_O

HIGH-level input voltage on pins CLK, SYNC, OSC, A0, A1,

SA0, SCL, and SDA

0.7V_DD

-

V

LOW-level input voltage

on pins CLK, SYNC, OSC, A0, A1,

SA0, SCL, and SDA

-

0.3V_DD

V

output voltage

on pins CLK and SYNC

on pin SDAACK

0.5

0.8V_DD

V_SS

-

V_DD+ 0.5 V

+5.5

V_DD

0.2V_DD

-

V

V_OH

V_OL

I_OH

HIGH-level output voltage on pin SYNC, CLK

V

LOW-level output voltage on pin SYNC, CLK, SDAACK

V

HIGH-level output current output source current;

1.5

mA

V_OH= 4.6 V;

V_DD= 5 V;

on pin CLK

I_OL

LOW-level output current output sink current;

on pins CLK and SYNC

V_OL= 0.4 V;

V_DD= 5 V

1.5

-

mA

on pin SDAACK

V_DD 2 V;

3

6

-

mA

V_OL= 0.2V_DD

2 V < V_DD< 3 V;

V_OL= 0.4 V

V_DD 3 V;

V_OL= 0.4 V

V_POR

I_L

power-on reset voltage

leakage current

1.0

1.3

-

1.6

+1

V

V_I= V_DDor V_SS

;

1

A

on pin OSC, CLK, A0, A1, SA0, SDA,

and SCL

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

Table 21. Static characteristics …continued

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 1.8 V to 8.0 V; T_amb= 40 C to +95 C; unless otherwise specified.

Symbol Parameter

LCD outputs

Conditions

Min

Typ

Max

Unit

[6][7]

V_O

output voltage variation

output resistance

on pins BP0 to BP3 and S0 to S159

V_LCD= 5 V

30

-

+30

mV

R_O

on pins BP0 to BP3

on pins S0 to S159

-

1.5

2.0

5

k

[1] LCD outputs are open-circuit; inputs at V_SSor V_DD; I²C-bus inactive; V_LCD= 8.0 V, V_DD= 5.0 V and RAM written with all logic 1.

[2] External clock with 50 % duty factor.

[3] For typical values, see Figure 24.

[4] For typical values, see Figure 25.

[5] The I²C-bus interface of PCA85232 is 5 V tolerant.

[6] Variation between any 2 backplanes on a given voltage level; static measured.

[7] Variation between any 2 segments on a given voltage level; static measured.

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(1) I_DDinternal is measured with the internal oscillator.

(2) _DDexternal is measured with an external clock.

T_amb= 30 C; 1:4 multiplex; V_LCD= 8 V; all RAM written with logic 1; no display connected.

I

Fig 24. I_DDwith respect to V_DD

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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_clk(ext)= 3.500 kHz.

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Fig 25. I_DD(LCD)with respect to V_LCD

PCA85232

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Product data sheet

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PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

13. Dynamic characteristics

Table 22. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 1.8 V to 8.0 V; T_amb= 40 C to +95 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min Typ Max Unit

[1][2][3]

[4]

f_clk(int)

internal clock frequency

on pin CLK;

V_DD= 5 V  0.5 V

3050 3500 4052 Hz

f_clk(ext)

t_clk(H)

t_clk(L)

f_fr

external clock frequency

HIGH-level clock time

LOW-level clock time

frame frequency variation

700

100

-

5000 Hz

external clock source used

V_DD= 5 V  0.5 V

-

s

f_fr= 146 Hz;

T_amb= 30 C

5.1

6.2

7.8

-

+5.1

+6.9

+7.6

%

f_fr= 135 Hz;

T

_amb= 95 C

f_fr= 157 Hz;

T_amb= 40 C

t_{PD(SYNC_N)}SYNC propagation delay

-

30

-

ns

s

t_{SYNC_NL}

t_PD(drv)

SYNC LOW time

100

-

driver propagation delay

V_LCD= 5 V

10

Timing characteristics: I²C-bus^[5]

f_SCL

t_BUF

SCL clock frequency

-

400 kHz

bus free time between a STOP and START

condition

1.3

-

s

t_HD;STA

t_SU;STA

t_VD;ACK

t_LOW

t_HIGH

t_f

hold time (repeated) START condition

set-up time for a repeated START condition

data valid acknowledge time

LOW period of the SCL clock

HIGH period of the SCL clock

fall time

0.6

-

s

-

0.9

-

1.3

0.6

-

of both SDA and SCL signals

0.3

t_r

rise time

-

C_b

capacitive load for each bus line

data set-up time

-

400 pF

t_SU;DAT

t_HD;DAT

t_SU;STO

t_SP

200

0

-

ns

s

ns

data hold time

-

set-up time for STOP condition

0.6

-

pulse width of spikes that must be

suppressed by the input filter

50

[1] Typical output duty factor: 50 % measured at the CLK output pin.

[2] For the respective frame frequency f_fr,see Table 12.

[3] For the characteristics of V_DDat a fixed temperature or of the temperature at a fixed V_DD, see Figure 26 and Figure 27.

[4] For f_clk(ext)> 4 kHz, it is recommended to use an external pull-up resistor between pin SYNC and pin V_DD. The value of the resistor

should be between 100 k and 1 M.

[5] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

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Product data sheet

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38 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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Condition: V_DD= 5 V  0.5 V; frame frequency prescaler = 011; 146 Hz typical.

The frame frequency is derived from the internal or external clock frequency by Equation 1.

Fig 27. Frame frequency variation

PCA85232

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Product data sheet

Rev. 4 — 8 April 2015

39 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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Fig 29. I²C-bus timing waveforms when SDA and SDAACK are connected

14. Application information

14.1 Pull-up resistor sizing on I²C-bus

14.1.1 Max value of pull-up resistor

The bus capacitance (C_b) is the total capacitance of wire, connections, and pins. This

capacitance on pin SDA limits the maximum value of the pull-up resistor (R_PU) due to the

specified rise time.

PCA85232

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Product data sheet

Rev. 4 — 8 April 2015

40 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

According to the I²C-bus specification the rise time (t_r) is defined between the V_DD-related

input threshold of V_IL= 0.3V_DDand V_IH= 0.7V_DD. The value for t_r(max)is 300 ns.

t_ris calculated with Equation 7:

t_r= t2 – t1

(7)

whereas t1 and t2 are the time since the charging started. The values for t1 and t2 are

derivatives of the functions V(t1) and V(t2):

C

Vt1 = 0.3V_DD= V_DD1 – e^{-t1  R}^b

(8)

(9)

PU

C

Vt2 = 0.7V_DD= V_DD1 – e^{-t2  R}^b

PU

with the results of

t1 = –R_PUC_b ln(0.7)

(10)

(11)

(12)

t2 = –R_PUC_b ln(0.3)

t_r= –R_PUC_b ln(0.3) + R_PUC_b ln(0.7)

R

_PU(max)is a function of the rise time (t_r) and the bus capacitance (C_b) and is calculated

with Equation 13:

t_r

300  10^–9

0.8473C_b

----------------------

R_PUmax

=

(13)

-------------------------

0.8473C_b

14.1.2 Min value of pull-up resistor

The supply voltage limits the minimum value of resistor R_PUdue to the specified minimum

sink current (see value of I_OLon pin SDAACK in Table 21 on page 35). R_PU(min)as a

function of V_DDis calculated with Equation 14:

V_DD– V_OL

R_PUmin

=

(14)

--------------------------

I_OL

The designer now has the minimum and maximum value of R_PU. The values for R_PU(max)

and R_PU(min)are shown in Figure 30 and Figure 31.

PCA85232

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Product data sheet

Rev. 4 — 8 April 2015

41 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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14.2 ITO track resistance

If an application requires to have a low V_DDsupply voltage compared to the V_LCDsupply

voltage, it is recommended to increase the ITO resistance on the V_LCDsupply track in

order to reduce the noise induced on the V_SSline when display is enabled. A low V_DD

voltage supply and noise peaks on V_SSinduced by display activities may introduce

disturbances into the I²C communication with the microcontroller.

Figure 32 shows that, when the ITO resistance of the V_SSpin has a certain value, it is

indicated to have a higher ITO resistance on the V_LCDtrack, especially if V_LCD(for

example, 9 V) is sharply higher than V_DD(for example, 1.8 V). With a higher ITO

resistance on the V_LCDtrack, the noise spikes induced to the V_SSof the PCA85232 are

getting smaller and the functionality is less affected.

PCA85232

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Product data sheet

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42 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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T_amb= 25 C; R_ITO(VSS)= 25 ; R_ITO(VDD)= 50 .

R_ITO(VLCD)= 50 .

(1)

(2) R_ITO(VLCD)= 100 .

(3) R_ITO(VLCD)= 150 .

a. Operating range of the PCA85232 with R_ITO(VSS)= 25 

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T_amb= 25 C; R_ITO(VSS)= 50 ; R_ITO(VDD)= 50 .

(1) R_ITO(VLCD)= 50 .

(2) _ITO(VLCD)= 75 .

R

(3) R_ITO(VLCD)= 100 .

(4) R_ITO(VLCD)= 150 .

(5)

R_ITO(VLCD)= 200 .

(6) R_ITO(VLCD)= 300 .

b. Operating range of the PCA85232 with R_ITO(VSS)= 50 

Fig 32. Operating range of the PCA85232 with respect to the ITO track resistance

PCA85232

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Product data sheet

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43 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

14.3 SDA and SDAACK configuration

The Serial DAta line (SDA) and the I²C-bus acknowledge line (SDAACK) are split. Both

lines can be connected together to facilitate a single-line SDA.

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Fig 33. SDA, SDAACK configurations

14.4 Cascaded operation

In large display configurations, up to 8 PCA85232 can be distinguished on the same

I²C-bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable

I²C-bus slave address (SA0).

Table 23. Addressing cascaded PCA85232

Cluster

Bit SA0

Pin A1

Pin A0

Device

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2

1

When cascaded PCA85232 are synchronized, they can share the backplane signals from

one of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCA85232 of the cascade contributes

additional segment outputs.The backplanes can be left open-circuit (as shown in the

examples of Figure 34 and Figure 35) or tied together to give enhanced drive capabilities

(see Section 7.4.1 on page 21).

For display sizes that are not multiple of 640 elements, a mixed cascaded system can be

considered containing only devices like PCA85232 and PCA85133. Depending on the

application, one must take care of the software commands compatibility and pin

connection compatibility.

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCA85232. This synchronization is guaranteed after the Power-On Reset (POR). The

only time that SYNC is likely to be needed is if synchronization is accidentally lost (for

example, by noise in adverse electrical environments, or by the definition of a multiplex

mode when PCA85232 with different SA0 levels are cascaded). SYNC is organized as an

input/output pin; the output selection being realized as an open-drain driver with an

internal pull-up resistor. A PCA85232 asserts the SYNC line at the onset of its last active

PCA85232

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Product data sheet

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44 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

backplane signal and monitors the SYNC line at all other times. Should synchronization in

the cascade be lost, it is restored by the first PCA85232 to assert SYNC. The timing

relationship between the backplane waveforms and the SYNC signal for the various drive

modes of the PCA85232 are shown in Figure 36 on page 48.

When using an external clock signal with high frequencies (f_clk(ext)> 4 kHz), it is

recommended to have an external pull-up resistor between pin SYNC and pin V_DD(see

Table 22 on page 38). This resistor should be present even when no cascading

configuration is used! When using it in a cascaded configuration, care must be taken not

to route the SYNC signal to close to noisy signals.

The contact resistance between the SYNC pads of cascaded devices must be controlled.

If the resistance is too high, the device is not able to synchronize properly. This is

particularly applicable to COG applications. Table 24 shows the limiting values for contact

resistance.

Table 24. SYNC contact resistance

Number of devices

Maximum contact resistance

2

6000 

2200 

1200 

3 to 5

6 to 8

In the cascaded applications, the OSC pin of the PCA85232 with subaddress 0 is

connected to V_SSso that this device uses its internal clock to generate a clock signal at

the CLK pin. The other PCA85232 devices are having the OSC pin connected to V_DD

,

meaning that these devices are ready to receive external clock, the signal being provided

by the device with subaddress 0.

If the master is providing the clock signal to the slave devices, care must be taken that the

sending of display enable or disable is received by both, the master and the slaves at the

same time. When the display is disabled, the output from pin CLK is disabled too. The

disconnection of the clock may result in a DC component for the display.

Alternatively, the schematic can be also constructed such that all the devices have OSC

pin connected to V_DDand thus an external CLK being provided for the system (all devices

connected to the same external CLK).

A configuration where SYNC is connected but all PCA85232 are using their internal clock

(OSC pin tied to V_SS) should not be used and may lead to display artifacts!

PCA85232

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Product data sheet

Rev. 4 — 8 April 2015

45 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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(1) Is master (OSC connected to V_SS).

(2) Is slave (OSC connected to V_DD).

Fig 34. Cascaded configuration with two PCA85232 using the internal clock of the master

PCA85232

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Product data sheet

Rev. 4 — 8 April 2015

46 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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(1) Is master (OSC connected to V_SS).

(2) Is slave (OSC connected to V_DD).

Fig 35. Cascaded configuration with one PCA85232 and one PCA85133 using the internal

clock of the master

PCA85232

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Product data sheet

Rev. 4 — 8 April 2015

47 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

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15. Test information

15.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

PCA85232

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Product data sheet

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48 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

16. Bare die outline

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PCA85232

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Product data sheet

Rev. 4 — 8 April 2015

49 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

Table 25. Bump locations

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 37.

Symbol

SDAACK

SDA

SCL

CLK

V_DD

SYNC

OSC

T1

Bump

1

X (m)

1165.3

1111.3

1057.3

854.8

800.8

746.8

575.8

521.8

467.8

316.2

204.1

150.1

96.1

Y (m)

481.5

Symbol

S68

S69

S70

S71

S72

S73

S74

S75

S76

S77

S78

S79

BP0

BP2

BP1

BP3

S80

S81

S82

S83

S84

S85

S86

S87

S88

S89

S90

S91

S92

S93

S94

S95

S96

S97

S98

S99

S100

S101

S102

Bump

100

101

102

103

104

105

106

107

108

109

110

111

X (m)

750.2

Y (m)

481.5

2

696.2

3

642.2

4

588.2

5

534.2

6

480.2

7

426.2

8

372.2

9

318.2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

264.2

210.2

156.2

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

86.8

6.9

32.8

119.4

21.2

203.1

75.2

T2

286.8

190.7

244.7

298.7

352.7

406.7

460.7

514.7

568.7

622.7

676.7

730.7

784.7

838.7

892.7

946.7

1000.7

1054.7

1108.7

1224.2

1278.2

1332.2

1386.2

1440.2

T3

389.9

T3

443.9

T3

497.9

A0

640.5

A1

724.2

SA0

V_SS

807.9

893.0

V_SS

947.0

V_SS

1001.0

1107.2

1161.2

1215.2

1303.4

1357.4

1411.4

1465.4

1519.4

1573.4

1627.4

1681.4

1735.4

1789.4

V_LCD

BP2

BP0

S0

S1

S2

S3

S4

S5

S6

S7

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Table 25. Bump locations …continued

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 37.

Symbol

S8

Bump

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

X (m)

1843.4

1897.4

1951.4

2005.4

2059.4

2113.4

2167.4

2221.4

2363.9

2417.9

2471.9

2525.9

2579.9

2633.9

2687.9

2741.9

2795.9

2849.9

2903.9

2957.9

3011.9

3067.7

3013.7

2959.7

2905.7

2851.7

2797.7

2743.7

2689.7

2635.7

2520.2

2466.2

2412.2

2358.2

2304.2

2250.2

2196.2

2142.2

2088.2

Y (m)

481.5

481.5

Symbol

S103

S104

S105

S106

S107

S108

S109

S110

S111

S112

S113

S114

S115

S116

S117

S118

S119

S120

S121

S122

S123

S124

S125

S126

S127

S128

S129

S130

S131

S132

S133

S134

S135

S136

S137

S138

S139

S140

S141

Bump

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

X (m)

Y (m)

481.5

481.5

1494.2

1548.2

1602.2

1656.2

1710.2

1764.2

1818.2

1872.2

1926.2

1980.2

2034.2

2088.2

2142.2

2284.7

2338.7

2392.7

2446.7

2500.7

2554.7

2608.7

2662.7

2716.7

2770.7

2824.7

2878.7

2932.7

2986.7

3040.7

3025.2

2971.2

2917.2

2863.2

2809.2

2755.2

2701.2

2647.2

2593.2

2539.2

2485.2

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

S40

S41

S42

S43

S44

S45

S46

481.5

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Table 25. Bump locations …continued

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 37.

Symbol

S47

S48

S49

S50

S51

S52

S53

S54

S55

S56

S57

S58

S59

S60

S61

S62

S63

S64

S65

S66

S67

Bump

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

X (m)

2034.2

1891.7

1837.7

1783.7

1729.7

1675.7

1621.7

1567.7

1513.7

1459.7

1405.7

1351.7

1297.7

1243.7

1189.7

1135.7

1081.7

1027.7

973.7

Y (m)

481.5

Symbol

S142

S143

S144

S145

S146

S147

S148

S149

S150

S151

S152

S153

S154

S155

S156

S157

S158

S159

BP3

Bump

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

X (m)

Y (m)

481.5

2431.2

2377.2

2234.7

2180.7

2126.7

2072.7

2018.7

1964.7

1910.7

1856.7

1802.7

1748.7

1694.7

1640.7

1586.7

1532.7

1478.7

1424.7

1370.7

1316.7

858.2

BP1

804.2

The dummy pins are connected to the segments shown (see Table 26) but are not tested.

Table 26. Dummy bumps

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 37 on page 49.

Symbol

D1

Connected to pin

X (m)

3079.2

3065.9

3121.7

3094.7

Y (m)

481.5

481.5

S131

S28

D2

D3

S29

D4

S130

481.5

The alignment marks are shown in Table 27.

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D

ꢄ

D

ꢅ

D

ꢁ

E

ꢄ

E

ꢁ

ꢅ

5()

6ꢄ

&ꢄ

ꢀꢁꢂDDDꢇꢄꢀ

Fig 38. Alignment marks

Table 27. Alignment marks

All x/y coordinates represent the position of the REF point (see Figure 38) with respect to the center

(x/y = 0) of the chip; see Figure 37 on page 49.

a

a₁

a₂

a₃

b

b₁

b₂

b₃

Coordinates

Unit

X

Y

Alignment mark S1

121.5

-

121.5

-

2733.75 47.25 m

Alignment mark C1

121.5 36.45 48.6

36.45 121.5 36.45 48.6

36.45 2603.7

47.25 m

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17. Packing information

17.1 Tray information

-

$

+

%

$

[ꢑꢄ

ꢄꢑꢄ

;

GLH

.

)

(

GHWDLOꢀ;

'

ꢄꢑ\

\

*

)

[

(

&

1

/

0

6(&7,21ꢅ$ꢍ$

<

GHWDLOꢀ<

'LPHQVLRQVꢀLQꢀPP

DDDꢅꢀꢀꢂꢂꢆꢈ

Fig 39. Tray details

Table 28. Description of tray details

Tray details are shown in Figure 39.

Tray details

Dimensions

A

B

C

D

E

F

G

H

J

K

L

M

N

O

Unit

mm

8.50

2.40

6.596 1.259 50.8

45.72 34.0

5.0

8.40

40.80 3.96

2.18

2.49

0.5

Number of pockets

x direction

5

y direction

18

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PDUNLQJꢀFRGH

ꢀꢀꢁDDMꢇꢆꢂ

Fig 40. Tray alignment

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19. Abbreviations

Table 30. Abbreviations

Acronym

AEC

COG

DC

Description

Automotive Electronics Council

Chip-On-Glass

Direct Current

HBM

I²C

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

ITO

Indium Tin Oxide

LCD

LSB

MM

Liquid Crystal Display

Least Significant Bit

Machine Model

MSB

POR

RC

Most Significant Bit

Power-On Reset

Resistance and Capacitance

Random Access Memory

Root Mean Square

Serial CLock line

RAM

RMS

SCL

SDA

Serial DAta line

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20. References

[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD

drivers

[2] AN10706 — Handling bare die

[3] AN11267 — EMC and system level ESD design guidelines for LCD drivers

[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[8] JESD78 — IC Latch-Up Test

[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[10] UM10204 — I²C-bus specification and user manual

[11] UM10569 — Store and transport requirements

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21. Revision history

Table 31. Revision history

Document ID

PCA85232 v.4

Modifications:

Release date

20150408

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCA85232 v.3

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Changed description of backplane connections when cascading

PCA85232 v.3

PCA85232 v.2

PCA85232 v.1

20130711

20120905

20101208

Product data sheet

-

PCA85232 v.2

PCA85232 v.1

-

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22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

22.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

22.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

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No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Bare die — All die are tested on compliance with their related technical

specifications as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

23. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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24. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 5. Definition of PCA85232 commands . . . . . . . . . .6

Table 6. Mode-set - command bit description . . . . . . . . .6

Table 7. Load-data-pointer-MSB - command bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 8. Load-data-pointer-LSB - command bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 9. Device-select - command bit description . . . . . .7

Table 10. Bank-select - command bit description . . . . . . .7

Table 11. Blink-select - command bit description . . . . . . .8

Table 12. Frequency-ctrl - command bit description . . . .10

Table 13. Blink frequencies . . . . . . . . . . . . . . . . . . . . . . .10

Table 14. Selection of possible display configurations . . .12

Table 15. Biasing characteristics . . . . . . . . . . . . . . . . . . .13

Table 16. Standard RAM filling in 1:3 multiplex drive

mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 17. Entire RAM filling by rewriting in 1:3 multiplex

drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 18. I²C slave address byte . . . . . . . . . . . . . . . . . . .30

Table 19. Control byte description . . . . . . . . . . . . . . . . . .31

Table 20. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 21. Static characteristics . . . . . . . . . . . . . . . . . . . .35

Table 22. Dynamic characteristics . . . . . . . . . . . . . . . . . .38

Table 23. Addressing cascaded PCA85232 . . . . . . . . . .44

Table 24. SYNC contact resistance . . . . . . . . . . . . . . . . .45

Table 25. Bump locations . . . . . . . . . . . . . . . . . . . . . . . .50

Table 26. Dummy bumps . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 27. Alignment marks. . . . . . . . . . . . . . . . . . . . . . . .53

Table 28. Description of tray details . . . . . . . . . . . . . . . . .54

Table 29. Selection of LCD segment drivers . . . . . . . . . .56

Table 30. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 31. Revision history . . . . . . . . . . . . . . . . . . . . . . . .60

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25. Figures

Fig 1. Block diagram of PCA85232 . . . . . . . . . . . . . . . . .3

Fig 2. Pinning diagram of PCA85232 . . . . . . . . . . . . . . .4

Fig 3. Frequency generation of the PCA85232 . . . . . . . .9

Fig 4. Example of displays suitable for PCA85232 . . . .12

Fig 5. Typical system configuration . . . . . . . . . . . . . . . .12

Fig 6. Electro-optical characteristic: relative

transmission curve of the liquid . . . . . . . . . . . . . .15

Fig 7. Static drive mode waveforms. . . . . . . . . . . . . . . .16

Fig 8. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₂bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Fig 9. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Fig 10. Waveforms for the 1:3 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 11. Waveforms for the 1:4 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 12. Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .22

Fig 13. Relationships between LCD layout, drive mode,

display RAM filling order, and display data

transmitted over the I²C-bus . . . . . . . . . . . . . . . .23

Fig 14. RAM banks in static and multiplex driving

mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 15. Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 16. Example of the Bank-select command with

multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .27

Fig 17. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 18. Definition of START and STOP conditions. . . . . .29

Fig 19. System configuration . . . . . . . . . . . . . . . . . . . . . .29

Fig 20. Acknowledgement on the I²C-bus . . . . . . . . . . . .30

Fig 21. I²C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 22. Control byte format . . . . . . . . . . . . . . . . . . . . . . .31

Fig 23. Device protection diagram. . . . . . . . . . . . . . . . . .33

Fig 24. I_DDwith respect to V_DD. . . . . . . . . . . . . . . . . . . .36

Fig 25. I_DD(LCD)with respect to V_LCD. . . . . . . . . . . . . . . .37

Fig 26. Typical clock frequency (f_clk) with respect

to V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Fig 27. Frame frequency variation. . . . . . . . . . . . . . . . . .39

Fig 28. Driver timing waveforms . . . . . . . . . . . . . . . . . . .40

Fig 29. I²C-bus timing waveforms when SDA and

SDAACK are connected . . . . . . . . . . . . . . . . . . .40

Fig 30. Values for R_PU(max). . . . . . . . . . . . . . . . . . . . . . . .42

Fig 31. Values for R_PU(min). . . . . . . . . . . . . . . . . . . . . . . .42

Fig 32. Operating range of the PCA85232 with respect

to the ITO track resistance. . . . . . . . . . . . . . . . . .43

Fig 33. SDA, SDAACK configurations . . . . . . . . . . . . . . .44

Fig 34. Cascaded configuration with two PCA85232

using the internal clock of the master . . . . . . . . .46

Fig 35. Cascaded configuration with one PCA85232

and one PCA85133 using the internal clock of

the master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Fig 36. Synchronization of the cascade for the various

PCA85232 drive modes. . . . . . . . . . . . . . . . . . . .48

Fig 37. Bare die outline of PCA85232 . . . . . . . . . . . . . . .49

Fig 38. Alignment marks . . . . . . . . . . . . . . . . . . . . . . . . .53

Fig 39. Tray details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Fig 40. Tray alignment . . . . . . . . . . . . . . . . . . . . . . . . . . .55

PCA85232

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 8 April 2015

64 of 65

PCA85232

NXP Semiconductors

LCD driver for low multiplex rates

26. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.1

8.1.1

8.2

8.3

8.4

8.5

8.6

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

START and STOP conditions. . . . . . . . . . . . . 28

System configuration . . . . . . . . . . . . . . . . . . . 29

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 29

I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 30

Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 30

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

3.1

4

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

9

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 33

Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34

Static characteristics . . . . . . . . . . . . . . . . . . . 35

Dynamic characteristics. . . . . . . . . . . . . . . . . 38

10

11

12

13

7

7.1

Functional description . . . . . . . . . . . . . . . . . . . 6

Commands of PCA85232. . . . . . . . . . . . . . . . . 6

Command: mode-set . . . . . . . . . . . . . . . . . . . . 6

Command: load-data-pointer . . . . . . . . . . . . . . 7

Command: device-select . . . . . . . . . . . . . . . . . 7

Command: bank-select. . . . . . . . . . . . . . . . . . . 7

Command: blink-select. . . . . . . . . . . . . . . . . . . 8

Clock frequency and timing . . . . . . . . . . . . . . . 8

Clock source selection . . . . . . . . . . . . . . . . . . . 8

Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . 9

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Frame frequency . . . . . . . . . . . . . . . . . . . . . . . 9

Command: frequency-ctrl . . . . . . . . . . . . . . . . 10

Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 11

Possible display configurations . . . . . . . . . . . 11

LCD bias generator . . . . . . . . . . . . . . . . . . . . 13

Display register. . . . . . . . . . . . . . . . . . . . . . . . 13

LCD voltage selector . . . . . . . . . . . . . . . . . . . 13

Electro-optical performance . . . . . . . . . . . . . . 14

LCD drive mode waveforms . . . . . . . . . . . . . . 16

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 16

1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 17

1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 19

1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 20

Backplane and segment outputs . . . . . . . . . . 21

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 21

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 21

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 21

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Subaddress counter . . . . . . . . . . . . . . . . . . . . 24

RAM writing in 1:3 multiplex drive mode. . . . . 24

Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 25

Output bank selector . . . . . . . . . . . . . . . . . . . 25

Input bank selector . . . . . . . . . . . . . . . . . . . . . 26

RAM bank switching. . . . . . . . . . . . . . . . . . . . 26

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.6

7.1.6.1

7.1.6.2

7.1.6.3

7.1.6.4

7.1.6.5

7.1.6.6

7.2

14

Application information . . . . . . . . . . . . . . . . . 40

Pull-up resistor sizing on I²C-bus. . . . . . . . . . 40

Max value of pull-up resistor . . . . . . . . . . . . . 40

Min value of pull-up resistor. . . . . . . . . . . . . . 41

ITO track resistance. . . . . . . . . . . . . . . . . . . . 42

SDA and SDAACK configuration . . . . . . . . . . 44

Cascaded operation. . . . . . . . . . . . . . . . . . . . 44

14.1

14.1.1

14.1.2

14.2

14.3

14.4

15

15.1

16

Test information . . . . . . . . . . . . . . . . . . . . . . . 48

Quality information. . . . . . . . . . . . . . . . . . . . . 48

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 49

Packing information . . . . . . . . . . . . . . . . . . . . 54

Tray information . . . . . . . . . . . . . . . . . . . . . . . 54

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

LCD segment driver selection . . . . . . . . . . . . 56

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 58

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Revision history . . . . . . . . . . . . . . . . . . . . . . . 60

17

17.1

18

18.1

19

7.3

7.3.1

7.3.2

7.3.3

7.3.3.1

7.3.4

7.3.4.1

7.3.4.2

7.3.4.3

7.3.4.4

7.4

7.4.1

7.4.2

7.5

7.5.1

7.5.2

7.5.3

7.5.4

7.5.4.1

7.5.4.2

7.5.4.3

20

21

22

Legal information . . . . . . . . . . . . . . . . . . . . . . 61

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 61

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 62

22.1

22.2

22.3

22.4

23

24

25

26

Contact information . . . . . . . . . . . . . . . . . . . . 62

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8

Characteristics of the I²C-bus . . . . . . . . . . . . 28

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 April 2015

Document identifier: PCA85232


型号：	PCA85232U/2DA/Q1,0
厂家：	NXP
描述：	PCA85232 - LCD driver for low multiplex rates DIE 197-Pin PC CD
文件：	总65页 (文件大小：572K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA85232U/2DA/Q1,0 [NXP]

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