PCA8576CH/Q900/1,1_技术文档

PCA8576C

Automotive LCD driver for low multiplex rates

Rev. 3 — 8 April 2015

Product data sheet

1. General description

The PCA8576C is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)¹with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 40 segments and can easily

be cascaded for larger LCD applications. The PCA8576C is compatible with most

microcontrollers and communicates via the two-line bidirectional I²C-bus. Communication

overheads are minimized by a display RAM with auto-incremented addressing and by

hardware subaddressing.

For a selection of NXP LCD segment drivers, see Table 21 on page 45.

2. Features and benefits

 AEC-Q100 compliant for automotive applications

 Single-chip LCD controller and driver

 40 segment drives:

 Up to twenty 7-segment alphanumeric characters

 Up to ten 14-segment alphanumeric characters

 Any graphics of up to 160 elements

 Versatile blinking modes

 No external components required (even in multiple device applications)

 Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

 Selectable display bias configuration: static, ¹⁄₂, or ¹⁄₃

 Internal LCD bias generation with voltage-follower buffers

 40  4-bit RAM for display data storage

 Auto-incremented display data loading across device subaddress boundaries

 Display memory bank switching in static and duplex drive modes

 Wide logic LCD supply range:

 From 2 V for low-threshold LCDs

 Up to 6 V for guest-host LCDs and high-threshold twisted nematic LCDs

 Low power consumption

 May be cascaded for large LCD applications (up to 2560 segments possible)

 No external components

 Separate or combined LCD and logic supplies

 Optimized pinning for plane wiring in both and multiple PCA8576C applications

 Power-saving mode for extremely low power consumption in battery-operated and

telephone applications

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCA8576CH

PCA8576CT

LQFP64

plastic low profile quad flat package;

64 leads; body 10  10  1.4 mm

SOT314-2

VSO56

plastic very small outline package,

56 leads

SOT190-1

3.1 Ordering options

Table 2.

Ordering options

Product type number Sales item

(12NC)

Orderable part

number

IC

revision

Delivery form

PCA8576CH/Q900/1

PCA8576CT/Q900/1

4. Marking

935290244157 PCA8576CH/Q900,157 1

tray pack

935290244118 PCA8576CH/Q900/1,1

935301673518 PCA8576CT/Q900/1Y

1

tape and reel, 13 inch

Table 3.

Marking codes

Type number

Marking code

PCA8576CQ900

PCA8576CT/Q

PCA8576CH/Q900/1

PCA8576CT/Q900/1

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

2 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

5. Block diagram

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PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

3 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

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Top view. For mechanical details, see Figure 31.

Fig 2. Pin configuration for LQFP64 (PCA8576CH/Q900/1)

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

4 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

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Top view. For mechanical details, see Figure 32.

Fig 3. Pin configuration for VSO56 (PCA8576CT/Q900/1)

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

5 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

6.2 Pin description

Table 4.

Pin description

Input or input/output pins must always be at a defined level (V_SSor V_DD) unless otherwise specified.

Symbol

Description

LQFP64

VSO56

Type

(PCA8576CH/Q900/1) (PCA8576CT)

SDA

SCL

10

1

input/output

input

I²C-bus serial data input and output

I²C-bus serial clock input

cascade synchronization input and output

external clock input/output

supply voltage

11

2

SYNC

CLK

12

3

input/output

supply

13

4

V_DD

14

5

OSC

A0 to A2

SA0

15

6

input

internal oscillator enable input

16 to 18

19

7 to 9

10

input

subaddress inputs

input

I²C-bus address input; bit 0

ground supply voltage

V_SS

20

11

supply

V_LCD

21

12

supply

LCD supply voltage

BP0, BP2, 25 to 28

BP1, BP3

13 to 16

output

LCD backplane outputs

S0 to S39

2 to 7, 29 to 32,

34 to 47, 49 to 64

17 to 56

-

output

-

LCD segment outputs

n.c.

1, 8, 9, 22 to 24, 33,

48

not connected; do not connect and do not use

as feed through

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

6 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

7. Functional description

The PCA8576C is a versatile peripheral device designed to interface between any

microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays

(see Figure 4). It can directly drive any static or multiplexed LCD containing up to four

backplanes and up to 40 segments.

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Fig 4. Example of displays suitable for PCA8576C

The possible display configurations of the PCA8576C depend on the number of active

backplane outputs required. A selection of display configurations is shown in Table 5. All

of these configurations can be implemented in the typical system shown in Figure 5.

Table 5.

Selection of possible display configurations

Number of

Backplanes

Icons

Digits/Characters

Dot matrix/

Elements

7-segment

14-segment

4

3

2

1

160

120

80

20

15

10

5

10

7

160 dots (4  40)

120 dots (3  40)

80 dots (2  40)

40 dots (1  40)

5

40

2

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

7 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

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Fig 5. Typical system configuration

The host microprocessor or microcontroller maintains the 2-line I²C-bus communication

channel with the PCA8576C.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to V_SS. The only other connections required to complete the system are the

power supplies (pins V_DD, V_SS, and V_LCD) and the LCD panel selected for the application.

7.1 Power-On-Reset (POR)

At power-on the PCA8576C resets to the following starting conditions:

• All backplane and segment outputs are set to V_DD

• The selected drive mode is 1:4 multiplex with ¹⁄₃bias

• Blinking is switched off

• Input and output bank selectors are reset (as defined in Table 9)

• The I²C-bus interface is initialized

• The data pointer and the subaddress counter are cleared

Remark: Do not transfer data on the I²C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.2 LCD bias generator

The full-scale LCD voltage (V_oper) is obtained from V_DD V_LCD. The LCD voltage may be

temperature compensated externally through the V_LCDsupply to pin V_LCD

.

Fractional LCD biasing voltages are obtained from an internal voltage divider comprising

three series resistors connected between V_DDand V_LCD. The center resistor can be

switched out of the circuit to provide a ¹⁄₂bias voltage level for the 1:2 multiplex

configuration.

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

8 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

7.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

V

_LCDand the resulting discrimination ratios (D) are given in Table 6.

Table 6.

Biasing characteristics

Number of:

LCD drive

mode

LCD bias

configuration

V_offRMSV_onRMS

------------------------ ----------------------- D = ------------------------

V_LCDV_LCDV_offRMS

V_onRMS

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1



1

⁄

1:2 multiplex

1:3 multiplex

1:4 multiplex

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

2

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a defined LCD

threshold voltage (V_th), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode a suitable choice is V_LCD> 3V_th.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 1:

a²+ 2a + n

n  1 + a²

V_onRMS

=

-----------------------------

(1)

V

LCD

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 2:

a²– 2a + n

n  1 + a²

V_offRMS

=

-----------------------------

(2)

(3)

V

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 3:

a + 1²+ n – 1

V_onRMS

D =

=

-------------------------------------------

----------------------

a – 1²+ n – 1

V_offRMS

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

9 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V_LCD

• 1:4 multiplex (¹⁄₂bias): V_LCD

=

6  V_offRMS= 2.449V_offRMS

4  3

---------------------

= 2.309V_offRMS

3

These compare with V_LCD= 3V_offRMSwhen ¹⁄₃bias is used.

_LCDis sometimes referred as the LCD operating voltage.

V

7.3.1 Electro-optical performance

Suitable values for V_on(RMS)and V_off(RMS)are dependent on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at V_th(off)) and the other at 90 % relative transmission (at V_th(on)), see

Figure 6. For a good contrast performance, the following rules should be followed:

V

_onRMS V_thon

_offRMS V_thoff

(4)

(5)

V

_on(RMS)and V_off(RMS)are properties of the display driver and are affected by the selection

of a (see Equation 1), n (see Equation 3), and the V_LCDvoltage.

V_th(off)and V_th(on)are properties of the LCD liquid and can be provided by the module

manufacturer. V_th(off)is sometimes named V_th. V_th(on)is sometimes named saturation

voltage V_sat

.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

10 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

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PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

11 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

7.4 LCD drive mode waveforms

7.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD.

Backplane and segment drive waveforms for this mode are shown in Figure 7.

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= V_LCD

_state2(t) = V_Sn+1(t)  V_BP0(t).

V_off(RMS)= 0 V.

.

V

Fig 7. Static drive mode waveforms

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

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PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

7.4.2 1:2 Multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCA8576C allows the use of ¹⁄₂bias or ¹⁄₃bias (see Figure 8 and Figure 9).

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.791V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

_off(RMS)= 0.354V_LCD

.

V

Fig 8. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

13 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.745V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t)

V_off(RMS)= 0.333V_LCD.

Fig 9. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

PCA8576C

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7.4.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as

shown in Figure 10.

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.638V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

_off(RMS)= 0.333V_LCD.

.

V

Fig 10. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

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7.4.4 1:4 multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as

shown in Figure 11.

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V_state1(t) = V_Sn(t)  V_BP0(t).

V_on(RMS)= 0.577V_LCD

V_state2(t) = V_Sn(t)  V_BP1(t).

_off(RMS)= 0.333V_LCD.

.

V

Fig 11. Waveforms for the 1:4 multiplex mode with ¹⁄₃bias

PCA8576C

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7.5 Oscillator

The internal logic and the LCD drive signals of the PCA8576C are timed by the frequency

f_clk, which equals either the built-in oscillator frequency f_oscor the external clock frequency

f_clk(ext)

.

The clock frequency (f_clk) determines the LCD frame frequency (f_fr) and the maximum rate

for data reception from the I²C-bus. To allow I²C-bus transmissions at their maximum data

rate of 100 kHz, f_clkshould be chosen to be above 125 kHz.

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to pin V_SS. In this case, the

output from pin CLK is the clock signal for any cascaded PCA8576C in the system.

7.5.2 External clock

Connecting pin OSC to V_DDenables an external clock source. Pin CLK then becomes the

external clock input.

Remark: A clock signal must always be supplied to the device. Removing the clock,

freezes the LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing

The timing of the PCA8576C sequences the internal data flow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. In

cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between the PCA8576Cs in the system. The timing also generates the LCD

frame frequency which is derived as an integer division of the clock frequency (see

Table 7). The frame frequency is set by the mode-set command (see Table 10) when an

internal clock is used or by the frequency applied to the pin CLK when an external clock is

used.

Table 7.

LCD frame frequencies ^[1]

PCA8576C mode

Frame frequency

Nominal frame frequency (Hz)

Normal-power mode

69 ^[2]

f_clk

f_fr

=

------------

2880

Power-saving mode

65 ^[3]

f_clk

---------

480

f_fr

[1] The possible values for f_clksee Table 17.

[2] For f_clk= 200 kHz.

[3] For f_clk= 31 kHz.

The ratio between the clock frequency and the LCD frame frequency depends on the

power mode in which the device is operating. In the power-saving mode the reduction

ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six.

The reduced clock frequency results in a significant reduction in power consumption.

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The lower clock frequency has the disadvantage of increasing the response time when

large amounts of display data are transmitted on the I²C-bus. When a device is unable to

process a display data byte before the next one arrives, it holds the SCL line LOW until

the first display data byte is stored. This slows down the transmission rate of the I²C-bus

but no data loss occurs.

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

7.8 Shift register

The shift register transfers display information from the display RAM to the display register

while previous data is displayed.

7.9 Segment outputs

The LCD drive section includes 40 segment outputs, S0 to S39, which must be connected

directly to the LCD. The segment output signals are generated based on the multiplexed

backplane signals and with data residing in the display register. When less than

40 segment outputs are required, the unused segment outputs should be left open-circuit.

7.10 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated based on the selected LCD drive mode.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required the unused outputs can be left as an

open-circuit.

• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same

signals and can also be paired to increase the drive capabilities.

• In static drive mode: the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

7.11 Display RAM

The display RAM is a static 40  4-bit RAM which stores LCD data.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

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The display RAM bit map Figure 12 shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the

segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,

second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,

and BP3 respectively.

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The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs; and between the bits in a RAM row and the backplane outputs.

Fig 12. Display RAM bit map

When display data is transmitted to the PCA8576C, the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and does not wait for an acknowledge cycle as with the commands. Depending

on the current multiplex drive mode, data is stored singularly, in pairs, triples or

quadruples. To illustrate the filling order, an example of a 7-segment numeric display

showing all drive modes is given in Figure 13; the RAM filling organization depicted

applies equally to other LCD types.

The following applies to Figure 13:

• In the static drive mode, the eight transmitted data bits are placed in row 0 of eight

successive 4-bit RAM words.

• In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into

row 0 and 1 of four successive 2-bit RAM words.

• In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1, and 2 to

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted.

• In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into

row 0, 1, 2, and 3 of two successive 4-bit RAM words.

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7.12 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 11). After this, the data byte is

stored starting at the display RAM address indicated by the data pointer (see Figure 13).

Once each byte is stored, the data pointer is automatically incremented based on the

selected LCD configuration.

The contents of the data pointer are incremented as follows:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I²C-bus data access terminates early, the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.13 Sub-address counter

The storage of display data is conditioned by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter match

with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is

defined by the device-select command (see Table 12). If the contents of the subaddress

counter and the hardware subaddress do not match then data storage is blocked but the

data pointer will be incremented as if data storage had taken place. The subaddress

counter is also incremented when the data pointer overflows.

The storage arrangements described lead to extremely efficient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCA8576C occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character.

7.14 Bank selector

7.14.1 Output bank selector

The output bank selector (see Table 13), selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the LCD

drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode: all RAM addresses of row 0 are selected, followed sequentially

by the contents of row 1, row 2, and then row 3.

• In 1:3 multiplex mode: rows 0, 1, and 2 are selected sequentially.

• In 1:2 multiplex mode: rows 0 and 1 are selected.

• In the static mode: row 0 is selected.

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Automotive LCD driver for low multiplex rates

The PCA8576C includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. In the static drive mode, the bank-select command may request the contents

of row 2 to be selected for display instead of the contents of row 0. In 1:2 multiplex drive

mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This

enables preparation of display information in an alternative bank and the ability to switch

to it once it has been assembled.

7.14.2 Input bank selector

The input bank selector (see Table 13) loads display data into the display RAM based on

the selected LCD drive configuration. Using the bank-select command, display data can

be loaded in row 2 into static drive mode or in rows 2 and 3 into 1:2 multiplex drive mode.

The input bank selector functions independently of the output bank selector.

7.15 Blinking

The display blinking capabilities of the PCA8576C are very versatile. The whole display

can be blinked at frequencies selected by the blink-select command. The blinking

frequencies are integer fractions of the clock frequency; the ratios between the clock and

blinking frequencies depend on the mode in which the device is operating (see Table 8).

Table 8.

Blink frequencies

Blinking mode

Normal-power mode Power-saving mode

Blink frequency

ratio

off

1

-

blinking off

2 Hz

f_clk

f_blink

=

f_blink

=

----------------

92160

----------------

15360

2

3

1 Hz

f_clk

-------------------

184320

----------------

30720

0.5 Hz

f_clk

-------------------

368640

----------------

61440

An additional feature is for an arbitrary selection of LCD segments to be blinked. This

applies to the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. Using the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blinking frequency. This mode can also be

specified by the blink-select command (see Table 14).

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can be blinked by selectively changing the display RAM data at fixed time

intervals.

If the entire display needs to be blinked at a frequency other than the nominal blink

frequency, this can be done using the mode-set command to set and reset the display

enable bit E at the required rate (see Table 10).

7.16 Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

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7.16.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse. Changes in the data line at this time will

be interpreted as a control signal. Bit transfer is illustrated in Figure 14.

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7.16.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change

of the data line, while the clock is HIGH, is defined as the START condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP

condition (P). The START and STOP conditions are illustrated in Figure 15.

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7.16.3 System configuration

A device generating a message is a transmitter and a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is illustrated in

Figure 16.

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PCA8576C

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7.16.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is illustrated in Figure 17.

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7.16.5 PCA8576C I²C-bus controller

The PCA8576C acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCA8576C are

the acknowledge signals of the selected devices. Device selection depends on the

I²C-bus slave address, the transferred command data and the hardware subaddress.

In single device application, the hardware subaddress inputs A0, A1, and A2 are normally

tied to V_SSwhich defines the hardware subaddress 0. In multiple device applications

A0, A1, and A2 are tied to V_SSor V_DDusing a binary coding scheme so that no two

devices with a common I²C-bus slave address have the same hardware subaddress.

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In the power-saving mode it is possible that the PCA8576C is not able to keep up with the

highest transmission rates when large amounts of display data are transmitted. If this

situation occurs, the PCA8576C forces the SCL line LOW until its internal operations are

completed. This is known as the clock synchronization feature of the I²C-bus and serves

to slow down fast transmitters. Data loss does not occur.

7.16.6 Input filter

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

7.17 I²C-bus protocol

Two I²C-bus slave addresses (0111000 and 0111001) are reserved for the PCA8576C.

The least significant bit of the slave address that a PCA8576C responds to is defined by

the level tied at its input SA0. Therefore, two types of PCA8576C can be distinguished on

the same I²C-bus which allows:

• Up to 16 PCA8576Cs on the same I²C-bus for very large LCD applications.

• The use of two types of LCD multiplex on the same I²C-bus.

The I²C-bus protocol is shown in Figure 18. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of the two PCA8576C

slave addresses available. All PCA8576Cs with the corresponding SA0 level

acknowledge in parallel with the slave address but all PCA8576Cs with the alternative

SA0 level ignore the whole I²C-bus transfer.

After acknowledgement, one or more command bytes follow which define the status of the

addressed PCA8576Cs.

The last command byte is tagged with a cleared most significant bit, the continuation bit C.

The command bytes are also acknowledged by all addressed PCA8576Cs on the bus.

After the last command byte, a series of display data bytes may follow. These display

bytes are stored in the display RAM at the address specified by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data is directed to the intended PCA8576C device. The acknowledgement after

each byte is made only by the (A0, A1, and A2) addressed PCA8576C. After the last

display byte, the I²C-bus master issues a STOP condition (P).

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Fig 18. I²C-bus protocol

PCA8576C

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PCA8576C

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7.18 Command decoder

The command decoder identifies command bytes that arrive on the I²C-bus. All available

commands carry a continuation bit C in their most significant bit position as shown in

Figure 19. When this bit is set logic 1, it indicates that the next byte of the transfer to arrive

will also represent a command. If this bit is set logic 0, it indicates that the command byte

is the last in the transfer. Further bytes will be regarded as display data.

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(1) C = 0; last command

(2) C = 1; commands continue

Fig 19. General format of the command byte

The five commands available to the PCA8576C are defined in Table 9.

Table 9.

Definition of PCA8576C commands

Operation Code

Command

Bit

Reference

7

6

1

0

1

5

4

3

2

1

0

mode-set

C

0

LP

E

B

M[1:0]

Section 7.18.1

Section 7.18.2

Section 7.18.3

Section 7.18.4

Section 7.18.5

load-data-pointer

device-select

bank-select

blink-select

P[5:0]

1

0

1

0

1

0

A[2:0]

0

I

O

AB

BF[1:0]

7.18.1 Mode-set command

Table 10. Mode-set command bit description

Bit

7

Symbol Value

Description

see Figure 19

fixed value

C

-

0, 1

10

6 to 5

4

LP

power dissipation (see Table 7)

normal-power mode

power-saving mode

display status

disabled^[1]

0

1

3

2

E

B

0

1

enabled

LCD bias configuration^[2]

¹⁄₃bias

¹⁄₂bias

0

1

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Table 10. Mode-set command bit description …continued

Bit

Symbol Value

Description

1 to 0

M[1:0]

01

LCD drive mode selection

static; BP0

10

1:2 multiplex; BP0, BP1

1:3 multiplex; BP0, BP1, BP2

1:4 multiplex; BP0, BP1, BP2, BP3

11

00

[1] The possibility to disable the display allows implementation of blinking under external control.

[2] Bit B is not applicable for the static LCD drive mode.

7.18.2 Load-data-pointer command

Table 11. Load-data-pointer command bit description

Bit

7

Symbol Value

Description

see Figure 19

fixed value

C

0, 1

0

6

-

5 to 0

P[5:0]

000000 to

100111

6 bit binary value, 0 to 39; transferred to the data pointer to

define one of forty display RAM addresses

7.18.3 Device-select command

Table 12. Device-select command bit description

Bit

Symbol Value

Description

see Figure 19

fixed value

7

C

0, 1

6 to 4

3 to 0

-

1100

A[2:0]

000 to 111

3 bit binary value, 0 to 7; transferred to the subaddress

counter to define one of eight hardware subaddresses

7.18.4 Bank-select command

Table 13. Bank-select command bit description

Bit

Symbol Value

Description

Static

1:2 multiplex^[1]

7

C

-

0, 1

see Figure 19

fixed value

6 to 2

1

11110

I

input bank selection; storage of arriving display data

0

1

RAM bit 0

RAM bit 2

RAM bits 0 and 1

RAM bits 2 and 3

0

O

output bank selection; retrieval of LCD display data

0

1

RAM bit 0

RAM bit 2

RAM bits 0 and 1

RAM bits 2 and 3

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

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7.18.5 Blink-select command

Table 14. Blink-select command bit description

Bit

7

Symbol Value

Description

C

0, 1

see Figure 19

6 to 3

2

-

1110

fixed value

AB

blink mode selection

0

1

normal blinking^[1]

alternate RAM bank blinking^[2]

1 to 0

BF[1:0]

blink frequency selection

00

01

10

11

off

1

2

3

[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

7.19 Display controller

The display controller executes the commands identified by the command decoder. It

contains the status registers of the PCA8576C and coordinates their effects. The

controller is also responsible for loading display data into the display RAM as required by

the filling order.

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8. Internal circuitry

9

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Fig 20. Device protection diagram

9. Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

PCA8576C

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10. Limiting values

Table 15. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V

V_DD

V_LCD

V_I

supply voltage

LCD supply voltage

input voltage

0.5

+8.0

[1]

V_DD 8.0 V_DD

V

on each of the pins SCL, SDA, 0.5

+8.0

V

CLK, SYNC, SA0, OSC and

A0 to A2

[1]

V_O

output voltage

on each of the pins

0.5

+8.0

V

S0 to S39 and BP0 to BP3

I_I

input current

20

25

50

-

+20

+25

+50

400

100

4000

mA

mW

V

I_O

output current

I_DD

I_SS

supply current

ground supply current

I_DD(LCD)LCD supply current

P_tot

P_o

total power dissipation

output power

-

[2]

[3]

V_ESD

electrostatic discharge

voltage

HBM

-

CDM

PCA8576CH

all pins

-

500

V

corner pins

PCA8576CT

all pins

1000

-

500

750

150

+150

+85

V

corner pins

-

V

[4]

[5]

I_lu

latch-up current

-

mA

C

T_stg

T_amb

storage temperature

ambient temperature

65

40

operating device

[1] Values with respect to V_DD

.

[2] Pass level; Human Body Model (HBM), according to Ref. 6 “JESD22-A114”.

[3] Pass level; Charged-Device Model (CDM), according to Ref. 7 “JESD22-C101”.

[4] Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (T_amb(max)).

[5] According to the store and transport requirements (see Ref. 10 “UM10569”) the devices have to be stored

at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.

PCA8576C

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11. Static characteristics

Table 16. Static characteristics

V_DD= 2.0 V to 6.0 V; V_SS= 0 V; V_LCD= V_DD 6.0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

2.0

-

6.0

V

[1]

[2]

V_LCD

I_DD

LCD supply voltage

supply current:

V_DD 6.0

V_DD 2.0 V

f_clk= 200 kHz

-

120

60

A

I_DD(lp)

low-power mode supply

current

V_DD= 3.5 V; V_LCD= 0 V; f_clk= 35 kHz;

A0, A1 and A2 connected to V_SS

A

Logic

V_IL

LOW-level input voltage

HIGH-level input voltage

on pins CLK, SYNC, OSC,

A0 to A2 and SA0

V_SS

-

0.3V_DD

V_DD

V

V_IH

on pins CLK, SYNC, OSC,

A0 to A2 and SA0

0.7V_DD

V_OL

V_OH

I_OL

LOW-level output voltage

HIGH-level output voltage

LOW-level output current

I_OL= 0 mA

I_OH= 0 mA

-

0.05

V

V_DD 0.05 -

-

V

output sink current;

1

-

mA

V_OL= 1.0 V; V_DD= 5.0 V;

on pins CLK and SYNC

I_L

leakage current

V_I= V_DDor V_SS; on pins

1

-

+1

A

CLK, SCL, SDA, A0 to A2 and SA0

I_L(OSC)

I_pd

leakage current on pin OSC

pull-down current

V_I= V_DD

1

-

+1

A

V_I= 1.0 V; V_DD= 5.0 V;

15

50

150

on pins A0 to A2 and OSC

R_{SYNC_N}SYNC resistance

20

-

50

1.0

-

150

1.6

7

k

V

[3]

[4]

V_POR

C_I

power-on reset voltage

input capacitance

-

pF

I²C-bus; pins SDA and SCL

V_IL

LOW-level input voltage

HIGH-level input voltage

V_SS

0.7V_DD

1

-

0.3V_DD

V

V_IH

6.0

-

V

I_OH(CLK)

HIGH-level output current on output source current;

mA

pin CLK

V_OH= 4.0 V; V_DD= 5.0 V

I_OL(SDA)

LOW-level output current on

pin SDA

output sink current;

V_OL= 0.4 V; V_DD= 5.0 V

3

-

mA

PCA8576C

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Table 16. Static characteristics …continued

V_DD= 2.0 V to 6.0 V; V_SS= 0 V; V_LCD= V_DD 6.0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

LCD outputs

Conditions

Min

Typ

Max

Unit

V_BP

V_S

voltage on pin BP

C_bpl= 35 nF; on pins BP0 to BP3

C_sgm= 5 nF; on pins S0 to S39

20

-

+20

5

mV

k

voltage on pin S

20

[5]

R_BP

R_S

resistance on pin BP

resistance on pin S

V_LCD= V_DD 5 V; on pins BP0 to BP3

V_LCD= V_DD 5 V; on pins S0 to S39

-

7.5

[1] V_LCD V_DD 3 V for ¹⁄₃bias.

[2] LCD outputs are open-circuit; inputs at V_SSor V_DD; external clock with 50 % duty factor; I²C-bus inactive.

[3] Resets all logic when V_DDV_POR

.

[4] Periodically sampled, not 100 % tested.

[5] Outputs measured one at a time.

11.1 Typical supply current characteristics

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Fig 21. I_SSas a function of f_fr

Fig 22. I_DD(LCD)as a function of f_fr

PCA8576C

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Automotive LCD driver for low multiplex rates

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Fig 23. I_SSas a function of V_DD

Fig 24. I_DD(LCD)as a function of V_DD

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11.2 Typical LCD output characteristics

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Fig 25. R_O(max)as a function of V_DD

Fig 26. R_O(max)as a function of T_amb

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PCA8576C

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12. Dynamic characteristics

Table 17. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Timing characteristics: driver timing waveforms (see Figure 27)

[1]

f_clk

clock frequency

normal-power mode;

V_DD= 5 V

125

21

200

31

315

48

kHz

power-saving mode;

V_DD= 3 V

t_clk(H)

t_clk(L)

clock HIGH time

clock LOW time

1

-

s

ns

s

-

t_{PD(SYNC_N)}SYNC propagation delay

400

-

t_{SYNC_NL}

SYNC LOW time

1

-

t_PD(drv)

driver propagation delay

V_LCD= 5 V

30

Timing characteristics: I²C-bus (see Figure 28)^[2]

t_BUF

bus free time between a STOP and START

condition

4.7

-

s

t_HD;STA

t_SU;STA

t_LOW

t_HIGH

t_r

hold time (repeated) START condition

set-up time for a repeated START condition

LOW period of the SCL clock

HIGH period of the SCL clock

rise time of both SDA and SCL signals

fall time of both SDA and SCL signals

capacitive load for each bus line

data set-up time

4.0

4.7

4.0

-

s

pF

ns

s

-

1

t_f

-

0.3

C_b

-

400

t_SU;DAT

t_HD;DAT

t_SU;STO

250

0

-

data hold time

set-up time for STOP condition

4.0

[1] f_clk 125 kHz, I²C-bus maximum transmission speed is derated.

[2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

PCA8576C

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PCA8576C

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PCA8576C

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13. Application information

13.1 Cascaded operation

In large display configurations, up to 16 PCA8576Cs can be recognized on the same

I²C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable

I²C-bus slave address (SA0).

Table 18. Addressing cascaded PCA8576C

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2

1

8

9

10

11

12

13

14

15

Cascaded PCA8576Cs are synchronized. They can share the backplane signals from one

of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCA8576C of the cascade contribute

additional segment outputs. The backplanes can either be connected together to enhance

the drive capability, some can be left open-circuit (as shown in Figure 29) or just some of

one and some of the other device can be taken to facilitate the layout of the display.

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PCA8576C

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9

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Fig 29. Cascaded PCA8576C configuration

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCA8576Cs. This synchronization is guaranteed after the power-on reset. The only time

that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments; or by the defining a multiplex mode when PCA8576Cs

with differing SA0 levels are cascaded).

SYNC is organized as an input/output pin; the output selection being realized as an

open-drain driver with an internal pull-up resistor. A PCA8576C asserts the SYNC line and

monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is

restored by the first PCA8576C to assert SYNC. The timing relationship between the

backplane waveforms and the SYNC signal for the various drive modes of the PCA8576C

are shown in Figure 30.

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PCA8576C

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Automotive LCD driver for low multiplex rates

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Excessive capacitive coupling between SCL or CLK and SYNC will cause erroneous

synchronization. If this is a problem you can increase the capacitance of the SYNC line (e.g. by an

external capacitor between SYNC and V_DD.) Degradation of the positive edge of the SYNC pulse

can be countered by an external pull-up resistor.

Fig 30. Synchronization of the cascade for the various PCA8576C drive modes

14. Test information

14.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated

circuits, and is suitable for use in automotive applications.

PCA8576C

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 8 April 2015

39 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

15. Package outline

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Fig 31. Package outline SOT314-2 (LQFP64) of PCA8576CH

PCA8576C

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 8 April 2015

40 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

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PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

41 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

42 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

17.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 33) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 19 and 20

Table 19. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 20. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 33.

PCA8576C

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Product data sheet

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PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 33. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

44 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

19. Abbreviations

Table 22. Abbreviations

Acronym

AEC

CDM

DC

Description

Automotive Electronics Council

Charged-Device Model

Direct Current

HBM

I²C

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

LCD

LSB

MM

Liquid Crystal Display

Least Significant Bit

Machine Model

MOS

MSB

MSL

PCB

POR

RC

Metal-Oxide Semiconductor

Most Significant Bit

Moisture Sensitivity Level

Printed-Circuit Board

Power-On Reset

Resistance-Capacitance

Random Access Memory

Root Mean Square

RAM

RMS

SCL

SDA

SMD

Serial CLock line

Serial DAta line

Surface-Mount Device

20. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN11267 — EMC and system level ESD design guidelines for LCD drivers

[3] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[5] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[7] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[8] JESD78 — IC Latch-Up Test

[9] UM10204 — I²C-bus specification and user manual

[10] UM10569 — Store and transport requirements

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

47 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

21. Revision history

Table 23. Revision history

Document ID

PCA8576C v.3

Modifications:

Release date

20150408

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCA8576C v.2

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Fixed typo

PCA8576C v.2

PCA8576C v.1

20131216

Product data sheet

-

PCA8576C v.1

20100722

Product data sheet

-

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

48 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

22.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

22.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

PCA8576C

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 8 April 2015

49 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

23. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCA8576C

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Product data sheet

Rev. 3 — 8 April 2015

50 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

24. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 5. Selection of possible display configurations . . . .7

Table 6. Biasing characteristics . . . . . . . . . . . . . . . . . . . .9

Table 7. LCD frame frequencies ^[1]. . . . . . . . . . . . . . . .17

Table 8. Blink frequencies . . . . . . . . . . . . . . . . . . . . . . .22

Table 9. Definition of PCA8576C commands . . . . . . . . .26

Table 10. Mode-set command bit description . . . . . . . . .26

Table 11. Load-data-pointer command bit description . . .27

Table 12. Device-select command bit description . . . . . .27

Table 13. Bank-select command bit description . . . . . . .27

Table 14. Blink-select command bit description . . . . . . . .28

Table 15. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 16. Static characteristics . . . . . . . . . . . . . . . . . . . .31

Table 17. Dynamic characteristics . . . . . . . . . . . . . . . . . .35

Table 18. Addressing cascaded PCA8576C . . . . . . . . . .37

Table 19. SnPb eutectic process (from J-STD-020D) . . .43

Table 20. Lead-free process (from J-STD-020D) . . . . . .43

Table 21. Selection of LCD segment drivers . . . . . . . . . .45

Table 22. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 23. Revision history . . . . . . . . . . . . . . . . . . . . . . . .48

PCA8576C

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 8 April 2015

51 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

25. Figures

Fig 1. Block diagram of PCA8576C. . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration for LQFP64

(PCA8576CH/Q900/1) . . . . . . . . . . . . . . . . . . . . . .4

Fig 3. Pin configuration for VSO56

(PCA8576CT/Q900/1) . . . . . . . . . . . . . . . . . . . . . .5

Fig 4. Example of displays suitable for PCA8576C . . . . .7

Fig 5. Typical system configuration . . . . . . . . . . . . . . . . .8

Fig 6. Electro-optical characteristic: relative transmission

curve of the liquid. . . . . . . . . . . . . . . . . . . . . . . . .11

Fig 7. Static drive mode waveforms. . . . . . . . . . . . . . . .12

Fig 8. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₂bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Fig 9. Waveforms for the 1:2 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 10. Waveforms for the 1:3 multiplex drive mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Fig 11. Waveforms for the 1:4 multiplex mode

with ¹⁄₃bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Fig 12. Display RAM bit map . . . . . . . . . . . . . . . . . . . . . .19

Fig 13. Relationship between LCD layout, drive mode,

display RAM filling order, and display data

transmitted over the I²C-bus . . . . . . . . . . . . . . . .20

Fig 14. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 15. Definition of START and STOP conditions. . . . . .23

Fig 16. System configuration . . . . . . . . . . . . . . . . . . . . . .23

Fig 17. Acknowledgement of the I²C-bus . . . . . . . . . . . .24

Fig 18. I²C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .25

Fig 19. General format of the command byte . . . . . . . . .26

Fig 20. Device protection diagram. . . . . . . . . . . . . . . . . .29

Fig 21. I_SSas a function of f_fr. . . . . . . . . . . . . . . . . . . . . .32

Fig 22. -I_DD(LCD)as a function of f_fr. . . . . . . . . . . . . . . . . .32

Fig 23. I_SSas a function of V_DD. . . . . . . . . . . . . . . . . . . .33

Fig 24. -I_DD(LCD)as a function of V_DD. . . . . . . . . . . . . . . .33

Fig 25. R_O(max)as a function of V_DD. . . . . . . . . . . . . . . . .34

Fig 26. R_O(max)as a function of T_amb. . . . . . . . . . . . . . . .34

Fig 27. Driver timing waveforms . . . . . . . . . . . . . . . . . . .36

Fig 28. I²C-bus timing waveforms . . . . . . . . . . . . . . . . . .36

Fig 29. Cascaded PCA8576C configuration . . . . . . . . . .38

Fig 30. Synchronization of the cascade for the various

PCA8576C drive modes . . . . . . . . . . . . . . . . . . .39

Fig 31. Package outline SOT314-2 (LQFP64) of

PCA8576CH . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Fig 32. Package outline SOT190-1 (VSO56) of

PCA8576CT/1 . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 33. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

PCA8576C

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 8 April 2015

52 of 53

PCA8576C

NXP Semiconductors

Automotive LCD driver for low multiplex rates

26. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

7.18.5

7.19

Blink-select command . . . . . . . . . . . . . . . . . . 28

Display controller . . . . . . . . . . . . . . . . . . . . . . 28

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

8

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 29

Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 30

3

3.1

4

9

10

11

11.1

11.2

Static characteristics . . . . . . . . . . . . . . . . . . . 31

Typical supply current characteristics . . . . . . 32

Typical LCD output characteristics. . . . . . . . . 34

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

12

Dynamic characteristics. . . . . . . . . . . . . . . . . 35

Application information . . . . . . . . . . . . . . . . . 37

Cascaded operation. . . . . . . . . . . . . . . . . . . . 37

Test information . . . . . . . . . . . . . . . . . . . . . . . 39

Quality information. . . . . . . . . . . . . . . . . . . . . 39

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40

Handling information . . . . . . . . . . . . . . . . . . . 42

13

13.1

14

14.1

15

7

7.1

7.2

7.3

7.3.1

7.4

7.4.1

7.4.2

7.4.3

7.4.4

7.5

7.5.1

7.5.2

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.14.1

7.14.2

7.15

7.16

7.16.1

7.16.2

7.16.3

7.16.4

7.16.5

7.16.6

7.17

7.18

7.18.1

7.18.2

7.18.3

7.18.4

Functional description . . . . . . . . . . . . . . . . . . . 7

Power-On-Reset (POR) . . . . . . . . . . . . . . . . . . 8

LCD bias generator . . . . . . . . . . . . . . . . . . . . . 8

LCD voltage selector . . . . . . . . . . . . . . . . . . . . 9

Electro-optical performance . . . . . . . . . . . . . . 10

LCD drive mode waveforms . . . . . . . . . . . . . . 12

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 12

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 13

1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 15

1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 16

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 17

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 17

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Display register. . . . . . . . . . . . . . . . . . . . . . . . 18

Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 18

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 18

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Sub-address counter . . . . . . . . . . . . . . . . . . . 21

Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 21

Output bank selector . . . . . . . . . . . . . . . . . . . 21

Input bank selector . . . . . . . . . . . . . . . . . . . . . 22

Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Characteristics of the I²C-bus. . . . . . . . . . . . . 22

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

START and STOP conditions . . . . . . . . . . . . . 23

System configuration . . . . . . . . . . . . . . . . . . . 23

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24

PCA8576C I²C-bus controller. . . . . . . . . . . . . 24

Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 25

Command decoder. . . . . . . . . . . . . . . . . . . . . 26

Mode-set command . . . . . . . . . . . . . . . . . . . . 26

Load-data-pointer command. . . . . . . . . . . . . . 27

Device-select command . . . . . . . . . . . . . . . . . 27

Bank-select command . . . . . . . . . . . . . . . . . . 27

16

17

Soldering of SMD packages. . . . . . . . . . . . . . 42

Introduction to soldering. . . . . . . . . . . . . . . . . 42

Wave and reflow soldering. . . . . . . . . . . . . . . 42

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 43

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 43

17.1

17.2

17.3

17.4

18

18.1

19

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

LCD segment driver selection . . . . . . . . . . . . 45

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Revision history . . . . . . . . . . . . . . . . . . . . . . . 48

20

21

22

Legal information . . . . . . . . . . . . . . . . . . . . . . 49

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 49

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 50

22.1

22.2

22.3

22.4

23

24

25

26

Contact information . . . . . . . . . . . . . . . . . . . . 50

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 April 2015

Document identifier: PCA8576C


型号：	PCA8576CH/Q900/1,1
厂家：	NXP
描述：	PCA8576C - Automotive LCD driver for low multiplex rates QFP 64-Pin PC 驱动 CD 接口集成电路
文件：	总53页 (文件大小：468K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA8576CH/Q900/1,1 [NXP]

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