PCA9306GD1 [NXP]
Dual bidirectional I2C-bus and SMBus voltage-level translator; 双路双向I2C总线和SMBus电压电平转换器
| 型号： | PCA9306GD1 |
| 厂家： | 
NXP |
| 描述： | Dual bidirectional I2C-bus and SMBus voltage-level translator |
| 文件： | 总26页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Rev. 05 — 19 March 2010
Product data sheet
1. General description
The PCA9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator with an
enable (EN) input, and is operational from 1.0 V to 3.6 V (Vref(1)) and 1.8 V to 5.5 V
(Vbias(ref)(2)).
The PCA9306 allows bidirectional voltage translations between 1.0 V and 5 V without the
use of a direction pin. The low ON-state resistance (Ron) of the switch allows connections
to be made with minimal propagation delay. When EN is HIGH, the translator switch is on,
and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,
allowing bidirectional data flow between ports. When EN is LOW, the translator switch is
off, and a high-impedance state exists between ports.
The PCA9306 is not a bus buffer like the PCA9509 or PCA9517A that provide both level
translation and physically isolates the capacitance to either side of the bus when both
sides are connected. The PCA9306 only isolates both sides when the device is disabled
and provides voltage level translation when active.
The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency
and the other at 100 kHz operating frequency. If the two buses are operating at different
frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other
bus is required. If the master is running at 400 kHz, the maximum system operating
frequency may be less than 400 kHz because of the delays added by the translator.
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector
configuration of the I2C-bus. The size of these pull-up resistors depends on the system,
but each side of the translator must have a pull-up resistor. The device is designed to work
with Standard-mode, Fast-mode and Fast mode Plus I2C-bus devices in addition to
SMBus devices. The maximum frequency is dependent on the RC time constant, but
generally supports > 2 MHz.
When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the
voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain
pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2
channel.
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features
2-bit bidirectional translator for SDA and SCL lines in mixed-mode I2C-bus applications
Standard-mode, Fast-mode, and Fast-mode Plus I2C-bus and SMBus compatible
Less than 1.5 ns maximum propagation delay to accommodate Standard mode and
Fast mode I2C-bus devices and multiple masters
Allows voltage level translation between:
1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)
1.2 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)
1.8 V Vref(1) and 3.3 V or 5 V Vbias(ref)(2)
2.5 V Vref(1) and 5 V Vbias(ref)(2)
3.3 V Vref(1) and 5 V Vbias(ref)(2)
Provides bidirectional voltage translation with no direction pin
Low 3.5 Ω ON-state connection between input and output ports provides less signal
distortion
Open-drain I2C-bus I/O ports (SCL1, SDA1, SCL2 and SDA2)
5 V tolerant I2C-bus I/O ports to support mixed-mode signal operation
High-impedance SCL1, SDA1, SCL2 and SDA2 pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Packages offered: SO8, TSSOP8, VSSOP8, XQFN8, XSON8, XSON8U
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
2 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
3. Ordering information
Table 1.
Ordering information
Tamb = −40 °C to +85 °C.
Type number
Topside
mark
Package
Name
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
PCA9306D
PCA9306
306P
SOT96-1
SOT505-1
PCA9306DP
TSSOP8[1] plastic thin shrink small outline package; 8 leads;
body width 3 mm
PCA9306DC
306C
306T
P06
VSSOP8
TSSOP8
VSSOP8
XSON8U
XQFN8
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
SOT505-2
SOT765-1
SOT996-2
SOT902-1
SOT1089
PCA9306DP1[2]
PCA9306DC1[3]
PCA9306GD1[4]
PCA9306GM
PCA9306GF
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
P06
plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
P6X[5]
06
plastic extremely thin quad flat package; no leads;
8 terminals; body 1.6 × 1.6 × 0.5 mm
XSON8
extremely thin small outline package; no leads; 8 terminals;
body 1.35 × 1 × 0.5 mm
[1] Also known as MSOP8.
[2] Same footprint and pinout as the Texas Instruments PCA9306DCT.
[3] Same footprint and pinout as the Texas Instruments PCA9306DCU.
[4] Low cost, thinner, drop-in replacement for VSSOP8 (SOT765-1) package.
[5] ‘X’ will change based on date code.
4. Functional diagram
VREF1
VREF2
7
2
PCA9306
8
6
EN
3
4
SCL1
SDA1
SCL2
SW
5
SDA2
SW
1
GND
002aab844
Fig 1. Logic diagram of PCA9306 (positive logic)
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
3 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
5. Pinning information
5.1 Pinning
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
GND
VREF1
SCL1
EN
GND
VREF1
SCL1
EN
VREF2
SCL2
SDA2
VREF2
SCL2
SDA2
PCA9306DP1
PCA9306DP
SDA1
SDA1
002aab842
002aac373
Fig 2. Pin configuration for TSSOP8
(DP1)
Fig 3. Pin configuration for TSSOP8 (DP)
(MSOP8)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VREF1
SCL1
SDA1
GND
EN
GND
VREF1
SCL1
EN
VREF2
SCL2
SDA2
VREF2
SCL2
SDA2
PCA9306DC
PCA9306DC1
SDA1
002aac374
002aab843
Fig 4. Pin configuration for VSSOP8 (DC) Fig 5. Pin configuration for VSSOP8
(DC1)
terminal 1
index area
GND
1
7
6
5
VREF2
SCL2
PCA9306GM
VREF1
SCL1
2
3
1
2
3
4
8
7
6
5
GND
VREF1
SCL1
EN
SDA2
VREF2
SCL2
SDA2
PCA9306D
002aac375
SDA1
Transparent top view
002aac372
Fig 6. Pin configuration for SO8
Fig 7. Pin configuration for XQFN8
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
4 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
GND
VREF1
SCL1
1
2
8
7
EN
GND
1
2
3
4
8
7
6
5
EN
VREF2
SCL2
SDA2
VREF1
SCL1
VREF2
SCL2
SDA2
PCA9306GF
PCA9306GD1
3
4
6
5
SDA1
SDA1
002aae014
002aaf393
Transparent top view
Transparent top view
Fig 8. Pin configuration for XSON8U
(GD1)
Fig 9. Pin configuration for XSON8
5.2 Pin description
Table 2.
Symbol Pin
SO8,
Pin description
Description
VSSOP8 (DC)
TSSOP8 (MSOP8),
TSSOP8,
VSSOP8 (DC1),
XQFN8, XSON8,
XSON8U (GD1)
GND
1
2
4
1
ground (0 V)
VREF1
low-voltage side reference supply voltage for
SCL1 and SDA1
SCL1
SDA1
SDA2
SCL2
VREF2
EN
3
4
5
6
7
8
2
3
5
6
7
8
serial clock, low-voltage side; connect to
VREF1 through a pull-up resistor
serial data, low-voltage side; connect to VREF1
through a pull-up resistor
serial data, high-voltage side; connect to
VREF2 through a pull-up resistor
serial clock, high-voltage side; connect to
VREF2 through a pull-up resistor
high-voltage side reference supply voltage for
SCL2 and SDA2
switch enable input; connect to VREF2 and
pull-up through a high resistor
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
5 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
6. Functional description
Refer to Figure 1 “Logic diagram of PCA9306 (positive logic)”.
6.1 Function table
Table 3.
Function selection (example)
H = HIGH level; L = LOW level.
Input EN[1]
Function
H
L
SCL1 = SCL2; SDA1 = SDA2
disconnect
[1] EN is controlled by the Vbias(ref)(2) logic levels and should be at least 1 V higher than Vref(1) for best
translator operation.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Over operating free-air temperature range.
Symbol
Parameter
Conditions
Min
−0.5
−0.5
−0.5[1]
−0.5[1]
-
Max
+6
Unit
V
Vref(1)
reference voltage (1)
Vbias(ref)(2) reference bias voltage (2)
+6
V
VI
input voltage
+6
V
VI/O
Ich
voltage on an input/output pin
channel current (DC)
input clamping current
storage temperature
+6
V
128
−50
+150
mA
mA
°C
IIK
VI < 0 V
-
Tstg
−65
[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp
current ratings are observed.
8. Recommended operating conditions
Table 5.
Symbol
Operating conditions
Parameter
Conditions
Min
Max
Unit
VI/O
voltage on an input/output pin SCL1, SDA1,
SCL2, SDA2
0
5
V
[1]
Vref(1)
reference voltage (1)
reference bias voltage (2)
input voltage on pin EN
pass switch current
VREF1
VREF2
0
5
V
[1]
Vbias(ref)(2)
VI(EN)
Isw(pass)
Tamb
0
5
V
0
5
V
-
64
+85
mA
°C
ambient temperature
operating in free-air
−40
[1] Vref(1) ≤ Vbias(ref)(2) − 1 V for best results in level shifting applications.
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
6 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
9. Static characteristics
Table 6.
Static characteristics
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
V
VIK
input clamping voltage
II = −18 mA; VI(EN) = 0 V
VI = 5 V; VI(EN) = 0 V
VI = 3 V or 0 V
-
-
-
-
-
−1.2
IIH
HIGH-level input current
-
5
-
μA
pF
pF
Ci(EN)
Cio(off)
input capacitance on pin EN
off-state input/output capacitance
7.1
4
SCLn, SDAn;
6
VO = 3 V or 0 V; VI(EN) = 0 V
Cio(on)
Ron
on-state input/output capacitance
ON-state resistance[2]
SCLn, SDAn;
-
9.3
12.5
pF
VO = 3 V or 0 V; VI(EN) = 3 V
[3]
SCLn, SDAn;
VI = 0 V; IO = 64 mA
VI(EN) = 4.5 V
VI(EN) = 3 V
-
-
-
-
-
2.4
3.0
3.8
9.0
32
5.0
6.0
8.0
20
Ω
Ω
Ω
Ω
Ω
VI(EN) = 2.3 V
VI(EN) = 1.5 V
VI(EN) = 1.5 V
VI = 2.4 V; IO = 15 mA
VI(EN) = 4.5 V
[4]
80
-
-
4.8
46
7.5
80
Ω
Ω
VI(EN) = 3 V
VI = 1.7 V; IO = 15 mA
VI(EN) = 2.3 V
-
40
80
Ω
[1] All typical values are at Tamb = 25 °C.
[2] Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.
ON-state resistance is determined by the lowest voltage of the two terminals.
[3] Guaranteed by design.
[4] For DC and DC1 (VSSOP8) package only.
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
7 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
10. Dynamic characteristics
Table 7.
Dynamic characteristics (translating down)
Tamb = −40 °C to +85 °C, unless otherwise specified. Values guaranteed by design.
Symbol Parameter Conditions CL = 50 pF
CL = 30 pF
CL = 15 pF
Unit
Min
Max
Min
Max
Min
Max
VI(EN) = 3.3 V; VIH = 3.3 V; VIL = 0 V; VM = 1.15 V (see Figure 10)
tPLH
LOW to HIGH
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
0
0
2.0
2.0
0
0
1.2
1.5
0
0
0.6 ns
0.75 ns
tPHL
HIGH to LOW
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
VI(EN) = 2.5 V; VIH = 2.5 V; VIL = 0 V; VM = 0.75 V (see Figure 10)
tPLH
LOW to HIGH
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
0
0
2.0
2.5
0
0
1.2
1.5
0
0
0.6 ns
0.75 ns
tPHL
HIGH to LOW
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
Table 8.
Dynamic characteristics (translating up)
Tamb = −40 °C to +85 °C, unless otherwise specified. Values guaranteed by design.
Symbol Parameter Conditions CL = 50 pF
Min Max
VI(EN) = 3.3 V; VIH = 2.3 V; VIL = 0 V; VTT = 3.3 V; VM = 1.15 V; RL = 300 Ω (see Figure 10)
CL = 30 pF
CL = 15 pF
Unit
Min
Max
Min
Max
tPLH
LOW to HIGH
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
0
1.75
0
1.0
0
0
0.5 ns
0.8 ns
tPHL
HIGH to LOW
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
0
2.75
0
1.65
VI(EN) = 2.5 V; VIH = 1.5 V; VIL = 0 V; VTT = 2.5 V; VM = 0.75 V; RL = 300 Ω (see Figure 10)
tPLH
LOW to HIGH
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
0
1.75
0
1.0
2.0
0
0
0.5 ns
1.0 ns
tPHL
HIGH to LOW
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
0
3.3
0
V
V
V
V
IH
V
TT
input
V
V
V
V
M
M
M
IL
R
L
S1
S2 (open)
OH
OL
from output under test
output
M
C
L
002aab846
002aab845
a. Load circuit
b. Timing diagram
S1 = translating up; S2 = translating down.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2 ns; tf ≤ 2 ns.
The outputs are measured one at a time, with one transition per measurement.
Fig 10. Load circuit for outputs
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
8 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
11. Application information
(1)
V
pu(D)
= 3.3 V
200 kΩ
PCA9306
(1)
V
ref(1)
= 1.8 V
8 EN
R
R
PU
PU
VREF1
VREF2
2
7
R
R
PU
PU
V
CC
V
CC
SCL1
SDA1
3
4
6
5
SCL2
SDA2
SCL
SW
SW
SCL
2
2
I C-BUS
MASTER
I C-BUS
DEVICE
SDA
SDA
GND
1
GND
GND
002aab847
(1) The applied voltages at Vref(1) and Vpu(D) should be such that Vbias(ref)(2) is at least 1 V higher than
ref(1) for best translator operation.
V
Fig 11. Typical application circuit (switch always enabled)
(1)
V
pu(D)
= 3.3 V
3.3 V enable signal
on
off
200 kΩ
PCA9306
(1)
V
ref(1)
= 1.8 V
8 EN
R
R
PU
PU
VREF1
VREF2
2
7
R
R
PU
PU
V
CC
V
CC
SCL1
SDA1
3
4
6
5
SCL2
SDA2
SCL
SW
SW
SCL
2
2
I C-BUS
MASTER
I C-BUS
DEVICE
SDA
SDA
GND
1
GND
GND
002aab848
(1) In the Enabled mode, the applied enable voltage and the applied voltage at Vref(1) should be such
that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator operation.
Fig 12. Typical application circuit (switch enable control)
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
9 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
11.1 Bidirectional translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled
to HIGH side Vpu(D) through a pull-up resistor (typically 200 kΩ). This allows VREF2 to
regulate the EN input. A filter capacitor on VREF2 is recommended. The I2C-bus master
output can be totem-pole or open-drain (pull-up resistors may be required) and the
I2C-bus device output can be totem-pole or open-drain (pull-up resistors are required to
pull the SCL2 and SDA2 outputs to Vpu(D)). However, if either output is totem-pole, data
must be unidirectional or the outputs must be 3-stateable and be controlled by some
direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If
both outputs are open-drain, no direction control is needed.
The reference supply voltage (Vref(1)) is connected to the processor core power supply
voltage. When VREF2 is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V Vpu(D)
power supply, and Vref(1) is set between 1.0 V and (Vpu(D) − 1 V), the output of each SCL1
and SDA1 has a maximum output voltage equal to VREF1, and the output of each SCL2
and SDA2 has a maximum output voltage equal to Vpu(D)
.
Table 9.
Application operating conditions
Refer to Figure 11.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
V
Vbias(ref)(2) reference bias voltage (2)
Vref(1) + 0.6 2.1
Vref(1) + 0.6 2.1
5
VI(EN)
Vref(1)
Isw(pass)
Iref
input voltage on pin EN
reference voltage (1)
pass switch current
reference current
5
V
0
1.5
14
5
4.4
V
-
-
mA
μA
°C
transistor
-
-
Tamb
ambient temperature
operating in
free-air
−40
-
+85
[1] All typical values are at Tamb = 25 °C.
11.2 Sizing pull-up resistor
The pull-up resistor value needs to limit the current through the pass transistor when it is
in the ON state to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the
current through the pass transistor is higher than 15 mA, the pass voltage also is higher in
the ON state. To set the current through each pass transistor at 15 mA, the pull-up resistor
value is calculated as:
Vpu(D) – 0.35 V
-------------------------------------
0.015 A
RPU
=
(1)
Table 10 summarizes resistor reference voltages and currents at 15 mA, 10 mA, and
3 mA. The resistor values shown in the +10 % column or a larger value should be used to
ensure that the pass voltage of the transistor would be 350 mV or less. The external driver
must be able to sink the total current from the resistors on both sides of the PCA9306
device at 0.175 V, although the 15 mA only applies to current flowing through the
PCA9306 device.
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
10 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
Table 10. Pull-up resistor values
Calculated for VOL = 0.35 V; assumes output driver VOL = 0.175 V at stated current.
Vpu(D)
Pull-up resistor value (Ω)
15 mA
Nominal
10 mA
3 mA
+10 %[1]
341
217
158
106
85
Nominal
465
+10 %[1]
Nominal
1550
983
+10 %[1]
1705
1082
788
5 V
310
197
143
97
512
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
295
325
215
237
717
145
160
483
532
77
115
127
383
422
57
63
85
94
283
312
[1] +10 % to compensate for VCC range and resistor tolerance.
11.2.1 Maximum frequency calculation
The maximum frequency is totally dependent upon the specifics of the application and the
device can operate > 33 MHz. Basically, the PCA9306 behaves like a wire with the
additional characteristics of transistor device physics and should be capable of performing
at higher frequencies if used correctly.
Here are some guidelines to follow that will help maximize the performance of the device:
• Keep trace length to a minimum by placing the PCA9306 close to the processor.
• The trace length should be less than half the time of flight to reduce ringing and
reflections.
• The faster the edge of the signal, the higher the chance for ringing.
• The higher the drive strength (up to 15 mA), the higher the frequency the device can
use.
In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side is being driven by a totem pole type
driver no pull-up resistor is needed on the 3.3 V side. The capacitance and line length of
concern is on the 1.8 V side since it is driven through the ON resistance of the PCA9306.
If the line length on the 1.8 V side is long enough there can be a reflection at the
chip/terminating end of the wire when the transition time is shorter than the time of flight of
the wire because the PCA9306 looks like a high-impedance compared to the wire. If the
wire is not too long and the lumped capacitance is not excessive the signal will only be
slightly degraded by the series resistance added by passing through the PCA9306. If the
lumped capacitance is large the rise time will deteriorate, the fall time is much less
affected and if the rise time is slowed down too much the duty cycle of the clock will be
degraded and at some point the clock will no longer be useful. So the principle design
consideration is to minimize the wire length and the capacitance on the 1.8 V side for the
clock path. A pull-up resistor on the 1.8 V side can also be used to trade a slower fall time
for a faster rise time and can also reduce the overshoot in some cases.
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
11 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
11.2.1.1 Example maximum frequency
Question — We need to make the PLL area of a new line card backwards compatible and
need to need to convert one GTL signal to LVTTL, invert it, and convert it back to GTL.
The signal we want to convert is random in nature but will mostly be around 19 MHz with
very long periods of inactivity where either a HIGH or LOW state will be maintained. The
traces are 1 or 2 inches long with trace capacitance of about 2 pF per inch.
Answer — The frequency of the PCA9306 is limited by the capacitance of the part, the
capacitance of the traces and the pull-up resistors used. The limiting case is probably the
LOW-to-HIGH transition in the GTL to LVTTL direction, and there the use of the lowest
acceptable resistor values will minimize the rise time delay. Assuming 50 pF capacitance
and 220 Ω resistance, the RC time constant is 11 ns (50 pF × 220 Ω). With 19 MHz
corresponding to 50 ns period the PCA9306 will support this application.
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
12 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
12. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT96-1
076E03
MS-012
Fig 13. Package outline SOT96-1 (SO8)
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
13 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
A
(A )
2
A
3
A
1
pin 1 index
θ
L
p
L
1
4
detail X
e
w M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.05
0.95
0.80
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
5.1
4.7
0.7
0.4
0.70
0.35
6°
0°
mm
1.1
0.65
0.25
0.94
0.1
0.1
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-04-09
03-02-18
SOT505-1
Fig 14. Package outline SOT505-1 (TSSOP8)
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
14 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
H
v
M
y
A
E
Z
5
8
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
4.1
3.9
0.47
0.33
0.70
0.35
8°
0°
mm
1.1
0.65
0.25
0.5
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-01-16
SOT505-2
- - -
Fig 15. Package outline SOT505-2 (TSSOP8)
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
15 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
A
1
(A )
3
pin 1 index
θ
L
p
L
detail X
1
4
e
w
M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
L
L
p
Q
UNIT
v
w
y
Z
θ
1
2
3
p
E
max.
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
3.2
3.0
0.40
0.15
0.21
0.19
0.4
0.1
8°
0°
mm
1
0.5
0.12
0.4
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-06-07
SOT765-1
MO-187
Fig 16. Package outline SOT765-1 (VSSOP8)
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
16 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D
B
A
terminal 1
index area
E
A
A
1
detail X
e
L
1
e
C
y
C
1
y
L
M
M
∅ v
∅ w
C A
C
B
4
5
6
7
3
2
metal area
not for soldering
e
1
b
e
1
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
v
w
y
y
1
1
max
0.05 0.25 1.65 1.65
0.00 0.15 1.55 1.55
0.35 0.15
0.25 0.05
mm
0.5
0.55
0.5
0.1
0.05 0.05 0.05
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
MO-255
JEITA
05-11-25
07-11-14
SOT902-1
- - -
- - -
Fig 17. Package outline SOT902-1 (XQFN8)
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
17 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
SOT1089
E
terminal 1
index area
D
A
A
1
detail X
(2)
(4×)
e
b
(2)
(8×)
L
4
5
e
1
1
8
terminal 1
index area
b
1
X
0
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
1
b
b
1
D
E
e
e
1
L
max 0.5 0.04 0.35 0.40 1.40 1.05
0.20
0.30 0.35 1.35 1.00 0.55 0.35 0.15
0.27 0.32 1.30 0.95 0.12
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1089_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
09-04-10
09-10-22
SOT1089
MO-252
Fig 18. Package outline SOT1089 (XSON8)
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
18 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
M
M
v
w
C A
C
B
b
e
L
1
y
1
y
C
1
4
L
2
L
8
5
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
b
D
E
e
e
1
L
L
L
v
w
y
y
1
1
2
max
0.05 0.35
0.00 0.15
2.1
1.9
3.1
2.9
0.5
0.3
0.15
0.05
0.6
0.4
mm
0.5
0.5
1.5
0.1
0.05 0.05
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-12-18
07-12-21
SOT996-2
- - -
Fig 19. Package outline SOT996-2 (XSON8U)
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
19 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
20 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 20) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 11 and 12
Table 11. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 12. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 20.
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
21 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 20. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
14. Abbreviations
Table 13. Abbreviations
Acronym
CDM
ESD
Description
Charged-Device Model
ElectroStatic Discharge
Human Body Model
Inter-Integrated Circuit bus
Input/Output
HBM
I2C-bus
I/O
MM
Machine Model
PRR
Pulse Repetition Rate
Resistor-Capacitor network
System Management Bus
RC
SMBus
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
22 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
15. Revision history
Table 14. Revision history
Document ID
PCA9306_5
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20100319
Product data sheet
-
PCA9306_4
• Section 2 “Features”:
added XSON8 and XSON8U packages to last bullet item
• Table 1 “Ordering information”:
–
–
added “PCA9306GF” package option
–
added “PCA9306GD1” package option
• Section 5.1 “Pinning”: added PCA9306GF and PCA9306GD1 pin configurations.
• Section 12 “Package outline”:
–
added Figure 18 “Package outline SOT1089 (XSON8)”
–
added Figure 19 “Package outline SOT996-2 (XSON8U)”
PCA9306_4
PCA9306_3
PCA9306_2
PCA9306_1
20091026
20080804
20070221
20061020
Product data sheet
Product data sheet
Product data sheet
Product data sheet
-
-
-
-
PCA9306_3
PCA9306_2
PCA9306_1
-
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
23 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
16.3 Disclaimers
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
non-automotive qualified products in automotive equipment or applications.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
24 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9306_5
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 05 — 19 March 2010
25 of 26
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
18. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
6.1
7
Functional description . . . . . . . . . . . . . . . . . . . 6
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
8
9
10
11
Application information. . . . . . . . . . . . . . . . . . . 9
Bidirectional translation . . . . . . . . . . . . . . . . . 10
Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . 10
Maximum frequency calculation . . . . . . . . . . . 11
11.1
11.2
11.2.1
11.2.1.1 Example maximum frequency . . . . . . . . . . . . 12
12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13
Soldering of SMD packages . . . . . . . . . . . . . . 20
Introduction to soldering . . . . . . . . . . . . . . . . . 20
Wave and reflow soldering . . . . . . . . . . . . . . . 20
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 20
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 21
13.1
13.2
13.3
13.4
14
15
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 25
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 March 2010
Document identifier: PCA9306_5
相关型号：
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