PCA9306GM,125 [NXP]
PCA9306 - Dual bidirectional I2C-bus and SMBus voltage-level translator QFN 8-Pin;
| 型号： | PCA9306GM,125 |
| 厂家： | 
NXP |
| 描述： | PCA9306 - Dual bidirectional I2C-bus and SMBus voltage-level translator QFN 8-Pin PC 接口集成电路 |
| 文件： | 总35页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9306
Dual bidirectional I2C-bus and SMBus voltage-level translator
Rev. 8 — 22 January 2014
Product data sheet
1. General description
The PCA9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator with an
enable (EN) input, and is operational from 1.0 V to 3.6 V (Vref(1)) and 1.8 V to 5.5 V
(Vbias(ref)(2)).
The PCA9306 allows bidirectional voltage translations between 1.0 V and 5 V without the
use of a direction pin. The low ON-state resistance (Ron) of the switch allows connections
to be made with minimal propagation delay. When EN is HIGH, the translator switch is on,
and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively,
allowing bidirectional data flow between ports. When EN is LOW, the translator switch is
off, and a high-impedance state exists between ports.
The PCA9306 is not a bus buffer like the PCA9509 or PCA9517A that provide both level
translation and physically isolates the capacitance to either side of the bus when both
sides are connected. The PCA9306 only isolates both sides when the device is disabled
and provides voltage level translation when active.
The PCA9306 can also be used to run two buses, one at 400 kHz operating frequency
and the other at 100 kHz operating frequency. If the two buses are operating at different
frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other
bus is required. If the master is running at 400 kHz, the maximum system operating
frequency may be less than 400 kHz because of the delays added by the translator.
As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the translator’s bus. The PCA9306 has a standard open-collector
configuration of the I2C-bus. The size of these pull-up resistors depends on the system,
but each side of the translator must have a pull-up resistor. The device is designed to work
with Standard-mode, Fast-mode and Fast-mode Plus I2C-bus devices in addition to
SMBus devices. The maximum frequency is dependent on the RC time constant, but
generally supports > 2 MHz.
When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port when the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the
voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain
pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2
channel.
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
2-bit bidirectional translator for SDA and SCL lines in mixed-mode I2C-bus applications
Standard-mode, Fast-mode, and Fast-mode Plus I2C-bus and SMBus compatible
Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and
Fast-mode I2C-bus devices and multiple masters
Allows voltage level translation between:
1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)
1.2 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)
1.8 V Vref(1) and 3.3 V or 5 V Vbias(ref)(2)
2.5 V Vref(1) and 5 V Vbias(ref)(2)
3.3 V Vref(1) and 5 V Vbias(ref)(2)
Provides bidirectional voltage translation with no direction pin
Low 3.5 ON-state connection between input and output ports provides less signal
distortion
Open-drain I2C-bus I/O ports (SCL1, SDA1, SCL2 and SDA2)
5 V tolerant I2C-bus I/O ports to support mixed-mode signal operation
High-impedance SCL1, SDA1, SCL2 and SDA2 pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: SO8, TSSOP8, VSSOP8, XQFN8, XSON8, XSON8U
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
2 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
3. Ordering information
Table 1.
Ordering information
Tamb = 40 C to +85 C.
Type number
Topside
mark
Package
Name
Description
Version
PCA9306D
PCA9306
306C
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
SOT765-1
PCA9306DC
VSSOP8
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
PCA9306DC1[1]
P06
VSSOP8
VSSOP8
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
SOT765-1
SOT505-1
SOT505-2
SOT996-2
PCA9306DC1/DG[2] P06
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
PCA9306DP
306P
306T
P06
TSSOP8[3] plastic thin shrink small outline package; 8 leads;
body width 3 mm
PCA9306DP1[4]
PCA9306GD1[5]
PCA9306GF
TSSOP8
XSON8U
XSON8
XQFN8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 2 0.5 mm
06
extremely thin small outline package; no leads; 8 terminals; SOT1089
body 1.35 1 0.5 mm
PCA9306GM
P6X[6]
plastic extremely thin quad flat package; no leads;
SOT902-2
8 terminals; body 1.6 1.6 0.5 mm
[1] Same footprint and pinout as the Texas Instruments PCA9306DCU.
[2] PCA9306DC1/DG is functionally the same (electrically and mechanically) as the PCA9306DC1 and the Texas Instruments
PCA9306DCT. It is produced in Dark Green (lead-free and halogen/antimony-free) package material, with a unique orderable part
number for customers who desire to order and only receive Dark Green package material.
[3] Also known as MSOP8.
[4] Same footprint and pinout as the Texas Instruments PCA9306DCT.
[5] Low cost, thinner, drop-in replacement for VSSOP8 (SOT765-1) package.
[6] ‘X’ will change based on date code.
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
Package Packing method
Minimum Temperature
part number
order
quantity
PCA9306D
PCA9306D,112
PCA9306D,118
PCA9306DC,125
PCA9306DC1,125
SO8
SO8
Standard marking *
IC’s tube - DSC bulk pack
2000
2500
3000
3000
3000
T
amb = 40 C to +85 C
Tamb = 40 C to +85 C
Tamb = 40 C to +85 C
Reel 13” Q1/T1
*standard mark SMD
PCA9306DC
PCA9306DC1
VSSOP8 Reel 7” Q3/T4
*standard mark
VSSOP8 Reel 7” Q3/T4
*standard mark
Tamb = 40 C to +85 C
Tamb = 40 C to +85 C
PCA9306DC1/DG PCA9306DC1/DG,125 VSSOP8 Reel 7” Q3/T4
*standard mark
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
3 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
Table 2.
Ordering options …continued
Type number
Orderable
Package Packing method
Minimum Temperature
part number
order
quantity
PCA9306DP
PCA9306DP1
PCA9306GD1
PCA9306GF
PCA9306GM
PCA9306DP,118
PCA9306DP1,125
PCA9306GD1,125
PCA9306GF,115
PCA9306GM,125
TSSOP8 Reel 13” Q1/T1
*standard mark SMD
2500
3000
3000
5000
4000
Tamb = 40 C to +85 C
Tamb = 40 C to +85 C
Tamb = 40 C to +85 C
TSSOP8 Reel 7” Q3/T4
*standard mark
XSON8U Reel 7” Q3/T4
*standard mark
XSON8
Reel 7” Q1/T1
Tamb = 40 C to +85 C
Tamb = 40 C to +85 C
*standard mark SMD
XQFN8
Reel 7” Q3/T4
*standard mark
4. Functional diagram
VREF1
2
VREF2
7
PCA9306
8
6
EN
3
4
SCL1
SDA1
SCL2
SW
5
SDA2
SW
1
GND
002aab844
Fig 1. Logic diagram of PCA9306 (positive logic)
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
4 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
5. Pinning information
5.1 Pinning
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
GND
VREF1
SCL1
EN
GND
VREF1
SCL1
EN
VREF2
SCL2
SDA2
VREF2
SCL2
SDA2
PCA9306DP1
PCA9306DP
SDA1
SDA1
002aab842
002aac373
Fig 2. Pin configuration for TSSOP8
(DP1)
Fig 3. Pin configuration for TSSOP8 (DP)
(MSOP8)
PCA9306DC1
PCA9306DC1/DG
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VREF1
SCL1
SDA1
GND
EN
GND
VREF1
SCL1
EN
VREF2
SCL2
SDA2
VREF2
SCL2
SDA2
PCA9306DC
SDA1
002aac374
002aab843
Fig 4. Pin configuration for VSSOP8 (DC) Fig 5. Pin configuration for VSSOP8
(DC1; DC1/DG)
terminal 1
index area
GND
1
7
6
5
VREF2
SCL2
PCA9306GM
VREF1
SCL1
2
3
1
2
3
4
8
7
6
5
GND
VREF1
SCL1
EN
SDA2
VREF2
SCL2
SDA2
PCA9306D
002aac375
SDA1
Transparent top view
002aac372
Fig 6. Pin configuration for SO8
Fig 7. Pin configuration for XQFN8
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
5 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
GND
VREF1
SCL1
1
2
8
7
EN
GND
1
2
3
4
8
7
6
5
EN
VREF2
SCL2
SDA2
VREF1
SCL1
VREF2
SCL2
SDA2
PCA9306GF
PCA9306GD1
3
4
6
5
SDA1
SDA1
002aae014
002aaf393
Transparent top view
Transparent top view
Fig 8. Pin configuration for XSON8U
(GD1)
Fig 9. Pin configuration for XSON8
5.2 Pin description
Table 3.
Symbol Pin
SO8,
Pin description
Description
VSSOP8 (DC)
TSSOP8 (MSOP8),
TSSOP8,
VSSOP8 (DC1),
XQFN8, XSON8,
XSON8U (GD1)
GND
1
2
4
1
ground (0 V)
VREF1
low-voltage side reference supply voltage for
SCL1 and SDA1
SCL1
SDA1
SDA2
SCL2
VREF2
EN
3
4
5
6
7
8
2
3
5
6
7
8
serial clock, low-voltage side; connect to
VREF1 through a pull-up resistor
serial data, low-voltage side; connect to VREF1
through a pull-up resistor
serial data, high-voltage side; connect to
VREF2 through a pull-up resistor
serial clock, high-voltage side; connect to
VREF2 through a pull-up resistor
high-voltage side reference supply voltage for
SCL2 and SDA2
switch enable input; connect to VREF2 and
pull-up through a high resistor
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
6 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
6. Functional description
Refer to Figure 1 “Logic diagram of PCA9306 (positive logic)”.
6.1 Function table
Table 4.
Function selection (example)
H = HIGH level; L = LOW level.
Input EN[1]
Function
H
L
SCL1 = SCL2; SDA1 = SDA2
disconnect
[1] EN is controlled by the Vbias(ref)(2) logic levels and should be at least 1 V higher than Vref(1) for best
translator operation.
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Over operating free-air temperature range.
Symbol
Parameter
Conditions
Min
0.5
0.5
0.5[1]
0.5[1]
-
Max
+6
Unit
V
Vref(1)
reference voltage (1)
Vbias(ref)(2) reference bias voltage (2)
+6
V
VI
input voltage
+6
V
VI/O
Ich
voltage on an input/output pin
channel current (DC)
input clamping current
storage temperature
+6
V
128
50
+150
mA
mA
C
IIK
VI < 0 V
-
Tstg
65
[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp
current ratings are observed.
8. Recommended operating conditions
Table 6.
Symbol
Operating conditions
Parameter
Conditions
Min
Max
Unit
VI/O
voltage on an input/output pin SCL1, SDA1,
SCL2, SDA2
0
5
V
[1]
Vref(1)
reference voltage (1)
reference bias voltage (2)
input voltage on pin EN
pass switch current
VREF1
VREF2
0
5
V
[1]
Vbias(ref)(2)
VI(EN)
Isw(pass)
Tamb
0
5
V
0
5
V
-
64
+85
mA
C
ambient temperature
operating in free-air
40
[1] Vref(1) Vbias(ref)(2) 1 V for best results in level shifting applications.
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
7 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
9. Static characteristics
Table 7.
Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
V
VIK
input clamping voltage
II = 18 mA; VI(EN) = 0 V
VI = 5 V; VI(EN) = 0 V
VI = 3 V or 0 V
-
-
-
-
-
1.2
IIH
HIGH-level input current
-
5
-
A
pF
pF
Ci(EN)
Cio(off)
input capacitance on pin EN
off-state input/output capacitance
7.1
4
SCLn, SDAn;
6
VO = 3 V or 0 V; VI(EN) = 0 V
Cio(on)
Ron
on-state input/output capacitance
ON-state resistance[2]
SCLn, SDAn;
-
9.3
12.5
pF
VO = 3 V or 0 V; VI(EN) = 3 V
[3]
SCLn, SDAn;
VI = 0 V; IO = 64 mA
VI(EN) = 4.5 V
VI(EN) = 3 V
-
-
-
-
-
2.4
3.0
3.8
15
5.0
6.0
8.0
32
VI(EN) = 2.3 V
VI(EN) = 1.5 V
VI(EN) = 1.5 V
VI = 2.4 V; IO = 15 mA
VI(EN) = 4.5 V
[4]
32
80
-
-
4.8
46
7.5
80
V
I(EN) = 3 V
VI = 1.7 V; IO = 15 mA
VI(EN) = 2.3 V
-
40
80
[1] All typical values are at Tamb = 25 C.
[2] Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.
ON-state resistance is determined by the lowest voltage of the two terminals.
[3] Guaranteed by design.
[4] For DC, DC1 (VSSOP8) and GD1 (XSON8U) packages only.
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
8 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
10. Dynamic characteristics
Table 8.
Dynamic characteristics (translating down)
Tamb = 40 C to +85 C, unless otherwise specified. Values guaranteed by design.
Symbol Parameter Conditions CL = 50 pF
CL = 30 pF
CL = 15 pF
Unit
Min
Max
Min
Max
Min
Max
VI(EN) = 3.3 V; VIH = 3.3 V; VIL = 0 V; VM = 1.15 V (see Figure 10)
tPLH
LOW to HIGH
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
0
0
2.0
2.0
0
0
1.2
1.5
0
0
0.6 ns
0.75 ns
tPHL
HIGH to LOW
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
VI(EN) = 2.5 V; VIH = 2.5 V; VIL = 0 V; VM = 0.75 V (see Figure 10)
tPLH
LOW to HIGH
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
0
0
2.0
2.5
0
0
1.2
1.5
0
0
0.6 ns
0.75 ns
tPHL
HIGH to LOW
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
Table 9.
Dynamic characteristics (translating up)
Tamb = 40 C to +85 C, unless otherwise specified. Values guaranteed by design.
Symbol Parameter Conditions CL = 50 pF
Min Max
VI(EN) = 3.3 V; VIH = 2.3 V; VIL = 0 V; VTT = 3.3 V; VM = 1.15 V; RL = 300 (see Figure 10)
CL = 30 pF
CL = 15 pF
Unit
Min
Max
Min
Max
tPLH
LOW to HIGH
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
0
1.75
0
1.0
0
0
0.5 ns
0.8 ns
tPHL
HIGH to LOW
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
0
2.75
0
1.65
VI(EN) = 2.5 V; VIH = 1.5 V; VIL = 0 V; VTT = 2.5 V; VM = 0.75 V; RL = 300 (see Figure 10)
tPLH
LOW to HIGH
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
0
1.75
0
1.0
2.0
0
0
0.5 ns
1.0 ns
tPHL
HIGH to LOW
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
0
3.3
0
V
V
V
V
IH
V
TT
input
V
V
V
V
M
M
M
IL
R
L
S1
S2 (open)
OH
OL
from output under test
output
M
C
L
002aab846
002aab845
a. Load circuit
b. Timing diagram
S1 = translating up; S2 = translating down.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr 2 ns; tf 2 ns.
The outputs are measured one at a time, with one transition per measurement.
Fig 10. Load circuit for outputs
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
9 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
11. Application information
(1)
V
= 3.3 V
pu(D)
200 kΩ
PCA9306
(1)
V
= 1.8 V
8
7
EN
ref(1)
R
PU
R
PU
VREF1
VREF2
2
R
PU
R
PU
V
V
CC
CC
SCL1
SDA1
3
4
6
5
SCL2
SDA2
SCL
SW
SW
SCL
2
2
I C-BUS
MASTER
I C-BUS
DEVICE
SDA
SDA
GND
1
GND
GND
002aab847
(1) The applied voltages at Vref(1) and Vpu(D) should be such that Vbias(ref)(2) is at least 1 V higher than
Vref(1) for best translator operation.
Fig 11. Typical application circuit (switch always enabled)
(1)
V
= 3.3 V
pu(D)
3.3 V enable signal
on
off
200 kΩ
PCA9306
(1)
V
= 1.8 V
8
7
EN
ref(1)
R
PU
R
PU
VREF1
VREF2
2
R
PU
R
PU
V
V
CC
CC
SCL1
SDA1
3
4
6
5
SCL2
SDA2
SCL
SW
SW
SCL
2
2
I C-BUS
MASTER
I C-BUS
DEVICE
SDA
SDA
GND
1
GND
GND
002aab848
(1) In the Enabled mode, the applied enable voltage and the applied voltage at Vref(1) should be such
that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator operation.
Fig 12. Typical application circuit (switch enable control)
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
10 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
11.1 Bidirectional translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled
to HIGH side Vpu(D) through a pull-up resistor (typically 200 k). This allows VREF2 to
regulate the EN input. A filter capacitor on VREF2 is recommended. The I2C-bus master
output can be totem pole or open-drain (pull-up resistors may be required) and the
I2C-bus device output can be totem pole or open-drain (pull-up resistors are required to
pull the SCL2 and SDA2 outputs to Vpu(D)). However, if either output is totem pole, data
must be unidirectional or the outputs must be 3-stateable and be controlled by some
direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If
both outputs are open-drain, no direction control is needed.
The reference supply voltage (Vref(1)) is connected to the processor core power supply
voltage. When VREF2 is connected through a 200 k resistor to a 3.3 V to 5.5 V Vpu(D)
power supply, and Vref(1) is set between 1.0 V and (Vpu(D) 1 V), the output of each SCL1
and SDA1 has a maximum output voltage equal to VREF1, and the output of each SCL2
and SDA2 has a maximum output voltage equal to Vpu(D)
.
Table 10. Application operating conditions
Refer to Figure 11.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
V
Vbias(ref)(2) reference bias voltage (2)
Vref(1) + 0.6 2.1
Vref(1) + 0.6 2.1
5
VI(EN)
Vref(1)
Isw(pass)
Iref
input voltage on pin EN
reference voltage (1)
pass switch current
reference current
5
V
0
1.5
14
5
4.4
V
-
-
mA
A
C
transistor
-
-
Tamb
ambient temperature
operating in
free-air
40
-
+85
[1] All typical values are at Tamb = 25 C.
11.2 How to size pull-up resistor value
Sizing the pull-up resistor on an open-drain bus is specific to the individual application and
is dependent on the following driver characteristics:
• The driver sink current
• The VOL of driver
• The VIL of the driver
• Frequency of operation
The following tables can be used to estimate the pull-up resistor value in different use
cases so that the minimum resistance for the pull-up resistor can be found.
Table 11, Table 12 and Table 13 contain suggested minimum values of pull-up resistors for
the PCA9306 and NVT20xx devices with typical voltage translation levels and drive
currents. The calculated values assume that both drive currents are the same.
V
OL = VIL = 0.1 VCC and accounts for a 5 % VCC tolerance of the supplies, 1 %
resistor values. It should be noted that the resistor chosen in the final application should
be equal to or larger than the values shown in Table 11, Table 12 and Table 13 to ensure
that the pass voltage is less than 10 % of the VCC voltage, and the external driver should
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
11 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
be able to sink the total current from both pull-up resistors. When selecting the minimum
resistor value in Table 11, Table 12 or Table 13, the drive current strength that should be
chosen should be the lowest drive current seen in the application and account for any
drive strength current scaling with output voltage. For the GTL devices, the resistance
table should be recalculated to account for the difference in ON resistance and bias
voltage limitations between VCC(B) and VCC(A)
.
Table 11. Pull-up resistor minimum values, 3 mA driver sink current for PCA9306 and NVT20xx
A-side
1.0 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
B-side
1.2 V
1.5 V
1.8 V
pu(A) = 976
2.5 V
3.3 V
5.0 V
Rpu(A) = 750
Rpu(B) = 750
R
pu(A) = 845
R
R
pu(A) = none
R
pu(A) = none
R
pu(A) = none
Rpu(B) = 845
Rpu(A) = 931
Rpu(B) = 976
Rpu(B) = 887
Rpu(B) = 1.18 k Rpu(B) = 1.82 k
Rpu(A) = none Rpu(A) = none
Rpu(A) = 1.02 k
Rpu(A) = none
R
pu(B) = 931
R
pu(B) = 1.02 k
Rpu(A) = 1.1 k
pu(B) = 1.1 k
R
pu(B) = 887
R
pu(B) = 1.18 k
R
pu(B) = 1.82 k
Rpu(A) = none
Rpu(A) = none
Rpu(A) = none
R
Rpu(B) = 866
R
pu(B) = 1.18 k
R
pu(B) = 1.78 k
Rpu(A) = 1.47 k
Rpu(A) = none
Rpu(A) = none
Rpu(B) = 1.47 k Rpu(B) = 1.15 k Rpu(B) = 1.78 k
Rpu(A) = 1.96 k Rpu(A) = none
pu(B) = 1.96 k
R
R
pu(B) = 1.78 k
Rpu(A) = none
Rpu(B) = 1.74 k
Table 12. Pull-up resistor minimum values, 10 mA driver sink current for PCA9306 and NVT20xx
A-side
1.0 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
B-side
1.2 V
1.5 V
1.8 V
Rpu(A) = 287
pu(B) = 287
Rpu(A) = 309
pu(B) = 309
Rpu(A) = 332
pu(B) = 332
2.5 V
3.3 V
5.0 V
Rpu(A) = 221
Rpu(A) = 255
Rpu(A) = none
Rpu(A) = none
Rpu(A) = none
R
pu(B) = 221
R
pu(B) = 255
Rpu(A) = 274
pu(B) = 274
R
Rpu(B) = 267
R
pu(B) = 357
R
pu(B) = 549
Rpu(A) = none
Rpu(A) = none
Rpu(A) = none
R
R
Rpu(B) = 267
R
pu(B) = 357
R
pu(B) = 549
Rpu(A) = none
Rpu(A) = none
Rpu(A) = none
R
Rpu(B) = 261
R
pu(B) = 348
R
pu(B) = 536
Rpu(A) = 442
Rpu(A) = none
Rpu(A) = none
Rpu(B) = 442
R
pu(B) = 348
R
pu(B) = 536
Rpu(A) = 590
Rpu(A) = none
R
pu(B) = 590
R
pu(B) = 523
Rpu(A) = none
Rpu(B) = 523
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
12 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
Table 13. Pull-up resistor minimum values, 15 mA driver sink current for PCA9306 and NVT20xx
A-side
1.0 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
B-side
1.2 V
1.5 V
1.8 V
Rpu(A) = 191
pu(B) = 191
Rpu(A) = 205
pu(B) = 205
2.5 V
3.3 V
5.0 V
Rpu(A) = 147
Rpu(A) = 169
Rpu(A) = none
Rpu(A) = none
Rpu(A) = none
R
pu(B) = 147
R
pu(B) = 169
Rpu(A) = 182
pu(B) = 182
R
Rpu(B) = 178
R
pu(B) = 237
R
pu(B) = 365
Rpu(A) = none
Rpu(A) = none
Rpu(A) = none
R
R
R
pu(B) = 178
Rpu(A) = none
Rpu(B) = 174
Rpu(A) = 294
R
pu(B) = 237
Rpu(A) = none
Rpu(B) = 232
Rpu(A) = none
R
pu(B) = 365
Rpu(A) = none
Rpu(B) = 357
Rpu(A) = none
Rpu(A) = 221
Rpu(B) = 221
Rpu(B) = 294
R
pu(B) = 232
Rpu(A) = 392
pu(B) = 392
R
pu(B) = 357
Rpu(A) = none
R
R
pu(B) = 357
Rpu(A) = none
Rpu(B) = 348
11.3 How to design for maximum frequency operation
The maximum frequency is limited by the minimum pulse width LOW and HIGH as well as
rise time and fall time. See Equation 1 as an example of the maximum frequency. The rise
and fall times are shown in Figure 13.
1
------------------------------------------------------------------------------------------------------------
fmax
=
(1)
t
LOWmin + tHIGHmin + tractual + tfactual
t
t
f(actual)
r(actual)
t
HIGH(min)
V
CC
V
0.9 × V
0.1 × V
IH
CC
t
LOW(min)
V
IL
CC
V
OL
1 / f
max
GND
002aag912
Fig 13. An example waveform for maximum frequency
The rise and fall times are dependent upon translation voltages, the drive strength, the
total node capacitance (CL(tot)) and the pull-up resistors (RPU) that are present on the bus.
The node capacitance is the addition of the PCB trace capacitance and the device
capacitance that exists on the bus. Because of the dependency of the external
components, PCB layout and the different device operating states the calculation of rise
and fall times is complex and has several inflection points along the curve.
The main component of the rise and fall times is the RC time constant of the bus line when
the device is in its two primary operating states: when device is in the ON state and it is
low-impedance, the other is when the device is OFF isolating the A-side from the B-side.
A description of the fall time applied to either An or Bn output going from HIGH to LOW is
as follows. Whichever side is asserted first, the B-side down must discharge to the VCC(A)
voltage. The time is determined by the pull-up resistor, pull-down driver strength and the
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
13 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
capacitance. As the level moves below the VCC(A) voltage, the channel resistance drops
so that both A and B sides equal. The capacitance on both sides is connected to form the
total capacitance and the pull-up resistors on both sides combine to the parallel equivalent
resistance. The Ron of the device is small compared to the pull-up resistor values, so its
effect on the pull-up resistance can be neglected and the fall is determined by the driver
pulling the combined capacitance and pull-up resistor currents. An estimation of the actual
fall time seen by the device is equal to the time it takes for the B-side to fall to the VCC(A)
voltage and the time it takes for both sides to fall from the VCC(A) voltage to the VIL level.
A description of the rise time applied to either An or Bn output going from LOW to HIGH is
as follows. When the signal level is LOW, the Ron is at its minimum, so the A and B sides
are essentially one node. They will rise together with an RC time constant that is the sum
of all the capacitance from both sides and the parallel of the resistance from both sides.
As the signal approaches the VCC(A) voltage, the channel resistance goes up and the
waveforms separate, with the B side finishing its rise with the RC time constant of the
B side. The rise to VCC(A) is essentially the same for both sides.
There are some basic guidelines to follow that will help maximize the performance of the
device:
• Keep trace length to a minimum by placing the NVT device close to the processor.
• The signal round trip time on trace should be shorter than the rise or fall time of signal
to reduce reflections.
• The faster the edge of the signal, the higher the chance for ringing.
• The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher
the frequency the device can use.
The system designer must design the pull-up resistor value based on external current
drive strength and limit the node capacitance (minimize the wire, stub, connector and
trace length) to get the desired operation frequency result.
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
14 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
15 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
16 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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PCA9306
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
17 of 35
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NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
18 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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PCA9306
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
19 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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Fig 19. Package outline SOT1089 (XSON8)
PCA9306
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
20 of 35
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NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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Fig 20. Package outline SOT996-2 (XSON8U)
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Product data sheet
Rev. 8 — 22 January 2014
21 of 35
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NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
22 of 35
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NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
13.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 21) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Table 14. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 15. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 21.
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
23 of 35
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NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 21. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
24 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
14. Soldering: PCB footprints
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PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
25 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
26 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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Fig 25. PCB footprint for SOT505-2 (TSSOP8); reflow soldering
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
27 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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Fig 26. PCB footprint for SOT765-1 (VSSOP8); reflow soldering
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
28 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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Fig 27. PCB footprint for SOT1089 (XSON8); reflow soldering
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
29 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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Fig 28. PCB footprint for SOT996-2 (XSON8U); reflow soldering
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
30 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
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Fig 29. PCB footprint for SOT902-2 (XQFN8); reflow soldering
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
31 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
15. Abbreviations
Table 16. Abbreviations
Acronym
CDM
ESD
Description
Charged-Device Model
ElectroStatic Discharge
Gunning Transceiver Logic
Human Body Model
GTL
HBM
I2C-bus
I/O
Inter-Integrated Circuit bus
Input/Output
LVTTL
PLL
Low Voltage Transistor-Transistor Logic
Phase-Locked Loop
PRR
Pulse Repetition Rate
RC
Resistor-Capacitor network
System Management Bus
SMBus
16. Revision history
Table 17. Revision history
Document ID
PCA9306 v.8
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20140122
Product data sheet
-
PCA9306 v.7
• deleted (old) Section 11.2, “Sizing pull-up resistor”
• added (new) Section 11.2 “How to size pull-up resistor value”
• added (new) Section 11.3 “How to design for maximum frequency operation”
PCA9306 v.7
PCA9306 v.6
PCA9306 v.5
PCA9306 v.4
PCA9306 v.3
PCA9306 v.2
PCA9306 v.1
20130517
20101125
20100319
20091026
20080804
20070221
20061020
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
-
-
-
-
-
-
-
PCA9306 v.6
PCA9306 v.5
PCA9306 v.4
PCA9306 v.3
PCA9306 v.2
PCA9306 v.1
-
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
32 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
17.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
33 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 22 January 2014
34 of 35
PCA9306
NXP Semiconductors
Dual bidirectional I2C-bus and SMBus voltage-level translator
19. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
2
3
3.1
4
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
6.1
7
Functional description . . . . . . . . . . . . . . . . . . . 7
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
8
9
10
11
Application information. . . . . . . . . . . . . . . . . . 10
Bidirectional translation . . . . . . . . . . . . . . . . . 11
How to size pull-up resistor value. . . . . . . . . . 11
How to design for maximum frequency
11.1
11.2
11.3
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
13
Soldering of SMD packages . . . . . . . . . . . . . . 22
Introduction to soldering . . . . . . . . . . . . . . . . . 22
Wave and reflow soldering . . . . . . . . . . . . . . . 22
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 22
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 23
13.1
13.2
13.3
13.4
14
15
16
Soldering: PCB footprints. . . . . . . . . . . . . . . . 25
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 32
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 33
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 33
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 34
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 January 2014
Document identifier: PCA9306
相关型号：
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