PCA9538BS_技术文档

INTEGRATED CIRCUITS

PCA9538

8-bit I²C and SMBus low power I/O port

with interrupt and reset

Product data sheet

2004 Oct 05

Supersedes data of 2004 Sep 30

Philips

Semiconductors

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

DESCRIPTION

The PCA9538 is a 16-pin CMOS device that provide 8 bits of

General Purpose parallel Input/Output (GPIO) expansion with

2

interrupt and reset for I C/SMBus applications and was developed

2

to enhance the Philips family of I C I/O expanders. I/O expanders

provides a simple solution when additional I/O is needed for ACPI

power switches, sensors, pushbuttons, LEDs, fans, etc.

The PCA9538 consists of an 8-bit Configuration register (Input or

Output selection); 8-bit Input register, 8-bit Output register and an

8-bit Polarity inversion register (Active HIGH or Active LOW

operation). The system master can enable the I/Os as either inputs

or outputs by writing to the I/O configuration bits. The data for each

Input or Output is kept in the corresponding Input or Output register.

The polarity of the input port register can be inverted with the

Polarity Inversion Register. All registers can be read by the system

master.

FEATURES

2

• 8-bit I C GPIO with interrupt and reset

• Operating power supply voltage range of 2.3 V to 5.5 V

• 5 V tolerant I/Os

• Polarity inversion register

• Active LOW interrupt output

• Active LOW reset input

• Low stand-by current

The PCA9538 is identical to the PCA9554 except for the removal of

the internal I/O pull-up resistor which greatly reduces power

consumption when the I/Os are held LOW, replacement of A2 with

RESET and different address range.

The PCA9538 open-drain interrupt output is activated when any

input state differs from its corresponding input port register state and

is used to indicate to the system master that an input state has

changed. The power-on reset sets the registers to their default

values and initializes the device state machine. The RESET pin

causes the same reset/initialization to occur without depowering the

device.

• Noise filter on SCL/SDA inputs

• No glitch on power-up

• Internal power-on reset

• 8 I/O pins which default to 8 inputs

• 0 kHz to 400 kHz clock frequency

2

• ESD protection exceeds 2000 V HBM per JESD22-A114,

Two hardware pins (A0 and A1) vary the fixed I C address and allow

2

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

up to four devices to share the same I C/SMBus.

• Latch-up testing is done to JESDEC Standard JESD78 which

exceeds 100 mA

• Offered in three different packages: SO16, TSSOP16, and

HVQFN16

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

16-Pin Plastic SO (wide)

16-Pin Plastic TSSOP

16-Pin Plastic HVQFN

–40 °C to +85 °C

PCA9538D

PCA9538PW

PCA9538BS

PCA9538D

PCA9538

9538

SOT162-1

SOT403-1

SOT629-1

Standard packing quantities and other packing data are available at www.standardproducts.philips.com/packaging.

2

I C-bus is a trademark of Philips Semiconductors Corporation.

SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I C patent.

2

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

PIN CONFIGURATION — SO, TSSOP

PIN CONFIGURATION — HVQFN

A1

A0

V

SDA

DD

V

1

2

3

4

5

6

7

8

16

DD

A0

A1

15 SDA

SCL

12

1

2

3

4

RESET

I/O0

SCL

14

RESET

I/O0

INT

13

INT

11

10

9

I/O7

I/O6

I/O1

12

11

10

9

I/O1

I/O2

I/O7

I/O6

I/O2

I/O3

I/O5

I/O4

V

SS

I/O3

V

I/O4

I/O5

SW02172

SS

TOP VIEW

SW02173

Figure 1. Pin configuration — SO, TSSOP

Figure 2. Pin Configuration — HVQFN

PIN DESCRIPTION

SO, TSSOP

PIN NUMBER

HVQFN

PIN NUMBER

SYMBOL

FUNCTION

1

2

15

16

1

A0

A1

Address input 0

Address input 1

3

RESET

I/O0–3

Active LOW reset input

I/O0 to I/O3

4–7

8

2–5

6

V

SS

Supply ground

9–12

13

14

15

16

7–10

11

I/O4–7

INT

I/O4 to I/O7

Interrupt output (open drain)

Serial clock line

Serial data line

12

13

14

SCL

SDA

V

DD

Supply voltage

BLOCK DIAGRAM

PCA9538

A0

A1

I/O0

I/O1

I/O2

I/O3

SCL

SDA

INPUT

FILTER

INPUT/

OUTPUT

PORTS

8-BIT

2

I C/SMBUS

CONTROL

I/O4

I/O5

WRITE pulse

READ pulse

I/O6

I/O7

V

DD

V

CC

POWER-ON

RESET

INT

V

SS

LP

FILTER

NOTE: ALL I/Os ARE SET TO INPUTS AT RESET

SW02174

Figure 3. Block diagram

3

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

REGISTERS

Power-on Reset

When power is applied to V , an internal power-on reset holds the

DD

Command Byte

PCA9538 in a reset condition until V has reached V

. At that

DD

POR

point, the reset condition is released and the PCA9538 registers and

Command

Protocol

Function

state machine will initialize to their default states. Thereafter, V

must be lowered below 0.2 V to reset the device.

DD

0

1

2

3

Read byte

Input port register

Output port register

Polarity inversion register

Configuration register

Read/write byte

For a power reset cycle, V must be lowered below 0.2 V and then

DD

restored to the operating voltage.

RESET Input

A reset can be accomplished by holding the RESET pin LOW for a

The command byte is the first byte to follow the address byte during

a write transmission. It is used as a pointer to determine which of the

following registers will be written or read.

2

minimum of t . The PCA9538 registers and SMBus/I C state

W

machine will be held in their default state until the RESET input is

once again HIGH. This input requires a pull-up resistor to V if no

DD

active connection is used.

Register 0 – Input Port Register

Interrupt Output

bit

I7

X

I6

X

I5

X

I4

X

I3

X

I2

X

I1

X

I0

X

The open-drain interrupt output is activated when one of the port

pins change state and the pin is configured as an input. The

interrupt is deactivated when the input returns to its previous state or

the input port register is read.

default

This register is a read only port. It reflects the incoming logic levels

of the pins, regardless of whether the pin is defined as an input or an

output by Register 3. Writes to this register have no effect.

Note that changing an I/O from an output to an input may cause a

false interrupt to occur if the state of the pin does not match the

contents of the input port register.

The default value ‘X’ is determined by the externally applied logic

level.

Register 1 – Output Port Register

bit

O7

1

O6

1

O5

1

O4

1

O3

1

O2

1

O1

1

O0

1

default

This register reflects the outgoing logic levels of the pins defined as

outputs by Register 3. Bit values in this register have no effect on

pins defined as inputs. Reads from this register return the value that

is in the flip-flop controlling the output selection, NOT the actual pin

value.

Register 2 – Polarity Inversion Register

bit

N7

0

N6

0

N5

0

N4

0

N3

0

N2

0

N1

0

N0

0

default

This register allows the user to invert the polarity of the Input Port

Register data. If a bit in this register is set (written with ‘1’), the

corresponding Input Port data is inverted. If a bit in this register is

cleared (written with a ‘0’), the Input Port data polarity is retained.

Register 3 – Configuration Register

bit

C7

1

C6

1

C5

1

C4

1

C3

1

C2

1

C1

1

C0

1

default

This register configures the directions of the I/O pins. If a bit in this

register is set, the corresponding port pin is enabled as an input with

high-impedance output driver. If a bit in this register is cleared, the

corresponding port pin is enabled as an output. At reset, the I/Os are

configured as inputs.

4

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7

DATA FROM

SHIFT REGISTER

OUTPUT PORT

REGISTER DATA

CONFIGURATION

REGISTER

V

DD

DATA FROM

SHIFT REGISTER

Q

D

Q1

FF

ESD PROTECTION DIODE

WRITE

CONFIGURATION

PULSE

D

C

Q

C

K

FF

I/O0 TO I/O7

WRITE PULSE

K

Q2

OUTPUT

PORT

ESD PROTECTION DIODE

REGISTER

V

SS

INPUT PORT

REGISTER

INPUT PORT

REGISTER DATA

D

Q

FF

READ PULSE

Q

C

K

TO INT

DATA FROM

SHIFT REGISTER

POLARITY

REGISTER DATA

D

Q

FF

WRITE

POLARITY

PULSE

C

K

POLARITY

INVERSION

REGISTER

SU01784

NOTE: At Power-on Reset, all registers return to default values.

Figure 4. Simplified schematic of I/O0 to I/O7

I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off,

creating a high-impedance input. The input voltage may be raised

above V to a maximum of 5.5 V.

DD

If the I/O is configured as an output, then either Q1 or Q2 is enabled,

depending on the state of the output port register. Care should be

exercised if an external voltage is applied to an I/O configured as an

output because of the low impedance paths that exist between the

pin and either V or V

.

SS

DD

5

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

Device address

SLAVE ADDRESS

1

0

A1 A0 R/W

FIXED

HARDWARE SELECTABLE

SW02175

Figure 5. PCA9538 address

Bus transactions

Data is transmitted to the PCA9538 registers using the write mode as shown in Figures 6 and 7. Data is read from the PCA9538 registers using

the read mode as shown in Figures 8 and 9. These devices do not implement an auto-increment function so once a command byte has been

sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent.

1

2

3

4

5

6

7

8

9

SCL

SDA

command byte

slave address

data to port

DATA 1

1

0

A1 A0

S

0

A

0

1

A

P

start condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

WRITE TO

PORT

DATA OUT

FROM PORT

DATA 1 VALID

t

pv

SW02176

Figure 6. WRITE to output port register

1

2

3

4

5

6

7

8

0

9

SCL

SDA

command byte

slave address

data to register

DATA

1

0

A1 A0

P

S

A

0

1

1/0

start condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

DATA TO

REGISTER

SW02177

Figure 7. WRITE to configuration or polarity inversion registers

6

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge

from master

slave address

data from register

0

A1

0

A1

A0

1

A0

1

COMMAND BYTE

DATA

S

0

A

S

A

first byte

R/W

at this moment master-transmitter

becomes master-receiver and

slave-receiver becomes

slave-transmitter

no acknowledge

from master

data from register

NA

P

DATA

last byte

SW02178

Figure 8. READ from register

1

2

3

4

5

6

7

8

1

9

SCL

SDA

slave address

data from port

DATA 1

data from port

DATA 4

S

1

0

A1 A0

A

NA

P

start condition

R/W acknowledge

from slave

acknowledge

from master

no acknowledge

from master

stop

condition

READ FROM

PORT

DATA INTO

PORT

DATA 2

DATA 3

DATA 4

t

ph

t

ps

INT

t

iv

t

ir

SW02179

NOTES:

1. This figure assumes the command byte has previously been programmed with 00h.

2. Transfer of data can be stopped at any moment by a stop condition.

Figure 9. READ input port register

7

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

TYPICAL APPLICATION

V

DD

(5 V)

2 kΩ

100 kΩ

(×3)

V

10 kΩ

DD

V

DD

SUBSYSTEM 1

(e.g. temp sensor)

SCL

SDA

SCL

I/O

0

SDA

INT

MASTER

CONTROLLER

INT

1

INT

I/O

2

IRESET

RESET

GND

3

SUBSYSTEM 2

(e.g. counter)

I/O

4

PCA9538

I/O

5

I/O

6

I/O

7

A

Controlled Switch

(e.g. CBT device)

ENABLE

A1

A0

B

V

SS

ALARM

SUBSYSTEM 3

(e.g. alarm

system)

NOTE: Device address configured as 1110000 for this example

I/O , I/O , I/O , configured as outputs

0

2

3

I/O , I/O , I/O , configured as inputs

1

4

5

V

I/O , I/O , are not used and need 100 kΩ pull-up resistors to protect them from floating.

DD

06

7

SW02180

Figure 10. Typical application

Minimizing I when the I/O is used to control LEDs

DD

When the I/Os are used to control LEDs, they are normally connected to V through a resistor as shown in Figure 10. Since the LED acts as a

DD

diode, when the LED is off the I/O V is about 1.2 V less than V . The supply current , I , increases as V becomes lower than V and is

IN

DD

IN

DD

specified as ∆I in the DC characteristics table.

DD

Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or

equal to V when the LED is off. Figure 11 shows a high value resistor in parallel with the LED. Figure 12 shows V less than the LED supply

DD

voltage by at least 1.2 V. Both of these methods maintain the I/O V at or above V and prevents additional supply current consumption when

IN

DD

the LED is off.

3.3 V

5 V

V

DD

LED

100 kΩ

V

LED

DD

V

DD

LEDx

SW02086

SW02087

Figure 11. High value resistor in parallel with the LED

Figure 12. Device supplied by a lower voltage

8

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN

–0.5

—

MAX

UNIT

V

DD

Supply voltage

6.0

±20

5.5

I

DC input current

mA

V

DC voltage on an I/O

V

– 0.5

I/O

DD

SS

I

DC output current on an I/O

Supply current

—

±50

85

mA

mW

°C

I

SS

Supply current

—

100

200

+150

+85

+125

P

tot

Total power dissipation

Storage temperature range

Operating ambient temperature

Maximum junction temperature

—

T

stg

–65

–40

—

T

amb

°C

T

°C

J(MAX)

9

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take

precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”.

DC CHARACTERISTICS

V

= 2.3 to 5.5 V; V = 0 V; T

= –40 to +85 °C; unless otherwise specified.

DD

SS

amb

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supplies

V

Supply voltage

Supply current

2.3

—

5.5

V

DD

Operating mode; V = 5.5 V; no load;

DD

I

104

175

µA

DD

f

= 100 kHz

SCL

Standby mode; V = 5.5 V; no load;

DD

I

Standby current

—

0.25

1

µA

stbl

V = V ; f

= 0 kHz; I/O = inputs

I

SS SCL

Standby mode; V = 5.5 V; no load;

DD

I

Standby current

—

0.25

1.5

1

µA

stbh

V = V ; f

= 0 kHz; I/O = inputs

I

DD SCL

V

Power-on reset voltage (Note 1)

No load; V = V or V

1.65

V

POR

I

DD

SS

Input SCL; input/output SDA

V

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

Leakage current

–0.5

—

tbd

—

5

0.3 V

V

IL

IH

DD

V

0.7 V

3

5.5

—

DD

I

OL

V

= 0.4V

mA

µA

pF

OL

I

L

V = V = V

I

–1

+1

10

DD

SS

C

Input capacitance

V = V

I

—

I

SS

I/Os

V

LOW-level input voltage

HIGH-level input voltage

–0.5

2.0

8

—

10

13

17

24

14

19

—

5

0.8

5.5

—

1

V

IL

V

IH

V

= 0.5 V; V = 2.3 V; Note 2

mA

V

OL

OH

DD

= 0.7 V; V = 2.3 V; Note 2

10

8

DD

= 0.5 V; V = 4.5 V; Note 2

DD

I

OL

LOW-level output current

HIGH-level output voltage

= 0.7 V; V = 4.5 V; Note 2

10

8

DD

= 0.5 V; V = 3.0 V; Note 2

DD

= 0.7 V; V = 3.0 V; Note 2

10

1.8

1.7

2.6

2.5

4.1

4.0

–1

—

DD

I

= –8 mA; V = 2.3 V; Note 3

DD

= –10 mA; V = 2.3 V; Note 3

V

DD

= –8 mA; V = 3.0 V; Note 3

V

DD

V

OH

= –10 mA; V = 3.0 V; Note 3

V

DD

= –8 mA; V = 4.5 V; Note 3

V

DD

= –10 mA; V = 4.5 V; Note 3

V

DD

I

IL

Input leakage current

Input capacitance

V = V = V

I

µA

pF

DD

SS

C

10

I

Interrupt INT

I

OL

LOW-level output current

V

OL

= 0.4 V

3

tbd

—

mA

Select Inputs A0, A1, and RESET

V

LOW-level input voltage

HIGH-level input voltage

Input leakage current

–0.5

2.0

–1

—

0.8

5.5

1

V

IL

IH

LI

V

I

µA

NOTES:

1. V must be lowered to 0.2 V in order to reset part.

DD

2. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.

3. The total current sourced by all I/Os must be limited to 85 mA.

10

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

AC SPECIFICATIONS

STANDARD MODE

FAST MODE

I C-bus

2

I C-bus

SYMBOL

PARAMETER

UNITS

MIN

0

MAX

100

—

MIN

MAX

400

—

f

Operating frequency

0

kHz

µs

ns

µs

ns

µs

ns

SCL

t

Bus free time between STOP and START conditions

Hold time after (repeated) START condition

Repeated START condition setup time

Setup time for STOP condition

4.7

4.0

4.7

4.0

0

1.3

BUF

t

—

0.6

—

HD;STA

t

—

0.6

—

SU;STA

t

—

0.6

—

SU;STO

t

Data in hold time

—

0

0.1

—

HD;DAT

VD;ACK

2

t

Valid time for ACK condition

0.3

300

250

4.7

4.0

—

3.45

—

0.9

—

3

t

Data out valid time

50

VD;DAT

Data setup time

—

100

—

SU;DAT

t

Clock LOW period

—

1.3

—

LOW

t

Clock HIGH period

—

0.6

—

HIGH

1

t

F

Clock/Data fall time

300

1000

50

20 + 0.1 C

—

300

50

b

t

R

Clock/Data rise time

—

b

t

Pulse width of spikes that must be suppressed by the input filters

—

SP

Port Timing

t

Output data valid

—

100

1

200

—

100

1

200

—

ns

µs

PV

PS

PH

Input data setup time

Input data hold time

t

—

Interrupt Timing

t

Interrupt valid

Interrupt reset

—

4

—

4

µs

IV

IR

t

RESET

t

Reset pulse width

Reset recovery time

Time to reset

4

0

—

4

0

—

ns

W

t

REC

t

400

RESET

NOTES:

1. C = total capacitance of one bus line in pF.

b

2. t

3. t

= time for Acknowledgement signal from SCL low to SDA (out) low.

= minimum time for SDA data out to be valid following SCL low.

VD;ACK

VD;DAT

SDA

SCL

t

R

t

F

t

SP

HD;STA

t

LOW

BUF

t

SU;STO

HD;STA

SU;STA

t

SU;DAT

HD;DAT

HIGH

P

S

Sr

P

SU00645

Figure 13. Definition of timing

11

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

START

ACK OR READ CYCLE

SCL

SDA

30%

t

RESET

50%

t

REC

t

W

RESET

50%

I/Ox

I/O configured as inputs

SW02340

Figure 14. Definition of RESET timing

70 %

30 %

SCL

SDA

2

1

0

A

P

t

PH

PS

INPUT

50 %

t

IV

t

IR

INT

SW02329

Figure 15. Expanded view of Read input port register

70 %

30 %

SCL

SDA

2

1

0

A

P

t

PV

OUTPUT

50 %

SW02330

Figure 16. Expanded view of Write to output port register

12

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

BIT 7

MSB

(A7)

START

CONDITION

(S)

STOP

CONDITION

(S)

BIT 6

(A6)

BIT 0

(R/W)

ACKNOWLEDGE

(A)

PROTOCOL

t

HIGH

SU;STA

LOW

1 / f

SCL

SDA

t

f

BUF

r

t

SU;STO

t

HD;STA

SU;DAT

VD;DAT

HD;DAT

t

VD;ACK

SW02210

2

Figure 17. I C-bus timing diagram; rise and fall times refer to V and V

IL

IH

TEST CIRCUITS

V

DD

V

DD

Open

R

= 500 Ω

L

V

O

I

PULSE

GENERATOR

D.U.T.

R

T

C

L

50 pF

DEFINITIONS

R = Load resistor.

L

C = Load capacitance includes jig and probe capacitance

L

R = Termination resistance should be equal to the output

T

impedance Z of the pulse generators.

O

SW02181

Figure 18. Test circuitry for switching times

2V

DD

500 Ω

S1

From Output

Under Test

Open

GND

500 Ω

C

= 50 pF

L

Load Circuit

TEST

S1

2 V

t

pv

DD

SA00652

Figure 19. Test circuit

13

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

SO16: plastic small outline package; 16 leads; body width 7.5 mm

SOT162-1

14

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

15

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals;

body 4 x 4 x 0.85 mm

SOT629-1

16

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

REVISION HISTORY

Rev

Date

Description

_3

20041005

Product data sheet (9397 750 14176). Supersedes data of 2004 Sep 30 (9397 750 14049).

Modifications:

• Upgrade status to “Product data sheet”

_2

_1

20040930

20040820

Objective data sheet (9397 750 14049). Supersedes data of 2004 Aug 20 (9397 750 12881).

Objective data sheet (9397 750 12881).

17

2004 Oct 05

Philips Semiconductors

Product data sheet

8-bit I²C and SMBus low power I/O port

with interrupt and reset

PCA9538

2

Purchase of Philips I C components conveys a license under the Philips’ I C patent

2

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

2

code 9398 393 40011.

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

I

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

Preliminary data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

Product data

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

copyright, or mask work right infringement, unless otherwise specified.

Koninklijke Philips Electronics N.V. 2004

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 10-04

9397 750 14176

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

18

2004 Oct 05


型号：	PCA9538BS
厂家：	NXP
描述：	8-bit I2C and SMBus low power I/O port with interrupt and reset 8位I2C和SMBus低功率I /带中断和复位输出端口并行IO端口微控制器和处理器外围集成电路
文件：	总18页 (文件大小：201K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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