PCA9544BS [NXP]
IC 9544 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PQCC20, 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-662-1, VQFN-20, Multiplexer/Demultiplexer;
| 型号： | PCA9544BS |
| 厂家： | 
NXP |
| 描述： | IC 9544 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PQCC20, 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-662-1, VQFN-20, Multiplexer/Demultiplexer 输出元件 逻辑集成电路 |
| 文件： | 总17页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCA9544
4-channel I2C multiplexer with interrupt logic
Product data sheet
2004 Sep 29
Supersedes data of 2002 Jul 26
Philips
Semiconductors
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
DESCRIPTION
The PCA9544 is a 1-of-4 bi-directional translating multiplexer,
2
controlled via the I C-bus. The SCL/SDA upstream pair fans out to
four SCx/SDx downstream pairs, or channels. Only one SCx/SDx
channel is selected at a time, determined by the contents of the
programmable control register. Four interrupt inputs, INT0 to INT3,
one for each of the SCx/SDx downstream pairs, are provided. One
interrupt output, INT, which acts as an AND of the four interrupt
inputs, is provided.
A power-on reset function puts the registers in their default state and
2
initializes the I C state machine with no channels selected.
FEATURES
The pass gates of the multiplexer are constructed such that the V
• 1-of-4 bi-directional translating multiplexer
• I C interface logic; compatible with SMBus
• 4 Active LOW Interrupt Inputs
• Active LOW Interrupt Output
DD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9544. This allows the use of different bus
voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V or 3.3 V parts
can communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
2
2
• 3 address pins allowing up to 8 devices on the I C-bus
2
• Channel selection via I C-bus
• Power up with all multiplexer channels deselected
• Low Rds switches
ON
• Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
• No glitch on power-up
• Supports hot insertion
• Low stand-by current
• Operating power supply voltage range of 2.3 V to 5.5 V
• 5 V tolerant Inputs
• 0 kHz to 400 kHz clock frequency
• ESD protection exceeds 2000 V HBM per JESD22-A114,
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
• Latchup testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
• Three packages offered: SO20, TSSOP20, and HVQFN20
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40 °C to +85 °C
ORDER CODE
PCA9544D
TOPSIDE MARK
PCA9544D
PCA9544
DRAWING NUMBER
SOT163-1
20-Pin Plastic SO
20-Pin Plastic TSSOP
20-Pin Plastic HVQFN
–40 °C to +85 °C
PCA9544PW
PCA9544BS
SOT360-1
–40 °C to +85 °C
9544
SOT662-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
2
I C is a trademark of Philips Semiconductors Corporation.
2
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
PIN CONFIGURATION — SO, TSSOP
PIN CONFIGURATION — HVQFN
A1 A0
V
SDA SCL
DD
A0
A1
V
DD
1
2
3
4
5
6
7
8
20
19
18
SDA
SCL
A2
INT0
SD0
SC0
INT1
15 INT
14 SC3
1
2
3
4
5
A2
INT0
SD0
17 INT
SD3
INT3
SC2
13
12
11
SC3
16
SD3
INT3
SC2
15
14
13
SC0
INT1
SD1
SC1
SD2
9
12
11
SD1 SC1 V
INT2 SD2
SS
10
VSS
INT2
TOP VIEW
su01666
SW00373
Figure 1. Pin configuration — SO, TSSOP
Figure 2. Pin configuration — HVQFN
FUNCTION
PIN DESCRIPTION
SO, TSSOP
PIN NUMBER
HVQFN
PIN NUMBER
SYMBOL
1
2
19
20
1
A0
A1
Address input 0
Address input 1
3
A2
Address input 2
4
2
INT0
SD0
SC0
INT1
SD1
SC1
Active LOW interrupt input 0
Serial data 0
5
3
6
4
Serial clock 0
7
5
Active LOW interrupt input 1
Serial data 1
8
6
9
7
Serial clock 1
10
11
12
13
14
15
16
17
18
19
20
8
V
Supply ground
SS
9
INT2
SD2
SC2
INT3
SD3
SC3
INT
Active LOW interrupt input 2
Serial data 2
10
11
12
13
14
15
16
17
18
Serial clock 2
Active LOW interrupt input 3
Serial data 3
Serial clock 3
Active LOW interrupt output
Serial clock line
SCL
SDA
Serial data line
V
DD
Supply voltage
3
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
BLOCK DIAGRAM
PCA9544
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
SWITCH CONTROL LOGIC
V
V
SS
DD
POWER-ON
RESET
A0
A1
A2
SCL
SDA
2
I C-BUS
INPUT
FILTER
CONTROL
INT[0–3]
INT LOGIC
INT
SW00379
Figure 3. Block diagram
4
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
DEVICE ADDRESSING
INTERRUPT HANDLING
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9544 is
shown in Figure 4. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
The PCA9544 provides 4 interrupt inputs, one for each channel and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9544 and the interrupt output
will be driven LOW. The channel need not be active for detection of
the interrupt. A bit is also set in the control byte. Bits 4 – 7 of the
control byte correspond to channels 0 – 3 of the PCA9544,
respectively. Therefore, if an interrupt is generated by any device
connected to channel 2, the state of the interrupt inputs is loaded into
the control register when a read is accomplished. Likewise, an
interrupt on any device connected to channel 0 would cause bit 4 of
the control register to be set on the read. The master can then
address the PCA9544 and read the contents of the control byte to
determine which channel contains the device generating the interrupt.
The master can then reconfigure the PCA9544 to select this
channel, and locate the device generating the interrupt and clear it.
The interrupt clears when the device originating the interrupt clears.
1
1
1
0
A2 A1 A0 R/W
FIXED
HARDWARE SELECTABLE
SW00862
Figure 4. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9544 which will be stored
in the Control Register. If multiple bytes are received by the
PCA9544, it will save the last byte received. This register can be
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
If unused, interrupt input(s) must be connected to V through a
2
DD
written and read via the I C-bus.
pull-up resistor.
INTERRUPT BITS
(READ ONLY)
CHANNEL SELECTION BITS
(READ/WRITE)
Table 2. Control Register Read — Interrupt
INT3 INT2 INT1 INT0
D3
B2
B1
B0
COMMAND
7
6
5
4
3
2
1
0
No interrupt
on channel 0
0
INT3 INT2 INT1 INT0
ENABLE BIT
X
B2 B1 B0
X
X
X
X
X
X
X
X
X
X
Interrupt on
channel 0
1
SW00386
No interrupt
on channel 1
Figure 5. Control register
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
Interrupt on
channel 1
CONTROL REGISTER DEFINITION
A SCx/SDx downstream pair, or channel, is selected by the contents
of the control register. This register is written after the PCA9544 has
been addressed. The 3 LSBs of the control byte are used to
determine which channel is to be selected. When a channel is
selected, it will become active after a stop condition has been placed
No interrupt
on channel 2
0
1
X
X
X
X
Interrupt on
channel 2
2
No interrupt
on channel 3
on the I C-bus. This ensures that all SCx/SDx lines will be in a
HIGH state when the channel is made active, so that no false
conditions are generated at the time of connection.
0
1
X
Interrupt on
channel 3
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
NOTE: Several interrupts can be active at the same time.
Ex: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no
interrupt on channels 0 and 3, and there is interrupt on channels 1
and 2.
INT3 INT2 INT1 INT0
D3
B2
B1
B0
COMMAND
X
X
X
X
X
0
X
X
X
X
X
0
X
X
X
X
X
0
X
X
X
X
X
0
X
0
X
X
No channel
selected
X
X
X
X
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
Channel 0
enabled
POWER-ON RESET
When power is applied to V , an internal Power On Reset holds
DD
Channel 1
enabled
the PCA9544 in a reset state until V has reached V
. At this
DD
POR
point, the reset condition is released and the PCA9544 registers and
I C state machine are initialized to their default states, all zeroes
2
Channel 2
enabled
causing all the channels to be deselected.
Channel 3
enabled
No channel
selected;
power-up
default state
5
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
Figure 6 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9544 to act as a voltage translator, the V
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9544 are constructed such that
the V voltage can be used to limit the maximum voltage that will
DD
2
pass
be passed from one I C-bus to another.
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then V
should be equal to or below
pass
V
vs. V
DD
pass
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 6, we see that V (max.) will be at 2.7 V when the
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
pass
PCA9544 supply voltage is 3.5 V or lower so the PCA9544 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 13).
MAXIMUM
TYPICAL
More Information can be found in Application Note AN262 PCA954X
V
pass
2
family of I C/SMBus multiplexers and switches.
MINIMUM
5.0
2.0
2.5
3.0
3.5
4.0
4.5
5.5
V
DD
SW00820
Figure 6. V
voltage
pass
6
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
2
CHARACTERISTICS OF THE I C-BUS
Start and stop conditions
2
The I C-bus is for 2-way, 2-line communication between different ICs
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 8).
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
System configuration
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 7).
A device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 9).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 7. Bit transfer
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
SW00365
Figure 8. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
2
SLAVE
RECEIVER
I C
MASTER
TRANSMITTER
MULTIPLEXER
SLAVE
SW00366
Figure 9. System configuration
7
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START condition
SW00368
2
Figure 10. Acknowledgement on the I C-bus
SLAVE ADDRESS
CONTROL REGISTER
SDA
1
1
1
0
A2 A1 A0
B2 B1 B0
A
P
S
0
A
X
X
X
X
X
start condition
R/W acknowledge
from slave
acknowledge
from slave
SW00802
Figure 11. WRITE control register
SLAVE ADDRESS
CONTROL REGISTER
last byte
SDA
1
1
1
0
A2 A1 A0
S
1
A
INT3INT2INT1 INT0
X
B2 B1 B0 NA
P
start condition
R/W acknowledge
from slave
no acknowledge
from master
stop condition
SW00378
Figure 12. READ control register
8
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
TYPICAL APPLICATION
V
= 2.7 – 5.5 V
DD
V
= 3.3 V
DD
V = 2.7 – 5.5 V
SEE NOTE (1)
SDA
SCL
SDA
SCL
INT
SD0
CHANNEL 0
SC0
INT0
V = 2.7 – 5.5 V
SEE NOTE (1)
2
I C/SMBus MASTER
SD1
CHANNEL 1
SC1
INT1
V = 2.7 – 5.5 V
SEE NOTE (1)
SD1
CHANNEL 2
SC1
INT2
V = 2.7 – 5.5 V
SEE NOTE (1)
NOTE:
1.
If the device generating the Interrupt has an open-drain output
structure or can be tri-stated, a pull-up resistor is required.
SD1
If the device generating the Interrupt has a totem-pole output
structure and cannot be tri-stated, a pull-up resistor is not
required.
CHANNEL 3
A2
SC1
A1
A0
The Interrupt inputs should not be left floating.
INT3
V
SS
PCA9544
SW00864
Figure 13. Typical application
9
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–0.5 to +7.0
±20
UNIT
V
V
DD
V
I
DC input voltage
V
I
I
DC input current
mA
mA
mA
mA
mW
°C
I
O
DC output current
±25
I
Supply current
±100
DD
I
SS
Supply current
±100
P
tot
total power dissipation
Storage temperature range
Operating ambient temperature
400
T
stg
–60 to +150
–40 to +85
T
amb
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
DC CHARACTERISTICS
V
= 2.3 V to 3.6 V; V = 0 V; T
= –40 °C to +85 °C; unless otherwise specified. (See page 10 for V = 3.6 V to 5.5 V)
DD
SS
amb
DD
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Supply
V
I
Supply voltage
Supply current
2.3
—
—
3.6
V
DD
Operating mode; V = 3.6 V;
DD
no load; V = V or V ;
40
100
µA
I
DD
SS
DD
f
= 100 kHz
SCL
Standby mode; V = 3.6 V;
DD
I
Standby current
—
—
25
100
2.1
µA
stb
no load; V = V or V
f
= 0 kHz
I
DD
SS; SCL
V
POR
Power-on reset voltage
no load; V = V or V
SS
1.6
V
I
DD
Input SCL; input/output SDA
V
LOW-level input voltage
HIGH-level input voltage
–0.5
—
—
—
—
—
12
0.3V
6
V
V
IL
DD
V
IH
0.7V
DD
V
V
= 0.4 V
= 0.6 V
3
6
—
—
+1
13
OL
I
OL
LOW-level output current
mA
OL
I
L
Leakage current
Input capacitance
V = V or V
SS
–1
—
µA
I
DD
C
V = V
SS
pF
i
I
Select inputs A0 to A2 / INT0 to INT3
V
LOW-level input voltage
HIGH-level input voltage
Input leakage current
Input capacitance
–0.5
—
—
+0.3V
V
V
IL
IH
LI
DD
V
0.7V
V
DD
+ 0.5
DD
I
pin at V or V
–1
—
—
+1
µA
pF
DD
SS
C
V = V
I SS
1.6
3
i
Pass Gate
V
= 3.0 V to 3.6 V; V = 0.4 V; I = 15 mA
5
7
20
26
2.2
—
1.5
—
—
3
30
55
—
CC
O
O
R
Switch resistance
Ω
ON
V
= 2.3 V to 2.7 V; V = 0.4V; I = 10 mA
CC
O
O
V
swin
= V = 3.3 V; I = –100 µA
swout
—
1.6
—
1.1
–1
—
DD
V
V
= V = 3.0 V to 3.6 V; I = –100 µA
swout
2.8
—
swin
DD
V
Pass
Switch output voltage
V
V
swin
= V = 2.5 V; I
= –100 µA
swout
DD
= V = 2.3 V to 2.7 V; I = –100 µA
swout
2.0
+1
5
swin
DD
I
Leakage current
V = V or V
SS
µA
L
I
DD
C
Input/output capacitance
V = V
I SS
pF
io
INT Output
I
LOW-level output current
HIGH-level output current
V
OL
= 0.4 V
10
3
—
—
—
mA
OL
I
—
+100
µA
OH
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
DC CHARACTERISTICS
V
= 3.6 V to 5.5 V; V = 0 V; T
= –40 °C to +85 °C; unless otherwise specified. (See page 9 for V = 2.3 V to 3.6 V)
DD
SS
amb
DD
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MAX
MIN
TYP
Supply
V
I
Supply voltage
Supply current
3.6
—
—
5.5
V
DD
Operating mode; V = 5.5 V;
DD
no load; V = V or V ;
575
600
µA
I
DD
SS
DD
f
= 100 kHz
SCL
Standby mode; V = 5.5 V;
DD
I
Standby current
—
—
130
1.7
300
2.1
µA
stb
no load; V = V or V
f
= 0 kHz
I
DD
SS; SCL
V
POR
Power-on reset voltage
no load; V = V or V
SS
V
I
DD
Input SCL; input/output SDA
V
LOW–level input voltage
HIGH-level input voltage
–0.5
—
—
—
—
—
—
12
0.3V
6
V
IL
DD
V
IH
0.7V
V
DD
V
V
= 0.4 V
= 0.6 V
3
6
—
—
mA
mA
µA
µA
pF
OL
I
OL
LOW-level output current
OL
I
IL
LOW-level input current
HIGH-level input current
Input capacitance
V = V
–10
—
—
+10
100
13
I
SS
DD
SS
I
IH
V = V
I
C
V = V
I
i
Select inputs A0 to A2 / INT0 to INT3
V
LOW-level input voltage
HIGH-level input voltage
Input leakage current
Input capacitance
–0.5
—
—
—
2
+0.3V
V
V
IL
IH
LI
DD
V
0.7V
V
DD
+ 0.5
DD
I
pin at V or V
–1
—
+50
µA
pF
DD
SS
C
V = V
I SS
5
i
Pass Gate
R
Switch resistance
V
= 4.5 V to 5.5 V; V = 0.4 V; I = 15 mA
4
11
3.5
—
—
3
24
—
Ω
V
ON
CC
O
O
V
swin
= V = 5.0 V; I = –100 µA
swout
—
DD
V
Pass
Switch output voltage
V
swin
= V = 4.5 V to 5.5 V; I = –100 µA
swout
2.6
–10
—
4.5
+100
5
V
DD
I
Leakage current
V = V or V
SS
µA
pF
L
I
DD
C
Input/output capacitance
V = V
I SS
io
INT Output
I
LOW-level output current
HIGH-level output current
V
OL
= 0.4 V
3
—
—
—
mA
OL
I
—
+100
µA
OH
11
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
AC CHARACTERISTICS
STANDARD-MODE
FAST-MODE
I C-BUS
2
2
I C-BUS
SYMBOL
PARAMETER
UNIT
MIN
—
MAX
MIN
—
MAX
1
1
t
Propagation delay from SDA to SD or SCL to SC
0.3
0.3
ns
kHz
µs
pd
n
n
f
SCL clock frequency
0
100
—
0
400
—
SCL
BUF
t
Bus free time between a STOP and START condition
4.7
1.3
Hold time (repeated) START condition
After this period, the first clock pulse is generated
t
t
4.0
—
0.6
—
µs
HD;STA
t
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Set-up time for STOP condition
Data hold time
4.7
4.0
4.7
4.0
—
—
1.3
0.6
0.6
0.6
—
—
µs
µs
µs
µs
µs
ns
ns
µs
µs
LOW
t
HIGH
—
—
SU;STA
SU;STO
t
—
—
2
2
t
0
3.45
—
0
0.9
—
HD;DAT
t
Data set-up time
250
—
100
SU;DAT
3
t
R
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
1000
300
400
20 + 0.1C
20 + 0.1C
—
300
300
400
b
3
t
F
—
b
C
—
b
Pulse width of spikes which must be suppressed
by the input filter
t
SP
—
50
—
50
ns
t
Data valid (HL)
—
—
—
1
0.6
1
—
—
—
1
0.6
1
µs
µs
µs
VD:DATL
t
Data valid (LH)
VD:DATH
t
Data valid Acknowledge
VD:ACK
INT
t
INTn to INT active valid time
—
—
4
2
—
—
4
2
µs
µs
ns
ns
iv
t
INTn to INT inactive delay time
ir
L
pwr
LOW level pulse width rejection or INTn inputs
HIGH level pulse width rejection or INTn inputs
10
—
—
1
—
—
H
500
500
pwr
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical R and and the 15 pF load capacitance.
ON
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
of the SCL signal) in order to bridge
IH(min)
the undefined region of the falling edge of SCL.
3. C = total capacitance of one bus line in pF.
b
SDA
t
R
t
F
t
t
SP
HD;STA
t
t
LOW
BUF
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
SU00645
2
Figure 14. Definition of timing on the I C-bus
12
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
13
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
14
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals;
body 5 x 5 x 0.85 mm
SOT662-1
15
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
REVISION HISTORY
Rev
Date
Description
_10
20040929
Product data sheet (9397 750 14113). Supersedes data of 2002 Jul 26 (9397 750 10162).
Modifications:
• Table 1 “Control Register; Write—Channel Selection / Read—Channel Status” on page 5:
add ‘No channel selected; power-up default state’ row to bottom of table.
_9
_8
20020726
20020220
Product data (9397 750 10162). ECN 853-2178 28672 of 20 February 2002.
Supersedes data of 2002 Feb 20.
16
2004 Sep 29
Philips Semiconductors
Product data sheet
4-channel I2C multiplexer with interrupt logic
PCA9544
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data sheet
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data sheet
Product data sheet
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Published in the U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 09-04
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document number:
9397 750 14113
Philips
Semiconductors
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