PCA9557BS [NXP]
8-bit I2C-bus and SMBus I/O port with reset; 8位I2C总线和复位的SMBus I / O端口型号: | PCA9557BS |
厂家: | NXP |
描述: | 8-bit I2C-bus and SMBus I/O port with reset |
文件: | 总26页 (文件大小:154K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PCA9557
8-bit I2C-bus and SMBus I/O port with reset
Rev. 06 — 11 June 2008
Product data sheet
1. General description
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for
SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register,
8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption
and a high-impedance open-drain output pin, IO0.
The system master can enable the PCA9557’s I/O as either input or output by writing to
the configuration register. The system master can also invert the PCA9557 inputs by
writing to the active HIGH polarity inversion register. Finally, the system master can reset
the PCA9557 in the event of a time-out by asserting a LOW in the reset input.
The power-on reset puts the registers in their default state and initializes the
I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to
occur without de-powering the part.
2. Features
I Lower voltage, higher performance migration path for the PCA9556
I 8 general purpose input/output expander/collector
I Input/output configuration register
I Active HIGH polarity inversion register
I I2C-bus and SMBus interface logic
I Internal power-on reset
I Noise filter on SCL/SDA inputs
I Active LOW reset input
I 3 address pins allowing up to 8 devices on the I2C-bus/SMBus
I High-impedance open-drain on IO0
I No glitch on power-up
I Power-up with all channels configured as inputs
I Low standby current
I Operating power supply voltage range of 2.3 V to 5.5 V
I 5 V tolerant inputs/outputs
I 0 kHz to 400 kHz clock frequency
I ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Three packages offered: SO16, TSSOP16, HVQFN16
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
PCA9557D
PCA9557PW
PCA9557BS
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
HVQFN16 plastic thermal enhanced very thin quad flat package; SOT629-1
no leads; 16 terminals; body 4 × 4 × 0.85 mm
3.1 Ordering options
Table 2.
Ordering options
Type number
PCA9557D
PCA9557PW
PCA9557BS
Topside mark
PCA9557D
PCA9557
9557
Temperature range
Tamb = −40 °C to +85 °C
Tamb = −40 °C to +85 °C
Tamb = −40 °C to +85 °C
4. Block diagram
PCA9557
A0
A1
A2
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
8-bit
SCL
SDA
INPUT
FILTER
INPUT/
OUTPUT
PORTS
2
I C-BUS/SMBus
CONTROL
write pulse
read pulse
V
DD
POWER-ON
RESET
V
SS
RESET
002aad275
Fig 1. Block diagram of PCA9557
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
2 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
data from
shift register
configuration
register
data from
shift register
D
Q
output port
register data
FF
write configuration
pulse
D
Q
CK
Q
FF
IO0
write pulse
CK
ESD protection
diode
output port
register
V
SS
input port
register
D
Q
input port
register data
FF
CK
read pulse
polarity inversion
register
data from
shift register
polarity inversion
register data
D
Q
FF
write polarity
pulse
CK
002aad277
On power-up or reset, all registers return to default values.
Fig 2. Simplified schematic of IO0
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
3 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
data from
shift register
output port
register data
configuration
register
V
DD
data from
shift register
D
Q
ESD protection
diode
FF
write configuration
pulse
D
Q
CK
Q
FF
IO1 to IO7
write pulse
CK
ESD protection
diode
output port
register
V
SS
input port
register
D
Q
input port
register data
FF
CK
read pulse
polarity inversion
register
data from
shift register
polarity inversion
register data
D
Q
FF
write polarity
pulse
CK
002aad278
On power-up or reset, all registers return to default values.
Fig 3. Simplified schematic of IO1 to IO7
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
4 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
5. Pinning information
5.1 Pinning
1
16
15
14
13
12
11
10
9
SCL
SDA
A0
V
DD
2
3
4
5
6
7
8
RESET
IO7
1
2
3
4
5
6
7
8
16
15
14
13
SCL
SDA
A0
V
DD
RESET
IO7
A1
IO6
PCA9557D
A2
IO5
A1
IO6
PCA9557PW
12 IO5
IO0
IO1
IO4
A2
11
10
9
IO0
IO1
IO4
IO3
IO2
IO3
V
SS
IO2
V
SS
002aad272
002aad273
Fig 4. Pin configuration for SO16
Fig 5. Pin configuration for TSSOP16
terminal 1
index area
1
2
3
4
12
11
10
9
A0
A1
IO7
IO6
IO5
IO4
PCA9557BS
A2
IO0
002aad274
Transparent top view
Fig 6. Pin configuration for HVQFN16
5.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
SO16, TSSOP16
HVQFN16
SCL
SDA
A0
1
2
3
4
5
6
7
15
16
1
serial clock line
serial data line
address input 0
address input 1
address input 2
input/output 0 (open-drain)
input/output 1
A1
2
A2
3
IO0
IO1
4
5
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
5 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
Table 3.
Pin description …continued
Symbol
Pin
Description
SO16, TSSOP16
HVQFN16
VSS
IO2
8
6[1]
supply ground
input/output 2
input/output 3
input/output 4
input/output 5
input/output 6
input/output 7
active LOW reset input
supply voltage
9
7
IO3
10
11
12
13
14
15
16
8
IO4
9
IO5
10
11
12
13
14
IO6
IO7
RESET
VDD
[1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to the supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
6. System diagram
INPUT
PORT
POLARITY
INVERSION
CONFIG.
Q7
OUTPUT
PORT
1.1 kΩ
1.1 kΩ
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
IO0
RESET
Q6
Q5
Q4
Q3
Q2
Q1
Q0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
1.6 kΩ
SCL
2
I C-BUS/SMBus
1.6 kΩ
1.1 kΩ
1.1 kΩ
1.1 kΩ
INTERFACE
LOGIC
SDA
A2
or
or
or
A1
A0
002aad276
Fig 7. System diagram
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
6 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
7. Functional description
Refer to Figure 1 “Block diagram of PCA9557”.
7.1 Device address
Following a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9557 is shown in Figure 8. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
slave address
0
0
1
1
A2 A1 A0 R/W
fixed
programmable
002aad279
Fig 8. PCA9557 device address
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
7.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9557, which will be stored in the control register. This register can be
written and read via the I2C-bus.
bit:
7
0
6
0
5
0
4
0
3
0
2
0
1
0
D1 D0
002aad280
Fig 9. Control register
Table 4.
Register definition
D1
0
D0
0
Name
Access
Description
Register 0
Register 1
Register 2
Register 3
read-only
read/write
read/write
read/write
Input port register
Output port register
Polarity inversion register
Configuration register
0
1
1
0
1
1
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
7 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
7.3 Register descriptions
7.3.1 Register 0 - Input port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by the Configuration register. Writes
to this register have no effect.
Table 5.
Bit
Register 0 - Input port register bit allocation
7
6
5
4
3
2
1
0
Symbol
I7
I6
I5
I4
I3
I2
I1
I0
7.3.2 Register 1 - Output port register
This register reflects the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs.
In turn, reads from this register reflect the value that is in the flip-flop controlling the output
selection, not the actual pin value.
Table 6.
Bit
Register 1 - Output port register bit allocation
7
O7
0
6
O6
0
5
O5
0
4
O4
0
3
O3
0
2
O2
0
1
O1
0
0
O0
0
Symbol
Default
7.3.3 Register 2 - Polarity inversion register
This register enables polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with logic 1), the corresponding port pin’s
polarity is inverted. If a bit in this register is cleared (written with logic 0), the
corresponding port pin’s original polarity is retained.
Table 7.
Bit
Register 2 - Polarity inversion register bit allocation
7
N7
1
6
N6
1
5
N5
1
4
N4
1
3
N3
0
2
N2
0
1
N1
0
0
N0
0
Symbol
Default
7.3.4 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output.
Table 8.
Bit
Register 3 - Configuration register bit allocation
7
C7
1
6
C6
1
5
C5
1
4
C4
1
3
C3
1
2
C2
1
1
C1
1
0
C0
1
Symbol
Default
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
8 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
7.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9557 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9557 registers and I2C-bus/SMBus state machine will initialize to their default
states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
7.5 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9557 registers and SMBus/I2C-bus state machine will be held in their default state
until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if
no active connection is used.
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 10).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 10. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 11).
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
9 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
SDA
SCL
SDA
SCL
S
P
STOP condition
mba608
START condition
Fig 11. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 12).
SDA
SCL
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
2
SLAVE
RECEIVER
MASTER
TRANSMITTER
I C-BUS
MULTIPLEXER
SLAVE
002aaa966
Fig 12. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
10 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
data output
by transmitter
not acknowledge
acknowledge
data output
by receiver
SCL from master
1
2
8
9
S
clock pulse for
START
condition
acknowledgement
002aaa987
Fig 13. Acknowledgement on the I2C-bus
8.4 Bus transactions
Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figure 14
and Figure 15). Data is read from the PCA9557 registers using Read and Receive Byte
transfers (see Figure 16 and Figure 17).
SCL
1
2
3
4
5
6
7
8
9
STOP
condition
slave address
A2 A1 A0
command byte
data to port
DATA 1
SDA
S
0
0
1
1
0
A
0
0
0
0
0
0
0
1
A
A
P
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
write to port
t
v(Q)
data out from port
DATA 1 VALID
002aad281
Fig 14. Write to output port register
SCL
1
2
3
4
5
6
7
8
9
STOP
condition
slave address
A2 A1 A0
command byte
data to register
DATA
SDA
S
0
0
1
1
0
A
0
0
0
0
0
0
1
1/0
A
A
P
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
002aad282
Fig 15. Write to I/O configuration or polarity inversion registers
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
11 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
slave address
command byte
(cont.)
SDA
S
0
0
1
1
A2 A1 A0
0
A
A
START condition
R/W
acknowledge
from slave
acknowledge
from slave
slave address
data from register
DATA (first byte)
data from register
(cont.)
S
0
0
1
1
A2 A1 A0
1
A
A
DATA (last byte)
NA P
(repeated)
START condition
R/W
acknowledge
from master
no acknowledge STOP
from master condition
acknowledge
from slave
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
002aad283
Fig 16. Read from register
no acknowledge
from master
slave address
A2 A1 A0
data from port
DATA 1
data from port
DATA 4
SDA
S
0
0
1
1
1
A
A
NA
P
START condition
R/W acknowledge
from slave
acknowledge
from master
STOP
condition
read from
port
t
t
su(D)
h(D)
data into
port
DATA 1
DATA 2
DATA 3
DATA 4
002aad284
Remark: This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge
phase is valid (output mode). Input data is lost.
Fig 17. Read input port register
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
12 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
9. Application design-in information
V
(5 V)
DD
100 kΩ
(× 5)
620 Ω
1.8 kΩ
1.8 kΩ
2 kΩ
2 kΩ
V
V
DD
DD
MASTER
CONTROLLER
PCA9557
SUBSYSTEM 1
IO0
(e.g., temp. sensor)
SCL
SCL
SDA
INT
SDA
IO1
IO2
IO3
IO4
IO5
IO6
IO7
RESET
RESET
RESET
SUBSYSTEM 2
(e.g., counter)
V
SS
A
controlled switch
(e.g., CBT device)
enable
A2
A1
A0
B
V
SS
ALARM
SUBSYSTEM 3
(e.g., alarm system)
V
DD
002aad285
Device address configured as 0011 100x for this example.
IO0, IO2, IO3 configured as outputs.
IO1, IO4, IO5 configured as inputs.
IO6, IO7 are not used.
Fig 18. Typical application
9.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 18. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD
.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 19 shows a high value resistor in parallel with the LED. Figure 20 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI
at or above VDD and prevents additional supply current consumption when the LED is off.
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
13 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
3.3 V
5 V
V
DD
V
100 kΩ
V
DD
DD
LED
LED
IOn
IOn
002aac660
002aac661
Fig 19. High value resistor in parallel with
the LED
Fig 20. Device supplied by a lower voltage
10. Limiting values
Table 9.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
Parameter
Conditions
Min
Max
+6
Unit
V
supply voltage
input voltage
input current
−0.5
VI
V
-
SS − 0.5
5.5
V
II
±20
±400
mA
µA
IIHL(max)
maximum allowed input current
VI ≥ VDD or VI ≤ VSS
-
through protection diode (IO1 to IO7)
VI/O
voltage on an input/output pin
input/output current
I/O as an input, except IO0
IO0 as an input
V
V
-
SS − 0.5
SS − 0.5
5.5
V
5.5
V
II/O
IO0 as an input
+400
−20
±50
85
µA
mA
mA
mA
mA
mW
°C
-
IO(IOn)
IDD
output current on pin IOn
supply current
-
-
ISS
ground supply current
total power dissipation
storage temperature
ambient temperature
-
100
200
+150
+85
Ptot
-
Tstg
Tamb
−65
−40
operating
°C
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
14 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
11. Static characteristics
Table 10. Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Supplies
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
supply current
2.3
-
-
5.5
25
V
IDD
operating mode; VDD = 5.5 V;
no load; fSCL = 100 kHz
19
µA
IstbL
LOW-level standby current
standby mode; VDD = 5.5 V;
no load; VI = VSS; fSCL = 0 kHz;
I/O = inputs
-
-
-
-
0.25
0.25
0.8
1
µA
µA
mA
V
IstbH
∆Istb
VPOR
HIGH-level standby current standby mode; VDD = 5.5 V;
no load; VI = VDD; fSCL = 0 kHz;
I/O = inputs
1
additional standby current
standby mode; VDD = 5.5 V;
every LED I/O at VI = 4.3 V;
1
fSCL = 0 kHz
[1]
power-on reset voltage
no load; VI = VDD or VSS
1.65
2.1
Input SCL; input/output SDA
VIL
VIH
IOL
IL
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
leakage current
−0.5
-
+0.3VDD
V
0.7VDD
-
5.5
-
V
VOL = 0.4 V
VI = VDD or VSS
VI = VSS
3
-
mA
µA
pF
−1
-
-
+1
10
Ci
input capacitance
6
I/Os
VIL
VIH
IOL
IOH
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
HIGH-level output current
−0.5
-
+0.8
V
2.0
-
5.5
V
[2]
[3]
8
4
-
10
-
-
mA
mA
µA
µA
µA
pF
pF
except pin IO0; VOH = 2.4 V
pin IO0; VOH = 4.6 V
pin IO0; VOH = 3.3 V
VDD = 5.5 V; VI = VSS
-
-
1
-
-
1
ILI
Ci
Co
input leakage current
input capacitance
output capacitance
-
-
−100
-
3.7
3.7
5
5
-
Select inputs A0, A1, A2 and RESET
VIL
VIH
ILI
LOW-level input voltage
HIGH-level input voltage
input leakage current
−0.5
2.0
−1
-
-
-
+0.8
5.5
+1
V
V
µA
[1] VDD must be lowered to 0.2 V in order to reset part.
[2] The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit.
[3] The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit.
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
15 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
12. Dynamic characteristics
Table 11. Dynamic characteristics
Symbol Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode I2C-bus Unit
Min
0
Max
100
-
Min
0
Max
400
-
fSCL
tBUF
SCL clock frequency
kHz
bus free time between a STOP and
START condition
4.7
1.3
µs
tHD;STA
tSU;STA
hold time (repeated) START condition
4.0
4.7
-
-
0.6
0.6
-
-
µs
µs
set-up time for a repeated START
condition
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
tSU;DAT
tLOW
tHIGH
tf
set-up time for STOP condition
data hold time
4.0
-
0.6
-
-
µs
ns
µs
ms
ns
µs
µs
ns
ns
ns
0
-
0
[1]
[2]
data valid acknowledge time
data valid time
-
-
1
-
0.9
0.9
-
1
-
data set-up time
250
4.7
4.0
-
-
-
100
1.3
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
-
-
0.6
-
[3]
[3]
300
1000
50
20 + 0.1Cb
20 + 0.1Cb
-
300
300
50
tr
-
tSP
pulse width of spikes that must be
suppressed by the input filter
-
Port timing
tv(Q)
data output valid time
pin IO0
-
-
250
-
-
250
ns
ns
ns
ns
pins IO1 to IO7
200
200
tsu(D)
th(D)
Reset timing
data input set-up time
0
-
-
0
-
-
data input hold time
200
200
tw(rst)
trec(rst)
trst
reset pulse width
6
0
-
-
-
6
0
-
-
-
ns
ns
ns
reset recovery time
reset time
400
400
[1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3] Cb = total capacitance of one bus line in pF.
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
16 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
SDA
t
t
t
t
SP
t
r
f
HD;STA
BUF
t
LOW
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
002aaa986
Fig 21. Definition of timing on the I2C-bus
ACK or read cycle
START
SCL
SDA
30 %
t
rst
RESET
50 %
50 %
50 %
t
rec(rst)
t
w(rst)
t
rst
I/O configured
as inputs
IOn
50 %
002aad289
Fig 22. Definition of RESET timing
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
17 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
13. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 23. Package outline SOT109-1 (SO16)
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
18 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 24. Package outline SOT403-1 (TSSOP16)
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
19 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 4 x 4 x 0.85 mm
SOT629-1
B
A
D
terminal 1
index area
A
A
1
E
c
detail X
e
1
C
1/2 e
y
y
e
v
M
M
b
C
C
A B
C
1
w
5
8
L
9
4
1
e
e
E
h
2
1/2 e
12
terminal 1
index area
16
13
X
D
h
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
E
e
e
1
e
2
y
D
D
E
L
v
w
y
1
1
h
h
max.
0.05 0.38
0.00 0.23
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.75
0.50
mm
0.05
0.1
1
0.2
0.65
1.95 1.95
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-22
SOT629-1
- - -
MO-220
- - -
Fig 25. Package outline SOT629-1 (HVQFN16)
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
20 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
14. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe you must take normal precautions appropriate to handling
integrated circuits.
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
© NXP B.V. 2008. All rights reserved.
PCA9557
Product data sheet
Rev. 06 — 11 June 2008
21 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 26) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
235
≥ 350
220
< 2.5
≥ 2.5
220
220
Table 13. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 26.
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
22 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 26. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Abbreviations
Table 14. Abbreviations
Acronym
CBT
Description
Cross Bar Technology
Charged-Device Model
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
CDM
CMOS
ESD
HBM
I2C-bus
I/O
Inter-Integrated Circuit bus
Input/Output
LED
Light-Emitting Diode
MM
Machine Model
PCB
Printed-Circuit Board
Power-On Reset
POR
SMBus
System Management Bus
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
23 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
17. Revision history
Table 15. Revision history
Document ID
PCA9557_6
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20080611
Product data sheet
-
PCA9557_5
• Section 2 “Features”, 17th bullet item: changed from “200 V MM” to “150 V MM”
• Table 11 “Dynamic characteristics”, sub-section “Reset timing”: changed Min value for tw(rst) from
“4 ns” to “6 ns” (for both Standard-mode and Fast-mode)
• Updated soldering information
PCA9557_5
20070912
Product data sheet
-
-
PCA9557_4
PCA9557_3
PCA9557_4
20041124
Product data sheet
(9397 750 13336)
PCA9557_3
(9397 750 10872)
20021213
20020513
20011212
Product data
Product data
Product data
ECN 853-2308 29160
of 06 Nov 2002
PCA9557_2
PCA9557_1
-
PCA9557_2
(9397 750 09819)
ECN 853-2308 28188
of 13 May 2002
PCA9557_1
ECN 853-2308 27449
of 12 Dec 2001
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
24 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
to result in personal injury, death or severe property or environmental
18.2 Definitions
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9557
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 June 2008
25 of 26
PCA9557
NXP Semiconductors
8-bit I2C-bus and SMBus I/O port with reset
20. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
18.4
19
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Contact information . . . . . . . . . . . . . . . . . . . . 25
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3
3.1
4
20
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
System diagram . . . . . . . . . . . . . . . . . . . . . . . . . 6
7
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
Functional description . . . . . . . . . . . . . . . . . . . 7
Device address. . . . . . . . . . . . . . . . . . . . . . . . . 7
Control register . . . . . . . . . . . . . . . . . . . . . . . . . 7
Register descriptions . . . . . . . . . . . . . . . . . . . . 8
Register 0 - Input port register . . . . . . . . . . . . . 8
Register 1 - Output port register. . . . . . . . . . . . 8
Register 2 - Polarity inversion register . . . . . . . 8
Register 3 - Configuration register . . . . . . . . . . 8
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9
RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.5
8
Characteristics of the I2C-bus. . . . . . . . . . . . . . 9
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
START and STOP conditions . . . . . . . . . . . . . . 9
System configuration . . . . . . . . . . . . . . . . . . . 10
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11
8.1
8.1.1
8.2
8.3
8.4
9
9.1
Application design-in information . . . . . . . . . 13
Minimizing IDD when the I/Os are used to
control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10
11
12
13
14
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
Static characteristics. . . . . . . . . . . . . . . . . . . . 15
Dynamic characteristics . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Handling information. . . . . . . . . . . . . . . . . . . . 21
15
Soldering of SMD packages . . . . . . . . . . . . . . 21
Introduction to soldering . . . . . . . . . . . . . . . . . 21
Wave and reflow soldering . . . . . . . . . . . . . . . 21
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22
15.1
15.2
15.3
15.4
16
17
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
18.1
18.2
18.3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 June 2008
Document identifier: PCA9557
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