PCA9702PW/Q900 [NXP]
18 V tolerant SPI 16-bit/8-bit GPI with INT; 18 V电压SPI 16位/ 8位GPI与INT
| 型号： | PCA9702PW/Q900 |
| 厂家： | 
NXP |
| 描述： | 18 V tolerant SPI 16-bit/8-bit GPI with INT |
| 文件： | 总28页 (文件大小：428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9701; PCA9702
18 V tolerant SPI 16-bit/8-bit GPI with INT
Rev. 05 — 11 November 2009
Product data sheet
1. General description
The PCA9701/PCA9702 are low power 18 V tolerant SPI General Purpose Input (GPI)
shift register designed to monitor the status of switch inputs. It generates an interrupt
when one or more of the switch inputs change state. The input level is recognized as a
HIGH when it is greater than 0.7 × VDD and as a LOW when it is less than 0.4 × VDD
(minimum threshold of 2 V at 5 V node). The PCA9701 can monitor up to 16 switch inputs
and the PCA9702 can monitor up to 8 switch inputs.
The falling edge of the CS pin samples the input port status and clears the interrupt. When
CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of
the shift register. The serial input is sampled on the falling edge of SCLK.
Each of the input ports has a 18 V breakdown ESD protection circuit. When used with a
series resistor (minimum 100 kΩ), the input can connect to a 12 V battery and support
double battery, reverse battery, 27 V jump start and 40 V load dump conditions in
automotive applications. Higher voltages can be tolerated on the inputs depending on the
series resistor used to limit the input current.
With both the high breakdown voltage and high ESD, these devices are useful for both
automotive (AEC-Q100 compliance available) and mobile applications.
The PCA9703/PCA9704 are new pin compatible devices for the PCA9701/PCA9702
which have an interrupt masking feature allowing selected inputs to not generate
interrupts and provides higher ground offset of 0.55 × VDD (minimum of 2.5 V at 5 V node)
with minimum hysteresis of 0.05 × VDD (minimum of 225 mV at 5 V node).
2. Features
I 16 general purpose input ports (PCA9701) or 8 general purpose input ports
(PCA9702)
I 18 V tolerant input ports with 100 kΩ external series resistor
I Input LOW threshold 0.4 × VDD with minimum of 2 V at VDD = 4.5 V
I Open-drain interrupt output
I Interrupt enable pin (INT_EN) disables interrupt output
I VDD range: 2.5 V to 5.5 V
I IDD is very low 2.5 µA maximum
I SPI serial interface with speeds up to 5 MHz
I AEC-Q100 compliance available
I ESD protection exceeds 8 kV HBM per JESD22-A114, 350 V MM per AEC-Q100, and
1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
I Operating temperature range: −40 °C to +125 °C
I PCA9701 offered in SO24, TSSOP24 and HWQFN24 packages
I PCA9702 offered in TSSOP16 package
3. Applications
I Body control modules
I Switch monitoring
I Industrial equipment
I Cellular telephones
I Emergency lighting
I SBC wake pin extension
4. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA9701D
PCA9701HF
PCA9701PW
PCA9701D
9701
SO24
plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
HWQFN24 plastic thermal enhanced very very thin quad flat
SOT994-1
SOT355-1
SOT355-1
SOT403-1
SOT403-1
package; no leads; 24 terminals; body 4 × 4 × 0.75 mm
PCA9701PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
PCA9701PW/Q900[1] PCA9701PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
PCA9702PW
PCA9702
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
PCA9702PW/Q900[2] PCA9702
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
[1] PCA9701PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP.
[2] PCA9702PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP.
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
2 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
5. Block diagram
V
DD
PCA9701/PCA9702
INT
INT_EN
IN0
IN1
DFF0
DFF1
SHIFT
REGISTER
SDOUT
SDIN
SCLK
CS
(1)
(1)
INn
DFFn
INPUT
STATUS
REGISTER
20 µA
002aac422
V
SS
(1) n = 15 for PCA9701; n = 7 for PCA9702
Fig 1. Block diagram of PCA9701; PCA9702
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
3 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
6. Pinning information
6.1 Pinning
1
2
24
23
22
21
20
19
18
17
16
15
14
13
1
2
24
23
22
21
20
19
18
17
16
15
14
13
SDOUT
INT
V
SDOUT
INT
V
DD
DD
SDIN
SCLK
CS
SDIN
SCLK
CS
3
3
INT_EN
IN0
INT_EN
IN0
4
4
5
5
IN1
IN15
IN14
IN13
IN12
IN11
IN10
IN9
IN1
IN15
IN14
IN13
IN12
IN11
IN10
IN9
6
6
IN2
IN2
PCA9701PW
PCA9701PW/Q900
PCA9701D
7
7
IN3
IN3
8
8
IN4
IN4
9
9
IN5
IN5
10
11
12
10
11
12
IN6
IN6
IN7
IN7
V
SS
IN8
V
SS
IN8
002aac636
002aac424
Fig 2. Pin configuration for SO24
Fig 3. Pin configuration for TSSOP24
terminal 1
index area
1
2
3
4
5
6
18
CS
IN0
IN1
IN2
IN3
IN4
IN5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SDOUT
INT
V
17
16
15
14
13
IN15
IN14
IN13
IN12
IN11
DD
SDIN
SCLK
CS
PCA9701HF
INT_EN
IN0
PCA9702PW
PCA9702PW/Q900
IN1
IN7
IN2
IN6
IN3
IN5
002aad050
V
SS
IN4
002aac425
Transparent top view
Fig 4. Pin configuration for HWQFN24
Fig 5. Pin configuration for TSSOP16
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
4 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
6.2 Pin description
Table 2.
Symbol
Pin description
Pin
Type
Description
SO24, TSSOP24 HWQFN24 TSSOP16
SDOUT
INT
1
2
3
22
23
24
1
2
3
output
output
input
3-state serial data output; normally high-impedance
open-drain interrupt output (active LOW)
interrupt output enable
1 = interrupt is enabled
0 = interrupt is disabled and high-impedance
input port 0
INT_EN
IN0
4
1
4
input
input
input
input
input
input
input
input
ground
input
input
input
input
input
input
input
input
input
input
input
supply
IN1
5
2
5
input port 1
IN2
6
3
6
input port 2
IN3
7
4
7
input port 3
IN4
8
5
9
input port 4
IN5
9
6
10
11
12
8
input port 5
IN6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
input port 6
IN7
8
input port 7
VSS
IN8
9[1]
10
11
12
13
14
15
16
17
18
19
20
21
ground supply
-
input port 8
IN9
-
input port 9
IN10
IN11
IN12
IN13
IN14
IN15
CS
-
input port 10
-
input port 11
-
input port 12
-
input port 13
-
input port 14
-
input port 15
13
14
15
16
chip select (active LOW)
serial input clock
serial data input (20 µA pull-down)
supply voltage
SCLK
SDIN
VDD
[1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
5 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
7. Functional description
PCA9701 is a 16-bit General Purpose Input (GPI) with an open-drain interrupt output
designed to monitor switch status. By putting an external 100 kΩ series resistor at the
input port, the device allows the input to tolerate momentary double 12 V battery, reverse
battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted
when an input port status changes. The open-drain interrupt output is enabled when
INT_EN is HIGH and disabled when INT_EN is LOW. The input port status is accessed
via the 4-wire SPI interface. The PCA9702 is the 8-bit version of the PCA9701.
Multiple PCA9701 or PCA9702 devices can be serially connected for monitoring a large
number of switches by connecting the SDOUT of one device to the SDIN of the next
device. SCLK and CS must be common among all devices and interrupt outputs may be
tied together. No external logic is necessary because all the devices’ interrupt outputs are
open-drain that function as ‘wired-AND’ and can simply be connected together to a single
pull-up resistor.
7.1 SPI bus operation
The PCA9701 or PCA9702 interfaces with the controller via the 4-wire SPI bus that is
comprised of the following signals: chip select (CS), serial clock (SCLK), serial data in
(SDIN), and serial data out (SDOUT). To access the device, the controller asserts CS
LOW, then sends SCLK and SDIN. When reading/writing is complete, the controller
de-asserts CS. See Figure 6 for register access timing.
7.1.1 CS - chip select
The CS pin is the device chip select and is an active LOW input. The falling edge of CS
captures the input port status in the input status register. If the interrupt output is asserted,
the falling edge of CS will clear the interrupt. When CS is LOW, the SPI interface is active.
When CS is HIGH, the SPI interface is disabled.
7.1.2 SCLK - serial clock input
SCLK is the serial clock input to the device. It should be LOW and remain LOW during the
falling and rising edge of CS. When CS is LOW, the first rising edge of SCLK parallel loads
the shift register from the input. The subsequent rising edges on SCLK serially shifts data
out from the shift register. The falling edge of SCLK samples the data on SDIN.
7.1.3 SDIN - serial data input
SDIN is the serial data input port. The data is sampled into the shift register on the falling
edge of SCLK. SDIN is only active when CS is LOW. This input has a 20 µA pull-down
current source.
7.1.4 SDOUT - serial data output
SDOUT is the serial data output signal. SDOUT is high-impedance when CS is HIGH and
switches to low-impedance after CS goes LOW. When CS is LOW, after the first rising
edge of SCLK the most significant bit in the shift register is presented on SDOUT.
Subsequent rising edges of SCLK shift the remaining data from the shift register onto
SDOUT.
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
6 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
7.1.5 Register access timing
Figure 6 shows the waveforms of the device operation. Initially CS is HIGH and SCLK is
LOW. On the falling edge of CS, input port status, DATA[n:0] is captured into the input
status register, and subsequently the first rising edge of SCLK parallel loads the shift
register. The falling edge of SCLK samples the data on the SDIN. The MSB from the shift
register is valid and available on the SDOUT after the first rising edge of SCLK.
sample
SDIN
CS
SCLK
SDIN
MSB in
MSB − 1 in
LSB in
high-impedance
SDOUT
MSB out
MSB − 1 out
LSB out
shift
register
DATA[n:0]
input status
register
DATA[n:0]
002aac426
DATA[n:0] is data on the input pins, IN[n:0].
For 8-bit GPI (PCA9702), n = 7; for 16-bit GPI (PCA9701), n = 15.
Shaded areas indicate active but invalid data.
Fig 6. Register access timing
7.2 Interrupt output
INT is the open-drain interrupt output and is active LOW. A pull-up resistor of
approximately 10 kΩ is recommended. The interrupt output is asserted when the input
status is changed, and is cleared on the falling edge of CS or when the input port status
matches the input status register. When there are multiple devices, the INT outputs may
be tied together to a single pull-up.
Table 3 illustrates the state of the interrupt output versus the state of the input port and
input status register. The interrupt output is asserted when the input port and input status
register differ.
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
7 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
Table 3.
Interrupt output function truth table
H = HIGH; L = LOW; X = don’t care
INT_EN
Input port status
Input status register[1]
INT output[2]
H
H
H
H
L
L
L
H
L
L
H
L
H
H
X
L
H
X
H
H
[1] Input status register is the value or content of the D flip-flops.
[2] Logic states shown for INT pin assumes 10 kΩ pull-up resistor.
7.3 General Purpose Inputs
The General Purpose Inputs (GPI) are designed to behave like a typical input in the 0 V to
5.5 V range, but are also designed to have low leakage currents at elevated voltages. The
input structure allows for elevated voltages to be applied through a series resistor. The
series resistor is required when the input voltage is above 5.5 V. The series resistor is
required for two reasons: first, to prevent damage to the input avalanche diode, and
second, to prevent the ESD protection circuitry from creating an excessive current flow.
The ESD protection circuitry includes a latch-back style device, which provides excellent
ESD protection during assembly or typical 5.5 V applications. The series resistor limits the
current flowing into the part and provides additional ESD protection. The limited current
prevents the ESD latch-back device from latching back to a low voltage, which would
cause excessive current flow and damage the part.
The minimum required series resistance for applications with input voltages above 5.5 V is
100 kΩ. For applications requiring an applied voltage above 27 V, Equation 1 is
recommended to determine the series resistor. Failure to include the appropriate input
series resistor may result in product failure and will void the warranty.
voltage applied – 17 V
Rs =
(1)
------------------------------------------------------------
II
The series resistor should be placed physically as close as possible to the connected
input to reduce the effective node capacitance. The input response time is effected by the
RC time constant of the series resistor and the input node capacitance.
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
8 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
7.3.1 VIL, VIH and switching points
A minimum LOW threshold of 2.0 V is guaranteed for the logical switching points for the
inputs. See Figure 7 for details.
V
I
HIGH
V
DD
0.7V
0.4V
DD
DD
V
IH
V
IL
hysteresis
minimum
possible ground shift
LOW
0 V
002aae128
Fig 7. Logic level thresholds for general purpose inputs
The VIL is specified as a maximum of 0.40 × VDD and is 2.0 V at 4.5 V VDD. This means
that if the user applies 2.0 V or less to the input (with VDD = 4.5 V), or as the voltage
passes this threshold, they will always see a LOW.
The VIH is specified as a minimum of 0.7 × VDD. This means that if the user applies 3.15 V
or more to the input (with VDD = 4.5 V), or as the voltage passes this threshold, they will
always see a HIGH.
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
9 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
8. Application design-in information
8.1 General application
2.5 V to 5.5 V
18 V
1.5 kΩ
100 kΩ
V
DD
IN0
10 kΩ
relay
INT
CS
CONTROLLER
OR
PROCESSOR
SCLK
SDIN
18 V
SDOUT
100 kΩ
INT_EN
IN1
IN2
180 V
open
PCA9701/
PCA9702
500 kΩ
50 kΩ
5 V
10 kΩ
(1)
INn
V
SS
002aac423
(1) n = 15 for PCA9701; n = 7 for PCA9702
Fig 8. Typical application
8.2 Automotive application
Supports:
• 12 V battery (8 V to 16 V)
• Double battery (16 V to 32 V)
• Reverse battery (−8 V to −16 V)
• Jump start (27 V for 60 seconds)
• Load dump (40 V)
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
10 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1 SBC wake port extension with cyclic biasing
System Basis Chips (SBC) offer many functions needed for in-vehicle networking
solutions. Some of the features built into SBC are:
• Transceivers (HS-CAN, LIN 2.0)
• Scalable voltage regulators
• Watchdog timers; wake-up function
• Fail-safe function
For more information on SBC, refer to
http://www.nxp.com/index.html#/pip/pip=[pfp=53482]|pp=[t=pfp,i=53482].
8.2.1.1 UJA106x with PCA9701, standby
V3
alternate
PVR100AD-B5V0
UJA106x
WAKE
IN0
IN1
INT
V1 GND
INT_EN
PCA9701
V
DD
CS
SDIN
V
CC
SDOUT
SCLK
IN15
CSN
V
µC
SS
MOSI
MISO
SCLK
GND
002aae016
Fig 9. UJA106x with PCA9701 with supplied µC (standby)
• PCA970x fits to SBC UJA106x and UJA107x family
• PCA970x can be powered by V1 of SBC
• Extends the SBC with 8/16 additional wake inputs
• µC can be set to stop-mode during standby to save ECU standby current. SBC with
GPI periodically monitors the wake inputs
– Cyclic bias via V3
– Very low system current consumption even with clamped switches
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
11 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1.2 UJA106x with PCA9701, sleep
alternate
alternate
PVR100AD-B5V0
PMEM4010ND
V3
UJA106x
WAKE
V
DD
IN0
IN1
INT_EN
INT
RSTN
V1 GND
alternate
PDTC144TU
PCA9701
CS
SDIN
V
CC
SDOUT
SCLK
IN15
CSN
V
µC
SS
MOSI
MISO
SCLK
GND
002aae017
Fig 10. UJA106x with PCA9701 with unsupplied µC (sleep)
• Very low quiescent system current (50 µA) due to disabled µC and cyclically biasing
of switches
• Wake-up upon change of switches or upon bus traffic (CAN and LIN)
• PCA970x supplied out of cyclically biased transistor regulator
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
12 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
8.2.1.3 UJA107x with PCA9701, standby
BAT
alternate
PDTA144EU
BAT
WBIAS
UJA107x
WAKE
V1
IN0
IN1
INT
GND
INT_EN
PCA9701
V
DD
CS
SDIN
V
CC
SDOUT
SCLK
IN15
CSN
V
µC
SS
MOSI
MISO
SCLK
GND
002aae018
Fig 11. UJA107x with PCA9701 with supplied µC (standby)
• UJA107x SBC provides WBIAS pin for cyclic biasing of the inputs
• Compatible with UJA107x based ASSPs
8.2.2 Application examples including switches to battery
BAT BAT
switch bias
switch bias
IN0
IN1
IN0
IN1
PCA9701
PCA9701
clamp 15
IN15
IN15
002aae019
002aae020
Fig 12. Clamp 15 (ignition) detection
Fig 13. Switches to battery and ground with
cyclic biasing
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
13 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
9. Limiting values
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134).
amb = −40 °C to +125 °C, unless otherwise specified.
Limiting values
T
Symbol
Parameter
Conditions
Min
−0.5
-
Max
+6.0
350
Unit
V
VDD
II
supply voltage
input current
[1][2]
[1][2]
IN[n:0] pins with series resistor
and VI > 5.5 V,
µA
VI
input voltage
GPI pins IN[n:0]; no series resistor
SPI pins
−0.5
−0.5
−65
-
+6
V
+6
V
Tstg
storage temperature
+150
125
°C
°C
Tj(max)
maximum junction temperature
operating
[1] With GPI external series resistors, the inputs support double battery, reverse battery and load dump conditions. During double battery or
load dump the input pin will drain slightly higher leakage current until the input drops to 18 V. For more detail of leakage current
specification, please refer to Table 5 “Static characteristics”. See Section 7.3 for series resistor requirements.
[2] n = 15 for PCA9701; n = 7 for PCA9702.
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
14 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
10. Static characteristics
Table 5.
Static characteristics
VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +125 °C; unless otherwise specified.
Symbol Parameter
Supply
Conditions
Min
Typ
Max
Unit
VDD
IDD
supply voltage
2.5
3.3
1.0
1.8
5.5
2.5
2.2
V
supply current
power-on reset voltage[1]
VDD = 5.5 V; input = 5 V or 18 V; INT_EN = VDD
-
-
µA
V
VPOR
General Purpose Inputs
[2]
[3]
VIL
VIH
II
LOW-level input voltage
-
-
-
-
0.4VDD
V
HIGH-level input voltage
input current
0.7VDD
-
-
V
GPI recommended maximum current;
VI > 5.5 V; with series resistor Rs
100
µA
IIH
ILI
Ci
HIGH-level input current each input; VI = VDD
−1
−1
-
-
+1
+1
5.0
µA
µA
pF
input leakage current
input capacitance
VI = 17 V; 100 kΩ series resistor
VI = VSS or VDD
-
2.0
Interrupt output
IOL
LOW-level output current VDD = 4.5 V; VOL = 0.4 V
VDD = 2.5 V; VOL = 0.4 V
6
-
-
mA
mA
µA
pF
3
-
-
IOH
Co
HIGH-level output current VOH = VDD
output capacitance
−1
-
-
+1
5
2
SPI and control
VIL
VIH
IIH
LOW-level input voltage
-
-
0.3VDD
5.5
V
HIGH-level input voltage
0.7VDD
-
-
V
HIGH-level input current SDIN; VI = VDD = 5.5 V
20
40
µA
IOL
LOW-level output current SDOUT; VOL = 0.4 V
VDD = 4.5 V
5
3
-
-
-
-
mA
mA
VDD = 2.5 V
HIGH-level output current SDOUT; VOH = VDD − 0.5 V
VDD = 4.5 V
IOH
−5
−3
-
−11
−7
2
-
mA
mA
pF
VDD = 2.5 V
-
Ci
input capacitance
output capacitance
VI = VSS or VDD
5
6
Co
SDOUT; CS = VDD
-
4
pF
[1] VDD must be lowered to 0.2 V for at least 5 µs in order to reset device.
[2] Minimum VIL is 2.0 V at VDD = 4.5 V.
[3] For GPI pin voltages > 5.5 V, see Section 7.3.
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
15 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
11. Dynamic characteristics
Table 6.
Dynamic characteristics
VDD = 2.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +125 °C; unless otherwise specified.
Symbol
fmax
Parameter
Conditions
Min
-
Typ
Max
Unit
MHz
ns
maximum input clock frequency
rise time
-
5
60
50
-
tr
SDOUT; 10 % to 90 % at 5 V
SDOUT; 90 % to 10 % at 5 V
SCLK
-
35
25
-
tf
fall time
-
ns
tWH
pulse width HIGH
pulse width LOW
SPI enable lead time
SPI enable lag time
SDIN set-up time
SDIN hold time
50
50
50
50
20
30
-
ns
tWL
SCLK
-
-
ns
tSPILEAD
tSPILAG
tsu(SDIN)
th(SDIN)
ten(SDOUT)
CS falling edge to SCLK rising edge
SCLK falling edge to CS rising edge
SDIN to SCLK falling edge
from SCLK falling edge
-
-
ns
-
-
ns
-
-
ns
-
-
ns
SDOUT enable time
from CS LOW to
-
55
ns
SDOUT low-impedance; Figure 17
tdis(SDOUT)
SDOUT disable time
from rising edge of CS to SDOUT
high-impedance; Figure 17
-
-
85
ns
tv(SDOUT)
tsu(SCLK)
th(SCLK)
tPOR
SDOUT valid time
SCLK set-up time
SCLK hold time
from rising edge of SCLK; Figure 18
SCLK falling to CS falling
-
-
-
-
-
55
ns
ns
ns
ns
50
50
-
-
SCLK rising after CS rising
-
power-on reset pulse time
time before CS is active
after VDD > VPOR
250
trel(int)
interrupt release time
valid time on pin INT
after CS going LOW; Figure 19
-
-
-
-
500
100
ns
ns
tv(INT_N)
after INn changes or INT_EN
goes HIGH
CS
t
t
t
t
h(SCLK)
su(SCLK) SPILEAD
SPILAG
t
t
WL
WH
50 %
50 %
SCLK
SDIN
t
su(SDIN)
t
h(SDIN)
MSB in
t
en(SDOUT)
t
t
dis(SDOUT)
v(SDOUT)
high-impedance
SDOUT
INT
MSB out
t
rel(int)
002aac428
Fig 14. Timing diagram
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
16 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
2.5 V
0 V
V
V
POR
DD
CS
SCLK
SDOUT
MSB out
MSB − 1
t
POR
002aad158
Fig 15. AC waveform for tPOR timing
CS
INn
STATE 0
STATE 1
STATE 0
INT_EN
INT
t
t
v(INT_N)
v(INT_N)
t
t
rel(int)
rel(int)
002aad159
Fig 16. AC waveform for INT timing
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
17 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
12. Test information
V
DD
open
V
R
10 kΩ
DD
L
V
V
O
I
PULSE
DUT
GENERATOR
C
50 pF
L
R
T
10 kΩ
002aac580
Fig 17. Test circuitry for enable/disable times, SDOUT (ten(SDOUT) and tdis(SDOUT)
)
V
DD
V
V
O
I
PULSE
GENERATOR
DUT
C
50 pF
L
R
T
002aac581
Fig 18. Test circuitry for switching times, SDOUT (tv(SDOUT)
)
V
DD
V
R
10 kΩ
DD
L
V
V
O
I
PULSE
DUT
GENERATOR
C
50 pF
L
R
T
002aac582
Fig 19. Test circuitry for switching times, INT
RL = load resistance.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse
generators.
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
18 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
13. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT137-1
075E05
MS-013
Fig 20. Package outline SOT137-1 (SO24)
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
19 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 21. Package outline SOT355-1 (TSSOP24)
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
20 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 22. Package outline SOT403-1 (TSSOP16)
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
21 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.75 mm
SOT994-1
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
1/2 e
b
C
M
M
v
C A
B
e
y
C
1
y
w
C
7
12
L
13
6
e
E
e
2
h
1/2 e
1
18
terminal 1
index area
24
19
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
D
D
E
E
e
e
1
e
2
L
v
w
y
y
1
1
h
h
max
0.05 0.30
0.00 0.18
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
0.3
mm
0.8
0.2
0.5
2.5
2.5
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
- - -
07-02-07
07-03-03
SOT994-1
- - -
MO-220
Fig 23. Package outline SOT994-1 (HWQFN24)
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
22 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
23 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 7 and 8
Table 7.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
220
< 2.5
235
220
≥ 2.5
220
Table 8.
Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 24.
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
24 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Abbreviations
Table 9.
Abbreviations
Description
Acronym
ASSP
CAN
CDM
DUT
ECU
ESD
GPI
Application Specific Standard Product
Controller Area Network
Charged-Device Model
Device Under Test
Electronic Control Unit
ElectroStatic Discharge
General Purpose Input
Human Body Model
HBM
HS-CAN
LIN
High-Speed Controller Area Network
Local Interconnect Network
Least Significant Bit
LSB
MM
Machine Model
MSB
PCB
PPAP
RC
Most Significant Bit
Printed-Circuit Board
Production Part Approval Process
Resistor-Capacitor network
System Basis Chip
SBC
SPI
Serial Peripheral Interface
microcontroller
µC
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
25 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
16. Revision history
Table 10. Revision history
Document ID
Release date
20091111
Data sheet status
Change notice
Supersedes
PCA9701_PCA9702_5
Modifications:
Product data sheet
-
PCA9701_PCA9702_4
• Table 5 “Static characteristics”, sub-section “SPI and control”:
–
–
–
–
IOH for condition VDD = 4.5 V: Min value changed from “5 mA” to “−5 mA”
IOH for condition VDD = 4.5 V: Typ value changed from “-” to “−11 mA”
IOH for condition VDD = 2.5 V: Min value changed from “3 mA” to “−3 mA”
I
OH for condition VDD = 2.5 V: Typ value changed from “-” to “−7 mA”
PCA9701_PCA9702_4
PCA9701_PCA9702_3
PCA9701_PCA9702_2
PCA9701_PCA9702_1
20090716
20081203
20070829
20070323
Product data sheet
Product data sheet
Product data sheet
Objective data sheet
-
-
-
-
PCA9701_PCA9702_3
PCA9701_PCA9702_2
PCA9701_PCA9702_1
-
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
26 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
17.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9701_PCA9702_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2009
27 of 28
PCA9701; PCA9702
NXP Semiconductors
18 V tolerant SPI 16-bit/8-bit GPI with INT
19. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 27
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7
7.1
Functional description . . . . . . . . . . . . . . . . . . . 6
SPI bus operation . . . . . . . . . . . . . . . . . . . . . . . 6
CS - chip select. . . . . . . . . . . . . . . . . . . . . . . . . 6
SCLK - serial clock input. . . . . . . . . . . . . . . . . . 6
SDIN - serial data input . . . . . . . . . . . . . . . . . . 6
SDOUT - serial data output . . . . . . . . . . . . . . . 6
Register access timing . . . . . . . . . . . . . . . . . . . 7
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 7
General Purpose Inputs . . . . . . . . . . . . . . . . . . 8
VIL, VIH and switching points. . . . . . . . . . . . . . . 9
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.3
7.3.1
8
8.1
8.2
8.2.1
8.2.1.1
8.2.1.2
8.2.1.3
8.2.2
Application design-in information . . . . . . . . . 10
General application. . . . . . . . . . . . . . . . . . . . . 10
Automotive application . . . . . . . . . . . . . . . . . . 10
SBC wake port extension with cyclic biasing . 11
UJA106x with PCA9701, standby. . . . . . . . . . 11
UJA106x with PCA9701, sleep. . . . . . . . . . . . 12
UJA107x with PCA9701, standby. . . . . . . . . . 13
Application examples including
switches to battery . . . . . . . . . . . . . . . . . . . . . 13
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
Static characteristics. . . . . . . . . . . . . . . . . . . . 15
Dynamic characteristics . . . . . . . . . . . . . . . . . 16
Test information. . . . . . . . . . . . . . . . . . . . . . . . 18
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
10
11
12
13
14
Soldering of SMD packages . . . . . . . . . . . . . . 23
Introduction to soldering . . . . . . . . . . . . . . . . . 23
Wave and reflow soldering . . . . . . . . . . . . . . . 23
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24
14.1
14.2
14.3
14.4
15
16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 27
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
17.1
17.2
17.3
17.4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 November 2009
Document identifier: PCA9701_PCA9702_5
相关型号：
PCA9745BTWJ
PCA9745B - 16-channel SPI serial bus 57 mA/20 V constant current LED driver TSSOP2 28-Pin
NXP
©2020 ICPDF网 联系我们和版权申明