PCD5002A [NXP]
Enhanced Pager Decoder for APOC1/POCSAG; 增强寻呼机解码器， APOC1 / POCSAG
| 型号： | PCD5002A |
| 厂家： | 
NXP |
| 描述： | Enhanced Pager Decoder for APOC1/POCSAG |
| 文件： | 总48页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCD5002A
Enhanced Pager Decoder for
APOC1/POCSAG
1999 Jan 08
Product specification
File under Integrated Circuits, IC17
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
CONTENTS
8.41
8.42
8.43
8.44
8.45
8.46
8.47
8.48
8.49
8.50
8.51
8.52
8.53
8.54
8.55
8.56
8.57
8.58
8.59
8.60
8.61
8.62
8.63
8.64
Warbled alert
Direct alert control
Alert priority
Cancelling alerts
Automatic POCSAG alerts
SRAM access
RAM write address pointer (06H; read)
RAM read address pointer (08H; read/write)
RAM data output register (09H; read)
EEPROM access
EEPROM address pointer (07H; read/write)
EEPROM data I/O register (0AH; read/write)
EEPROM access limitations
EEPROM read operation
1
2
3
4
5
6
7
8
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
LICENSE
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
8.1
Introduction
8.2
8.3
8.4
The POCSAG paging code
The APOC1 paging code
Error correction
EEPROM write operation
Invalid write address
Incomplete programming sequence
Unused EEPROM locations
Special programmed function allocation
Synthesizer programming data
Identifier storage allocation
Voltage doubler
8.5
Operating states
8.6
ON status
8.7
OFF status
8.8
Reset
8.9
Bit rates
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
8.22
8.23
8.24
8.25
8.26
8.27
8.28
8.29
8.30
8.31
8.32
8.33
8.34
8.35
8.36
8.37
8.38
8.39
8.40
Oscillator
Input data processing
Battery saving
POCSAG synchronization strategy
APOC1 synchronization strategy
Call termination
Enhanced call termination
Call data output format
Error type indication
Data transfer
Continuous data decoding
Receiver and oscillator control
Demodulator quick charge
External receiver control and monitoring
Battery condition input
Synthesizer control
Serial microcontroller interface
Decoder I2C-bus access
External interrupt
Level-shifted interface
Signal test mode
9
OPERATING INSTRUCTIONS
9.1
9.2
9.3
9.4
Reset conditions
Power-on reset circuit
Reset timing
Initial programming
10
11
12
LIMITING VALUES
DC CHARACTERISTICS
DC CHARACTERISTICS (WITH VOLTAGE
CONVERTER)
13
OSCILLATOR CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
14
15
16
17
SOLDERING
Interrupt masking
Status/control register
Pending interrupts
Out-of-range indication
Real-time clock
Periodic interrupt
Received call delay
Alert generation
Alert cadence register (03H; write)
Acoustic alert
Vibrator alert
17.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
17.2
17.3
17.4
17.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
18
19
20
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
LED alert
1999 Jan 08
2
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
1
FEATURES
• Wide operating supply voltage range: 1.5 to 6.0 V
• EEPROM programming requires only 2.0 V supply
• Low operating current: 50 µA typ. (ON), 25 µA typ.
(OFF)
• Slave I2C-bus interface to microcontroller for transfer of
message data, status/control and EEPROM
• Temperature range −25 to +70 °C
• “CCIR radio paging Code No. 1” (POCSAG) compatible
programming (data transfer at up to 100 kbits/s)
• Supports Advanced Pager Operator’s Code Phase 1
• Wake-up interrupt for microcontroller, programmable
(APOC1) for extended battery economy
polarity
• 512, 1200 and 2400 bits/s data rates using 76.8 kHz
• Direct and I2C-bus control of operating status (ON/OFF)
• Battery-low indication (external detector)
• Out-of-range condition indication
crystal
• Built-in data filter (16 times oversampling) and bit clock
recovery
• Advanced ACCESS synchronization algorithm
• Real-time clock reference output
• 2-bit random and (optional) 4-bit burst error correction
• On-chip voltage doubler
• Up to 6 user addresses Receiver Identity Codes (RICs),
each with 4 functions/alert cadences
• Interfaces directly to UAA2080 and UAA2082 paging
receivers.
• Optional automatic call termination when bit error rate is
high
2
APPLICATIONS
• Up to 6 user address frames, independently
programmable
• Advanced display pagers (POCSAG and APOC1)
• Basic alert-only pagers
• Information services
• Standard POCSAG sync word, plus up to 4 user
programmable sync words
• Personal organizers
• Continuous data decoding upon reception of user
programmable sync word (optional)
• Telepoint
• Received data inversion (optional)
• Telemetry/data transmission.
• Call alert via beeper, vibrator or LED
• 2-level acoustic alert using single external transistor
3
GENERAL DESCRIPTION
• Alert control: automatic (POCSAG type), via cadence
register or alert input pin
The PCD5002A is a very low power pager decoder and
controller, capable of handling both standard POCSAG
and the advanced APOC1 code. Continuous data
decoding upon reception of a dedicated sync word is
available for news pager applications.
• Separate power control of receiver and RF oscillator for
battery economy
• Dedicated pin for easy control of superheterodyne
receiver
Data rates supported are 512, 1200 and 2400 bits/s using
a single 76.8 kHz crystal. On-chip EEPROM is
• Synthesizer set-up and control interface (3-line serial)
programmable using a minimum supply voltage of 2.0 V,
allowing ‘over-the-air’ programming. I2C-bus compatible.
• On-chip EEPROM for storage of user addresses (RICs),
pager configuration and synthesizer data
• On-chip SRAM buffer for message data
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCD5002AH
LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
SOT358-1
1999 Jan 08
3
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
5
LICENSE
Supply of this IC does neither convey nor express an implied license under any patent right to use this in any APOC
application.
6
BLOCK DIAGRAM
EEPROM
7
RESET
SET-UP
RST
26
ZSD
ZSC
ZLE
27
28
SYNTHESIZER
CONTROL
9
EEPROM CONTROL
SDA
SCL
2
I C-BUS
10
CONTROL
24
25
22
5
RXE
ROE
DECODING
DATA
CONTROL
DQC
INT
RECEIVER
CONTROL
POCSAG
SYNCHRONIZATION
REGISTERS
AND
INTERRUPT
CONTROL
RAM
CONTROL
21
DATA FILTER
AND
BAT
23
MAIN DECODER
RDI
CLOCK
RECOVERY
30
31
1
VIB
RAM
LED
ATL
ATH
ALC
ALERT
GENERATION
AND
3
CLOCK
CONTROL
MASTER
DIVIDER
TIMER
REFERENCE
DON
32
2
CONTROL
16
20
4
TS1
TS2
REF
TEST
CONTROL
15
14
13
8
CCN
CCP
VOLTAGE
DOUBLER
AND LEVEL
SHIFTER
18
17
PCD5002A
XTAL1
XTAL2
OSCILLATOR
V
PO
V
PR
19, 6
n.c.
11
12, 29
MGL563
V
V
SS
DD
Fig.1 Block diagram.
4
1999 Jan 08
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
7
PINNING
SYMBOL PIN
DESCRIPTION
alert LOW level output
SYMBOL PIN
DESCRIPTION
ATL
1
2
TS1
16 test input 1 (normally LOW by internal
pull-down)
ALC
alert control input (normally LOW by
internal pull-down)
XTAL2
XTAL1
n.c.
17 decoder crystal oscillator output
18 decoder crystal oscillator input
19 not connected
DON
REF
3
4
direct ON/OFF input (normally LOW by
internal pull-down)
real-time clock frequency reference
output
TS2
20 test input 2 (normally LOW by internal
pull-down)
INT
n.c.
RST
5
6
7
interrupt output
not connected
BAT
DQC
RDI
21 battery sense input
22 demodulator quick charge output
reset input (normally LOW by internal
pull-down)
23 received data input (POCSAG or
APOC1)
VPR
8
external positive voltage reference
input
I2C-bus serial data input/output
RXE
ROE
ZSD
ZSC
ZLE
VSS
24 receiver circuit enable output
25 receiver oscillator enable output
26 synthesizer serial data output
27 synthesizer serial clock output
28 synthesizer latch enable output
29 main negative supply voltage
30 vibrator motor drive output
31 LED drive output
SDA
SCL
VDD
VSS
9
10 I2C-bus serial clock input
11 main positive supply voltage
12 main negative supply voltage
13 voltage converter positive output
VPO
CCP
VIB
14 voltage converter shunt capacitor
(positive side)
LED
ATH
32 alert HIGH level output
CCN
15 voltage converter shunt capacitor
(negative side)
ATL
ALC
DON
REF
INT
1
2
3
4
5
6
7
8
RXE
24
23 RDI
22 DQC
21 BAT
20 TS2
PCD5002AH
n.c.
19 n.c.
RST
18 XTAL1
17 XTAL2
V
PR
MGL564
Fig.2 Pin configuration.
5
1999 Jan 08
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
The PCD5002A contains a low-power, high-efficiency
voltage converter (doubler) designed to provide a higher
voltage supply to LCD drivers or microcontrollers.
In addition, an independent level shifted interface is
provided allowing communication to a microcontroller
operating at a higher voltage than the PCD5002A.
8
FUNCTIONAL DESCRIPTION
Introduction
8.1
The PCD5002A is a very low power decoder and pager
controller specifically designed for use in new generation
radio pagers. The architecture of the PCD5002A allows for
flexible application in a wide variety of radio pager designs.
Interface to such an external device is provided by an
I2C-bus which allows received call identity and message
data, data for the programming of the internal EEPROM,
alert control and pager status information to be transferred
between the devices. Pager status includes features
provided by the PCD5002A such as battery-low and
out-of-range indications. A dedicated interrupt line
minimizes the required microcontroller activity.
The PCD5002A is fully compatible with “CCIR Radio
paging Code No. 1” (also known as the POCSAG code)
operating at data rates of 512, 1200 and 2400 bits/s using
a single oscillator crystal of 76.8 kHz.
The PCD5002A also supports the new Advanced Pager
Operator’s Code Phase 1 (APOC1). This compatible
extension to the POCSAG code improves battery
economy by introducing ‘cycles’ and batch numbering.
A cycle consists of 5 or 15 standard POCSAG batches.
Each pager will be allocated a batch number in addition to
its POCSAG address and it will only search for its address
during this batch.
A selectable low frequency timing reference is provided for
use in real-time clock functions.
Data synchronization is achieved by the Philips patented
ACCESS algorithm ensuring that maximum advantage is
made of the POCSAG code structure particularly in fading
radio signal conditions. The algorithm allows for data
synchronization without preamble detection whilst
minimizing battery power consumption. The APOC1 code
uses an extended version of the ACCESS
In addition to the standard POCSAG sync word (used also
in APOC1) the PCD5002A is also capable of recognizing
up to 4 User Programmable Sync Words (UPSWs).
This permits the reception of both private services and
POCSAG or APOC1 transmissions via the same radio
channel. As an option reception of a UPSW may activate
Continuous Data Decoding (CDD).
synchronization algorithm.
Random (and optional) burst error correction techniques
are applied to the received data to optimize the call
success rate without increasing the falsing rate beyond
specified POCSAG levels.
Used together with the Philips UAA2080 or UAA2082
paging receiver, the PCD5002A offers a highly
sophisticated, miniature solution for the radio paging
market. Control of an RF synthesizer circuit is also
provided to ease alignment and channel selection.
8.2
The POCSAG paging code
A transmission using the “CCIR Radio paging Code No. 1”
(POCSAG code) is constructed in accordance with the
following rules (see Fig.3).
On-chip EEPROM provides storage for user addresses
(Receiver Identity Codes or RICs) and Special
Programmed Functions (SPFs) and UPSWs, which
eliminates the need for external storage devices and
interconnection. For other non-volatile storage 20 bytes of
general purpose EEPROM are available. The low
EEPROM programming voltage makes the PCD5002A
well suited for ‘over-the-air’ programming/reprogramming.
The transmission is started by sending a preamble,
consisting of at least 576 continuously alternating bits
(10101010...). The preamble is followed by an arbitrary
number of batch blocks. Only complete batches are
transmitted.
Each batch comprises 17 code-words of 32 bits each.
The first code-word is a synchronization code-word with a
fixed pattern. The sync word is followed by 8 frames
(0 to 7) of 2 code-words each, containing message
information. A code-word in a frame can either be an
address, message or idle code-word.
On request from an external controlling device or
automatically (by SPF programming), the PCD5002A will
provide standard POCSAG alert cadences by driving a
standard acoustic ‘beeper’. Non-standard alert cadences
may be generated via a cadence register or a dedicated
control input.
Idle code-words also have a fixed pattern and are used to
fill empty frames or to separate messages.
The PCD5002A can also produce a HIGH level acoustic
alert as well as drive an LED indicator and a vibrator motor
via external bipolar transistors.
1999 Jan 08
6
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Address code-words are identified by an MSB at logic 0
and are coded as shown in Fig.3. A user address or RIC
consists of 21 bits. Only the upper 18 bits are encoded in
the address code-word (bits 2 to 19). The lower 3 bits
designate the frame number (0 to 7) in which the address
is transmitted.
This permits correction of a maximum of 2 random errors
or up to 3 errors in a burst of 4 bits (a 4-bit burst error) per
code-word.
8.3
The APOC1 paging code
The APOC1 paging code is fully POCSAG compatible and
involves the introduction of batch grouping and a Batch
Zero Identifier (BZI). This reserved address code-word
indicates the start of a ‘cycle’ of 5 or 15 batches long and
is transmitted immediately after a sync word.
Four different call types (‘numeric’, ‘alphanumeric’ and two
‘alert only’ types) can be distinguished. The call type is
determined by two function bits in the address code-word
(bits 20 and 21), as shown in Table 1.
Alert-only calls consist only of a single address code-word.
Numeric and alphanumeric calls have message
code-words following the address. A message causes the
frame structure to be temporarily suspended. Message
code-words are sent until the message is completed, with
only the sync words being transmitted in their expected
positions.
Cycle transmission must be coherent i.e. a transmission
starting an integer number of cycle periods after the start
of the previous one.
Broadcast message data may be included in a
transmission. This information may occupy any number of
message code-words and immediately follows the batch
zero identifier of the first cycle after preamble.
Message code-words are identified by an MSB at logic 1
and are coded as shown in Fig.3. The message
information is stored in a 20-bit field (bits 2 to 21).
The presence of data is indicated by the function bits in the
batch zero identifier: 1,1 indicates ‘no broadcast data’.
Any other combination indicates a broadcast message.
The standard data format is determined by the call type:
4 bits per digit for numeric messages and 7 bits per
(ASCII) character for alphanumeric messages.
The PCD5002A can be configured for POCSAG or
APOC1 operation via SPF programming. The batch zero
identifier is programmable and can be stored in any
identifier location in EEPROM.
Each code-word is protected against transmission errors
by 10 CRC check bits (bits 22 to 31) and an even-parity bit
(bit 32).
The POCSAG standard only allows combinations of data
formats and function code bits as given in Table 1.
However, other (non-standard) combinations will be
decoded normally by the PCD5002A.
PREAMBLE
BATCH 1
BATCH 2
BATCH 3
LAST BATCH
10101 . . . 10101010
SYNC | CW CW | CW CW | . . . . . | CW CW
FRAME 0
FRAME 1
FRAME 7
Address code-word
Message code-word
0
1
18-bit address
20-bit message
2 function bits
10 CRC bits
P
P
10 CRC bits
MCD456
Fig.3 POCSAG code structure.
7
1999 Jan 08
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Table 1 POCSAG recommended call types and function bits
BIT 20 (MSB)
BIT 21 (LSB)
CALL TYPE
DATA FORMAT
0
0
1
1
0
1
0
1
numeric
alert only 1
alert only 2
alphanumeric
4-bits per digit
−
−
7-bits per ASCII character
8.4
Error correction
8.6
ON status
In the PCD5002A error correction methods have been
implemented as shown in Table 2.
In the ON status the decoder pulses the receiver and
oscillator enable outputs (RXE and ROE respectively)
according to the code structure and the synchronization
algorithm. Data received serially at the data input (RDI) is
processed for call reception.
Random error correction is default for both address and
message code-words. In addition, burst error correction
can be enabled by SPF programming. Up to 3 erroneous
bits in a 4-bit burst can be corrected.
The data protocol can be POCSAG or APOC1.
Continuous data decoding upon reception of a special
sync word is also supported. The data protocol is selected
by SPF programming.
The error type detected for each code-word is identified in
the message data output to the microcontroller, allowing
rejection of calls with too many errors.
Reception of a valid paging call is signalled to the
microcontroller by an interrupt signal. The received
address and message data can then be read via the
I2C-bus interface.
Table 2 Error correction
ITEM
Preamble
CORRECTION
4 random errors in 31 bits
2 random errors in 32 bits
8.7
OFF status
Synchronization
code-word
In the OFF status the decoder will neither activate the
receiver or oscillator enable outputs, nor process any data
at the data input. The crystal oscillator remains active to
permit communication with the microcontroller.
Address code-word
2 random errors; plus 4-bit burst
errors (optional)
Message code-word 2 random errors; plus 4-bit burst
errors (optional)
In both operating states an accurate timing reference is
available via the REF output. Using SPF programming the
signal periodicity may be selected as;
8.5
Operating states
32.768 kHz, 50 Hz, 2 Hz or 1⁄60 Hz.
The PCD5002A has 2 operating states:
• ON status
8.8
Reset
• OFF status.
The decoder can be reset by applying a positive pulse on
input pin RST. For successful reset at power-on, a HIGH
level must be present on the RST pin while the device is
powering-up.
The operating state is determined by a direct control input
(DON) and bit D4 in the control register (see Table 3).
Table 3 Truth table for decoder operating status
This can be applied by the microcontroller, or via a suitable
RC power-on reset circuit connected to the RST input.
Reset circuit details and conditions during and after a reset
are described in Chapter 9.
DON
INPUT
CONTROL
BIT D4
OPERATING STATUS
0
0
1
1
0
1
0
1
OFF
ON
ON
ON
1999 Jan 08
8
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
The current consumption of the complete pager can be
minimized by separately activating the RF oscillator circuit
(using output ROE) before activating the rest of the
receiver. This is possible using the UAA2082 receiver
which has external biasing for the oscillator circuit.
8.9
Bit rates
The PCD5002A can be configured for data rates of 512,
1200 or 2400 bits/s by SPF programming. These data
rates are derived from a single 76.8 kHz oscillator
frequency.
8.13 POCSAG synchronization strategy
8.10 Oscillator
In the ON status the PCD5002A synchronizes to the
POCSAG data stream by the Philips ACCESS algorithm.
A flow diagram is shown in Fig.4. Where ‘sync word’ is
used, this implies both the standard POCSAG sync word
and any enabled User Programmable Sync Word
(UPSW).
The oscillator circuit is designed to operate at 76.8 kHz.
Typically, a tuning fork crystal will be used as a frequency
source. Alternatively, an external clock signal can be
applied to pin XTAL1 (amplitude = VDD to VSS), but a
slightly higher oscillator current is consumed. A 2.2 MΩ
feedback resistor connected between XTAL1 and XTAL2
is required for proper operation.
Several modes of operation can be distinguished
depending on the synchronization state. Each mode uses
a different method to obtain or retain data synchronization.
The receiver and oscillator enable outputs (RXE and ROE
respectively) are switched accordingly, with the
appropriate establishment times (tRXON and tROON
respectively).
To allow easy oscillator adjustment (e.g. by a variable
capacitor) a 32.768 kHz reference frequency can be
selected at output REF by SPF programming.
8.11 Input data processing
Data input is binary and fully asynchronous. Input bit rates
of 512, 1200 and 2400 bits/s are supported. As a
programmable option, the polarity of the received data can
be inverted before further processing.
Before comparing received data with preamble, an
enabled sync word or programmed user addresses, the
appropriate error correction is applied.
Initially, after switching to the ON status, the decoder is in
switch-on mode. Here the receiver will be enabled for a
period up to 3 batches, testing for preamble and the sync
word. Failure to detect preamble or the sync word will
cause the device to switch to the ‘carrier off’ mode.
The input data is noise filtered by a digital filter. Data is
sampled at 16 times the data rate and averaged by
majority decision.
The filtered data is used to synchronize an internal clock
generator by monitoring transitions. The recovered clock
phase can be adjusted in steps of 1⁄8 or 1⁄32 bit period per
received bit.
When preamble is detected it will cause the device to
switch to the preamble receive mode, in which a sync
word is searched for. The receiver will remain enabled
while preamble is detected. When neither sync word nor
preamble is found within a 1 batch duration the ‘carrier off’
mode is entered.
The larger step size is used when bit synchronization has
not been achieved, the smaller when a valid data
sequence has been detected (e.g. preamble or sync
word).
Upon detection of a sync word the data receive mode is
entered. The receiver is activated only during enabled user
address frames and sync word periods. When an enabled
user address has been detected, the receiver will be kept
enabled for message code-word reception until the call
termination criteria are met.
8.12 Battery saving
Current consumption is reduced by switching off internal
decoder sections whenever the receiver is not enabled.
To further increase battery efficiency, reception and
decoding of an address code-word is stopped as soon as
the uncorrected address field differs by more than 3 bits
from the enabled RICs. If the next code-word must be
received again, the receiver is re-enabled thus observing
During call reception data bytes are stored in an internal
SRAM buffer, capable of storing 2 batches of message
data.
Messages are transmitted contiguously, only interrupted
by sync words at the beginning of each batch.
the programmed establishment times tRXE and tROE
.
1999 Jan 08
9
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
When a message extends beyond the end of a batch no
testing for sync takes place. Instead, a message data
transfer will be initiated by an interrupt to the external
controller. Data reception continues normally after a period
corresponding to the sync word duration.
15 batches, allowing recovery of synchronization from
long fades in the radio signal. Detection of preamble
causes switching to the ‘preamble receive’ mode, while
sync word detection causes switching to the ‘data receive’
mode. When neither is found within a period of 15 batches,
the radio signal is considered lost and the ‘carrier off’ mode
is entered.
If any message code-word is found to be uncorrectable,
the ‘data fail’ mode is entered and no data transfer will be
attempted at the next sync word position. Instead, a test for
sync word will be carried out.
The purpose of the carrier off mode is to detect a valid
radio transmission and synchronize to it quickly and
efficiently. Because transmissions may start at random,
the decoder enables the receiver for 1 code-word in every
18 code-words looking for preamble or sync word.
By using a buffer containing 32 bits (n bits from the current
scan, 32 − n from the previous scan) effectively every
batch bit position can be tested within a continuous
transmission of at least 18 batches. Detection of preamble
causes the device to switch to the ‘preamble receive’
mode, while sync word detection causes the device to
switch to the ‘data receive’ mode.
In the data fail mode message reception continues
normally for 1 batch duration. When a sync word is
detected at the expected position the decoder returns to
the ‘data receive’ mode. If the sync word again fails to
appear, then batch synchronization is deemed lost. Call
reception is then terminated and the ‘fade recovery’ mode
is entered.
The fade recovery mode is intended to scan for sync word
and preamble over an extended window (nominal
position ± 8 bits). This is performed for a period of up to
OFF to ON status
no preamble or
sync word
switch-on
(3 batches)
sync word
preamble
no preamble or
sync word
preamble receive
(1 batch)
sync word
data receive
data fail
sync word
no sync word
preamble
preamble
preamble
no preamble or
sync word
(1 batch)
sync word
sync word
fade recovery
no preamble or
sync word
(15 batches)
carrier off
MLC247
Fig.4 ACCESS synchronization algorithm for POCSAG.
10
1999 Jan 08
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
OFF to ON status
no preamble
or sync word
(3 batches)
preamble
switch on
sync word
carrier detect
preamble
sync word
TX off
time out
no preamble (1 batch)
preamble receive 1
long fade recovery
preamble
sync word
sync word
preamble
no sync word
batch zero detect
batch zero ID
batch zero identify
cycle receive
no batch zero ID
batch
zero ID
sync
word
no sync
word
preamble
short fade recovery
no sync word
or preamble
sync word
transmitter off
no preamble
(1 batch)
TX off time out
sync word
preamble
preamble receive 2
MGD269
Fig.5 APOC1 synchronization algorithm.
If preamble is not found within one batch duration then the
‘long fade recovery’ mode is entered.
8.14 APOC1 synchronization strategy
The synchronization strategy in APOC1 is an extended
version of the ACCESS scheme and is illustrated in Fig.5.
The PCD5002A counts the number of batches in a
transmission, starting from the first batch received after
preamble. Counter overflow occurs due to the size of a
cycle, as determined by SPF programming.
When in batch zero detect mode the PCD5002A
switches on every batch to maintain synchronization and
check for the batch zero identifier. Detection of the batch
zero identifier activates the ‘cycle receive’ mode. When
synchronization is lost the ‘long fade recovery’ mode is
entered. ‘preamble receive’ mode is entered when
preamble is detected.
Initially, after switching to the ON status, the decoder will
be in the switch-on mode. Here the receiver will be
enabled for up to 3 batches, testing for preamble and sync
word. Detection of preamble causes the device to switch
to the ‘preamble receive’ mode, while any enabled sync
word enters the ‘batch zero detect’ mode. Failure to detect
either will cause the device to switch to the ‘carrier detect’
mode.
In the batch zero identify mode the first code-word
immediately after the sync word of the first batch is
compared with the programmed batch zero identifier.
Failure to detect the batch zero identifier will cause the
device to enter the ‘short fade recovery’ mode.
When this comparison is successful the function bits
determine whether any broadcast message will follow.
Any function bit combination other than ‘1,1’ will cause the
PCD5002A to accept message code-words until
terminated by a valid address code-word.
In the preamble receive 1 mode the PCD5002A searches
for a sync word, the receiver remaining enabled while
preamble is detected. As soon as an enabled sync word is
found the ‘batch zero identify’ mode is started.
1999 Jan 08
11
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
After reception of any broadcast message data the
PCD5002A continues to operate in the ‘cycle receive’
mode.
Synchronization checking is performed over a window
ranging from ‘n’ bits before to ‘n’ bits after the expected
sync word position. The window tolerance ‘n’ depends on
the time since the ‘transmitter off’ mode was entered and
on the selected bit rate (see Table 4).
In the cycle receive mode the PCD5002A enables call
reception in only one programmed batch per cycle. Sync
word detection takes place from 2 bits before to 2 bits after
the expected sync word position of this batch. If the sync
word is not detected then the position of the current sync
word will be maintained and the ‘short fade recovery’
mode will be entered.
When a sync word is detected in this widened
synchronization window the PCD5002A enters the
‘batch zero identify’ mode. Time-out expiry before a sync
word has been detected causes the device to switch to the
‘long fade recovery’ mode.
When a valid sync word is found user address code-word
detection takes place, as in normal POCSAG code.
Any following message code-words are received normally.
If a message extends into a subsequent batch containing
a batch zero identifier, then the batch zero identifier is
detected normally and message reception will continue.
Detection of preamble in the ‘transmitter off’ mode initiates
the preamble receive 2 mode. Operation in this mode is
identical to ‘preamble receive mode’. Failure to detect
preamble for one batch period will cause the device to
switch back to the ‘transmitter off’ mode. This prevents
inadvertent loss of cycle synchronization due to spurious
signals resembling preamble.
Data reception is suspended after the programmed batch
until the same batch position in the next cycle.
The exception being when a received call continues into
the next batch.
The carrier detect mode is identical to the ‘carrier off’
mode in standard POCSAG operation. Upon first entry the
transmitter off time-out is started. The receiver is enabled
to receive one code-word in every 18 code-words to check
for sync word and preamble. This check is performed on
the last available 32 bits for every received bit.
In the short fade recovery mode the programmed data
receive batch will continue to be checked for user address
code-words. In addition the first code-word after the
programmed batch is checked for sync word or preamble. The ‘preamble receive’ mode is entered if preamble is
detected. If a valid sync word is found the
When a valid sync word is detected the ‘cycle receive’
‘batch zero detect’ mode is entered. If neither has been
mode is re-entered, while detection of preamble causes
detected and the time-out expires, then the
the device to switch to the ‘preamble receive’ mode. When
‘long fade recovery’ mode is entered.
neither is found then the ‘transmitter off’ mode is entered.
The long fade recovery mode is intended to quickly
In the transmitter off mode a time-out is set to a
regain synchronization in fading conditions (not caused by
pre-programmed duration. This time-out corresponds to
the transmitter switching off between transmissions) or
the maximum time between subsequent transmissions
when having been out of range, while maintaining
(preamble to preamble).
acceptable battery economy.
The PCD5002A then checks the first batch of every cycle
Initially, the receiver is switched off until one cycle duration
for sync word or preamble. The programmed data receive
after the last enabling in the ‘transmitter off’ mode.
batch is ignored (unless it is batch 0).
The receiver is then enabled for a 2 code-word period in
which each contiguous group of 32 bits is tested for any
decodable POCSAG code-word (including sync word)
and preamble. Single-bit error correction is applied.
Table 4 Synchronization window tolerance as a function
of bit rate
TOLERANCE
If a code-word is detected, the receiver enable period is
TIME FROM LOSS
extended by another code-word duration and the above
test is repeated. This process continues while valid
code-words are received.
512
(bits/s)
1200
(bits/s)
2400
(bits/s)
OF SIGNAL
≤30 s
≤60 s
4 bits
4 bits
4 bits
8 bits
4 bits
4 bits
8 bits
16 bits
4 bits
8 bits
≤120 s
≤240 s
16 bits
32 bits
1999 Jan 08
12
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Detection of preamble will cause the device to switch to the
‘preamble receive’ mode, while sync word detection will
cause the device to switch to the ‘batch zero detect’ mode.
When neither is detected during the 2 code-word window
or any following 32-bit group, the receiver will be disabled.
8.16 Enhanced call termination
The PCD5002A provides an enhanced mode of call
termination which is enabled by setting SPF byte 3, bit D7.
When enabled, the following call termination conditions
applies, in addition to those listed in Section 8.15.
If valid code-words are detected but no sync word or
preamble is detected over a period of 18 code-words, the
receiver is also disabled.
• Reception of two consecutive code-words (excluding
sync word), each of which are either uncorrectable or an
address code-word with more than one bit in error.
Data sampling, as previously described, is repeated one
cycle duration after the moment the receiver was last
activated.
8.17 Call data output format
POCSAG call information is stored in the decoder SRAM
in blocks of 3 bytes per code-word. Each stored call
consists of a call header, followed by message data blocks
and a call terminator. In the event of concatenated
messages the call terminator is replaced with the call
header of the next message. An alert-only call only has a
call header and a call terminator.
8.15 Call termination
Call reception is terminated:
• Upon reception of any address code-word (including idle
code-word but excluding the batch zero identifier in
APOC1 operation) requiring no more than single bit
error correction
The formats of a call header, a message data block and a
call terminator are shown in Tables 5, 7 and 9.
• Upon reception of a correctable address code-word
(error type other than ‘111’; see Table 11) that matches
an enabled RIC
A Call Header contains information on the last sync word
received, the RIC which began call reception and the type
of error correction performed on the address code-word.
• When a forced call termination command is received
from an external controller.
A Message Data block contains the data bits from a
message code-word plus the type of error correction
performed. No deformatting is performed on the data bits:
numeric data appear as 4-bit groups per digit,
• In ‘data fail’ mode, when a sync word is not detected at
the expected batch position.
The last method permits an external controller to stop call
reception, depending on the number and type of errors
which occurred in a call. After a forced call termination the
decoder will enter the ‘data fail’ mode.
alphanumeric data has a 7-bit ASCII representation.
The Call Terminator contains information on the last sync
word received, information on the way the call was
terminated (forced call termination command, loss of sync
word in ‘data fail’ mode) and the type of error correction
performed on the terminating code-word.
The type of error correction as well as the call termination
conditions are indicated by status bits in the message data
output.
In the event of the terminating code-word matching an
enabled RIC, a concatenated call will be started with the
call header replacing the terminator of the previous call.
Following call termination, transfer of the data received
since the previous sync word period is initiated by an
interrupt to the external controller.
1999 Jan 08
13
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Table 5 Call header format
BIT 7
(MSB)
BIT 0
BIT 1
BYTE NUMBER
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
(LSB)
1
2
3
0
0
X
S3
S3
X
S2
S2
F0
S1
S1
F1
R3
R3
E3
R2
R2
E2
R1
R1
E1
DF
0
0
Table 6 Call header bit identification
BITS (MSB TO LSB)
IDENTIFICATION
S3 to S1
R3 to R1
DF
identifier number of sync word for current batch (7 = standard POCSAG)
identifier number of user address (RIC)
data fail mode indication (1 = data fail mode); note 1
F0 and F1
E3 to E1
function bits of received address code-word (bits 20 and 21)
detected error type; see Table 11; E3 = 0 in a concatenated call header
Note
1. The DF bit in the call header is set:
a) When the sync word of the batch in which the (beginning of the) call was received, did not match the standard
POCSAG or a user-programmed sync word. The sync word identifier (bits S3 to S1) will then be made 0.
b) When any code-word of a previous call received in the same batch was uncorrectable.
Table 7 Message data format
BIT 7
(MSB)
BIT 0
(LSB)
BYTE NUMBER
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
1
2
3
M2
M3
M11
M19
M4
M5
M6
M14
E3
M7
M15
E2
M8
M16
E1
M9
M17
M1
M10
M18
M12
M20
M13
M21
Table 8 Message data bit identification
BITS (MSB TO LSB)
IDENTIFICATION
M2 to M21
E3 to E1
M1
message code-word data bits
detected error type; see Table 11
message code-word flag
Table 9 Call terminator format
BIT 7
BYTE NUMBER
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
1
2
3
FT
FT
X
S3
S3
X
S2
S2
X
S1
S1
X
0
0
0
0
0
0
DF
X
E3
E2
E1
0
1999 Jan 08
14
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Table 10 Call terminator bit identification
BITS (MSB TO LSB)
IDENTIFICATION
forced call termination (1 = yes)
identifier number of last sync word
data fail mode indication (1 = data fail mode); note 1
detected error type; see Table 11; E3 = 0 in a call terminator
FT
S3 to S1
DF
E3 to E1
Note
1. The DF bit in the call terminator is set:
a) When any call data code-word in the terminating batch was uncorrectable, while in ‘data receive’ mode.
b) When the sync word at the start of the terminating batch did not match the standard POCSAG or a
user-programmed sync word, while in ‘data fail’ mode.
Table 11 Error type identification (note 1)
E3
E2
E1
ERROR TYPE
NUMBER OF ERRORS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
no errors; correct code-word
parity bit in error
0
1
single bit error
1 + parity
single bit error and parity error
not used
1
−
4-bit burst error and parity error
2-bit random error
3 (e.g. 1101)
2
uncorrectable code-word
3 or more
Note
1. POCSAG code allows a maximum of three bit errors to be detected per code-word.
detected while in the ‘Data Fail’ mode (‘Short Fade
8.18 Error type indication
Recovery’ in APOC1).
Table 11 shows how the different types of detected errors
are encoded in the call data output format.
8.20 Continuous data decoding
Apart from transmissions in the POCSAG or APOC1
format, the PCD5002A is also capable of decoding
continuous transmissions with the same code-word
structure. Any User-Programmable Sync Word (UPSW)
may be designated to enable continuous data decoding.
8.19 Data transfer
Data transfer is initiated either during sync word periods or
as soon as the receiver is disabled after call termination.
If the SRAM buffer is full, data transfer is initiated
immediately during the next code-word.
When a Continuous Data Decoding (CDD) sync word is
detected at any sync word position, the receiver remains
enabled from then on. Status bits D1 and D0 show the
CDD mode to be active.
When the PCD5002A is ready to transfer received call
data an external interrupt will be generated via output INT.
Any message data can be read by accessing the RAM
output register via the I2C-bus interface. Bytes will be
output starting from the position indicated by the RAM read
pointer.
All code-words are decoded and their data fields are
stored in SRAM. The usual error information is appended.
No distinction is made between address and message
code-words: code-word bit 0 is treated as a data bit and is
stored in bit M1 of the 3-byte output format.
Call termination can occur on reception of an address
code-word (or even a message code-word if in Enhanced
Call Termination Mode) or when a sync word is not
1999 Jan 08
15
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Code-words received at the expected sync word positions
(POCSAG batch size) are matched against standard
POCSAG sync word, all enabled UPSWs and preamble.
Upon forced termination the ‘fade recovery’ mode is
entered. Detection of preamble causes the device to
switch to the ‘preamble receive’ mode. Detection of a
standard sync word or any enabled non-continuous UPSW
will cause the device to switch to the ‘data receive’ mode.
Data output to an external controller is initiated by an
interrupt at the next sync word position, after reception of
16 code-words.
Continuous data decoding will continue in the next batch if
any enabled CDD sync word is detected or no enabled
sync word is detected. It should be noted that the
enhanced call termination is ignored in CCD mode.
The call header preceding the data has a different
structure from normal POCSAG or APOC1 data. The data
header format is shown in Table 12.
Continuous data decoding continues until one of the
following conditions occur:
8.21 Receiver and oscillator control
A paging receiver and an RF oscillator circuit can be
controlled independently via enable outputs RXE and ROE
respectively. Their operating periods are optimized
according to the synchronization mode of the decoder.
Each enable signal has its own programmable
establishment time (see Table 14).
• The decoder is switched to the OFF state
• A Forced Call Termination (FCT) command is received
via the I2C-bus
• Preamble is detected at the sync word position
• Standard POCSAG sync word or an enabled non-CDD
sync word is detected.
Only a forced call termination command will be indicated in
the SRAM data by a call terminator. In the other events
continuous data decoding will stop without notification.
Table 12 Continuous data header format
BIT 7
(MSB)
BIT 0
(LSB)
BYTE NUMBER
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
1
2
3
0
0
X
X
C3
X
X
X
C3
C3
E3
C2
C2
E2
C1
C1
E1
0
0
0
C2
F0
C1
F1
Table 13 Data header bit identification
BITS (MSB TO LSB)
IDENTIFICATION
C3 to C1
F0 and F1
E3 to E1
identifier number of continuous data decoding sync word
function bits of received address code-word (bits 20 and 21)
detected error type (see Table 11); E3 = 0 in a concatenated call header
Table 14 Receiver and oscillator establishment times (note 1)
CONTROL OUTPUT
ESTABLISHMENT TIME
UNIT
RXE
ROE
5
10
30
15
40
30
50
ms
ms
20
Note
1. The exact values may differ slightly from the above values, depending on the bit rate (see Table 25).
1999 Jan 08
16
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
The timing of DQC is as follows (see Fig.6):
8.22 Demodulator quick charge
• Mode 0: Set along with RXE output (time tRXE before the
first code-word is expected); cleared during the second
bit of the code-word following tRXE
Two modes of operation are available that determine the
period when the DQC output is set
The operating mode is selected by EEPROM
programming of SPF byte 03, bit D5:
• Mode 1: Set during the second bit of the sync word;
cleared after the last bit of the sync word.
• Mode 0 (D5 = 0): DQC is active HIGH during the
receiver establishment time (tRXE) in all ACCESS and
APOC1 modes except data receive and data fail (cycle
receive and short fade recovery in APOC1). During
switch-on, DQC is active for 1 code-word duration.
Note: During switch-on, tRXE is not used: RXE and DQC
are switched on immediately.
• Mode 1 (D5 = 1): DQC is active during sync word
detection in all ACCESS and APOC1 modes. During
switch-on and preamble receive modes, DQC is active
continuously.
Data into RDI
RXE
code-word
code-word
code-word
t
RXE
Mode 0 DQC
Mode 1 DQC
MGL566
Fig.6 DQC Timing.
1999 Jan 08
17
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Data bits on ZSD change on the falling edges of ZSC. After
clocking all bits into the synthesizer, a latch enable pulse
copies the data to the internal divider registers. A timing
diagram is illustrated in Fig.7.
8.23 External receiver control and monitoring
An external controller may enable the receiver control
outputs continuously via an I2C-bus command, overruling
the normal enable pattern. Data reception continues
normally. This mode can be exited by means of a reset or
an I2C-bus command.
The data output timing is synchronous, but has a pause in
the bitstream of each block. This pause occurs in the
13th bit while ZSC is LOW. The nominal pause duration tp
depends on the programmed bit rate for data reception
and is shown in Table 15. The total duration of the 13th bit
is given by tZCL + tp.
External monitoring of the receiver control output RXE is
possible via bit D6 in the status register, when enabled via
the control register (D2 = 1). Each change of state of
output RXE will generate an external interrupt at output
INT.
A similar pause occurs between the first and the second
data block. The delay between the first latch enable pulse
and the second data block is given by tZDL2 + tp.
The complete start-up timing of the synthesizer interface is
illustrated in Fig.14.
8.24 Battery condition input
A logic signal from an external sense circuit, signalling
battery condition, can be applied to the BAT input. This
input is sampled each time the receiver is disabled
(RXE ↓ 0).
Table 15 Synthesizer programming pause
BIT RATE (bits/s)
tp (CLOCKS)
tp (µs)
When enabled via the control register (D2 = 0), the
condition of input BAT is reflected in bit D6 of the status
register. Each change of state of bit D6 causes an external
interrupt at output INT.
512
119
33
1
1549
430
13
1200
2400
When using the UAA2080 pager receiver a battery-low
condition corresponds to a logic HIGH level. With a
different sense circuit the reverse polarity can be used as
well, because every change of state is signalled to an
external controller.
8.26 Serial microcontroller interface
The PCD5002A has an I2C-bus serial microcontroller
interface capable of operating at 400 kbits/s.
The PCD5002A is a slave transceiver with a 7-bit I2C-bus
address 39 (bits A6 to A0 = 0100111).
After a reset the initial condition of the battery-low indicator
in the status register is zero.
Data transmission requires 2 lines: SDA (data) and SCL
(clock), each with an external pull-up resistor. The clock
signal (SCL) for any data transmission must be generated
by the external controlling device.
8.25 Synthesizer control
Control of an external frequency synthesizer is possible
via a dedicated 3-line serial interface (outputs ZSD, ZSC
and ZLE). This interface is common to a number of
available synthesizers. The synthesizer is enabled using
the oscillator enable output ROE.
A transmission is initiated by a START condition
(S: SCL = 1, SDA = ↓) and terminated by a STOP
condition (P: SCL = 1, SDA = ↑).
Data bits must be stable when SCL is HIGH. If there are
multiple transmissions, the STOP condition can be
replaced with a new START condition.
The frequency parameters must be programmed in
EEPROM. Two blocks of maximum 24 bits each can be
stored. Any unused bits must be programmed at the
beginning of a block: only the last bits are used by the
synthesizer.
Data is transferred on a byte basis, starting with a device
address and a read/write indicator. Each transmitted byte
must be followed by an acknowledge bit A (active LOW).
If a receiving device is not ready to accept the next
complete byte, it can force a bus wait state by holding SCL
LOW.
When the function is selected by SPF programming
(SPF byte 1, bit D6), data is transferred to the synthesizer
each time the PCD5002A is switched from the OFF to the
ON status. Transfer takes place serially in two blocks,
starting with bit 0 (MSB) of block 1 (see Table 28).
The general I2C-bus transmission format is illustrated in
Fig.6. Formats for master/slave communication are
illustrated in Fig.9.
1999 Jan 08
18
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
t
ZSD
MSB
LSB
23
0
12
ZSD
ZSC
ZLE
TIME
TIME
t
t
ZDL1
p
t
t
ZDS
ZCL
t
MLC248
ZLE
Fig.7 Synthesizer interface timing.
SDA
MSB
LSB
N
A
MSB
LSB
N
A
S
P
INTERRUPT
SERVICING
SCL
1
2
7
8
9
1
2
7
8
9
START
ADDRESS
R/W
A
DATA
A
STOP
MLC249
Fig.8 I2C-bus message format.
19
1999 Jan 08
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
A = Acknowledge
FROM
FROM
SLAVE
S = START condition
P = STOP condition
MASTER
N = Not acknowledge
(a)
S
S
SLAVE ADDRESS
SLAVE ADDRESS
R/W
A
INDEX
A
DATA
A
DATA
A
P
index
address
0
1
(write)
n bytes with acknowledge
(b)
R/W
A
DATA
A
DATA
N
P
(read)
n bytes with acknowledge
(c)
S
SL. ADR. R/W
A
INDEX
A
DATA
A
S
SL. ADR. R/W
A
DATA
N
P
index
address
1
(read)
0
(write)
n bytes with
acknowledge
n bytes with
acknowledge
change of direction
MLC250
(a) Master writes to slave.
(b) Master reads from slave.
(c) Combined format (shown: write plus read).
Fig.9 Message types.
8.27 Decoder I2C-bus access
Data written to read-only bits will be ignored. Values read
from write-only bits are undefined and must be ignored.
All internal access to the PCD5002A takes place via the
I2C-bus interface. For this purpose the internal registers,
SRAM and EEPROM have been memory mapped and are
accessed via an index register. Table 16 shows the index
addresses of all internal blocks.
Each I2C-bus write message to the PCD5002A must start
with its slave address, followed by the index address of the
memory element to be accessed. An I2C-bus read
message uses the last written index address as a data
source. The different I2C-bus message types are shown in
Fig.9.
Registers are addressed directly, while RAM and
EEPROM are addressed indirectly via address pointers
and I/O registers.
As a slave the PCD5002A cannot initiate bus transfers by
itself. To prevent an external controller from having to
monitor the operating status of the decoder, all important
events generate an external interrupt on output INT.
Remark: The EEPROM memory map is non-contiguous
and is organized as a matrix. The EEPROM address
pointer contains both row and column indicators.
1999 Jan 08
20
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Table 16 Index register
ADDRESS(1)
REGISTER FUNCTION
ACCESS
00H
00H
status
R
W
control
01H
real-time clock: seconds
real-time clock: 1⁄100 second
alert cadence
R/W
R/W
W
02H
03H
04H
alert set-up
W
05H
periodic interrupt modulus
periodic interrupt counter
RAM write address pointer
EEPROM address pointer
RAM read address pointer
RAM data output
W
05H
R
06H
R
07H
R/W
R/W
R
08H
09H
0AH
EEPROM data input/output
unused
R/W
note 2
0BH to 0FH
Notes
1. The index register only uses the least significant nibble, the upper 4 bits are ignored.
2. Writing to registers 0B to 0F has no effect, reading produces meaningless data.
The interrupt output INT is reset after completion of a
status read operation.
8.28 External interrupt
The PCD5002A can signal events to an external controller
via an interrupt signal at output INT. The interrupt polarity
is programmable via SPF programming. The interrupt
source is shown in the status register.
8.29 Interrupt masking
In the PCD5002A certain interrupts can be suppressed by
masking via the control register. The following interrupts
can be masked:
Interrupts are generated by the following events (more
than one event is possible):
• Out-of-Range (status bit D5): change of state
interrupt, masked by setting control register bit D5
• Call data available for output (bit D2)
• SRAM pointers becoming equal (bit D3)
• Expiry of periodic time-out (bit D7)
• BAT/RXE monitoring (status bit D6): change of state
interrupt (source selected by control register bit D2),
masked by setting control register bit D6
• Expiry of alert time-out (bit D4)
• Periodic Timer (status bit D7): timer overflow interrupt,
• Change of state in out-of-range indicator (bit D5)
masked by setting control register bit D7.
• Change of state in battery-low indicator or in receiver
control output RXE (bit D6).
Although no interrupts are generated by these conditions
when masked via the control register, the corresponding
status bits are updated normally and available via the
status register. At reset the control register is cleared,
causing all interrupts to be enabled.
Immediate interrupts are generated by status bits D3,
D4, D6 (RXE monitoring) and D7. Bits D2, D5 and D6
(BAT monitoring) generate interrupts as soon as the
receiver is disabled (RXE = 0).
When call data is available (D2 = 1) but the receiver
remains switched on, an interrupt is generated at the next
sync word position, if data fail mode (short fade recovery
mode in APOC1) is not active.
1999 Jan 08
21
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
8.30 Status/control register
The status/control register consists of two independent registers, one for reading (status) and one for writing (control).
The status register shows the current operating condition of the decoder and the cause(s) of an external interrupt.
The control register activates/deactivates certain functions. Tables 17 and 18 show the bit allocations of both registers.
All status bits will be reset after a status read operation except for the out-of-range, battery-low and receiver enable
indicator bits (see note 1 to Table 17).
Table 17 Status register (00H; read)
BIT(1)
VALUE
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
DESCRIPTION
no new call data
new call received (POCSAG or APOC1)
continuous decoding data available
batch zero data available (APOC1)
no data to be read (default after reset)
RAM read/write pointers different; data to be read
RAM read/write pointers equal; no more data to read
RAM buffer full or overflow
D1 and D0
D3 and D2
D4
D5
D6
D7
alert time-out expired
1
out-of-range
1
BAT input HIGH or RXE output active (selected by control bit D2)
periodic timer interrupt
1
Note
1. After a status read operation bits D3, D4 and D7 are always reset, bits D1 and D0 only when no second call is
pending. D2 is reset when the RAM is empty (read and write pointers equal).
Table 18 Control register (00H; write)
BIT (MSB: D7)
VALUE
DESCRIPTION
forced call termination (automatically reset after termination)
EEPROM programming enable
D0
D1
1
1
0
1
1
0
1
1
1
1
BAT input selected for monitoring (status bit D6)
RXE output selected for monitoring (status bit D6)
receiver continuously enabled (RXE = 1 and ROE = 1)
decoder in OFF status (while DON = 0)
decoder in ON status
D2
D3
D4
D5
D6
D7
out-of-range interrupt masked
BAT/RXE monitor interrupt masked
Periodic Timer interrupt masked
1999 Jan 08
22
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
to via the I2C-bus. The bit allocation of both registers is
shown in Tables 19 and 20.
8.31 Pending interrupts
A secondary status register is used for storing status bits
of pending interrupts. This occurs:
Table 19 Real-time clock; seconds register (01H;
• When a new call is received while the previous one was
not yet acknowledged by reading the status register
read/write)
BIT
(MSB D7)
• When an interrupt occurs during a status read operation.
VALUE
DESCRIPTION
After completion of the status read the primary register is
loaded with the contents of the secondary register, which
is then reset. An immediate interrupt is then generated,
output INT becoming active 1 decoder clock cycle after it
was reset following the status read.
D0
−
−
−
−
−
−
X
1 s
2 s
D1
D2
4 s
D3
8 s
D4
16 s
32 s
Remark: In the event of multiple pending calls, only the
status bits of the last call are retained.
D5
D6
not used: ignored when written;
undetermined when read
8.32 Out-of-range indication
The out-of-range condition occurs when entering the
‘fade recovery’ or ‘carrier off’ mode in POCSAG, or
‘transmitter off’ or ‘carrier detect’ mode in APOC1. This
condition is reflected in bit D5 of the status register.
The out-of-range condition is reset when either preamble
or a valid sync word is detected.
D7
X
not used: ignored when written;
undetermined when read
Table 20 Real-time clock; 1⁄100 second register (02H;
read/write)
BIT
(MSB D7)
The out-of-range bit (D5) in the status register is updated
each time the receiver is disabled (RXE ↓ 0). Every
change of state in bit D5 generates an interrupt.
VALUE
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
D7
−
−
−
−
−
−
−
X
0.01 s
0.02 s
0.04 s
0.08 s
0.16 s
0.32 s
0.64 s
8.33 Real-time clock
The PCD5002A provides a periodic reference pulse at
output REF. The frequency of this signal can be selected
by SPF programming:
• 32768 Hz
• 50 Hz (square wave)
not used: ignored when written;
undetermined when read
• 2 Hz
1
•
⁄60 Hz.
8.34 Periodic interrupt
The 32768 Hz signal does not have a fixed period, it
consists of 32 pulses distributed over 75 main oscillator
cycles at 76.8 kHz. The timing is illustrated in Fig.16.
A periodic interrupt can be realised with the periodic
interrupt counter. This 8-bit counter is incremented every
1
⁄
100 s and produces an interrupt when it reaches the value
When programmed for 1⁄60 Hz (1 pulse per minute) the
pulse at output REF is held off while the receiver is
enabled.
stored in the periodic interrupt modulus register.
The counter register is then reset and counting continues.
Operation is started by writing a non-zero value to the
modulus register. Writing a zero will stop interrupt
generation immediately and will halt the periodic interrupt
counter after 2.55 s.
Except for the 50 Hz frequency the pulse width tRFP is
equal to one decoder clock period.
The real-time clock counter runs continuously irrespective
of the operating condition of the PCD5002A. It contains a
seconds register (maximum 59) and a 1⁄100 second
register (maximum 99), which can be read from or written
The modulus register is write-only, the counter register is
read only. Both registers have the same index address
(05H).
1999 Jan 08
23
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
8.35 Received call delay
Call reception (detection of an enabled RIC) causes both the periodic interrupt modulus and the counter register to be
reset.
Since the periodic interrupt counter runs for another 2.55 s after a reset, the received call delay (in 1⁄100 s units) can be
determined by reading the counter register.
Table 21 Alert set-up register (04H; write)
BIT (MSB D7)
VALUE
DESCRIPTION
call alert via cadence register
0
1
D0
POCSAG call alert (pattern selected by D7 and D6)
LOW level acoustic alert (ATL), pulsed vibrator alert (25 Hz)
HIGH level acoustic alert (ATL + ATH), continuous vibrator alert
normal alerts (acoustic and LED)
0
D1
D2
1
0
1
warbled alerts: 16 Hz (LED: on/off, ATL/ATH: alternate fAWH, fAWL
acoustic alerts enable (ATL, ATH)
)
D3
D4
D5
1
1
vibrator alert enabled (VIB)
1
LED alert enabled (LED)
0 0
0 1
1 0
1 1
POCSAG alert pattern FC = 00; see Fig.10 (a)
POCSAG alert pattern FC = 01; see Fig.10 (b)
POCSAG alert pattern FC = 10; see Fig.10 (c)
POCSAG alert pattern FC = 11; see Fig.10 (d)
D7 and D6(1)
Note
1. Bits D7 and D6 correspond to function bits 20 and 21 respectively in the address code-word, which designate the
POCSAG call type as shown in Table 1.
D7, D6
0 0
(a)
0 1
(b)
1 0
(c)
1 1
MLC251
(d)
Fig.10 POCSAG alert patterns.
1999 Jan 08
24
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Since D1 acts immediately on the alert level, it is advisable
to reset the last bit of the previous pattern to prevent
unwanted audible level changes.
8.36 Alert generation
The PCD5002A is capable of controlling 3 different alert
transducers, acoustic beeper (high and low level), LED
and vibrator motor. The associated outputs are ATH/ATL,
LED and VIB respectively. ATL is an open-drain output
capable of directly driving an acoustic alerter via a resistor.
The other outputs require external transistors.
8.39 Vibrator alert
The vibrator output (VIB) is activated continuously during
a standard POCSAG alert or whenever the alert cadence
register is non-zero.
Each alert output can be individually enabled via the alert
set-up register. Alert level and warble can be separately
selected. The alert pattern can either be standard
POCSAG or determined via the alert cadence register.
Direct alert control is possible via input ALC.
Two alert levels are supported, LOW level (25 Hz square
wave) and HIGH level (continuous). The vibrator level is
controlled by bit D1 in the alert set-up register.
8.40 LED alert
The alert set-up register is shown in Table 21.
The LED output pattern corresponds either to the selected
POCSAG alert or to the contents of the alert cadence
register. No equivalent exists for HIGH/LOW level alerts.
Standard POCSAG alerts can be selected by setting
bit D0 in the alert set-up register, bits D6 and D7
determining the alert pattern used.
8.41 Warbled alert
8.37 Alert cadence register (03H; write)
When enabled, by setting bit D2 in the alert set-up register,
the signals on outputs ATL, ATH and LED are warbled with
a 16 Hz modulation frequency. Output LED is switched on
and off at the modulation rate, while outputs ATL and ATH
switch between fAWH and fAWL alerter frequencies.
When not programmed for POCSAG alerts (alert set-up
register bit D0 = 0), the 8-bit alert cadence register
determines the alert pattern. Each bit represents a
62.5 ms time slot, a logic 1 activating the enabled alert
transducers. The bit pattern is rotated with the
MSB (bit D7) being output first and the LSB (bit D0) last.
8.42 Direct alert control
When the last time slot (bit D0) is initiated an interrupt is
generated to allow loading of a new pattern. When the
pattern is not changed it will be repeated. Writing a zero to
the alert cadence register will halt alert generation within
62.5 ms.
A direct alert control input (ALC) is available for generating
user alarm signals (e.g. battery-low warning). A HIGH level
on input ALC activates all enabled alert outputs, overruling
any ongoing alert patterns.
8.43 Alert priority
8.38 Acoustic alert
Generation of a standard POCSAG alert (D0 = 1)
overrides any alert pattern in the alert cadence register.
After completion of the standard alert, the original cadence
is restarted from its last position. The alert set-up register
will now contain the settings for the standard alert.
Acoustic alerts are generated via outputs ATL and ATH.
For LOW level alerts only ATL is active, while for HIGH
level alerts ATH is also active. ATL is driven in counter
phase with ATH.
The alert level is controlled by bit D1 in the alert set-up
register.
The highest priority has been assigned to the alert control
input (ALC). All enabled alert outputs will be activated
while ALC is set. Outputs are activated/deactivated in
synchronism with the decoder clock. Activation requires an
extra delay of 1 clock when no alerts are being generated.
When D1 is reset, for standard POCSAG alerts (D0 = 1) a
LOW level acoustic alert is generated during the first
4 s (ATL), followed by 12 s at HIGH level (ATL + ATH).
When D1 is set, the full 16 s are at HIGH level. An interrupt
is generated after the full alert time has elapsed (indicated
by bit D4 in the status register).
When input ALC is reset, acoustic alerting does not cease
until the current output frequency cycle has been
completed.
When using the alert cadence register, D1 would normally
be updated by external control when the alert time-out
interrupt occurs at the start of the 8th cadence time slot.
1999 Jan 08
25
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
FC = 00
t
t
ALP
ALC
FC = 01
t
ALP
t
ALP
t
ALC
FC = 10
t
t
t
ALP
ALC
ALP
FC = 11
t
ALP
t
t
t
ALC
ALC
ALP
MLC252
Fig.11 POCSAG alert timing.
The RAM is filled by the decoder and can be read via the
I2C-bus interface. The RAM is accessed indirectly by a
read address pointer and a data output register. A write
address pointer indicates the position of the last message
byte stored.
8.44 Cancelling alerts
Standard POCSAG alerts (manual or automatic) are
cancelled by resetting bit D0 in the alert set-up register.
User defined alerts are cancelled by writing a zero to the
alert cadence register. Any ongoing alert is cancelled
when a reset pulse is applied to input RST.
Status register bit D2 is set when the read and write
pointers are different. It is reset only when the SRAM
pointers become equal during reading, i.e. when the RAM
becomes empty.
8.45 Automatic POCSAG alerts
Standard alert patterns have been defined for each
POCSAG call type, as indicated by the function bits in the
address code-word (see Table 1). The timing of these alert
patterns is shown in Fig.11. After completion of the full 16 s
alert period an interrupt is generated by status bit D4.
Status bit D3 is set when the read and write pointers
become equal. This can be due to a RAM empty or a RAM
full condition. It is reset after a status read operation.
Interrupts are generated as follows:
When enabled by SPF programming (SPF byte 03, bit D2)
standard POCSAG alerts will be automatically generated
at outputs ATL, ATH, LED and VIB upon call reception.
The alert pattern matches the call type as indicated by the
function bits in the received address code-word.
• When status bit D2 is set and the receiver is disabled
(RXE = 0); data is available for reading, if data fail mode
(short fade recovery mode in APOC1) is not active
• Immediately when status bit D3 is set: RAM is either
empty (status bit D2 = 0) or full (status bit D2 = 1).
The original settings of the alert set-up register will be lost.
Bit D0 is reset after completion of the alert.
To avoid loss of data due to RAM overflow at least 3 bytes
of data must be read during reception of the code-word
following the ‘RAM full’ interrupt.
8.46 SRAM access
The on-chip SRAM can hold up to 96 bytes of call data.
Each call consists of a call header (3 bytes), message data
blocks (3 bytes per code-word) and a call terminator
(3 bytes).
1999 Jan 08
26
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
8.47 RAM write address pointer (06H; read)
8.51 EEPROM address pointer (07H; read/write)
The RAM write address pointer is automatically
An EEPROM location is addressed via the EEPROM
address pointer. It is incremented automatically each time
a byte is read from or written to via the EEPROM data I/O
register.
incremented during call reception, because the decoder
writes each data byte to RAM. The RAM write address
pointer can only be read. Values range from 00H to 5FH.
Bit D7 (MSB) is not used and its value is undefined when
read. When a call data byte is written to location 5FH, the
write address pointer wraps around to 00H. This does not
necessarily imply a RAM full condition.
The EEPROM address pointer contains two counters for
the row and the column number. Bits D2 to D0 contain the
column number (0 to 5) and bits D5 to D3 the row number
(0 to 7). Bits D7 and D6 of the address pointer are not
used. Data written to these bits will be ignored, while their
values are undefined when read.
8.48 RAM read address pointer (08H; read/write)
The RAM read address pointer is automatically
incremented after reading a data byte via the RAM output
register.
The column and row counters are connected in series.
Upon overflow of the column counter (column = 5) the row
counter is automatically incremented and the column
counter wraps to 0. On overflow the row counter wraps
from 7 to 0.
The RAM read address pointer can be accessed for
reading and writing.
The values range from 00H to 5FH. When at 5FH a read
operation will cause wrapping around to 00H. Bit D7
(MSB) is not used; it is ignored when written to and
undefined when read from.
8.52 EEPROM data I/O register (0AH; read/write)
The byte addressed by the EEPROM address pointer can
be written to or read from via the EEPROM data I/O
register. Each access automatically increments the
EEPROM address pointer.
8.49 RAM data output register (09H; read)
The RAM data output register contains the byte addressed
by the RAM read address pointer and can only be read.
Each read operation causes an increment of the RAM read
address pointer.
8.53 EEPROM access limitations
Since the EEPROM address pointer is used during data
decoding, the EEPROM may not be accessed while the
receiver is active (RXE = 1). It is advisable to switch to the
OFF state before accessing the EEPROM.
8.50 EEPROM access
The EEPROM cannot be written to unless the EEPROM
programming enable bit (bit D1) in the control register is
set.
The EEPROM is intended for storage of user addresses
(RICs), sync words and special programmed function
(SPF) bits representing the decoder configuration.
For writing a minimum programming supply voltage
(VDD(prog)) is required (2.0 V typ.). The programming
supply current (IDD(prog)) required during writing is
approximately 500 µA.
The EEPROM can store 48 bytes of information and is
organized as a matrix of 8 rows by 6 columns.
The EEPROM is accessed indirectly via an address
pointer and a data I/O register.
The EEPROM is protected against inadvertent writing by
means of the programming enable bit in the control
register (bit D1).
8.54 EEPROM read operation
EEPROM read operations must start at a valid address in
the non-contiguous memory map. Single byte or block
reads are permitted.
The EEPROM memory map is non-contiguous. Figure 12
shows both the EEPROM organization and the access
method.
8.55 EEPROM write operation
Identifier locations contain RICs or sync words. A total of
20 unassigned bytes are available for general purpose
storage.
EEPROM write operations must always take place in
blocks of 6 bytes, starting at the beginning of a row.
Programming a single byte will reset the other bytes in the
same row. Modifying a single byte in a row requires
re-writing the unchanged bytes with their old contents.
1999 Jan 08
27
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
After writing each block a pause of 7.5 ms (max.) is
required to complete the internal programming operation.
During this time the external microcontroller may generate
an I2C-bus STOP condition. If another I2C-bus transfer is
initiated the decoder will pull SCL LOW during this pause.
8.58 Unused EEPROM locations
A total of 20 EEPROM bytes are available for general
purpose storage (see Table 22).
Table 22 Unused EEPROM addresses
After writing the EEPROM programming enable bit (D1) in,
the control register must be reset.
ROW
HEX
04 and 05(1)
28 to 2D
30 to 35
0
5
6
7
8.56 Invalid write address
When an invalid write address is used, the column counter
bits (D2 to D0) are forced to zero before being loaded into
the address pointer. The row counter bits are used
normally.
38 to 3D
Note
1. When using bytes 04H and 05H, care must be taken
to preserve the SPF information stored in bytes
00H to 03H.
8.57 Incomplete programming sequence
A programming sequence may be aborted by an I2C-bus
STOP condition. The EEPROM programming enable
bit (D1) in the control register must then be reset.
8.59 Special programmed function allocation
The SPF bit allocation in the EEPROM is shown in
Tables 23 to 27. The SPF bits are located in row 0 of the
EEPROM and occupy 4 bytes.
Any bytes received from the last 6-byte block will be
ignored and the contents of this (incomplete) EEPROM
block will remain unchanged.
Bytes 04H and 05H are not used and are available for
general purpose storage.
COLUMN
ADDRESS
POINTER
0
1
2
3
4
5
D7
D0
0
0
1
2
3
4
5
6
7
0
1
0
1
0
I
I
I
I
I
I
D
1
D
2
D
3
D
4
D
5
D
6
ROW COLUMN
I/O REGISTER
ROW
D7
D0
SPF bits
Synthesizer data
Identifiers
unused bytes
MLC254
Fig.12 EEPROM organization and access.
1999 Jan 08
28
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Table 23 Special programmed functions (EEPROM address 00H)
BIT (MSB: D7)
VALUE
DESCRIPTION
POCSAG decoding enabled
0
D0
1
APOC1 decoding enabled
0
cycle length: 5 batches
D1
1
0 to 4
0 to 14
1
cycle length: 15 batches
batch number (D1 = 0; MSB is ignored)
batch number (D1 = 1)
D5 to D2 (MSB D5)
D6
D7
continuous data decoding enabled
received data inversion enabled
1
Table 24 Special programmed functions (EEPROM address 01H)
BIT (MSB: D7)
VALUE
DESCRIPTION
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
5 ms receiver establishment time (nominal); note 1
10 ms receiver establishment time (nominal); note 1
15 ms receiver establishment time (nominal); note 1
30 ms receiver establishment time (nominal); note 1
20 ms oscillator establishment time (nominal); note 1
30 ms oscillator establishment time (nominal); note 1
40 ms oscillator establishment time (nominal); note 1
50 ms oscillator establishment time (nominal); note 1
512 bits/s received bit rate
D1 and D0
D3 and D2
D5 and D4
1024 bits/s (not used in POCSAG)
1200 bits/s
2400 bits/s
D6
D7
synthesizer interface enabled (programming at switch-on)
voltage converter enabled
1
Note
1. Since the exact establishment time is related to the programmed bit rate, Table 25 shows the values for the various
bit rates.
1999 Jan 08
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Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Table 25 Establishment time as a function of bit rate
NOMINAL
ACTUAL ESTABLISHMENT TIME
ESTABLISHMENT
512 (bits/s)
TIME
1024 (bits/s)
1200 (bits/s)
2400 (bits/s)
5 ms
10 ms
15 ms
20 ms
30 ms
40 ms
50 ms
5.9 ms (3 bits)
11.7 ms (6 bits)
15.6 ms (8 bits)
23.4 ms (12 bits)
31.2 ms (16 bits)
39.1 ms (20 bits)
46.9 ms (24 bits)
5.9 ms (6 bits)
11.7 ms (12 bits)
15.6 ms (16 bits)
23.4 ms (24 bits)
31.2 ms (32 bits)
39.1 ms (40 bits)
46.9 ms (48 bits)
5 ms (6 bits)
10 ms (12 bits)
16.7 ms (20 bits)
20 ms (24 bits)
26.7 ms (32 bits)
40 ms (48 bits)
53.3 ms (64 bits)
5 ms (12 bits)
10 ms (24 bits)
16.7 ms (40 bits)
20 ms (48 bits)
26.7 ms (64 bits)
40 ms (96 bits)
53.3 ms (128 bits)
Table 26 Special programmed functions (EEPROM address 02H)
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
X
not used
not used
X
0 0
0 1
1 0
1 1
1
32768 Hz real-time clock reference
50 Hz square wave
D3 and D2
2 Hz
1
⁄
60 Hz
D4
D5
signal test mode enabled (REF and INT outputs)
burst error correction enabled
0
0 0
0 1
1 0
1 1
30 s (+0.5 s max.) transmitter off time-out
60 s (+ 1 s max.) transmitter off time-out
120 s (+ 2 s max.) transmitter off time-out
240 s (+ 4 s max.) transmitter off time-out
D7 and D6
Table 27 Special programmed functions (EEPROM address 03H)
BIT (MSB: D7)
VALUE
DESCRIPTION
2048 Hz acoustic alerter frequency
0 0
0 1
1 0
1 1
1
2731 Hz acoustic alerter frequency
4096 Hz acoustic alerter frequency
3200 Hz acoustic alerter frequency
automatic POCSAG alert generation enabled
not used
D1 and D0
D2
D3
D4
X
X
not used
0
DQC mode 0
D5
D6
D7
1
DQC mode 1
0
INT output polarity: active LOW
INT output polarity: active HIGH
standard call termination
enhanced call termination
1
0
1
1999 Jan 08
30
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Identifiers are stored in EEPROM rows 2, 3 and 4. Each
identifier location consists of 3 bytes in the same column.
The identifier number is equal to the column number + 1.
8.60 Synthesizer programming data
Data for programming a PLL synthesizer via pins ZSD,
ZSC and ZLE can be stored in row 1 of the EEPROM.
Six bytes are available starting with address 08H.
Each identifier can be individually enabled. The standard
POCSAG sync word is always enabled and has identifier
number 7.
Data is transferred in two serial blocks of 24 bits each,
starting with bit 0 (MSB) of block 1. Any unused bits must
be programmed at the beginning of a block.
The identifier type is determined by bits D2 and D0 of
identifier byte 3, as shown in Table 31.
Table 28 Synthesizer programming data (EEPROM
Identifiers 1 and 2 always represent RICs or batch zero
identifiers. The last 4 identifiers (numbers 3 to 6) can
represent any identifier type.
address 08H to 0DH)
ADDRESS
(HEX)
BIT
(MSB: D7)
DESCRIPTION
A UPSW represents an unused address and must differ by
more than 6 bits from preamble to guarantee detection.
D7 to D0
bits 0 to 7 of data block 1
(bit 0 is MSB)
08
A batch zero identifier marks the start of a new cycle in the
APOC1 protocol. It is only recognized when APOC1
decoding has been enabled (SPF byte 00, bit D0).
09
0A
0B
D7 to D0
D7 to D0
D7 to D0
bits 8 to 15
bits 16 to 23
bits 0 to 7 of data block 2
(bit 0 is MSB)
Reception of a CDD sync word initiates continuous data
decoding. CDD sync words are only recognized when
continuous data decoding has been enabled
(SPF byte 00, bit 6).
0C
0D
D7 to D0
D7 to D0
bits 8 to 15
bits 16 to 23
Table 29 shows the memory locations of the 6 identifiers.
The bit allocation per identifier is given in Table 30.
8.61 Identifier storage allocation
Up to 6 different identifiers can be stored in EEPROM for
matching with incoming data. The PCD5002A can
distinguish two types of identifiers:
• User addresses (RIC)
• User Programmable Sync Words (UPSW)
• Batch zero identifiers
• Continuous Data Decoding (CDD) sync words.
Table 29 Identifier storage allocation (EEPROM address 10H to 25H)
ADDRESS (HEX)
BYTE
DESCRIPTION
10 to 15
18 to 1D
20 to 25
1
2
3
identifier number 1 to 6
identifier number 1 to 6
identifier number 1 to 6
1999 Jan 08
31
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Table 30 Identifier bit allocation
BYTE
BIT (MSB: D7)
DESCRIPTION
1
2
D7 to D0
D7 to D0
D7 and D6
D5
bits 2 to 9 of POCSAG code-word (RIC or UPSW); notes 1 and 2
bits 10 to 17
bits 18 and 19
frame number bit FR3 (RIC); note 3
frame number bit FR2 (RIC)
D4
3
D3
frame number bit FR1 (RIC)
D2
identifier type selection (0 = UPSW, 1 = RIC); note 4
identifier enable (1 = enabled)
D1
D0
batch zero ID/continuous decoding (1 = enabled)
Notes
1. The bit numbering corresponds with the numbering in a POCSAG code-word; bit 1 is the flag bit (0 = address,
1 = message).
2. A UPSW needs 18 bits to be matched for successful identification. Bit 1 (MSB) must be logic 0. Bits 2 to 19 contain
the identifier bit pattern, they are followed by 2 predetermined random (function) bits and the UPSW is completed by
10 CRC error correction bits and an even-parity bit.
3. Bits FR3 to FR1 (MSB: FR3) contain the 3 least significant bits of the 21-bit RIC.
4. Identifiers 1 and 2 (RIC only) will be disabled by programming bit D2 as logic 0.
Table 31 Identifier types
BYTE 3; BIT D2
BYTE 3; BIT D0
DESCRIPTION
user programmable sync word
0
0
1
1
0
1
0
1
continuous data decoding sync word
normal user address (RIC)
batch zero identifier
The level-shifted interface lines are RST, DON, ALC, REF
8.62 Voltage doubler
and INT.
An on-chip voltage doubler provides an unregulated DC
output for supplying an LCD or a low power microcontroller
at output VPO. An external ceramic capacitor of 100 nF
(typ.) is required between pins CCN and CCP. The voltage
doubler is enabled via SPF programming.
The I2C-bus interface lines SDA and SCL can be
level-shifted independently of VPR by the standard external
pull-up resistors.
8.64 Signal test mode
8.63 Level-shifted interface
A special ‘signal test’ mode is available for monitoring the
performance of a receiver circuit together with the
front-end of the PCD5002A.
All interface lines are suited for communication with a
microcontroller operating from a higher supply voltage.
The external device must have a common reference at VSS
of the PCD5002A.
For this purpose the output of the digital noise filter and the
recovered bit clock are made available at outputs REF and
INT respectively. All synchronization and decoding
functions are normally active.
The reference voltage for the level-shifted interface must
be applied to input VPR. If required this could be the
on-chip voltage doubler output VPO. When the
The ‘signal test’ mode is activated/deactivated by SPF
programming.
microcontroller has a separate (regulated) supply it should
be connected to VPR
.
1999 Jan 08
32
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Recommended minimum values in this case are
C = 2.2 nF and R = 100 kΩ (see Fig.17).
9
OPERATING INSTRUCTIONS
Reset conditions
9.1
9.3
Reset timing
When the PCD5002A is reset by applying a HIGH level to
input RST, the condition of the decoder is as follows:
The start-up time for the crystal oscillator may exceed 1 s
(typ. 800 ms). It is advisable to apply a reset condition, at
least during the first part of this period. The minimum reset
pulse duration tRST is 50 µs.
• OFF status (irrespective of DON input level)
• REF output frequency 32768 Hz
• All internal counters reset
During reset the oscillator is active, but clock signals are
inhibited internally. Once the reset condition is released
the end of the oscillator start-up period can be detected by
a rising edge on output INT.
• Status/control register reset
• All interrupts enabled
• No alert transducers selected
• LED, VIB and ATH outputs at LOW level
• ATL output high-impedance
During a reset the voltage converter clock (Vclk) is held at
zero. The resulting output voltage drop may cause
problems when the external resetting device is powered by
the internal voltage doubler. A sufficiently large buffer
capacitor connected between output VPO and VSS must be
provided to supply the microcontroller during reset.
The voltage at VPO will not drop below VDD − 0.7 V.
• SDA and SCL inputs high-impedance
• Voltage converter disabled.
The programmed functions are activated within tRSU after
release of the reset condition (RST LOW). The settings
affecting the external operation of the PCD5002A are as
follows:
Immediately after a reset all programmable internal
functions will start operating according to a programmed
value of 0. During the first 8 full clock cycles (tRSU) all
programmed values are loaded from EEPROM.
• REF output frequency
• Voltage converter
• INT output polarity
• Signal test mode.
After reset the receiver outputs RXE and ROE become
active immediately, if DON is HIGH and the synthesizer is
disabled. When the synthesizer is enabled, RXE and ROE
will only become active after the second pulse on ZLE
completes the loading of synthesizer data.
When input DON is HIGH, the decoder starts operating in
ON status immediately following tRSU
.
The full reset timing is illustrated in Fig.13. The start-up
timing including synthesizer programming is illustrated in
Fig.14.
9.2 Power-on reset circuit
During power-up of the PCD5002A a HIGH level of
minimum duration tRST = 50 µs must be applied to
pin RST. This is to prevent EEPROM corruption which
might otherwise occur because of the undefined contents
of the control register.
9.4
Initial programming
A newly-delivered PCD5002A has EEPROM contents
which are undefined. The EEPROM should therefore be
programmed, followed by a reset to activate the SPF
settings, before any attempt is made to use the device.
The reset signal can be applied by the external
microcontroller or by an RC power-on reset circuit on
pin RST (C to VPR, R to VSS). Such an RC-circuit should
have a time constant of at least 3tRST = 150 µs.
Input RST has an internal high-ohmic pull-down resistor
(nominal 2 MΩ at 2.5 V supply) which could be used
together with a suitable external capacitor connected to
VPR to create a power-on reset signal. However, since this
pull-down resistor varies considerably with processing and
supply voltage, the resulting time constant is inaccurate.
A more accurate reset duration can be realised with an
additional external resistor connected to VSS
.
1999 Jan 08
33
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XTAL1
RST
asynchronous
t
RST
REF
INT
programmed for 32768 Hz
active LOW
active HIGH
active LOW
active HIGH
V
clk
RXE (DON = 1)
(1)
ZLE
(2)
MLC253
t
RSU
(1) The RXE output signal is shown for disabled synthesizer. When the synthesizer is enabled RXE is held off until after the second pulse on ZLE (programming complete).
(2) The ZLE output signal is shown for enabled synthesizer and DON = 1. When DON = 0 output ZLE remains HIGH until ON state is entered (DON = 1 or control register bit D4 = 1).
ahdnbok,uflapegwidt
Fig.13 Reset timing.
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
DON
ZSC
ZLE
BLOCK 1
BLOCK 2
t
t
ZDL1
ZDL1
t
t
p
ZDL2
RXE
t
t
clk
ZSU
t
MLC255
OSU
Fig.14 Start-up timing including synthesizer programming.
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
−0.5
−0.5
MAX.
+7.0
+7.0
UNIT
VDD
VPR
Vn
supply voltage
external reference voltage input
V
V
PR ≥ VDD − 0.8 V
V
voltage on pins ALC, DON, RST, SDA and SCL Vn ≤ 7.0 V
V
V
−
−
SS − 0.8 VPR + 0.8
V
Vn1
Ptot
Pout
Tamb
Tstg
input voltage on any other pin
total power dissipation
V
n1 ≤ 7.0 V
SS − 0.8 VDD + 0.8
V
250
100
mW
mW
°C
°C
power dissipation per output
operating ambient temperature
storage temperature
−25
−55
+70
+125
1999 Jan 08
35
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
11 DC CHARACTERISTICS
VDD = 2.7 V; VPR = 2.7 V; VSS = 0 V; Tamb = −25 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
VPR
supply voltage
voltage converter disabled
1.5
2.7
6.0
V
V
external reference voltage
input
VPR ≥ VDD − 0.8 V
1.5
2.7
6.0
VDD(prog)
programming supply voltage
voltage converter disabled
voltage converter enabled
note 1
2.0
2.0
−
−
6.0
V
V
−
3.0
IDD0
supply current (OFF)
supply current (ON)
25.0
50.0
−
40.0
80.0
800
µA
µA
µA
IDD1
note 1; DON = VDD
−
IDD(prog)
programming supply current
−
Inputs
VIL
LOW-level input voltage pins
RDI and BAT
VSS
VSS
VSS
−
−
−
0.3VDD
0.3VPR
0.3VDD
V
V
V
DON, ALC and RST
SDA and SCL
VIH
HIGH-level input voltage pins
RDI and BAT
0.7VDD
0.7VPR
0.7VDD
0
−
−
−
−
VDD
VPR
VPR
−0.5
V
DON, ALC and RST
SDA and SCL
V
V
IIL
LOW-level input current pins
RDI, BAT,TS1, TS2, DON,
ALC and RST
Tamb = 25 °C; VI = VSS
µA
IIH
HIGH-level input current pins
TS1 and TS2
Tamb = 25 °C
VI = VDD
6
−
20
µA
µA
µA
nA
RDI and BAT
VI = VDD; RXE = 0
VI = VDD; RXE = 1
VI = VPR
6
−
20
RDI and BAT
0
−
0.5
850
DON, ALC and RST
250
500
Outputs
IOL
LOW-level output current pins Tamb = 25 °C
VIB and LED
ATH
V
OL = 0.3 V
VOL = 0.3 V
80
250
80
70
13
80
−
−
µA
µA
µA
µA
mA
µA
−
−
INT and REF
ZSD, ZSC and ZLE
ATL
V
V
V
OL = 0.3 V
−
−
OL = 0.3 V
−
−
OL = 1.2 V; note 2
27
−
55
−
ROE, RXE and DQC
VOL = 0.3 V
1999 Jan 08
36
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
SYMBOL
IOH
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
HIGH-level output current pins Tamb = 25 °C
VIB, LED and DQC
ATH
V
V
V
V
OH = 0.7 V
OH = 0.7 V
OH = 2.4 V
OH = 2.4 V
−0.6
−
−
−
−
−
−
−2.4
mA
−3.0
−80
−60
−
−11.0
mA
µA
µA
µA
µA
INT and REF
ZSD, ZSC and ZLE
ATL
−
−
ATL high-impedance; note 3
VOH = 2.4 V
−0.5
−
ROE and RXE
−600
Notes
1. Inputs: SDA and SCL pulled up to VDD; all other inputs connected to VSS
Outputs: RXE and ROE logic 0; REF: fref = 1⁄60 Hz; all other outputs open-circuit.
.
Oscillator: no crystal; external clock fosc = 76800 Hz; amplitude: VSS to VDD
Voltage convertor disabled (SPF byte 01, bit D7 = 0; see Table 24).
.
2. Maximum output current is subject to absolute maximum ratings per output (see Chapter 10).
3. When ATL (open-drain output) is not activated it is high impedance.
12 DC CHARACTERISTICS (WITH VOLTAGE CONVERTER)
VDD = 2.7 V; VSS = 0 V; VPR = VPO; Tamb = −25 to +70 °C; Cs = 100 nF; voltage converter enabled.
SYMBOL
VDD
PARAMETER
supply voltage
CONDITIONS
MIN.
1.5
TYP.
MAX.
UNIT
−
3.0
−
V
VPO(0)
VPO
output voltage; no load
output voltage
VDD = 2.7 V; IPO = 0
−
5.4
V
VDD = 2 V; IPO = −250 µA
VDD = 2 V; VPO = 2.7 V
3.0
3.5
−
V
IPO
output current
−400
−650
−650
−900
−
µA
µA
V
DD = 3 V; VPO = 4.5 V
−
13 OSCILLATOR CHARACTERISTICS
Quartz crystal type: MX-1V or equivalent. Quartz crystal parameters: f = 76800 Hz; RS(max) = 35 kΩ; CL = 8 pF;
C0 = 1.4 pF; C1 = 1.5 fF. Maximum overall tolerance: ±200 × 10−6 (includes: cutting, temperature, aging) for POCSAG,
±55 × 10−6 for APOC1 (‘transmitter off’ mode).
SYMBOL
CXO
PARAMETER
CONDITIONS
MIN.
TYP.
UNIT
output capacitance XTAL2
oscillator transconductance
−
10
12
pF
gm
VDD = 1.5 V
6
µS
1999 Jan 08
37
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
14 AC CHARACTERISTICS
V
DD = 2.7 V; VSS = 0 V; VPR = 2.7 V; Tamb = 25 °C;. fosc = 76800 Hz.
SYMBOLS PARAMETER CONDITIONS
System clock
Tclk system clock period
Call alert frequencies
MIN.
TYP.
MAX.
UNIT
fosc = 76800 Hz
−
13.02
−
µs
fAL
alert frequency
SPF byte 03H; bits
D1 and D0 = 0 0
D1 and D0 = 0 1
D1 and D0 = 1 0
D1 and D0 = 1 1
−
−
−
−
−
2048
2731
3200
4096
16
−
−
−
−
−
Hz
Hz
Hz
Hz
Hz
fAW
warbled alert; modulation
frequency
alert set-up bit D2 = 1; outputs
ATL, ATH and LED
fAWH
fAWL
fVBP
warbled alert; high acoustic
alert frequency
alert set-up bit D2 = 1; outputs
ATL and ATH
−
−
−
fAL
−
−
−
Hz
Hz
Hz
warbled alert; low acoustic alert alert set-up bit D2 = 1; outputs
frequency
1⁄2fAL
25
ATL and ATH
pulsed vibrator frequency
(square wave)
low-level alert
Call alert duration
tALT
tALL
tALH
tVBL
tVBH
tALC
tALP
alert time-out period
−
−
−
−
−
−
−
16
4
−
−
−
−
−
−
−
s
ATL output time-out period
ATH output time-out period
VIB output time-out period
VIB output time-out period
alert cycle period
low-level alert
high-level alert
low-level alert
high-level alert
s
12
4
s
s
12
1
s
s
alert pulse duration
125
ms
Real-time clock reference
fref
real-time clock reference
frequency
SPF byte 02H; bits
D3 and D2 = 0 0; note 1
D3 and D2 = 0 1; note 2
D3 and D2 = 1 0
−
−
−
−
−
32768
−
−
−
−
−
Hz
Hz
Hz
Hz
µs
50
2
1
D3 and D2 = 1 1
⁄
60
tRFP
real-time clock reference pulse all reference frequencies except
duration 50 Hz (square wave)
13.02
1999 Jan 08
38
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Receiver control
tRXT
RXE and ROE transition time
CL = 5 pF
−
100
−
ns
tRXON
RXE establishment time
(nominal values: actual duration
is bit rate dependent, see
Table 25)
SPF byte 01H; bits
D1 and D0 = 0 0
D1 and D0 = 0 1
D1 and D0 = 1 0
D1 and D0 = 1 1
SPF byte 01H; bits
D3 and D2 = 0 0
D3 and D2 = 0 1
D3 and D2 = 1 0
D3 and D2 = 1 1
−
−
−
−
5
−
−
−
−
ms
ms
ms
ms
10
15
30
tROON
ROE establishment time
(nominal values: actual duration
is bit rate dependent, see
Table 25)
−
−
−
−
20
30
40
50
−
−
−
−
ms
ms
ms
ms
I2C-bus interface
fSCL
SCL clock frequency
0
−
−
−
−
−
−
−
−
−
−
−
100
−
kHz
µs
µs
ns
ns
ns
ns
pF
µs
µs
µs
tLOW
tHIGH
tSU;DAT
tHD;DAT
tr
SCL clock low period
SCL clock HIGH period
data set-up time
4.7
4.0
250
500
−
−
−
data hold time
−
SDA and SCL rise time
SDA and SCL fall time
capacitive bus line load
START condition set-up time
START condition hold time
STOP condition set-up time
1000
300
400
−
tf
−
CB
−
tSU;STA
tHD;STA
tSU;STO
4.7
4.0
4.0
−
−
Reset
tRST
tRSU
tOSU
external reset duration
set-up time after reset
set-up time after switch-on
50
−
−
−
−
−
µs
µs
ms
oscillator running
oscillator running
105
4
−
Data input
tTDI
data input transition time
data input logic 1 duration
data input logic 0 duration
see Fig.15
see Fig.15
see Fig.15
−
−
−
−
100
∞
µs
tDI1
tBIT
tBIT
tDI0
∞
POCSAG data timing (512 bits/s)
fDI
data input rate
bit duration
SPF byte 01H; D5 = 0; D4 = 0
−
512
−
−
−
−
−
bits/s
ms
tBIT
tCW
tPA
−
1.9531
62.5
−
code-word duration
preamble duration
batch duration
−
ms
1125
ms
tBAT
−
1062.5
ms
1999 Jan 08
39
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
POCSAG data timing (1200 bits/s)
fDI
data input rate
bit duration
SPF byte 01H; D5 = 1; D4 = 0
−
−
−
1200
833.3
26.7
−
−
bits/s
µs
tBIT
tCW
tPA
−
−
−
−
code-word duration
preamble duration
batch duration
ms
480
ms
tBAT
−
453.3
ms
POCSAG data timing (2400 bits/s)
fDI
data input rate
bit duration
SPF byte 01H; D5 = 1; D4 = 1
−
2400
416.6
13.3
−
−
−
−
−
−
bits/s
µs
tBIT
tCW
tPA
−
code-word duration
preamble duration
batch duration
−
ms
240
−
ms
tBAT
226.6
ms
APOC1 batch timing
tSB
cycle duration
SPF byte 00H; bit D2 = 0
(5 batches)
−
−
2720
8160
−
−
bits
bits
SPF byte 00H; bit D2 = 0
(15 batches)
Synthesizer control
tZSU
fZSC
tZCL
tZSD
tZDS
tZDL1
tZLE
synthesizer set-up duration
oscillator running; note 3
note 4
1
−
−
−
−
−
−
−
−
2
−
−
−
−
−
−
−
bits
Hz
µs
µs
µs
µs
µs
µs
output clock frequency
clock pulse duration
data bit duration
38400
13.02
26.04
13.02
91.15
13.02
117.19
note 4
data bit set-up time
data load enable delay
load enable pulse duration
inter block delay
tZDL2
Notes
1. 32768 Hz reference signal; 32 pulses per 75 clock cycles, alternately separated by 1 or 2 pulse periods
(pulse duration: tRFP). The timing is shown in Fig.16.
2. 50 Hz reference signal: square wave.
3. Duration depends on programmed bit rate; after reset tZSU = 1.5 bits.
4. Nominal values; pause in 12th data bit (see Table 11).
1999 Jan 08
40
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
t
t
DI0
DI1
handbook, halfpage
t
MGL100
TDI
Fig.15 Data input timing.
t
RFP
t
RFP
MLC278
2t
RFP
Fig.16 Timing of the 32 768 Hz reference signal.
41
1999 Jan 08
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BATTERY
POSITIVE
M
C
s
100 nF
10
µF
(2)
(1)
(1)
function
keys
4.7
4.7
kΩ
kΩ
V
V
V
ANT
ATL ATH
RDI
VIB
LED
CCP CCN
V
V
DD
PO
PR
DATA
OUT
RST
BAT
REF
(2)
RECEIVER
BAT
RXE
PWR
CTRL
DON
INT
OSC
VCO
V
MICROCONTROLLER
REF
ALC
PCD5002A
DECODER
SDA
SCL
V
PWR
CTRL
ROE
V
FREQUENCY
SYNTHESIZER
DATA
CLK
ZSD
ZSC
ZLE
LATCH
V
LCD
V
V
XTAL1
XTAL2
SS
DQC
TS1
n.c.
TS2
DRIVER
V
n.c.
n.c.
LCD
BATTERY
NEGATIVE
76.8 kHz
2.2 MΩ
10 pF
V
LCD
DRIVER
V
2
I C-bus
MGL565
(1) Value depends on number of devices attached.
(2) Values should be chosen to give a time constant of at least 150 µs. C = 2.2 nF and R = 100 kΩ are recommended.
ahdnbok,uflapegwidt
Fig.17 Typical application example (display pager).
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
16 PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y
X
A
24
17
25
16
Z
E
e
H
E
A
E
(A )
3
2
A
A
1
w M
p
θ
b
L
p
pin 1 index
L
32
9
detail X
1
8
e
Z
D
v M
A
w M
b
p
D
B
H
v M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.4 0.18 7.1
0.3 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.9
0.5
0.9
0.5
mm
1.60
0.25
0.8
1.0
0.2 0.25 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-08-04
SOT358 -1
1999 Jan 08
43
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
If wave soldering is used the following conditions must be
observed for optimal results:
17 SOLDERING
17.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
17.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
17.4 Manual soldering
17.3 Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Jan 08
44
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
17.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
HLQFP, HSQFP, HSOP, SMS
PLCC(3), SO
not suitable(2)
suitable
suitable
suitable
suitable
suitable
suitable
not recommended(3)(4)
LQFP, QFP, TQFP
SQFP
not suitable
not recommended(5)
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Jan 08
45
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
18 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
19 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
20 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Jan 08
46
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
NOTES
1999 Jan 08
47
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For all other countries apply to: Philips Semiconductors,
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465008/00/01/pp48
Date of release: 1999 Jan 08
Document order number: 9397 750 04676
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