PCD5002U/10 [NXP]
Advanced POCSAG and APOC-1 Paging Decoder; 先进的POCSAG和APOC - 1解码器分页
| 型号： | PCD5002U/10 |
| 厂家： | 
NXP |
| 描述： | Advanced POCSAG and APOC-1 Paging Decoder |
| 文件： | 总48页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCD5002
Advanced POCSAG and APOC-1
Paging Decoder
1997 Jun 24
Product specification
Supersedes data of 1997 Mar 04
File under Integrated Circuits, IC17
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
CONTENTS
8.41
8.42
8.43
8.44
8.45
8.46
8.47
8.48
8.49
8.50
8.51
8.52
8.53
8.54
8.55
8.56
8.57
8.58
8.59
8.60
8.61
Cancelling alerts
Automatic POCSAG alerts
SRAM access
1
2
3
4
5
6
7
8
FEATURES
RAM write address pointer (06H; read)
RAM read address pointer (08H; read/write)
RAM data output register (09H; read)
EEPROM access
EEPROM address pointer (07H; read/write)
EEPROM data I/O register (0AH; read/write)
EEPROM access limitations
EEPROM read operation
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
LICENSE
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
EEPROM write operation
Invalid write address
8.1
Introduction
Incomplete programming sequence
Unused EEPROM locations
Special programmed function allocation
Synthesizer programming data
Identifier storage allocation
Voltage doubler
8.2
8.3
8.4
The POCSAG paging code
The APOC-1 paging code
Error correction
8.5
Operating states
8.6
ON status
8.7
OFF status
Level-shifted interface
Signal test mode
8.8
Reset
8.9
Bit rates
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
8.22
8.23
8.24
8.25
8.26
8.27
8.28
8.29
8.30
8.31
8.32
8.33
8.34
8.35
8.36
8.37
8.38
8.39
8.40
Oscillator
Input data processing
Battery saving
POCSAG Synchronization strategy
APOC-1 synchronization strategy
Call termination
Call data output format
Error type indication
Data transfer
Continuous data decoding
Receiver and oscillator control
External receiver control and monitoring
Battery condition input
Synthesizer control
Serial microcontroller interface
Decoder I2C-bus access
External interrupt
Status/Control register
Pending interrupts
Out-of-range indication
Real time clock
Periodic interrupt
Received call delay
Alert generation
Alert cadence register (03H; write)
Acoustic alert
Vibrator alert
LED alert
Warbled alert
Direct alert control
Alert priority
9
OPERATING INSTRUCTIONS
9.1
9.2
9.3
9.4
Reset conditions
Power-on reset circuit
Reset timing
Initial programming
10
11
12
LIMITING VALUES
DC CHARACTERISTICS
DC CHARACTERISTICS (WITH VOLTAGE
CONVERTER)
13
14
15
16
17
OSCILLATOR CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING QFP
17.1
17.2
17.3
17.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
18
19
20
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
1997 Jun 24
2
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
• On-chip SRAM buffer for message data
1
FEATURES
• Slave I2C-bus interface to microcontroller for transfer of
message data, status/control and EEPROM
programming (data transfer at up to 100 kbits/s)
• Wide operating supply voltage range: 1.5 to 6.0 V
• EEPROM programming requires only 2.0 V supply
• Low operating current: 50 µA typ. (ON), 25 µA typ.
(OFF)
• Wake-up interrupt for microcontroller, programmable
polarity
• Temperature range −25 to +70 °C
• Direct and I2C-bus control of operating status (ON/OFF)
• Battery-low indication (external detector)
• Out-of-range condition indication
• “CCIR radio paging Code No. 1” (POCSAG) compatible
• Supports Advanced Pager Operator’s Code Phase 1
(APOC-1) for extended battery economy
• Real time clock reference output
• 512, 1200 and 2400 bits/s data rates using 76.8 kHz
crystal
• On-chip voltage doubler
• Interfaces directly to UAA2080 and UAA2082 paging
receivers.
• Built-in data filter (16-times oversampling) and bit clock
recovery
• Advanced ACCESS synchronization algorithm
2
APPLICATIONS
• 2-bit random and (optional) 4-bit burst error correction
• Advanced display pagers (POCSAG and APOC-1)
• Basic alert-only pagers
• Information services
• Up to 6 user addresses (RICs), each with
4 functions/alert cadences
• Up to 6 user address frames, independently
programmable
• Personal organizers
• Standard POCSAG sync word, plus up to 4 user
programmable sync words
• Telepoint
• Telemetry/data transmission.
• Continuous data decoding upon reception of user
programmable sync word (optional)
3
GENERAL DESCRIPTION
• Received data inversion (optional)
The PCD5002 is a very low power pager decoder and
controller, capable of handling both standard POCSAG
and the advanced APOC-1 code. Continuous data
decoding upon reception of a dedicated sync word is
available for news pager applications.
• Call alert via beeper, vibrator or LED
• 2-level acoustic alert using single external transistor
• Alert control: automatic (POCSAG type), via cadence
register or alert input pin
• Separate power control of receiver and RF oscillator for
battery economy
Data rates supported are 512, 1200 and 2400 bits/s using
a single 76.8 kHz crystal. On-chip EEPROM is
programmable using a minimum supply voltage of 2.0 V,
allowing ‘over-the-air’ programming. I2C-bus compatible.
• Synthesizer set-up and control interface (3-line serial)
• On-chip EEPROM for storage of user addresses (RICs),
pager configuration and synthesizer data
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SOT358-1
−
PCD5002H
LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
PCD5002U/10
−
film-frame carrier (naked die) 32 pads
5
LICENSE
Supply of this IC does neither convey nor express an implied license under any patent right to use this in any APOC
application.
1997 Jun 24
3
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
6
BLOCK DIAGRAM
7
EEPROM
RESET
SET-UP
RST
26
ZSD
ZSC
ZLE
27
28
SYNTHESIZER
CONTROL
9
EEPROM CONTROL
SDA
2
I C-BUS
10
CONTROL
SCL
24
25
DECODING
DATA
CONTROL
RXE
ROE
RECEIVER
CONTROL
POCSAG
SYNCHRONIZATION
5
INT
REGISTERS
AND
INTERRUPT
CONTROL
RAM
CONTROL
21
DATA FILTER
AND
BAT
23
3
RDI
MAIN DECODER
CLOCK
30
31
1
RECOVERY
VIB
RAM
LED
ATL
ATH
ALC
ALERT
GENERATION
AND
CLOCK
CONTROL
MASTER
DIVIDER
TIMER
REFERENCE
DON
32
2
CONTROL
16
20
4
TS1
TS2
REF
TEST
CONTROL
15
14
13
8
CCN
CCP
VOLTAGE
DOUBLER
AND LEVEL
SHIFTER
18
17
PCD5002
XTAL1
XTAL2
OSCILLATOR
V
PO
V
PR
11
12, 29
MGD081
V
DD
V
SS
Fig.1 Block diagram.
4
1997 Jun 24
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
7
PINNING
SYMBOL PIN
DESCRIPTION
alert LOW level output
ATL
1
2
ALC
alert control input
(normally LOW by internal pull-down)
DON
REF
3
4
direct ON/OFF input
(normally LOW by internal pull-down)
real time clock frequency reference
output
INT
n.c.
RST
5
6
7
interrupt output
not connected
reset input
(normally LOW by internal pull-down)
VPR
8
external positive voltage reference
input
SDA
SCL
VDD
VSS
9
I2C-bus serial data input/output
10 I2C-bus serial clock input
11 main positive supply voltage
12 main negative supply voltage
13 voltage converter positive output
ATL
ALC
DON
REF
INT
1
2
3
4
5
6
7
8
RXE
24
VPO
CCP
23 RDI
22 n.c.
14 voltage converter shunt capacitor
(positive side)
21 BAT
20 TS2
19 n.c.
PCD5002H
CCN
TS1
15 voltage converter shunt capacitor
(negative side)
n.c.
16 test input 1
RST
18 XTAL1
17 XTAL2
(normally LOW by internal pull-down)
V
PR
XTAL2
XTAL1
n.c.
17 decoder crystal oscillator output
18 decoder crystal oscillator input
19 not connected
MGD080
TS2
20 test input 2
(normally LOW by internal pull-down)
BAT
n.c.
RDI
21 battery sense input
22 not connected
23 received data input
(POCSAG or APOC-1)
RXE
ROE
ZSD
ZSC
ZLE
VSS
24 receiver circuit enable output
25 receiver oscillator enable output
26 synthesizer serial data output
27 synthesizer serial clock output
28 synthesizer latch enable output
29 main negative supply voltage
30 vibrator motor drive output
31 LED drive output
VIB
LED
ATH
Fig.2 Pin configuration for SOT358-1 (LQFP32).
32 alert HIGH level output
1997 Jun 24
5
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
The PCD5002 contains a low-power, high-efficiency
8
FUNCTIONAL DESCRIPTION
Introduction
voltage converter (doubler) designed to provide a higher
voltage supply to LCD drivers or microcontrollers.
In addition, an independent level shifted interface is
provided allowing communication to a microcontroller
operating at a higher voltage than the PCD5002.
8.1
The PCD5002 is a very low power decoder and pager
controller specifically designed for use in new generation
radio pagers. The architecture of the PCD5002 allows for
flexible application in a wide variety of radio pager designs.
Interface to such an external device is provided by an
I2C-bus which allows received call identity and message
data, data for the programming of the internal EEPROM,
alert control and pager status information to be transferred
between the devices. Pager status includes features
provided by the PCD5002 such as battery-low and
out-of-range indications. A dedicated interrupt line
minimizes the required microcontroller activity.
The PCD5002 is fully compatible with “CCIR Radio paging
Code No. 1” (also known as the POCSAG code) operating
at data rates of 512, 1200 and 2400 bits/s using a single
oscillator crystal of 76.8 kHz.
The PCD5002 also supports the new Advanced Pager
Operator’s Code Phase 1 (APOC-1). This compatible
extension to the POCSAG code improves battery
economy by introducing ‘cycles’ and batch numbering.
A cycle consists of 5 or 15 standard POCSAG batches.
Each pager will be allocated a batch number in addition to
its POCSAG address and it will only search for its address
during this batch.
A selectable low frequency timing reference is provided for
use in real time clock functions.
Data synchronization is achieved by the Philips patented
ACCESS algorithm ensuring that maximum advantage is
made of the POCSAG code structure particularly in fading
radio signal conditions. The algorithm allows for data
synchronization without preamble detection whilst
minimizing battery power consumption. The APOC-1 code
uses an extended version of the ACCESS
In addition to the standard POCSAG sync word (used also
in APOC-1) the PCD5002 is also capable of recognizing
up to 4 User Programmable Sync Words (UPSWs).
This permits the reception of both private services and
POCSAG or APOC-1 transmissions via the same radio
channel. As an option reception of a UPSW may activate
Continuous Data Decoding (CDD).
synchronization algorithm.
Random (and optional) burst error correction techniques
are applied to the received data to optimize the call
success rate without increasing the falsing rate beyond
specified POCSAG levels.
Used together with the Philips UAA2080 or UAA2082
paging receiver, the PCD5002 offers a highly
sophisticated, miniature solution for the radio paging
market. Control of an RF synthesizer circuit is also
provided to ease alignment and channel selection.
8.2
The POCSAG paging code
A transmission using the “CCIR Radio paging Code No. 1”
(POCSAG code) is constructed in accordance with the
following rules (see Fig.3).
On-chip EEPROM provides storage for user addresses
(Receiver Identity Codes or RICs) and Special
Programmed Functions (SPFs) and UPSWs, which
eliminates the need for external storage devices and
interconnection. For other non-volatile storage 20 bytes of
general purpose EEPROM are available. The low
EEPROM programming voltage makes the PCD5002 well
suited for ‘over-the-air’ programming/reprogramming.
The transmission is started by sending a preamble,
consisting of at least 576 continuously alternating bits
(10101010...). The preamble is followed by an arbitrary
number of batch blocks. Only complete batches are
transmitted.
Each batch comprises 17 codewords of 32 bits each.
The first codeword is a synchronization codeword with a
fixed pattern. The sync word is followed by 8 frames
(0 to 7) of 2 codewords each, containing message
information. A codeword in a frame can either be an
address, message or idle codeword.
On request from an external controlling device or
automatically (by SPF programming), the PCD5002 will
provide standard POCSAG alert cadences by driving a
standard acoustic ‘beeper’. Non-standard alert cadences
may be generated via a cadence register or a dedicated
control input.
Idle codewords also have a fixed pattern and are used to
fill empty frames or to separate messages.
The PCD5002 can also produce a HIGH level acoustic
alert as well as drive an LED indicator and a vibrator motor
via external bipolar transistors.
1997 Jun 24
6
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Address codewords are identified by an MSB at logic 0
and are coded as shown in Fig.3. A user address or RIC
consists of 21 bits. Only the upper 18 bits are encoded in
the address codeword (bits 2 to 19). The lower 3 bits
designate the frame number (0 to 7) in which the address
is transmitted.
(bit 32). This permits correction of a maximum of 2 random
errors or up to 3 errors in a burst of 4 bits (a 4-bit burst
error) per codeword.
8.3
The APOC-1 paging code
The APOC-1 paging code is fully POCSAG compatible
and involves the introduction of batch grouping and a
Batch Zero Identifier. This reserved address codeword
indicates the start of a ‘cycle’ of 5 or 15 batches long and
is transmitted immediately after a sync word.
Four different call types (‘numeric’, ‘alphanumeric’ and two
‘alert only’ types) can be distinguished. The call type is
determined by two function bits in the address codeword
(bits 20 and 21), as shown in Table 1.
Alert-only calls consist only of a single address codeword.
Numeric and alphanumeric calls have message
codewords following the address. A message causes the
frame structure to be temporarily suspended. Message
codewords are sent until the message is completed, with
only the sync words being transmitted in their expected
positions.
Cycle transmission must be coherent i.e. a transmission
starting an integer number of cycle periods after the start
of the previous one.
Broadcast message data may be included in a
transmission. This information may occupy any number of
message codewords and immediately follows the batch
zero identifier of the first cycle after preamble.
Message codewords are identified by an MSB at logic 1
and are coded as shown in Fig.3. The message
information is stored in a 20-bit field (bits 2 to 21).
The presence of data is indicated by the function bits in the
batch zero identifier: 1,1 indicates ‘no broadcast data’.
Any other combination indicates a broadcast message.
The standard data format is determined by the call type: 4
bits per digit for numeric messages and 7 bits per (ASCII)
character for alphanumeric messages.
The PCD5002 can be configured for POCSAG or APOC-1
operation via SPF programming. The batch zero identifier
is programmable and can be stored in any identifier
location in EEPROM.
Each codeword is protected against transmission errors by
10 CRC check bits (bits 22 to 31) and an even-parity bit
PREAMBLE
BATCH 1
BATCH 2
BATCH 3
LAST BATCH
10101 . . . 10101010
SYNC | CW CW | CW CW | . . . . . | CW CW
FRAME 0
FRAME 1
FRAME 7
Address code-word
Message code-word
0
1
18-bit address
20-bit message
2 function bits
10 CRC bits
P
P
10 CRC bits
MCD456
Fig.3 POCSAG code structure.
7
1997 Jun 24
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 1 POCSAG recommended call types and function bits
BIT 20 (MSB)
BIT 21 (LSB)
CALL TYPE
DATA FORMAT
0
0
1
1
0
1
0
1
numeric
alert only 1
alert only 2
alphanumeric
4-bits per digit
−
−
7-bits per ASCII character
The POCSAG standard only allows combinations of data
formats and function code bits as given in Table 1.
However, other (non-standard) combinations will be
decoded normally by the PCD5002.
Table 3 Truth table for decoder operating status
DON
CONTROL
BIT D4
OPERATING STATUS
INPUT
0
0
1
1
0
1
0
1
OFF
ON
ON
ON
8.4
Error correction
In the PCD5002 error correction methods have been
implemented as shown in Table 2.
Random error correction is default for both address and
message codewords. In addition, burst error correction
can be enabled by SPF programming. Up to 3 erroneous
bits in a 4-bit burst can be corrected.
8.6
ON status
In the ON status the decoder pulses the receiver and
oscillator enable outputs (RXE and ROE respectively)
according to the code structure and the synchronization
algorithm. Data received serially at the data input (RDI) is
processed for call reception.
The error type detected for each codeword is identified in
the message data output to the microcontroller, allowing
rejection of calls with too many errors.
The data protocol can be POCSAG or APOC-1.
Continuous data decoding upon reception of a special
sync word is also supported. The data protocol is selected
by SPF programming.
Table 2 Error correction
ITEM
Preamble
CORRECTION
4 random errors in 31 bits
2 random errors in 32 bits
Reception of a valid paging call is signalled to the
microcontroller by an interrupt signal. The received
address and message data can then be read via the
I2C-bus interface.
Synchronization
codeword
Address codeword
2 random errors, plus 4-bit burst
errors (optional)
Message codeword
2 random errors, plus 4-bit burst
errors (optional)
8.7
OFF status
In the OFF status the decoder will neither activate the
receiver or oscillator enable outputs, nor process any data
at the data input. The crystal oscillator remains active to
permit communication with the microcontroller.
8.5
Operating states
The PCD5002 has 2 operating states:
• ON status
In both operating states an accurate timing reference is
available via the REF output. Using SPF programming the
signal periodicity may be selected as 32.768 kHz, 50 Hz,
2 Hz or 1⁄60 Hz.
• OFF status.
The operating state is determined by a Direct Control input
(DON) and bit D4 in the control register (see Table 3).
8.8
Reset
The decoder can be reset by applying a positive pulse on
input pin RST. For successful reset at power-on, a HIGH
level must be present on the RST pin while the device is
powering-up.
1997 Jun 24
8
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
This can be applied by the microcontroller, or via a suitable
RC power-on reset circuit connected to the RST input.
Reset circuit details and conditions during and after a reset
are described in Chapter 9.
received again, the receiver is re-enabled thus observing
the programmed establishment times tRXE and tROE
.
The current consumption of the complete pager can be
minimized by separately activating the RF oscillator circuit
(using output ROE) before activating the rest of the
receiver. This is possible using the UAA2082 receiver
which has external biasing for the oscillator circuit.
8.9
Bit rates
The PCD5002 can be configured for data rates of 512,
1200 or 2400 bits/s by SPF programming. These data
rates are derived from a single 76.8 kHz oscillator
frequency.
8.13 POCSAG Synchronization strategy
In the ON status the PCD5002 synchronizes to the
POCSAG data stream by the Philips ACCESS algorithm.
A flow diagram is shown in Fig.4. Where ‘sync word’ is
used, this implies both the standard POCSAG sync word
and any enabled User Programmable Sync Word
(UPSW).
8.10 Oscillator
The oscillator circuit is designed to operate at 76.8 kHz.
Typically, a tuning fork crystal will be used as a frequency
source. Alternatively, an external clock signal can be
applied to pin XTAL1 (amplitude = VDD to VSS), but a
slightly higher oscillator current is consumed. A 2.2 MΩ
feedback resistor connected between XTAL1 and XTAL2
is required for proper operation.
Several modes of operation can be distinguished
depending on the synchronization state. Each mode uses
a different method to obtain or retain data synchronization.
The receiver and oscillator enable outputs (RXE and ROE
respectively) are switched accordingly, with the
appropriate establishment times (tRXON and tROON
respectively).
To allow easy oscillator adjustment (e.g. by a variable
capacitor) a 32.768 kHz reference frequency can be
selected at output REF by SPF programming.
Before comparing received data with preamble, an
enabled sync word or programmed user addresses, the
appropriate error correction is applied.
8.11 Input data processing
Data input is binary and fully asynchronous. Input bit rates
of 512, 1200 and 2400 bits/s are supported. As a
programmable option, the polarity of the received data can
be inverted before further processing.
Initially, after switching to the ON status, the decoder is in
switch-on mode. Here the receiver will be enabled for a
period up to 3 batches, testing for preamble and the sync
word. Failure to detect preamble or the sync word will
cause the device to switch to the ‘carrier off’ mode.
The input data is noise filtered by a digital filter. Data is
sampled at 16 times the data rate and averaged by
majority decision.
When preamble is detected it will cause the device to
switch to the preamble receive mode, in which a sync
word is searched for. The receiver will remain enabled
while preamble is detected. When neither sync word nor
preamble is found within a 1 batch duration the ‘carrier off’
mode is entered.
The filtered data is used to synchronize an internal clock
generator by monitoring transitions. The recovered clock
phase can be adjusted in steps of 1⁄8 or 1⁄32 bit period per
received bit.
The larger step size is used when bit synchronization has
not been achieved, the smaller when a valid data
sequence has been detected (e.g. preamble or sync
word).
Upon detection of a sync word the data receive mode is
entered. The receiver is activated only during enabled user
address frames and sync word periods. When an enabled
user address has been detected, the receiver will be kept
enabled for message codeword reception until the call
termination criteria are met.
8.12 Battery saving
Current consumption is reduced by switching off internal
decoder sections whenever the receiver is not enabled.
During call reception data bytes are stored in an internal
SRAM buffer, capable of storing 2 batches of message
data.
To further increase battery efficiency, reception and
decoding of an address codeword is stopped as soon as
the uncorrected address field differs by more than 3 bits
from the enabled RICs. If the next codeword must be
Messages are transmitted contiguously, only interrupted
by sync words at the beginning of each batch.
1997 Jun 24
9
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
When a message extends beyond the end of a batch no
testing for sync takes place. Instead, a message data
transfer will be initiated by an interrupt to the external
controller. Data reception continues normally after a period
corresponding to the sync word duration.
15 batches, allowing recovery of synchronization from
long fades in the radio signal. Detection of preamble
causes switching to the ‘preamble receive’ mode, while
sync word detection causes switching to the ‘data receive’
mode. When neither is found within a period of 15 batches,
the radio signal is considered lost and the ‘carrier off’ mode
is entered.
If any message codeword is found to be uncorrectable, the
‘data fail’ mode is entered and no data transfer will be
attempted at the next sync word position. Instead, a test for
sync word will be carried out.
The purpose of the carrier off mode is to detect a valid
radio transmission and synchronize to it quickly and
efficiently. Because transmissions may start at random,
the decoder enables the receiver for 1 codeword in every
18 codewords looking for preamble or sync word.
By using a buffer containing 32 bits (n bits from the current
scan, 32 −n from the previous scan) effectively every batch
bit position can be tested within a continuous transmission
of at least 18 batches. Detection of preamble causes the
device to switch to the ‘preamble receive’ mode, while
sync word detection causes the device to switch to the
‘data receive’ mode.
In the data fail mode message reception continues
normally for 1 batch duration. When a sync word is
detected at the expected position the decoder returns to
the ‘data receive’ mode. If the sync word again fails to
appear, then batch synchronization is deemed lost. Call
reception is then terminated and the ‘fade recovery’ mode
is entered.
The fade recovery mode is intended to scan for sync word
and preamble over an extended window (nominal
position ± 8 bits). This is performed for a period of up to
OFF to ON status
no preamble or
sync word
switch-on
(3 batches)
sync word
preamble
no preamble or
sync word
preamble receive
(1 batch)
sync word
data receive
data fail
sync word
no sync word
preamble
preamble
preamble
no preamble or
sync word
(1 batch)
sync word
sync word
fade recovery
no preamble or
sync word
(15 batches)
carrier off
MLC247
Fig.4 ACCESS synchronization algorithm for POCSAG.
10
1997 Jun 24
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
OFF to ON status
switch on
no preamble
or sync word
(3 batches)
preamble
carrier detect
sync word
TX off
time out
preamble
sync word
no preamble (1 batch)
preamble receive 1
long fade recovery
preamble
sync word
sync word
preamble
no sync word
batch zero detect
batch zero ID
batch zero identify
cycle receive
no batch zero ID
batch
zero ID
sync
word
no sync
word
preamble
short fade recovery
no sync word
or preamble
sync word
transmitter off
no preamble
(1 batch)
TX off time out
sync word
preamble
preamble receive 2
MGD269
Fig.5 APOC-1 synchronization algorithm.
If preamble is not found within one batch duration then the
‘long fade recovery’ mode is entered.
8.14 APOC-1 synchronization strategy
The synchronization strategy in APOC-1 is an extended
version of the ACCESS scheme and is illustrated in Fig.5.
The PCD5002 counts the number of batches in a
transmission, starting from the first batch received after
preamble. Counter overflow occurs due to the size of a
cycle, as determined by SPF programming.
When in batch zero detect mode the PCD5002 switches
on every batch to maintain synchronization and check for
the batch zero identifier. Detection of the batch zero
identifier activates the ‘cycle receive’ mode. When
synchronization is lost the ‘long fade recovery’ mode is
entered. ‘preamble receive’ mode is entered when
preamble is detected.
Initially, after switching to the ON status, the decoder will
be in the switch-on mode. Here the receiver will be
enabled for up to 3 batches, testing for preamble and sync
word. Detection of preamble causes the device to switch
to the ‘preamble receive’ mode, while any enabled sync
word enters the ‘batch zero detect’ mode. Failure to detect
either will cause the device to switch to the ‘carrier detect’
mode.
In the batch zero identify mode the first codeword
immediately after the sync word of the first batch is
compared with the programmed batch zero identifier.
Failure to detect the batch zero identifier will cause the
device to enter the ‘short fade recovery’ mode.
When this comparison is successful the function bits
determine whether any broadcast message will follow.
Any function bit combination other than ‘1,1’ will cause the
PCD5002 to accept message codewords until terminated
by a valid address codeword.
In the preamble receive 1 mode the PCD5002 searches
for a sync word, the receiver remaining enabled while
preamble is detected. As soon as an enabled sync word is
found the ‘batch zero identify’ mode is started.
1997 Jun 24
11
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
After reception of any broadcast message data the
Synchronization checking is performed over a window
PCD5002 continues to operate in the ‘cycle receive’ mode. ranging from ‘n’ bits before to ‘n’ bits after the expected
sync word position. The window tolerance ‘n’ depends on
the time since the ‘transmitter off’ mode was entered and
on the selected bit rate (see Table 4).
In the cycle receive mode the PCD5002 enables call
reception in only one programmed batch per cycle. Sync
word detection takes place from 2 bits before to 2 bits after
the expected sync word position of this batch. If the sync
word is not detected then the position of the current sync
word will be maintained and the ‘short fade recovery’
mode will be entered.
When a sync word is detected in this widened
synchronization window the PCD5002 enters the
‘batch zero identify’ mode. Time-out expiry before a sync
word has been detected causes the device to switch to the
‘long fade recovery’ mode.
When a valid sync word is found user address codeword
detection takes place, as in normal POCSAG code.
Any following message codewords are received normally.
If a message extends into a subsequent batch containing
a batch zero identifier, then the batch zero identifier is
detected normally and message reception will continue.
Detection of preamble in the ‘transmitter off’ mode initiates
the preamble receive 2 mode. Operation in this mode is
identical to ‘preamble receive mode. Failure to detect
preamble for one batch period will cause the device to
switch back to the ‘transmitter off’ mode. This prevents
inadvertent loss of cycle synchronization due to spurious
signals resembling preamble.
Data reception is suspended after the programmed batch
until the same batch position in the next cycle.
The exception being when a received call continues into
the next batch.
The carrier detect mode is identical to the ‘carrier off’
mode in standard POCSAG operation. Upon first entry the
transmitter off time-out is started. The receiver is enabled
to receive one codeword in every 18 codewords to check
for sync word and preamble. This check is performed on
the last available 32 bits for every received bit.
In the short fade recovery mode the programmed data
receive batch will continue to be checked for user address
codewords. In addition the first codeword after the
programmed batch is checked for sync word or preamble.
The ‘preamble receive’ mode is entered if preamble is
detected. If a valid sync word is found the
‘batch zero detect’ mode is entered. If neither has been
detected and the time-out expires, then the
‘long fade recovery’ mode is entered.
When a valid sync word is detected the ‘cycle receive’
mode is re-entered, while detection of preamble causes
the device to switch to the ‘preamble receive’ mode. When
neither is found then the ‘transmitter off’ mode is entered.
In the transmitter off mode a time-out is set to a
pre-programmed duration. This time-out corresponds to
the maximum time between subsequent transmissions
(preamble to preamble).
The long fade recovery mode is intended to quickly
regain synchronization in fading conditions (not caused by
the transmitter switching off between transmissions) or
when having been out of range, while maintaining
acceptable battery economy.
The PCD5002 then checks the first batch of every cycle for
sync word or preamble. The programmed data receive
batch is ignored (unless it is batch 0).
Initially, the receiver is switched off until one cycle duration
after the last enabling in the ‘transmitter off’ mode.
The receiver is then enabled for a 2 codeword period in
which each contiguous group of 32 bits is tested for any
decodable POCSAG codeword (including sync word) and
preamble. Single-bit error correction is applied.
Table 4 Synchronization window tolerance as a function
of bit rate
TOLERANCE
TIME FROM
If a codeword is detected, the receiver enable period is
extended by another codeword duration and the above
test is repeated. This process continues while valid
codewords are received.
512
1200
2400
(bits/s)
LOSS OF SIGNAL
(bits/s)
(bits/s)
≤ 30 s
≤ 60 s
4 bits
4 bits
4 bits
8 bits
4 bits
4 bits
8 bits
16 bits
4 bits
8 bits
Detection of preamble will cause the device to switch to the
‘preamble receive’ mode, while sync word detection will
cause the device to switch to the ‘batch zero detect’ mode.
When neither is detected during the 2 codeword window or
any following 32-bit group, the receiver will be disabled.
≤ 120 s
≤ 240 s
16 bits
32 bits
1997 Jun 24
12
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
If valid codewords are detected but no sync word or
preamble is detected over a period of 18 codewords, the
receiver is also disabled.
A Call Header contains information on the last sync word
received, the RIC which began call reception and the type
of error correction performed on the address codeword.
Data sampling, as previously described, is repeated one
cycle duration after the moment the receiver was last
activated.
A Message Data block contains the data bits from a
message codeword plus the type of error correction
performed. No deformatting is performed on the data bits:
numeric data appear as 4-bit groups per digit,
alphanumeric data has a 7-bit ASCII representation.
8.15 Call termination
The Call Terminator contains information on the last sync
word received, information on the way the call was
terminated (forced call termination command, loss of sync
word in ‘data fail’ mode) and the type of error correction
performed on the terminating codeword.
Call reception is terminated:
• Upon reception of any address codeword (including Idle
codeword but excluding the batch zero identifier in
APOC-1 operation) requiring no more than single bit
error correction
• In ‘data fail’ mode, when a sync word is not detected at
the expected batch position
8.17 Error type indication
Table 11 shows how the different types of detected errors
are encoded in the call data output format.
• When a forced call termination command is received
from an external controller.
A message codeword containing more than a single bit
error (bit E3 = 1) may appear as an address codeword
(bit M1 = 0) after error correction. In this event the
codeword is processed as message data and does not
cause call termination.
The last method permits an external controller to stop call
reception, depending on the number and type of errors
which occurred in a call. After a forced call termination the
decoder will enter the ‘data fail’ mode.
The type of error correction as well as the call termination
conditions are indicated by status bits in the message data
output.
8.18 Data transfer
Data transfer is initiated either during sync word periods or
as soon as the receiver is disabled after call termination.
If the SRAM buffer is full, data transfer is initiated
immediately during the next codeword.
Following call termination, transfer of the data received
since the previous sync word period is initiated by an
interrupt to the external controller.
When the PCD5002 is ready to transfer received call data
an external interrupt will be generated via output INT.
Any message data can be read by accessing the RAM
output register via the I2C-bus interface. Bytes will be
output starting from the position indicated by the RAM read
pointer.
8.16 Call data output format
POCSAG call information is stored in the decoder SRAM
in blocks of 3 bytes per codeword. Each stored call
consists of a call header, followed by message data blocks
and a call terminator. In the event of concatenated
messages the call terminator is replaced with the call
header of the next message. An alert-only call only has a
call header and a call terminator.
The formats of a call header, a message data block and a
call terminator are shown in Tables 5, 7 and 9.
1997 Jun 24
13
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 5 Call header format
BIT 7
(MSB)
BIT 0
BIT 1
BYTE NUMBER
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
(LSB)
1
2
3
0
0
X
S3
S3
X
S2
S2
F0
S1
S1
F1
R3
R3
E3
R2
R2
E2
R1
R1
E1
DF
0
0
Table 6 Call header bit identification
BITS (MSB to LSB)
IDENTIFICATION
S3 to S1
R3 to R1
DF
identifier number of sync word for current batch (7 = standard POCSAG)
identifier number of user address (RIC)
data fail mode indication (1 = data fail mode); note 1
F0 and F1
E3 to E1
function bits of received address codeword (bits 20 and 21)
detected error type; see Table 11; E3 = 0 in a concatenated call header
Note
1. The DF bit in the call header is set:
a) When the sync word of the batch in which the (beginning of the) call was received, did not match the standard
POCSAG or a user-programmed sync word. The sync word identifier (bits S3 to S1) will then be made 0.
b) When any codeword of a previous call received in the same batch was uncorrectable.
Table 7 Message data format
BIT 7
(MSB)
BIT 0
(LSB)
BYTE NUMBER
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
1
2
3
M2
M3
M11
M19
M4
M5
M6
M14
E3
M7
M15
E2
M8
M16
E1
M9
M17
M1
M10
M18
M12
M20
M13
M21
Table 8 Message data bit identification
BITS (MSB to LSB)
IDENTIFICATION
M2 to M21
E3 to E1
M1
message codeword data bits
detected error type; see Table 11
message codeword flag
Table 9 Call terminator format
BIT 7
BYTE NUMBER
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
1
2
3
FT
FT
X
S3
S3
X
S2
S2
X
S1
S1
X
0
0
0
0
0
0
DF
X
E3
E2
E1
0
1997 Jun 24
14
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 10 Call terminator bit identification
BITS (MSB to LSB)
IDENTIFICATION
forced call termination (1 = yes)
FT
S3 to S1
DF
identifier number of last sync word
data fail mode indication (1 = data fail mode); note 1
F0 and F1
E3 to E1
function bits of received address codeword (bits 20 and 21)
detected error type; see Table 11; E3 = 0 in a call terminator
Note
1. The DF bit in the call terminator is set:
a) When any call data codeword in the terminating batch was uncorrectable, while in ‘data receive’ mode.
b) When the sync word at the start of the terminating batch did not match the standard POCSAG or a
user-programmed sync word, while in ‘data fail’ mode.
Table 11 Error type identification (note 1)
E3
E2
E1
ERROR TYPE
NUMBER OF ERRORS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
no errors - correct codeword
parity bit in error
0
1
single bit error
1 + parity
single bit error and parity error
not used
1
−
4-bit burst error and parity error
2-bit random error
3 (e.g.1101)
2
uncorrectable codeword
3 or more
Note
1. POCSAG code allows a maximum of 3 bit errors to be detected per codeword.
Successful call termination occurs on reception of a valid
address codeword with less than 2 bit errors.
Unsuccessful termination occurs when a sync word is not
detected while in the ‘data fail’ mode.
8.19 Continuous data decoding
Apart from transmissions in the POCSAG or APOC-1
format, the PCD5002 is also capable of decoding
continuous transmissions with the same codeword
structure. Any user-programmable sync word (UPSW)
may be designated to enable continuous data decoding.
It is generally possible to distinguish these two conditions
using the sync word identifier number (bits S3 to S1); the
identifier number will be non-zero for correct termination,
and zero for sync word failure.
When a Continuous Data Decoding (CDD) sync word is
detected at any sync word position, the receiver remains
enabled from then on. Status bits D1 and D0 show the
CDD mode to be active.
Only when a call is received in the ‘data fail’ mode and the
call is terminated before the end of the batch, is it not
possible to distinguish unsuccessful from successful
termination.
All codewords are decoded and their data fields are stored
in SRAM. The usual error information is appended. No
distinction is made between address and message
codewords: codeword bit 0 is treated as a data bit and is
stored in bit M1 of the 3-byte output format.
Reception of message data can be terminated at any time
by transmitting a forced call termination command to the
status register via the I2C-bus. Any call received will then
be terminated immediately and the ‘data fail’ mode will be
entered.
1997 Jun 24
15
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Codewords received at the expected sync word positions
(POCSAG batch size) are matched against standard
POCSAG sync word, all enabled UPSWs and preamble.
Continuous data decoding will continue in the next batch if
any enabled CDD sync word is detected or no enabled
sync word is detected.
Data output to an external controller is initiated by an
interrupt at the next sync word position, after reception of
16 codewords.
8.20 Receiver and oscillator control
A paging receiver and an RF oscillator circuit can be
controlled independently via enable outputs RXE and ROE
respectively. Their operating periods are optimized
according to the synchronization mode of the decoder.
Each enable signal has its own programmable
establishment time (see Table 14).
The call header preceding the data has a different
structure from normal POCSAG or APOC-1 data. The data
header format is shown in Table 12.
Continuous data decoding continues until one of the
following conditions occur:
8.21 External receiver control and monitoring
• The decoder is switched to the OFF state
• A Forced Call Termination (FCT) command is received
An external controller may enable the receiver control
outputs continuously via an I2C-bus command, overruling
the normal enable pattern. Data reception continues
normally. This mode can be exited by means of a reset or
an I2C-bus command.
via the I2C-bus
• Preamble is detected at the sync word position
• Standard POCSAG sync word or an enabled non-CDD
sync word is detected.
External monitoring of the receiver control output RXE is
possible via bit D6 in the status register, when enabled via
the control register (D2 = 1). Each change of state of
output RXE will generate an external interrupt at
output INT.
Only a forced call termination command will be indicated in
the SRAM data by a call terminator. In the other events
continuous data decoding will stop without notification.
Upon forced termination the ‘fade recovery’ mode is
entered. Detection of preamble causes the device to
switch to the ‘preamble receive’ mode. Detection of a
standard sync word or any enabled non-continuous UPSW
will cause the device to switch to the ‘data receive’ mode.
Table 12 Continuous data header format
BIT 7
(MSB)
BIT 0
(LSB)
BYTE NUMBER
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
1
2
3
0
0
X
X
C3
X
X
X
C3
C3
E3
C2
C2
E2
C1
C1
E1
0
0
0
C2
F0
C1
F1
Table 13 Data header bit identification
BITS (MSB to LSB)
IDENTIFICATION
C3 to C1
F0 and F1
E3 to E1
identifier number of continuous data decoding sync word
function bits of received address codeword (bits 20 and 21)
detected error type (see Table 11); E3 = 0 in a concatenated call header
1997 Jun 24
16
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
copies the data to the internal divider registers. A timing
diagram is illustrated in Fig.6.
8.22 Battery condition input
A logic signal from an external sense circuit, signalling
battery condition, can be applied to the BAT input. This
input is sampled each time the receiver is disabled
(RXE ↓ 0).
The data output timing is synchronous, but has a pause in
the bitstream of each block. This pause occurs in the
13th bit while ZSC is LOW. The nominal pause duration tp
depends on the programmed bit rate for data reception
and is shown in Table 15. The total duration of the 13th bit
is given by tZCL + tp.
When enabled via the control register (D2 = 0), the
condition of input BAT is reflected in bit D6 of the status
register. Each change of state of bit D6 causes an external
interrupt at output INT.
A similar pause occurs between the first and the second
data block. The delay between the first latch enable pulse
and the second data block is given by tZDL2 + tp.
The complete start-up timing of the synthesizer interface is
illustrated in Fig.13.
When using the UAA2080 pager receiver a battery-low
condition corresponds to a logic HIGH level. With a
different sense circuit the reverse polarity can be used as
well, because every change of state is signalled to an
external controller.
Table 15 Synthesizer programming pause
After a reset the initial condition of the battery-low indicator
in the status register is zero.
BIT RATE (bit/s)
tp (clocks)
tp (µs)
512
119
33
1
1549
430
13
Table 14 Receiver and oscillator establishment times
1200
2400
(note 1)
CONTROL
OUTPUT
ESTABLISHMENT TIME
UNIT
8.24 Serial microcontroller interface
The PCD5002 has an I2C-bus serial microcontroller
interface capable of operating at 400 kbits/s.
The PCD5002 is a slave transceiver with a 7-bit I2C-bus
address 39 (bits A6 to A0 = 0100111).
RXE
5
10
30
15
40
30
50
ms
ms
ROE
20
Note
1. The exact values may differ slightly from the above
values, depending on the bit rate (see Table 25).
Data transmission requires 2 lines: SDA (data) and SCL
(clock), each with an external pull-up resistor. The clock
signal (SCL) for any data transmission must be generated
by the external controlling device.
8.23 Synthesizer control
Control of an external frequency synthesizer is possible
via a dedicated 3-line serial interface (outputs ZSD, ZSC
and ZLE). This interface is common to a number of
available synthesizers. The synthesizer is enabled using
the oscillator enable output ROE.
A transmission is initiated by a START condition
(S: SCL = 1, SDA = ↓) and terminated by a STOP
condition (P: SCL = 1, SDA = ↑).
Data bits must be stable when SCL is HIGH. If there are
multiple transmissions, the STOP condition can be
replaced with a new START condition.
The frequency parameters must be programmed in
EEPROM. Two blocks of maximum 24 bits each can be
stored. Any unused bits must be programmed at the
beginning of a block: only the last bits are used by the
synthesizer.
Data is transferred on a byte basis, starting with a device
address and a read/write indicator. Each transmitted byte
must be followed by an acknowledge bit A (active LOW).
If a receiving device is not ready to accept the next
complete byte, it can force a bus wait state by holding SCL
LOW.
When the function is selected by SPF programming
(SPF byte 01, bit D6), data is transferred to the
synthesizer each time the PCD5002 is switched from the
OFF to the ON status. Transfer takes place serially in two
blocks, starting with bit 0 (MSB) of block 1 (see Table 28).
The general I2C-bus transmission format is illustrated in
Fig.7. Formats for master/slave communication are
illustrated in Fig.8.
Data bits on ZSD change on the falling edges of ZSC. After
clocking all bits into the synthesizer, a latch enable pulse
1997 Jun 24
17
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
t
ZSD
MSB
LSB
23
0
12
ZSD
ZSC
ZLE
TIME
TIME
t
t
ZDL1
p
t
t
ZDS
ZCL
t
MLC248
ZLE
Fig.6 Synthesizer interface timing.
SDA
MSB
LSB
N
A
MSB
LSB
N
A
S
P
INTERRUPT
SERVICING
SCL
1
2
7
8
9
1
2
7
8
9
START
ADDRESS
R/W
A
DATA
A
STOP
MLC249
Fig.7 I2C-bus message format.
18
1997 Jun 24
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
A = Acknowledge
FROM
FROM
SLAVE
S = START condition
P = STOP condition
MASTER
N = Not acknowledge
(a)
S
S
SLAVE ADDRESS
SLAVE ADDRESS
R/W
A
INDEX
A
DATA
A
DATA
A
P
index
address
0
1
(write)
n bytes with acknowledge
(b)
R/W
A
DATA
A
DATA
N
P
(read)
n bytes with acknowledge
(c)
S
SL. ADR. R/W
A
INDEX
A
DATA
A
S
SL. ADR. R/W
A
DATA
N
P
index
address
1
(read)
0
(write)
n bytes with
acknowledge
n bytes with
acknowledge
change of direction
MLC250
(a) Master writes to slave.
(b) Master reads from slave.
(c) Combined format (shown: write plus read).
Fig.8 Message types.
Each I2C-bus write message to the PCD5002 must start
with its slave address, followed by the index address of the
memory element to be accessed. An I2C-bus read
message uses the last written index address as a data
source. The different I2C-bus message types are shown in
Fig.8.
8.25 Decoder I2C-bus access
All internal access to the PCD5002 takes place via the
I2C-bus interface. For this purpose the internal registers,
SRAM and EEPROM have been memory mapped and are
accessed via an index register. Table 16 shows the index
addresses of all internal blocks.
As a slave the PCD5002 cannot initiate bus transfers by
itself. To prevent an external controller from having to
monitor the operating status of the decoder, all important
events generate an external interrupt on output INT.
Registers are addressed directly, while RAM and
EEPROM are addressed indirectly via address pointers
and I/O registers.
Remark: The EEPROM memory map is non-contiguous
and is organized as a matrix.
The EEPROM address pointer contains both row and
column indicators.
Data written to read-only bits will be ignored. Values read
from write-only bits are undefined and must be ignored.
1997 Jun 24
19
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 16 Index register
ADDRESS(1)
REGISTER FUNCTION
ACCESS
00H
00H
status
R
W
control
01H
real time clock: seconds
real time clock:1⁄100 second
alert cadence
R/W
R/W
W
02H
03H
04H
alert set-up
W
05H
periodic interrupt modulus
periodic interrupt counter
RAM write address pointer
EEPROM address pointer
RAM read address pointer
RAM data output
W
05H
R
06H
R
07H
R/W
R/W
R
08H
09H
0AH
EEPROM data input/output
unused
R/W
note 2
0BH to 0FH
Notes
1. The index register only uses the least significant nibble, the upper 4 bits are ignored.
2. Writing to registers 0B to 0F has no effect, reading produces meaningless data.
When call data is available (D2 = 1) but the receiver
remains switched on, an interrupt is generated at the next
sync word position.
8.26 External interrupt
The PCD5002 can signal events to an external controller
via an interrupt signal at output INT. The interrupt polarity
is programmable via SPF programming. The interrupt
source is shown in the status register.
The interrupt output INT is reset after completion of a
status read operation.
Interrupts are generated by the following events (more
than one event is possible):
8.27 Status/Control register
The status/control register consists of two independent
registers, one for reading (status) and one for writing
(control).
• Call data available for output (bit D2)
• SRAM pointers becoming equal (bit D3)
• Expiry of periodic time-out (bit D7)
The status register shows the current operating condition
of the decoder and the cause(s) of an external interrupt.
The control register activates/deactivates certain
functions. Tables 17 and 18 show the bit allocations of
both registers.
• Expiry of alert time-out (bit D4)
• Change of state in out-of-range indicator (bit D5)
• Change of state in battery-low indicator or in receiver
control output RXE (bit D6).
All status bits will be reset after a status read operation
except for the out-of-range, battery-low and receiver
enable indicator bits (see note 1 to Table 17).
Immediate interrupts are generated by status bits D3,
D4, D6 (RXE monitoring) and D7. Bits D2, D5 and D6
(BAT monitoring) generate interrupts as soon as the
receiver is disabled (RXE = 0).
1997 Jun 24
20
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 17 Status register (00H; read)
BIT(1)
VALUE
DESCRIPTION
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
no new call data
new call received (POCSAG or APOC-1)
continuous decoding data available
batch zero data available (APOC-1)
no data to be read (default after reset)
RAM read/write pointers different; data to be read
RAM read/write pointers equal; no more data to read
RAM buffer full or overflow
D1 and D0
D3 and D2
D4
D5
D6
D7
alert time-out expired
1
out-of-range
1
BAT input HIGH or RXE output active (selected by control bit D2)
periodic timer interrupt
1
Note
1. After a status read operation bits D3, D4 and D7 are always reset, bits D1 and D0 only when no second call is
pending. D2 is reset when the RAM is empty (read and write pointers equal).
Table 18 Control register (00H; write)
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
1
1
0
1
1
0
1
X
forced call termination (automatically reset after termination)
EEPROM programming enable
BAT input selected for monitoring (status bit D6)
RXE output selected for monitoring (status bit D6)
receiver continuously enabled (RXE = 1, ROE = 1)
decoder in OFF status (while DON = 0)
decoder in ON status
D2
D3
D4
D5 to D7
not used: ignored when written
8.28 Pending interrupts
8.29 Out-of-range indication
A secondary status register is used for storing status bits
of pending interrupts. This occurs:
The out-of-range condition occurs when entering the
‘fade recovery’ or ‘carrier off’ mode in POCSAG, or
‘transmitter off’ or ‘carrier detect’ mode in APOC-1. This
condition is reflected in bit D5 of the status register.
The out-of-range condition is reset when either preamble
or a valid sync word is detected.
• When a new call is received while the previous one was
not yet acknowledged by reading the status register
• When an interrupt occurs during a status read operation.
After completion of the status read the primary register is
loaded with the contents of the secondary register, which
is then reset. An immediate interrupt is then generated,
output INT becoming active 1 decoder clock cycle after it
was reset following the status read.
The out-of-range bit (D5) in the status register is updated
each time the receiver is disabled (RXE ↓ 0). Every
change of state in bit D5 generates an interrupt.
Remark: In the event of multiple pending calls, only the
status bits of the last call are retained.
1997 Jun 24
21
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 20 Real time clock; 1⁄100 second register (02H;
8.30 Real time clock
read/write)
The PCD5002 provides a periodic reference pulse at
output REF. The frequency of this signal can be selected
by SPF programming:
BIT
VALUE
DESCRIPTION
(MSB D7)
• 32768 Hz
D0
D1
D2
D3
D4
D5
D6
D7
−
−
−
−
−
−
−
X
0 01 s
0.02 s
0.04 s
0.08 s
0.16 s
0.32 s
0.64 s
• 50 Hz (square-wave)
• 2 Hz
1
•
⁄60 Hz.
The 32768 Hz signal does not have a fixed period, it
consists of 32 pulses distributed over 75 main oscillator
cycles at 76.8 kHz. The timing is illustrated in Fig.15.
When programmed for 1⁄60 Hz (1 pulse per minute) the
pulse at output REF is held off while the receiver is
enabled.
not used: ignored when written,
undetermined when read
8.31 Periodic interrupt
Except for the 50 Hz frequency the pulse width tRFP is
equal to one decoder clock period.
A periodic interrupt can be realised with the periodic
interrupt counter. This 8-bit counter is incremented every
The real time clock counter runs continuously irrespective
of the operating condition of the PCD5002. It contains a
seconds register (maximum 59) and a 1⁄100 second
register (maximum 99), which can be read from or written
to via the I2C-bus. The bit allocation of both registers is
shown in Tables 19 and 20.
1
⁄
100 s and produces an interrupt when it reaches the value
stored in the periodic interrupt modulus register.
The counter register is then reset and counting continues.
Operation is started by writing a non-zero value to the
modulus register. Writing a zero will stop interrupt
generation immediately and will halt the periodic interrupt
counter after 2.55 s.
Table 19 Real time clock; seconds register (01H;
read/write)
The modulus register is write-only, the counter register is
read only. Both registers have the same index address
(05H).
BIT
(MSB D7)
VALUE
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
−
−
−
−
−
−
X
1 s
2 s
8.32 Received call delay
Call reception (detection of an enabled RIC) causes both
the periodic interrupt modulus and the counter register to
be reset.
4 s
8 s
16 s
32 s
Since the periodic interrupt counter runs for another 2.55 s
after a reset, the received call delay (in 1⁄100 s units) can be
determined by reading the counter register.
not used: ignored when written,
undetermined when read
D7
X
not used: ignored when written,
undetermined when read
1997 Jun 24
22
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 21 Alert set-up register (04H; write)
BIT (MSB D7)
VALUE
DESCRIPTION
call alert via cadence register
0
1
D0
POCSAG call alert (pattern selected by D7 and D6)
LOW level acoustic alert (ATL), pulsed vibrator alert (25 Hz)
HIGH level acoustic alert (ATL + ATH), continuous vibrator alert
normal alerts (acoustic and LED)
0
D1
D2
1
0
1
warbled alerts: 16 Hz (LED: on/off, ATL/ATH: alternate fAWH, fAWL
)
D3
D4
D5
1
acoustic alerts enable (ATL, ATH)
1
vibrator alert enabled (VIB)
1
LED alert enabled (LED)
0 0
0 1
1 0
1 1
POCSAG alert pattern FC = 00, see Fig.9 (a)
POCSAG alert pattern FC = 01, see Fig.9 (b)
POCSAG alert pattern FC = 10, see Fig.9 (c)
POCSAG alert pattern FC = 11, see Fig.9 (d)
D7 and D6(1)
Note
1. Bits D7 and D6 correspond to function bits 20 and 21 respectively in the address codeword, which designate the
POCSAG call type as shown in Table 1.
D7, D6
0
0
1
1
0
1
0
1
(a)
(b)
(c)
(d)
MLC251
Fig.9 POCSAG alert patterns.
1997 Jun 24
23
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
it is advisable to reset the last bit of the previous pattern to
prevent unwanted audible level changes.
8.33 Alert generation
The PCD5002 is capable of controlling 3 different alert
transducers, acoustic beeper (HIGH and LOW level), LED
and vibrator motor. The associated outputs are ATH/ATL,
LED and VIB respectively. ATL is an open-drain output
capable of directly driving an acoustic alerter via a resistor.
The other outputs require external transistors.
8.36 Vibrator alert
The vibrator output (VIB) is activated continuously during
a standard POCSAG alert or whenever the alert cadence
register is non-zero.
Each alert output can be individually enabled via the alert
set-up register. Alert level and warble can be separately
selected. The alert pattern can either be standard
POCSAG or determined via the alert cadence register.
Direct alert control is possible via input ALC.
Two alert levels are supported, LOW level
(25 Hz square-wave) and HIGH level (continuous).
The vibrator level is controlled by bit D1 in the alert set-up
register.
8.37 LED alert
The alert set-up register is shown in Table 21.
The LED output pattern corresponds either to the selected
POCSAG alert or to the contents of the alert cadence
register. No equivalent exists for HIGH/LOW level alerts.
Standard POCSAG alerts can be selected by setting
bit D0 in the alert set-up register, bits D6 and D7
determining the alert pattern used.
8.38 Warbled alert
8.34 Alert cadence register (03H; write)
When enabled, by setting bit D2 in the alert set-up register,
the signals on outputs ATL, ATH and LED are warbled with
a 16 Hz modulation frequency. Output LED is switched on
and off at the modulation rate, while outputs ATL and ATH
switch between fAWH and fAWL alerter frequencies.
When not programmed for POCSAG alerts (alert set-up
register bit D0 = 0), the 8-bit alert cadence register
determines the alert pattern. Each bit represents a
62.5 ms time slot, a logic 1 activating the enabled alert
transducers. The bit pattern is rotated with the
MSB (bit D7) being output first and the LSB (bit D0) last.
8.39 Direct alert control
When the last time slot (bit D0) is initiated an interrupt is
generated to allow loading of a new pattern. When the
pattern is not changed it will be repeated. Writing a zero to
the alert cadence register will halt alert generation within
62.5 ms.
A direct alert control input (ALC) is available for generating
user alarm signals (e.g. battery-low warning). A HIGH level
on input ALC activates all enabled alert outputs, overruling
any ongoing alert patterns.
8.40 Alert priority
8.35 Acoustic alert
Generation of a standard POCSAG alert (D0 = 1)
overrides any alert pattern in the alert cadence register.
After completion of the standard alert, the original cadence
is restarted from its last position. The alert set-up register
will now contain the settings for the standard alert.
Acoustic alerts are generated via outputs ATL and ATH.
For LOW level alerts only ATL is active, while for HIGH
level alerts ATH is also active. ATL is driven in counter
phase with ATH.
The alert level is controlled by bit D1 in the alert set-up
register.
The highest priority has been assigned to the alert control
input (ALC). All enabled alert outputs will be activated
while ALC is set. Outputs are activated/deactivated in
synchrony with the decoder clock. Activation requires an
extra delay of 1 clock when no alerts are being generated.
When D1 is reset, for standard POCSAG alerts (D0 = 1) a
LOW level acoustic alert is generated during the first
4 s (ATL), followed by 12 s at HIGH level (ATL + ATH).
When D1 is set, the full 16 s are at HIGH level. An interrupt
is generated after the full alert time has elapsed (indicated
by bit D4 in the status register).
When input ALC is reset, acoustic alerting does not cease
until the current output frequency cycle has been
completed.
When using the alert cadence register, D1 would normally
be updated by external control when the alert time-out
interrupt occurs at the start of the 8th cadence time slot.
Since D1 acts immediately on the alert level,
1997 Jun 24
24
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
h
FC = 00
t
t
ALP
ALC
FC = 01
t
ALP
t
ALP
t
ALC
FC = 10
t
t
t
ALP
ALC
ALP
FC = 11
t
ALP
t
t
t
ALC
ALC
ALP
MLC252
Fig.10 POCSAG alert timing.
The RAM is filled by the decoder and can be read via the
I2C-bus interface. The RAM is accessed indirectly by a
read address pointer and a data output register. A write
address pointer indicates the position of the last message
byte stored.
8.41 Cancelling alerts
Standard POCSAG alerts (manual or automatic) are
cancelled by resetting bit D0 in the alert set-up register.
User defined alerts are cancelled by writing a zero to the
alert cadence register. Any ongoing alert is cancelled
when a reset pulse is applied to input RST.
Status register bit D2 is set when the read and write
pointers are different. It is reset only when the SRAM
pointers become equal during reading, i.e. when the RAM
becomes empty.
8.42 Automatic POCSAG alerts
Standard alert patterns have been defined for each
POCSAG call type, as indicated by the function bits in the
address codeword (see Table 1). The timing of these alert
patterns is shown in Fig.10. After completion of the full 16 s
alert period an interrupt is generated by status bit D4.
Status bit D3 is set when the read and write pointers
become equal. This can be due to a RAM empty or a RAM
full condition. It is reset after a status read operation.
Interrupts are generated as follows:
When enabled by SPF programming (SPF byte 03, bit D2)
standard POCSAG alerts will be automatically generated
at outputs ATL, ATH, LED and VIB upon call reception.
The alert pattern matches the call type as indicated by the
function bits in the received address codeword.
• When status bit D2 is set and the receiver is disabled
(RXE = 0); data is available for reading
• Immediately when status bit D3 is set: RAM is either
empty (status bit D2 = 0) or full (status bit D2 = 1).
To avoid loss of data due to RAM overflow at least 3 bytes
of data must be read during reception of the codeword
following the ‘RAM full’ interrupt.
The original settings of the alert set-up register will be lost.
Bit D0 is reset after completion of the alert.
8.43 SRAM access
The on-chip SRAM can hold up to 96 bytes of call data.
Each call consists of a call header (3 bytes), message data
blocks (3 bytes per codeword) and a call terminator
(3 bytes).
1997 Jun 24
25
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
8.44 RAM write address pointer (06H; read)
8.48 EEPROM address pointer (07H; read/write)
The RAM write address pointer is automatically
An EEPROM location is addressed via the EEPROM
address pointer. It is incremented automatically each time
a byte is read from or written to via the EEPROM data I/O
register.
incremented during call reception, because the decoder
writes each data byte to RAM. The RAM write address
pointer can only be read. Values range from 00H to 5FH.
Bit D7 (MSB) is not used and its value is undefined when
read. When a call data byte is written to location 5FH, the
write address pointer wraps around to 00H. This does not
necessarily imply a RAM full condition.
The EEPROM address pointer contains two counters for
the row and the column number. Bits D2 to D0 contain the
column number (0 to 5) and bits D5 to D3 the row number
(0 to 7). Bits D7 and D6 of the address pointer are not
used. Data written to these bits will be ignored, while their
values are undefined when read.
8.45 RAM read address pointer (08H; read/write)
The RAM read address pointer is automatically
incremented after reading a data byte via the RAM output
register.
The column and row counters are connected in series.
Upon overflow of the column counter (column = 5) the row
counter is automatically incremented and the column
counter wraps to 0. On overflow the row counter wraps
from 7 to 0.
The RAM read address pointer can be accessed for
reading and writing.
The values range from 00H to 5FH. When at 5FH a read
operation will cause wrapping around to 00H. Bit D7
(MSB) is not used; it is ignored when written to and
undefined when read from.
8.49 EEPROM data I/O register (0AH; read/write)
The byte addressed by the EEPROM address pointer can
be written to or read from via the EEPROM data I/O
register. Each access automatically increments the
EEPROM address pointer.
8.46 RAM data output register (09H; read)
The RAM data output register contains the byte addressed
by the RAM read address pointer and can only be read.
Each read operation causes an increment of the RAM read
address pointer.
8.50 EEPROM access limitations
Since the EEPROM address pointer is used during data
decoding, the EEPROM may not be accessed while the
receiver is active (RXE = 1). It is advisable to switch to the
OFF state before accessing the EEPROM.
8.47 EEPROM access
The EEPROM cannot be written to unless the EEPROM
programming enable bit (bit D1) in the control register is
set.
The EEPROM is intended for storage of user addresses
(RICs), sync words and special programmed function
(SPF) bits representing the decoder configuration.
For writing a minimum programmed supply voltage (VPG
is required (2.0 V typ.). The programmed supply current
(IPG) required during writing is approximately 500 µA.
)
The EEPROM can store 48 bytes of information and is
organized as a matrix of 8 rows by 6 columns.
The EEPROM is accessed indirectly via an address
pointer and a data I/O register.
8.51 EEPROM read operation
The EEPROM is protected against inadvertent writing by
means of the programming enable bit in the control
register (bit D1).
EEPROM read operations must start at a valid address in
the non-contiguous memory map. Single byte or block
reads are permitted.
The EEPROM memory map is non-contiguous. Figure 11
shows both the EEPROM organization and the access
method.
8.52 EEPROM write operation
EEPROM write operations must always take place in
blocks of 6 bytes, starting at the beginning of a row.
Programming a single byte will reset the other bytes in the
same row. Modifying a single byte in a row requires
re-writing the unchanged bytes with their old contents.
Identifier locations contain RICs or sync words. A total of
20 unassigned bytes are available for general purpose
storage.
1997 Jun 24
26
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
After writing each block a pause of 7.5 ms (max.) is
required to complete the internal programming operation.
During this time the external microcontroller may generate
an I2C-bus STOP condition. If another I2C-bus transfer is
initiated the decoder will pull SCL LOW during this pause.
8.55 Unused EEPROM locations
A total of 20 EEPROM bytes are available for general
purpose storage (see Table 22).
Table 22 Unused EEPROM addresses
After writing the EEPROM programming enable bit (D1) in,
the control register must be reset.
ROW
HEX
04 and 05(1)
28 to 2D
30 to 35
0
5
6
7
8.53 Invalid write address
When an invalid write address is used, the column counter
bits (D2 to D0) are forced to zero before being loaded into
the address pointer. The row counter bits are used
normally.
38 to 3D
Note
1. When using bytes 04H and 05H, care must be taken to
preserve the SPF information stored in
bytes 00H to 03H.
8.54 Incomplete programming sequence
A programming sequence may be aborted by an I2C-bus
STOP condition. The EEPROM programming enable
bit (D1) in the control register must then be reset.
8.56 Special programmed function allocation
The SPF bit allocation in the EEPROM is shown in
Tables 23 to 27. The SPF bits are located in row 0 of the
EEPROM and occupy 4 bytes.
Any bytes received from the last 6-byte block will be
ignored and the contents of this (incomplete) EEPROM
block will remain unchanged.
Bytes 04H and 05H are not used and are available for
general purpose storage.
COLUMN
ADDRESS
POINTER
0
1
2
3
4
5
D7
D0
0
0
1
2
3
4
5
6
7
0
1
0
1
0
I
I
I
I
I
I
D
1
D
2
D
3
D
4
D
5
D
6
ROW COLUMN
I/O REGISTER
ROW
D7
D0
SPF bits
Synthesizer data
Identifiers
unused bytes
MLC254
Fig.11 EEPROM organization and access.
27
1997 Jun 24
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 23 Special programmed functions (EEPROM address 00H)
BIT (MSB: D7)
VALUE
DESCRIPTION
POCSAG decoding enabled
0
D0
1
APOC-1 decoding enabled
cycle length: 5 batches
0
D1
1
0 to 4
0 to 14
1
cycle length: 15 batches
batch number (D1 = 0, MSB is ignored)
batch number (D1 = 1)
D5 to D2 (MSB: D5)
D6
D7
continuous data decoding enabled
received data inversion enabled
1
Table 24 Special programmed functions (EEPROM address 01H)
BIT (MSB: D7)
VALUE
DESCRIPTION
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
5 ms receiver establishment time (nominal); note 1
10 ms
D1 and D0
15 ms
30 ms
20 ms oscillator establishment time (nominal); note 1
30 ms
D3 and D2
D5 and D4
40 ms
50 ms
512 bits/s received bit rate
1024 bits/s (not used in POCSAG)
1200 bits/s
2400 bits/s
D6
D7
synthesizer interface enabled (programming at switch-on)
voltage converter enabled
1
Note
1. Since the exact establishment time is related to the programmed bit rate, Table 25 shows the values for the various
bit rates.
1997 Jun 24
28
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 25 Establishment time as a function of bit rate
NOMINAL
ESTABLISHMENT
TIME
ACTUAL ESTABLISHMENT TIME
512 (bits/s)
1024 (bits/s)
1200 (bits/s)
2400 (bits/s)
5 ms
10 ms
15 ms
20 ms
30 ms
40 ms
50 ms
5.9 ms (3 bits)
11.7 ms (6 bits)
15.6 ms (8 bits)
23.4 ms (12 bits)
31.2 ms (16 bits)
39.1 ms (20 bits)
46.9 ms (24 bits)
5.9 ms (6 bits)
11.7 ms (12 bits)
15.6 ms (16 bits)
23.4 ms (24 bits)
31.2 ms (32 bits)
39.1 ms (40 bits)
46.9 ms (48 bits)
5 ms (6 bits)
10 ms (12 bits)
16.7 ms (20 bits)
20 ms (24 bits)
26.7 ms (32 bits)
40 ms (48 bits)
53.3 ms (64 bits)
5 ms (12 bits)
10 ms (24 bits)
16.7 ms (40 bits)
20 ms (48 bits)
26.7 ms (64 bits)
40 ms (96 bits)
53.3 ms (128 bits)
Table 26 Special programmed functions (EEPROM address 02H)
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
X
X
not used
not used
0 0
0 1
1 0
1 1
1
32768 Hz real time clock reference
50 Hz square wave
D3 and D2
2 Hz
1
⁄
60 Hz
D4
D5
signal test mode enabled (REF and INT outputs)
burst error correction enabled
30 s (+ 0.5 s max.) transmitter off time-out
60 s (+ 1 s max.)
0
00
01
10
11
D7 and D6
120 s (+ 2 s max.)
240 s (+ 4 s max.)
Table 27 Special programmed functions (EEPROM address 03H)
BIT (MSB: D7)
VALUE
DESCRIPTION
2048 Hz acoustic alerter frequency
0 0
0 1
1 0
1 1
1
2731 Hz
D1 and D0
4096 Hz
3200 Hz
D2
D3
D4
D5
automatic POCSAG alert generation enabled
X
not used
X
not used
X
not used
0
INT output polarity: active LOW
INT output polarity: active HIGH
not used
D6
D7
1
X
1997 Jun 24
29
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Identifiers are stored in EEPROM rows 2, 3 and 4. Each
identifier location consists of 3 bytes in the same column.
The identifier number is equal to the column number + 1.
8.57 Synthesizer programming data
Data for programming a PLL synthesizer via pins ZSD,
ZSC and ZLE can be stored in row 1 of the EEPROM.
Six bytes are available starting with address 08H.
Each identifier can be individually enabled. The standard
POCSAG sync word is always enabled and has identifier
number 7.
Data is transferred in two serial blocks of 24 bits each,
starting with bit 0 (MSB) of block 1. Any unused bits must
be programmed at the beginning of a block.
The identifier type is determined by bits D2 and D0 of
identifier byte 3, as shown in Table 31.
Table 28 Synthesizer programming data (EEPROM
Identifiers 1 and 2 always represent RICs or batch zero
identifiers. The last 4 identifiers (numbers 3 to 6) can
represent any identifier type.
address 08H to 0DH)
ADDRESS
(HEX)
BIT
(MSB: D7)
DESCRIPTION
A UPSW represents an unused address and must differ by
more than 6 bits from preamble to guarantee detection.
D7 to D0
bits 0 to 7 of data
block 1 (bit 0 is MSB)
08
A batch zero identifier marks the start of a new cycle in the
APOC-1 protocol. It is only recognized when APOC-1
decoding has been enabled (SPF byte 00, bit D0).
09
0A
0B
D7 to D0
D7 to D0
D7 to D0
bits 8 to 15
bits 16 to 23
bits 0 to 7 of data
Reception of a CDD sync word initiates continuous data
decoding. CDD sync words are only recognized when
continuous data decoding has been enabled (SPF
byte 00, bit 6).
block 2 (bit 0 is MSB)
0C
0D
D7 to D0
D7 to D0
bits 8 to 15
bits 16 to 23
Table 29 shows the memory locations of the 6 identifiers.
The bit allocation per identifier is given in Table 30.
8.58 Identifier storage allocation
Up to 6 different identifiers can be stored in EEPROM for
matching with incoming data. The PCD5002 can
distinguish two types of identifiers:
• User addresses (RIC)
• User Programmable Sync Words (UPSW)
• Batch zero identifiers
• Continuous data decoding (CDD) sync words.
Table 29 Identifier storage allocation (EEPROM address 10H to 25H)
ADDRESS (HEX)
BYTE
DESCRIPTION
10 to 15
18 to 1D
20 to 25
1
2
3
identifier number 1 to 6
identifier number 1 to 6
identifier number 1 to 6
1997 Jun 24
30
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 30 Identifier bit allocation
BYTE
BIT (MSB: D7)
DESCRIPTION
1
2
D7 to D0
D7 to D0
D7 and D6
D5
bits 2 to 9 of POCSAG codeword (RIC or UPSW); notes 1 and 2
bits 10 to 17
bits 18 and 19
frame number bit FR3 (RIC); note 3
frame number bit FR2 (RIC)
D4
3
D3
frame number bit FR1 (RIC)
D2
identifier type selection (0 = UPSW, 1 = RIC); note 4
identifier enable (1 = enabled)
D1
D0
batch zero ID/continuous decoding (1 = enabled)
Notes
1. The bit numbering corresponds with the numbering in a POCSAG codeword; bit 1 is the flag bit (0 = address,
1 = message).
2. A UPSW needs 18 bits to be matched for successful identification. Bit 1 (MSB) must be logic 0. Bits 2 to 19 contain
the identifier bit pattern, they are followed by 2 predetermined random (function) bits and the UPSW is completed by
10 CRC error correction bits and an even-parity bit.
3. Bits FR3 to FR1 (MSB: FR3) contain the 3 least significant bits of the 21-bit RIC.
4. Identifiers 1 and 2 (RIC only) will be disabled by programming bit D2 as logic 0.
Table 31 Identifier types
BYTE 3, BIT D2
BYTE 3, BIT D0
DESCRIPTION
user programmable sync word (UPSW)
0
0
1
1
0
1
0
1
continuous data decoding (CDD) sync word
normal user address (RIC)
batch zero identifier
The level-shifted interface lines are RST, DON, ALC, REF
8.59 Voltage doubler
and INT.
An on-chip voltage doubler provides an unregulated DC
output for supplying an LCD or a low power microcontroller
at output VPO. An external ceramic capacitor of 100 nF
(typ.) is required between pins CCN and CCP. The voltage
doubler is enabled via SPF programming.
The I2C-bus interface lines SDA and SCL can be
level-shifted independently of VPR by the standard external
pull-up resistors.
8.61 Signal test mode
8.60 Level-shifted interface
A special ‘signal test’ mode is available for monitoring the
performance of a receiver circuit together with the
front-end of the PCD5002.
All interface lines are suited for communication with a
microcontroller operating from a higher supply voltage.
The external device must have a common reference at VSS
of the PCD5002.
For this purpose the output of the digital noise filter and the
recovered bit clock are made available at outputs REF and
INT respectively. All synchronization and decoding
functions are normally active.
The reference voltage for the level-shifted interface must
be applied to input VPR. If required this could be the
on-chip voltage doubler output VPO. When the
The ‘signal test’ mode is activated/deactivated by SPF
programming.
microcontroller has a separate (regulated) supply it should
be connected to VPR
.
1997 Jun 24
31
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
A more accurate reset duration can be realised with an
additional external resistor connected to VSS
Recommended minimum values in this case are
9
OPERATING INSTRUCTIONS
Reset conditions
.
9.1
C = 2.2 nF and R = 100 kΩ (see Fig.16).
When the PCD5002 is reset by applying a HIGH level to
input RST, the condition of the decoder is as follows:
9.3
Reset timing
• OFF status (irrespective of DON input level)
• REF output frequency 32768 Hz
• All internal counters reset
The start-up time for the crystal oscillator may exceed 1 s
(typ. 800 ms). It is advisable to apply a reset condition, at
least during the first part of this period. The minimum reset
pulse duration tRST is 50 µs.
• Status/control register reset
• INT output at LOW level
During reset the oscillator is active, but clock signals are
inhibited internally. Once the reset condition is released
the end of the oscillator start-up period can be detected by
a rising edge on output INT.
• No alert transducers selected
• LED, VIB and ATH outputs at LOW level
• ATL output high-impedance
During a reset the voltage converter clock (Vclk) is held at
zero. The resulting output voltage drop may cause
problems when the external resetting device is powered by
the internal voltage doubler. A sufficiently large buffer
capacitor connected between output VPO and VSS must be
provided to supply the microcontroller during reset.
The voltage at VPO will not drop below VDD − 0.7 V.
• SDA and SCL inputs high-impedance
• Voltage converter disabled.
The programmed functions are activated within tRSU after
release of the reset condition (RST LOW). The settings
affecting the external operation of the PCD5002 are as
follows:
• REF output frequency
• Voltage converter
• INT output polarity
• Signal test mode.
Immediately after a reset all programmable internal
functions will start operating according to a programmed
value of 0. During the first 8 full clock cycles (tRSU) all
programmed values are loaded from EEPROM.
After reset the receiver outputs RXE and ROE become
active immediately, if DON is HIGH and the synthesizer is
disabled. When the synthesizer is enabled, RXE and ROE
will only become active after the second pulse on ZLE
completes the loading of synthesizer data.
When input DON is HIGH, the decoder starts operating in
ON status immediately following tRSU
.
9.2 Power-on reset circuit
During power-up of the PCD5002 a HIGH level of
minimum duration tRST = 50 µs must be applied to pin
RST. This is to prevent EEPROM corruption which might
otherwise occur because of the undefined contents of the
Control register.
The full reset timing is illustrated in Fig.12. The start-up
timing including synthesizer programming is illustrated in
Fig.13.
9.4
Initial programming
The reset signal can be applied by the external
microcontroller or by an RC power-on reset circuit on pin
RST (C to VPR, R to VSS). Such an RC-circuit should have
a time constant of at least 3tRST = 150 µs.
A newly-delivered PCD5002 has EEPROM contents which
are undefined. The EEPROM should therefore be
programmed, followed by a reset to activate the SPF
settings, before any attempt is made to use the device.
Input RST has an internal high-ohmic pull-down resistor
(nominal 2 MΩ at 2.5 V supply) which could be used
together with a suitable external capacitor connected to
VPR to create a power-on reset signal. However, since this
pull-down resistor varies considerably with processing and
supply voltage, the resulting time constant is inaccurate.
1997 Jun 24
32
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
LM2C53
a n f u l l p a g e w i d t h
1997 Jun 24
33
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
DON
ZSC
ZLE
BLOCK 1
BLOCK 2
t
t
ZDL1
ZDL1
t
t
p
ZDL2
RXE
t
t
clk
ZSU
t
MLC255
OSU
Fig.13 Start-up timing including synthesizer programming.
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
−0.5
−0.5
MAX.
+7.0
+7.0
UNIT
VDD
VPR
Vn
supply voltage
external reference voltage input
V
V
PR ≥ VDD − 0.8 V
V
voltage on pins ALC, DON, RST, SDA and SCL Vn ≤ 7.0 V
V
V
−
−
SS − 0.8
V
PR + 0.8
DD + 0.8
V
Vn1
Ptot
PO
input voltage on any other pin
total power dissipation
V
n1 ≤ 7.0 V
SS − 0.8
V
V
250
100
+70
+125
mW
mW
°C
°C
power dissipation per output
operating ambient temperature
storage temperature
Tamb
Tstg
−25
−55
1997 Jun 24
34
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
11 DC CHARACTERISTICS
VDD = 2.7 V; VPR = 2.7 V; VSS = 0 V; Tamb = −25 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
VPR
IDD0
IDD1
VPG
supply voltage
voltage converter disabled
1.5
2.7
6.0
V
V
external reference voltage input
supply current (OFF)
VPR ≥ VDD − 0.8 V
1.5
−
2.7
25.0
50.0
−
6.0
note 1
40.0
80.0
6.0
µA
µA
V
supply current (ON)
note 1; DON = VDD
voltage converter disabled
voltage converter enabled
−
programming supply voltage
2.0
2.0
−
−
3.0
V
IPG
programming supply current
−
800
µA
Inputs
VIL
LOW level input voltage
RDI, BAT
VSS
VSS
VSS
−
−
−
0.3VDD
0.3VPR
0.3VDD
V
V
V
DON, ALC, RST
SDA, SCL
VIH
HIGH level input voltage
RDI, BAT
0.7VDD
0.7VPR
0.7VDD
0
−
−
−
−
VDD
VPR
VPR
−0.5
V
DON, ALC, RST
SDA, SCL
V
V
IIL
LOW level input current pins
RDI, BAT,TS1, TS2, DON,
ALC and RST
Tamb = 25 °C; VI = VSS
µA
IIH
HIGH level input current
TS1, TS2
Tamb = 25 °C
VI = VDD
6
−
20
µA
µA
µA
nA
RDI, BAT
VI = VDD; RXE = 0
VI = VDD; RXE = 1
VI = VPR
6
−
20
RDI, BAT
0
−
0.5
850
DON, ALC, RST
250
500
Outputs
IOL
LOW level output current
VIB, LED
Tamb = 25 °C
VOL = 0.3 V
80
250
80
70
13
80
−
−
µA
µA
µA
µA
mA
µA
ATH
V
V
V
OL = 0.3 V
OL = 0.3 V
OL = 0.3 V
−
−
INT, REF
−
−
ZSD, ZSC, ZLE
ATL
−
−
VOL = 1.2 V; note 2
VOL = 0.3 V
27
−
55
−
ROE, RXE
1997 Jun 24
35
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
SYMBOL
IOH
PARAMETER
CONDITIONS
Tamb = 25 °C
MIN.
TYP.
MAX.
UNIT
HIGH level output current
VIB, LED
V
V
V
V
OH = 0.7 V
−0.6
−
−
−
−
−
−
−2.4
mA
ATH
OH = 0.7 V
OH = 2.4 V
OH = 2.4 V
−3.0
−80
−60
−
−11.0
mA
µA
µA
µA
µA
INT, REF
−
ZSD, ZSC, ZLE
ATL
−
ATL high-impedance; note 3
VOH = 2.4 V
−0.5
−
ROE, RXE
−600
Notes
1. Inputs: SDA and SCL pulled up to VDD; all other inputs connected to VSS
Outputs: RXE and ROE logic 0; REF: fref = 1⁄60 Hz; all other outputs open-circuit.
.
Oscillator: no crystal; external clock fosc = 76800 Hz; amplitude: VSS to VDD
Voltage convertor disabled (SPF byte 01, bit D7 = 0; see Table 24).
.
2. Maximum output current is subject to absolute maximum ratings per output (see Chapter 10).
3. When ATL (open drain output) is not activated it is high impedance.
12 DC CHARACTERISTICS (WITH VOLTAGE CONVERTER)
VDD = 2.7 V; VSS = 0 V; VPR = VPO; Tamb = −25 to +70 °C; Cs = 100 nF; voltage converter enabled.
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
1.5
TYP.
MAX.
UNIT
VDD
VPO(0)
VPO
IPO
−
3.0
−
V
output voltage; no load
output voltage
VDD = 2.7; IPO = 0
−
5.4
V
VDD = 2 V; IPO = −250 µA
3.0
3.5
−
V
output current
VDD = 2 V; VPO = 2.7 V
−400
−650
−650
−900
−
µA
µA
V
DD = 3 V; VPO = 4.5 V
−
13 OSCILLATOR CHARACTERISTICS
Quartz crystal type: MX-1V or equivalent.
Quartz crystal parameters: f = 76 800 Hz; RS(max) = 35 kΩ; CL = 8 pF; C0 = 1.4 pF; C1 = 1.5 fF.
Maximum overall tolerance: ±200 × 10−6 (includes: cutting, temperature, aging) for POCSAG, ± 55 × 10−6 for APOC-1
(‘transmitter off’ mode).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
10
12
MAX.
UNIT
pF
µS
CXO
gm
output capacitance XTAL2
oscillator transconductance
−
−
VDD = 1.5 V
6
−
1997 Jun 24
36
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
14 AC CHARACTERISTICS
V
DD = 2.7 V; VSS = 0 V; VPR = 2.7 V; Tamb = 25 °C;. fosc = 76800 Hz.
SYMBOLS PARAMETER CONDITIONS
System clock
Tclk system clock period
Call alert frequencies
MIN.
TYP.
MAX.
UNIT
fosc = 76800 Hz
−
13.02
−
µs
fAL
alert frequency
SPF byte 03H; bits:
D1, D0 = 0 0
−
−
−
−
−
2048
2731
3200
4096
16
−
−
−
−
−
Hz
Hz
Hz
Hz
Hz
D1, D0 = 0 1
D1, D0 = 1 0
D1, D0 = 1 1
fAW
warbled alert; modulation
frequency
alert set-up bit D2 = 1;
outputs ATL, ATH and LED
fAWH
fAWL
fVBP
warbled alert; high acoustic
alert frequency
alert set-up bit D2 = 1;
outputs ATL and ATH
−
−
−
fAL
−
−
−
Hz
Hz
Hz
warbled alert; low acoustic alert alert set-up bit D2 = 1;
frequency
1⁄2fAL
25
outputs ATL and ATH
pulsed vibrator frequency
(square wave)
low-level alert
Call alert duration
tALT
tALL
tALH
tVBL
tVBH
tALC
tALP
alert time-out period
−
−
−
−
−
−
−
16
4
−
−
−
−
−
−
−
s
ATL output time-out period
ATH output time-out period
VIB output time-out period
VIB output time-out period
alert cycle period
low-level alert
high-level alert
low-level alert
high-level alert
s
12
4
s
s
12
1
s
s
alert pulse duration
125
ms
Real time clock reference
fref
real time clock reference
frequency
SPF byte 02H; bits:
D3, D2 = 0 0; note 1
D3, D2 = 0 1; note 2
D3, D2 = 1 0
−
−
−
−
−
32768
−
−
−
−
−
Hz
Hz
Hz
Hz
µs
50
2
1
D3, D2 = 1 1
⁄
60
tRFP
real time clock reference pulse all reference frequencies except
duration 50 Hz (square wave)
13.02
1997 Jun 24
37
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Receiver control
tRXT
RXE and ROE transition time
CL = 5 pF
−
100
−
ns
tRXON
RXE establishment time
(nominal values: actual
duration is bit rate dependent,
see Table 25)
SPF byte 01H; bits:
D1, D0 = 0 0
−
−
−
−
5
−
−
−
−
ms
ms
ms
ms
D1, D0 = 0 1
10
15
30
D1, D0 = 1 0
D1, D0 = 1 1
tROON
ROE establishment time
(nominal values: actual
duration is bit rate dependent,
see Table 25)
SPF byte 01H; bits:
D3, D2 = 0 0
−
−
−
−
20
30
40
50
−
−
−
−
ms
ms
ms
ms
D3, D2 = 0 1
D3, D2 = 1 0
D3, D2 = 1 1
I2C-bus interface
fSCL
SCL clock frequency
0
−
−
−
−
−
−
−
−
−
−
−
100
−
kHz
µs
µs
ns
ns
ns
ns
pF
µs
µs
µs
tLOW
tHIGH
tSU;DAT
tHD;DAT
tr
SCL clock low period
SCL clock HIGH period
data set-up time
4.7
4.0
250
500
−
−
−
data hold time
−
SDA and SCL rise time
SDA and SCL fall time
capacitive bus line load
START condition set-up time
START condition hold time
STOP condition set-up time
1000
300
400
−
tf
−
CB
−
tSU;STA
tHD;STA
tSU;STO
4.7
4.0
4.0
−
−
Reset
tRST
tRSU
tOSU
external reset duration
set-up time after reset
set-up time after switch-on
50
−
−
−
−
−
µs
µs
ms
oscillator running
oscillator running
105
4
−
Data input
tTDI
data input transition time
data input logic 1 duration
data input logic 0 duration
see Fig.14
see Fig.14
see Fig.14
−
−
−
−
100
∞
µs
tDI1
tBIT
tBIT
tDI0
∞
POCSAG data timing (512 bits/s)
fDI
data input rate
bit duration
SPF byte 01H; D5 = 0; D4 = 0
−
512
−
−
−
−
−
bits/s
ms
tBIT
tCW
tPA
−
1.9531
62.5
−
codeword duration
preamble duration
batch duration
−
ms
1125
ms
tBAT
−
1062.5
ms
1997 Jun 24
38
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
POCSAG data timing (1200 bits/s)
fDI
data input rate
bit duration
SPF byte 01H; D5 = 1; D4 = 0
−
−
−
1200
833.3
26.7
−
−
bits/s
µs
tBIT
tCW
tPA
−
−
−
−
codeword duration
preamble duration
batch duration
ms
480
ms
tBAT
−
453.3
ms
POCSAG data timing (2400 bits/s)
fDI
data input rate
bit duration
SPF byte 01H; D5 = 1; D4 = 1
−
2400
416.6
13.3
−
−
−
−
−
−
bits/s
µs
tBIT
tCW
tPA
−
codeword duration
preamble duration
batch duration
−
ms
240
−
ms
tBAT
226.6
ms
APOC-1 batch timing
tSB
cycle duration
SPF byte 00H; bit D2 = 0
(5 batches)
−
−
2720
8160
−
−
bits
bits
SPF byte 00H; bit D2 = 0
(15 batches)
Synthesizer control
tZSU
fZSC
tZCL
tZSD
tZDS
tZDL1
tZLE
synthesizer set-up duration
oscillator running; note 3
note 4
1
−
−
−
−
−
−
−
−
2
−
−
−
−
−
−
−
bits
Hz
µs
µs
µs
µs
µs
µs
output clock frequency
clock pulse duration
data bit duration
38400
13.02
26.04
13.02
91.15
13.02
117.19
note 4
data bit set-up time
data load enable delay
load enable pulse duration
inter block delay
tZDL2
Notes
1. 32768 Hz reference signal; 32 pulses per 75 clock cycles, alternately separated by 1 or 2 pulse periods
(pulse duration: tRFP). The timing is shown in Fig.15.
2. 50 Hz reference signal: square wave.
3. Duration depends on programmed bit rate; after reset tZSU = 1.5 bits.
4. Nominal values; pause in 12th data bit (see Table 11).
1997 Jun 24
39
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
t
t
DI0
DI1
handbook, halfpage
t
MGL100
TDI
Fig.14 Data input timing.
t
RFP
t
RFP
MLC278
2t
RFP
Fig.15 Timing of the 32 768 Hz reference signal.
1997 Jun 24
40
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
15 APPLICATION INFORMATION
GM0D79
a n d b o o k , f u l l p a g e w i d t h
1997 Jun 24
41
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
16 PACKAGE OUTLINE
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y
X
A
24
17
25
16
Z
E
e
Q
H
E
A
E
(A )
3
2
A
A
1
w M
p
θ
b
L
p
pin 1 index
L
32
9
detail X
1
8
e
Z
D
v M
A
w M
b
p
D
B
H
v M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.4 0.18 7.1
0.3 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75 0.69
0.45 0.59
0.9
0.5
0.9
0.5
mm
1.60
0.25
0.8
1.0
0.2 0.25 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
93-06-29
95-12-19
SOT358 -1
1997 Jun 24
42
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
If wave soldering cannot be avoided, the following
conditions must be observed:
17 SOLDERING
17.1 Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
17.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
17.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
17.3 Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Jun 24
43
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
18 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
19 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
20 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jun 24
44
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
NOTES
1997 Jun 24
45
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
NOTES
1997 Jun 24
46
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
NOTES
1997 Jun 24
47
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Belgium: see The Netherlands
Brazil: see South America
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Colombia: see South America
Czech Republic: see Austria
Slovakia: see Austria
Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Indonesia: see Singapore
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
437027/25/04/pp48
Date of release: 1997 Jun 24
Document order number: 9397 750 02432
相关型号：
PCD5003H-T
IC TELECOM, PAGING DECODER, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32, Paging Circuit
NXP
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