PCF2104NU/2 [NXP]
LCD controller/driver; LCD控制器/驱动器型号: | PCF2104NU/2 |
厂家: | NXP |
描述: | LCD controller/driver |
文件: | 总56页 (文件大小:367K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF2104x
LCD controller/driver
1997 Dec 16
Product specification
Supersedes data of 1997 Apr 01
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
CONTENTS
9.4
Display on/off control
9.4.1
9.4.2
9.4.3
9.5
D
C
B
1
2
3
FEATURES
APPLICATIONS
Cursor/display shift
Function set
DL (parallel mode only)
N, M
Set CGRAM address
Set DDRAM address
Read busy flag and address
GENERAL DESCRIPTION
9.6
3.1
3.2
Packages
Available types
9.6.1
9.6.2
9.7
9.8
9.9
4
5
6
7
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
9.10
9.11
Write data to CGRAM or DDRAM
Read data from CGRAM or DDRAM
PIN FUNCTIONS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
RS: register select (parallel control)
R/W: read/write (parallel control)
E: data bus clock (parallel control)
DB0 to DB7: data bus (parallel control)
C1 to C60: column driver outputs
R1 to R32: row driver outputs
VLCD: LCD power supply
OSC: oscillator
SCL: serial clock line
SDA: serial data line
SA0: address pin
T1: test pad
10
INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
11
INTERFACE TO MICROCONTROLLER
(I2C-BUS INTERFACE)
Characteristics of the I2C-bus
Bit transfer
11.1
11.2
11.3
11.4
11.5
11.6
Start and stop conditions
System configuration
Acknowledge
I2C-bus protocol
12
LIMITING VALUES
8
FUNCTIONAL DESCRIPTION
13
HANDLING
8.1
8.2
8.3
8.4
LCD bias voltage generator
Oscillator
External clock
Power-on reset
Registers
14
DC CHARACTERISTICS
AC CHARACTERISTICS
TIMING DIAGRAMS
APPLICATION INFORMATION
15
16
17
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
Busy Flag
17.1
8-bit operation, 2 × 12 display using internal
reset
4-bit operation, 2 × 12 display using internal
reset
8-bit operation, 2 × 24 display
I2C operation, 2 × 12 display
Initializing by instruction
Address Counter (AC)
Display data RAM (DDRAM)
Character generator ROM (CGROM)
Character generator RAM (CGRAM)
Cursor control circuit
Timing generator
LCD row and column drivers
Programming of MUX 1 : 16 displays with
PCF2104x
17.2
17.3
17.4
17.5
18
19
20
21
BONDING PAD LOCATIONS
DEFINITIONS
8.15
Programming of MUX 1 : 32 displays with
PCF2104x
Reset function
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
8.16
9
INSTRUCTIONS
9.1
9.2
9.3
9.3.1
9.3.2
Clear display
Return home
Entry mode set
I/D
S
1997 Dec 16
2
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
but does not contain the high voltage generator of that
device.
1
FEATURES
• Single chip LCD controller/driver
The PCF2104x is optimized for chip-on-glass applications.
The ‘x’ in ‘PCF2104x’ represents a specific letter code for
a character set in the character generator ROM (CGROM).
• 1 or 2-line display of up to 24 characters per line, or
2 or 4 lines of up to 12 characters per line
• 5 × 7 character format plus cursor; 5 × 8 for kana
Two standard character sets are currently available,
specified by the letters ‘C’ and ‘L’ (see Figs 5 and 6).
Other character sets are available on request.
(Japanese syllabary) and user-defined symbols
• On-chip:
– generation of intermediate LCD bias voltages
The PCF2104x is a low-power CMOS LCD controller and
driver, designed to drive a split screen dot matrix LCD
display of 1 or 2 lines by 24 characters or 2 or 4 lines by
12 characters with a 5 × 8 dot format. All necessary
functions for the display are provided in a single chip,
including on-chip generation of LCD bias voltages which
results in a minimum of external components and lower
system power consumption. To allow partial VDD shutdown
the ESD protection system of the SCL and SDA pins does
– oscillator requires no external components (external
clock also possible)
• Display data RAM: 80 characters
• Character generator ROM: 240 characters
• Character generator RAM: 16 characters
• 4 or 8-bit parallel bus or 2-wire I2C-bus interface
• CMOS/TTL compatible
not use a diode connected to VDD
.
• 32 row, 60 column outputs
The chip contains a character generator and displays
alphanumeric and kana characters. The PCF2104x
interfaces to most microcontrollers via a 4 or 8-bit bus, or
via the 2-wire I2C-bus.
• MUX rates 1 : 32 and 1 : 16
• Uses common 11 code instruction set
• Logic supply voltage range, VDD − VSS: 2.5 to 6 V
• Display supply voltage range, VDD − VLCD: 3.5 to 9 V
• Low power consumption.
3.1
Packages
• I2C-bus address: 011101 SA0.
• PCF2104xU/2; chip with bumps in tray
• PCF2104xU/7; chip with bumps on tape.
2
APPLICATIONS
For further details see Chapter 18.
• Telecom equipment
• Portable instruments
• Point-of-sale terminals.
3.2
Available types
• PCF2104CU/x: character set ‘C’ in CGROM
• PCF2104LU/x: character set ‘L’ in CGROM
• PCF2104NU/x: character set ‘N’ in CGROM.
3
GENERAL DESCRIPTION
The PCF2104x integrated circuit is similar to the
PCF2114x (described in the “PCF2116 family” data sheet)
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PCF2104CU/2
−
−
−
−
−
−
chip with bumps in tray
chip with bumps on tape
chip with bumps in tray
chip with bumps on tape
chip with bumps in tray
chip with bumps on tape
−
−
−
−
−
−
PCF2104CU/7
PCF2104LU/2
PCF2104LU/7
PCF2104NU/2
PCF2104NU/7
1997 Dec 16
3
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
5
BLOCK DIAGRAM
C1 to C60
80-21
R1 to R32
5-20
81-96
60
32
COLUMN DRIVERS
60
ROW DRIVERS
BIAS
VOLTAGE
GENERATOR
111
V
LCD
6
32
SHIFT REGISTER
32-BIT
DATA LATCHES
60
SHIFT REGISTER
5 x 12-bit
5
PCF2104x
CURSOR + DATA CONTROL
5
2
4
V
DD
CHARACTER
CHARACTER
GENERATOR
ROM
1
GENERATOR
RAM
V
OSCILLATOR
OSC
SS
(CGRAM)
16
(CGROM)
240
CHARACTERS
CHARACTERS
101
T1
TIMING
GENERATOR
8
DISPLAY DATA RAM
(DDRAM) 80 CHARACTERS
7
DISPLAY
ADDRESS
COUNTER
7
ADDRESS
COUNTER (AC)
7
POWER - ON
RESET
INSTRUCTION
DECODER
8
8
DATA
REGISTER (DR)
BUSY
FLAG
INSTRUCTION
REGISTER (IR)
8
7
8
I/O BUFFER
4
4
109-106
105-102
98
E
100
R/W
99
RS
97
SCL
110
SDA
3
MGC627
DB0 to DB3 DB4 to DB7
SA0
Fig.1 Block diagram.
4
1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
6
PINNING
SYMBOL
FFC PAD
TYPE
DESCRIPTION
OSC
1
2
I
P
I
oscillator/external clock input
logic supply voltage
I2C-bus address pin input
VDD
SA0
VSS
3
4
P
O
O
O
O
O
O
O
I
ground
R8 to R5
R32 to R29
R24 to R17
C60 to C1
R9 to R16
R25 to R28
R1 to R4
SCL
5 to 8
9 to12
13 to 20
21 to 80
81 to 88
89 to 92
93 to 96
97
LCD row driver outputs
LCD row driver outputs
LCD row driver outputs
LCD column driver outputs
LCD row driver outputs
LCD row driver outputs
LCD row driver outputs
I2C-bus serial clock input
data bus clock input
E
98
I
RS
99
I
register select input
R/W
100
I
read/write input
T1
101
I
test pad input
DB7 to DB0
SDA
102 to 109
110
I/O
I/O
I
8-bit bidirectional data bus input/output
I2C-bus serial data input/output
LCD supply voltage input
VLCD
111
7
PIN FUNCTIONS
RS: register select (parallel control)
7.4
DB0 to DB7: data bus (parallel control)
The bidirectional, 3-state data bus transfers data between
the system controller and the PCF2104x. DB7 may be
used as the Busy Flag, signalling that internal operations
are not yet completed. In 4-bit operations the 4 higher
order lines DB4 to DB7 are used; DB0 to DB3 must be left
open circuit. There is an internal pull-up on each of the
data lines. Note that these pins must be left open circuit
when I2C-bus control is used.
7.1
RS selects the register to be accessed for read and write
when the device is controlled by the parallel interface.
RS = logic 0 selects the instruction register for write and
the Busy Flag and Address Counter for read. RS = logic 1
selects the data register for both read and write. There is
an internal pull-up on pin RS.
7.2
R/W: read/write (parallel control)
7.5
C1 to C60: column driver outputs
R/W selects either the read (R/W = logic 1) or write
(R/W = logic 0) operation when control is by the parallel
interface. There is an internal pull-up on this pin.
These pins output the data for pairs of columns.
This arrangement permits optimized chip-on-glass (COG)
layout for 4-line by 12 characters.
7.3
E: data bus clock (parallel control)
7.6
R1 to R32: row driver outputs
The E pin is set HIGH to signal the start of a read or write
operation when the device is controlled by the parallel
interface. Data is clocked in or out of the chip on the
negative edge of the clock. Note that this pin must be tied
to logic 0 (VSS) when I2C-bus control is used.
These pins output the row select waveforms to the left and
right halves of the display.
7.7
VLCD: LCD power supply
Negative power supply for the liquid crystal display.
1997 Dec 16
5
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
7.8
OSC: oscillator
8.2
Oscillator
When the on-chip oscillator is used, this pin must be
connected to VDD. An external clock signal, if used, is input
at this pin.
The on-chip oscillator provides the clock signal for the
display system. No external components are required.
Pin OSC must be connected to VDD
.
7.9
SCL: serial clock line
8.3 External clock
Input for the I2C-bus clock signal.
If an external clock is to be used, it must be input at
pin OSC. The resulting display frame frequency is given by
f
frame = 1⁄2304 osc
f
. A clock signal must always be present,
7.10 SDA: serial data line
otherwise the LCD may be frozen in a DC state.
Input/output for the I2C-bus data line.
8.4
Power-on reset
7.11 SA0: address pin
The Power-on reset block initializes the chip after
power-on or power failure.
The hardware sub-address line is used to program the
device sub-address for 2 different PCF2104xs on the
same I2C-bus.
8.5
Registers
The PCF2104x has two 8-bit registers, an instruction
register (IR) and a data register (DR). The register select
signal (RS) determines which register will be accessed.
7.12 T1: test pad
Must be connected to VSS. Not user accessible.
The instruction register stores instruction codes such as
display clear and cursor shift, and address information for
the Display Data RAM (DDRAM) and Character Generator
RAM (CGRAM). The instruction register can be written to,
but not read from, by the system controller.
8
FUNCTIONAL DESCRIPTION (see Fig.1)
8.1
LCD bias voltage generator
The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system power consumption. The optimum levels depend
on the multiplex rate and are selected automatically when
the number of lines in the display is defined.
The data register temporarily stores data to be read from
the DDRAM and CGRAM. When reading, data from the
DDRAM or CGRAM (corresponding to the address in the
Address Counter) is written to the data register prior to
being read by the ‘Read data’ instruction.
The optimum value of VOP depends on the multiplex rate,
the LCD threshold voltage (Vth) and the number of bias
levels. The relationships are given in Table 1.
8.6
Busy Flag
The Busy Flag indicates the free/busy status of the
PCF2104x. Logic 1 indicates that the chip is busy and
further instructions will not be accepted. The Busy Flag is
output at pin DB7 when RS = logic 0 and R/W = logic 1.
Instructions should only be written after checking that the
Busy Flag is at logic 0 or waiting for the required number
of clock cycles.
Using a 5-level bias scheme for 1 : 16 MUX rate allows
VOP < 5 V for most LCD liquids. The effect on the display
contrast is negligible.
Table 1 Optimum values for VOP
NUMBER
MUX
RATE
DISCRIMINATION
Von/Voff
OF BIAS
LEVELS
VOP/Vth
1 : 16
1 : 32
5
6
3.67
5.19
1.277
1.196
1997 Dec 16
6
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
8.7
Address Counter (AC)
8.10 Character generator RAM (CGRAM)
The Address Counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
instructions ‘Set CGRAM address’ and
‘Set DDRAM address’. After a read/write operation the
Address Counter is automatically incremented or
decremented by 1. The Address Counter contents are
output to the bus (DB0 to DB6) when RS = logic 0 and
R/W = logic 1.
Up to 16 user-defined characters may be stored in the
character generator RAM. The CGROM and CGRAM use
a common address space, of which the first column is
reserved for the CGRAM (see Fig.5). Figure 8 shows the
addressing principle for the CGRAM.
8.11 Cursor control circuit
The cursor control circuit generates the cursor (underline
and/or character blink as shown in Fig.9) at the DDRAM
address contained in the Address Counter. When the
Address Counter contains the CGRAM address the cursor
will be inhibited.
8.8
Display data RAM (DDRAM)
The DDRAM stores up to 80 characters of display data,
represented by 8-bit character codes. DDRAM locations
not used for storing display data can be used as general
purpose RAM. The basic DDRAM-to-display mapping
scheme is shown in Fig.2. With no display shift, the
characters represented by the codes in the first 12 or 24
RAM locations, starting at address 00 in line 1, are
displayed. Subsequent lines display data starting at
addresses 20, 40, or 60 Hex. Figures 3 and 4 show the
DDRAM-to-display mapping scheme when the display is
shifted.
8.12 Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
8.13 LCD row and column drivers
The PCF2104x contains 32 row and 60 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display, in accordance with the data to be
displayed. The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 10 and 11 show typical waveforms.
The address range for a 1-line display is 00 to 4F; for a
2-line display from 00 to 27 (line 1) and 40 to 67 (line 2);
for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and
60 to 73 for lines 1, 2, 3 and 4 respectively. For 2 and
4-line displays the end address of one line and the start
address of the next line are not consecutive. When the
display is shifted each line wraps around independently of
the others (see Figs 3 and 4).
In the 1-line mode (1 : 16) the row outputs are driven in
pairs: R1/R17, R2/R18 for example. This allows the output
pairs to be connected in parallel, thereby providing greater
drive capability.
When data is written to the DDRAM wrap-around occurs
from 4F to 00 in 1-line mode and from 27 to 40 and
67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60
and 73 to 00 in 4-line mode.
Unused outputs should be left unconnected.
8.9
Character generator ROM (CGROM)
The character generator ROM generates 240 character
patterns in 5 × 8 dot format from 8-bit character codes.
Figures 5 and 6 show the character sets currently
available.
1997 Dec 16
7
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
non-displayed DDRAM addresses
Display
Position
handbook, 4 columns
1
2
3
4
5
22 23 24
(decimal)
00 01 02 03 04
15 16 17 18 19
4C 4D 4E 4F
DDRAM
Address
(hex)
1-line display
non-displayed DDRAM address
24 25 26 27
00 01 02 03 04
40 41 42 43 44
15 16 17 18 19
55 56 57 58 59
line 1
line 2
DDRAM
Address
(hex)
64 65 66 67
MLA792
2-line display
non-displayed DDRAM addresses
9 10 11 12
handbook, 4 columns
1
2
3
4
5
6
7
8
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 line 1
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 line 2
DDRAM
Address
(hex)
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
line 3
line 4
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
MLA793
4 line display
Fig.2 DDRAM-to-display mapping; no shift (PCF2104x).
8
1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
Display
Position
(decimal)
Display
Position
(decimal)
1
2
3
4
5
22 23 24
14 15 16
1
2
3
4
5
22 23 24
16 17 18
4F 00 01 02 03
01 02 03 04 05
DDRAM
Address
(hex)
DDRAM
Address
(hex)
1-line display
1-line display
line 1
line 1
line 2
14 15 16
16 17 18
27 00 01 02 03
01 02 03 04 05
41 42 43 44 45
DDRAM
Address
(hex)
DDRAM
Address
(hex)
56 57 58
MLA815
67 40 41 42 43
54 55 56 line 2
MLA802
2-line display
2-line display
1
2
3
4
5
6
7
8
9 10 11 12
1
2
3
4
5
6
7
8
9 10 11 12
line 1
line 2
line 3
line 4
line 1
line 2
line 3
13 00 01 02 03 04 05 06 07 08 09 0A
33 20 21 22 23 24 25 26 27 28 29 2A
53 40 41 42 43 44 45 46 47 48 49 4A
73 60 61 62 63 64 65 66 67 68 69 6A
01 02 03 04 05 06 07 08 09 0A 0B 0C
21 22 23 24 25 26 27 28 29 2A 2B 2C
41 42 43 44 45 46 47 48 49 4A 4B 4C
DDRAM
DDRAM
Address
(hex)
Address
(hex)
61 62 63 64 65 66 67 68 69 6A 6B 6C
4-line display
line 4
MLA803
4-line display
MLA816
Fig.3 DDRAM-to-display mapping; right shift
(PCF2104x).
Fig.4 DDRAM-to-display mapping; left shift
(PCF2104x).
1997 Dec 16
9
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
lower
4 bits
CG
RAM 1
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MLB895
Fig.5 Character set ‘C’ in CGROM; PCF2104C.
1997 Dec 16
10
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
lower
6 bits
CG
RAM 1
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MGC629
Fig.6 Character set ‘L’ in CGROM; PCF2104L.
1997 Dec 16
11
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
upper
4 bits
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
lower
4 bits
CG
RAM 1
xxxx 0000
xxxx 0001
xxxx 0010
xxxx 0011
xxxx 0100
xxxx 0101
xxxx 0110
xxxx 0111
xxxx 1000
xxxx 1001
xxxx 1010
xxxx 1011
xxxx 1100
xxxx 1101
xxxx 1110
xxxx 1111
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MGM134
Fig.7 Character set ‘N’ in CGROM; PCF2104N.
1997 Dec 16
12
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
character codes
(DDRAM data)
CGRAM
address
character patterns
(CGRAM data)
7
6
5
4
3
2
1
0
0
6
0
5
4
3
2
1
0
4
3
2
1
0
higher
order
bits
lower
order
bits
higher
order
bits
lower
order
bits
higher
order
bits
lower
order
bits
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
character
pattern
example 1
0
0
0
0
0
0
0
0
0
0
0
0
0
cursor
position
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
character
pattern
example 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
MGA800 - 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the
cursor. Data in the 8th line will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4; bit 4 being at the left end, as shown in the figure.
CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘Set CGRAM address’ instruction. Bit 6 can be set using the ‘Set DDRAM address’ instruction or
by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘Read Busy Flag and address’ instruction.
Fig.8 Relationship between CGRAM addresses, data and display patterns.
1997 Dec 16
13
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
MGA801
cursor
5 x 7 dot character font
alternating display
cursor display example
blink display example
Fig.9 Cursor and blink display examples.
1997 Dec 16
14
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
frame n
frame n 1
state 1 (ON)
state 2 (ON)
V
DD
V
2
V /V
ROW 1
ROW 9
ROW 2
3
4
V
5
V
LCD
V
V
DD
2
V /V
3
4
1-line display
(1:16)
V
5
V
LCD
V
V
DD
2
V /V
3
4
V
5
V
LCD
V
V
DD
2
V /V
COL 1
3
4
V
5
V
LCD
V
V
DD
2
COL 2
V /V
4
3
5
V
V
LCD
V
OP
0.25 V
0 V
OP
OP
state 1
0.25 V
V
OP
V
OP
0.25 V
0 V
OP
OP
state 2
0.25 V
V
OP
MGA802 - 1
1
2
3
16
1
2
3
16
Fig.10 Typical LCD waveforms; 1-line mode.
15
1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
frame n
frame n 1
state 1 (ON)
state 2 (ON)
V
DD
V
2
V
3
V
ROW 1
4
V
5
V
LCD
V
DD
V
2
V
3
ROW 9
V
4
V
5
V
LCD
V
DD
V
2
V
3
V
2-line display
(1:32)
ROW 2
4
V
5
V
LCD
V
DD
V
2
V
3
COL 1
V
4
V
5
V
LCD
V
DD
V
2
V
3
COL 2
V
4
V
5
V
LCD
V
OP
0.15 V
OP
0 V
state 1
0.15 V
OP
V
OP
V
OP
0.15 V
state 2 0 V
0.15 V
OP
OP
V
OP
MGA803 - 1
123
32 12 3
32
Fig.11 Typical LCD waveforms; 2-line mode.
16
1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
Using the ‘Function set’ instruction, M and N are set to 0, 0
(respectively). Figures 12, 13 and 14 show the DDRAM
addresses of the display characters. The second row of
each table corresponds to either the right half of a 1-line
display or to the second line of a 2-line display. Wrap
around of data during display shift or when writing data is
non-standard.
8.14 Programming of MUX 1 : 16 displays with
PCF2104x
The PCF2104x can be used in the following ways:
•
•
1-line mode to drive a 2-line display
2 × 12 characters with MUX rate 1 : 16, resulting in
better contrast. The internal data flow of the chip is
optimized for this purpose.
display position
DDRAM address
1
2
3
4
5
6
7
8
9
10
09
11
0A
12
0B
00
01
02
03
04
05
06
07
08
display position
DDRAM address
13
14
15
0E
16
0F
17
10
18
11
19
12
20
13
21
14
22
15
23
16
24
17
0C
0D
MLB899
Fig.12 DDRAM-to-display mapping; no shift (PCF2104x).
display position
DDRAM address
1
2
3
4
5
6
7
8
9
10
08
11
09
12
0A
4F
00
01
02
03
04
05
06
07
display position
DDRAM address
13
0B
14
15
16
0E
17
0F
18
10
19
11
20
12
21
13
22
14
23
15
24
16
0C
0D
MLB900
Fig.13 DDRAM-to-display mapping; right shift (PCF2104x).
display position
DDRAM address
1
2
3
4
5
6
7
8
9
10
0A
11
0B
12
01
02
03
04
05
06
07
08
09
0C
display position
DDRAM address
13
14
0E
15
0F
16
10
17
11
18
12
19
13
20
14
21
15
22
16
23
17
24
18
0D
MLB901
Fig.14 DDRAM-to-display mapping; left shift (PCF2104x).
17
1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
8.15 Programming of MUX 1 : 32 displays with
PCF2104x
9
INSTRUCTIONS
Only two PCF2104x registers, the instruction register (IR)
and the data register (DR) can be directly controlled by the
microcontroller. Before internal operation, control
information is stored temporarily in these registers to allow
interface to various types of microcontrollers which
operate at different speeds or to allow interfacing to
peripheral control ICs.
The PCF2104x operation is controlled by the instructions
shown in Table 3 together with their execution time.
Details are explained in subsequent sections.
To drive a 2-line by 24 characters MUX 1 : 32 display, use
instruction ‘Function set’ to set M, N to 0, 1 (respectively).
To drive a 4-line by 12 characters MUX 1:32 display, use
instruction ‘Function set’ to set M, N to 1, 1 (respectively).
8.16 Reset function
The PCF2104 automatically initializes (resets) when
power is turned on. The state after reset is given in
Table 2.
Instructions are of 4 categories, those that:
1. Designate PCF2104x functions such as display
format, data length, etc.
Table 2 State after reset
STEP
DESCRIPTION
2. Set internal RAM addresses
3. Perform data transfer with internal RAM
4. Others.
1
2
Display clear.
Function set:
DL = 1: 8-bit interface
M, N = 0 1-line display
G = 0: not used
In normal use, category 3 instructions are used most
frequently. However, automatic incrementing by 1
(or decrementing by 1) of internal RAM addresses after
each data write lessens the microcontroller program load.
The display shift in particular can be performed
concurrently with display data write, thus enabling the
designer to develop systems in minimum time with
maximum programming efficiency.
3
Display on/off control:
D = 0: display off
C = 0: cursor off;
B = 0: blink off;
4
5
Entry mode set:
During internal operation, no instruction other than the
Busy Flag/address read instruction will be executed.
I/D = 1: +1 (increment)
G = 0: not used
Because the Busy Flag is set to logic 1 while an instruction
is being executed, it is advisable to ensure that the flag it
is at logic 0 before sending the next instruction or wait for
the maximum instruction execution time, as given in
Table 3. An instruction sent while the Busy Flag is HIGH
will not be executed.
Default address pointer to DDRAM. The Busy
Flag (BF) indicates the busy state (BF = logic 1)
until initialization ends. The busy state lasts
2 ms. The chip may also be initialized by
software. See Tables 10 and 11.
6
I2C-bus interface reset.
1997 Dec 16
18
-------
-
Table 3 Instructions (note 1)
REQUIRED
CLOCK
INSTRUCTION
NOP
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
CYCLES(2)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
No operation.
0
Clear display
Clears entire display and sets DDRAM
address 0 in Address Counter.
165
Return home
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
Sets DDRAM address 0 in Address Counter
Also returns shifted display to original position
DDRAM contents remain unchanged.
3
3
Entry mode set
I/D
S
Sets cursor move direction and specifies shift
of display. These operations are performed
during data write and read.
Display control
Cursor/display shift
Function set
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
D
C
0
B
0
0
Sets entire display on/off (D), cursor on/off (C)
and blink of cursor position character (B).
3
3
3
S/C R/L
Moves cursor and shifts display without
changing DDRAM contents.
DL
N
M
G
Sets interface data length (DL), number of
display lines (N, M) and voltage generator
control (G).
Set CGRAM
address
0
0
0
0
0
1
0
1
1
ACG
Sets CGRAM address.
3
3
0
Set DDRAM
address
ADD
AC
Sets DDRAM address.
Read busy flag and
address
BF
Reads Busy Flag (BF) indicating internal
operation is being performed and reads
Address Counter contents.
Read data
Write data
1
1
1
0
read data
write data
Reads data from CGRAM or DDRAM.
Writes data to CGRAM or DDRAM.
3
3
Notes
1. In the I2C-bus mode the DL bit is don't care. 8-bit mode is assumed.
In the I2C-bus mode a control byte is required when RS or R/W is changed; control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0.
1
fosc
2. Example: fosc = 150 kHz, Tcy
=
= 6.67 µs; 3 cycles = 20 µs, 165 cycles = 1.1 ms.
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
Table 4 Command bit identities
BIT
LOGIC 0
LOGIC 1
I/D
S
decrement
increment
display shift
display on
cursor on
display freeze
D
display off
C
cursor off
B
character at cursor position does not blink
character at cursor position blinks
display shift
S/C
R/L
DL
cursor move
left shift
right shift
4 bits
8 bits
N (M = 0)
N (M = 1)
BF
2 line × 12 characters; MUX 1 : 16
reserved
2 lines × 24 characters; MUX 1 : 32
4 lines × 12 characters; MUX 1 : 32
internal operation in progress
end of internal operation
last control byte, only data bytes to follow
Co
next two bytes are a data byte and another control byte
RS
R/W
E
DB7
DB6
DB5
DB4
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
BF
AC3
AC2
AC1
AC0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
AC6
AC5
AC4
busy flag and
address counter read
data register
read
instruction
write
MGA804
Fig.15 4-bit transfer example.
1997 Dec 16
20
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
RS
R/W
E
internal
internal operation
not
busy
DB7
IR7
IR3
AC3
AC3
D7
D3
busy
instruction
write
busy flag
check
busy flag
check
instruction
write
MGA805
IR7, IR3: instruction 7th bit, 3rd bit.
AC3: Address Counter 3rd bit.
Fig.16 An example of 4-bit data transfer timing sequence.
RS
R/W
E
internal
internal operation
not
busy
data
busy
busy
data
DB7
instruction
write
busy flag
check
busy flag
check
busy flag
check
instruction
write
MGA806
Fig.17 Example of Busy Flag check timing sequence.
21
1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
9.1
Clear display
9.4.2
C
‘Clear display’ writes space code 20 (hexadecimal) into all
DDRAM addresses (the character pattern for character
code 20 must be a blank pattern), sets the DDRAM
Address Counter to logic 0 and returns the display to its
original position if it was shifted. Consequently, the display
disappears and the cursor or blink position goes to the left
edge of the display (the first line if 2 or 4 lines are
displayed) and sets the entry mode to I/D = logic 1
(increment mode). S of entry mode does not change.
The cursor is displayed when C = logic 1 and inhibited
when C = logic 0. Even if the cursor disappears, the
display functions I/D, etc. remain in operation during
display data write. The cursor is displayed using 5 dots in
the 8th line (see Fig.9).
9.4.3
B
The character indicated by the cursor blinks when
B = logic 1. The blink is displayed by switching between
display characters and all dots on with a period of
1 second when fosc = 150 kHz (see Fig.9). At other clock
The instruction ‘Clear display’ requires extra execution
time. This may be allowed for by checking the Busy Flag
(BF) or by waiting until 2 ms has elapsed. The latter must
be applied where no read-back options are foreseen, as in
some chip-on-glass (COG) applications.
frequencies the blink period is equal to 150 kHz/fosc
The cursor and the blink can be set to display
simultaneously.
.
9.2
Return home
9.5
Cursor/display shift
‘Return home’ sets the DDRAM Address Counter to
logic 0 and returns the display to its original position if it
was shifted. DDRAM contents do not change. The cursor
or blink position goes to the left of the display (the first line
if 2 or 4 lines are displayed). I/D and S of entry mode do
not change.
‘Cursor/display shift’ moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In 2 or 4-line displays, the
cursor moves to the next line when it passes the last
position of the line (40 or 20 decimal). When the displayed
data is shifted repeatedly all lines shift at the same time;
displayed characters do not shift into the next line.
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the cursor shift.
9.3
Entry mode set
9.3.1
I/D
When I/D = logic 1 (0) the DDRAM or CGRAM address
increments (decrements) by 1 when data is written to or
read from the DDRAM or CGRAM. The cursor or blink
position moves to the right when incremented and to the
left when decremented. The cursor and blink are inhibited
when the CGRAM is accessed.
9.6
Function set
9.6.1
DL (PARALLEL MODE ONLY)
Sets interface data width. Data is sent or received in bytes
(DB7 to DB0) when DL = logic 1 or in two nibbles
(DB7 to DB4) when DL = logic 0. When 4-bit width is
selected, data is transmitted in two cycles using the
parallel bus(1).
9.3.2
S
When S = logic 1, the entire display shifts either to the right
(I/D = logic 0) or to the left (I/D = logic 1) during a DDRAM
write. Consequently, it looks as if the cursor stands still and
the display moves. The display does not shift when
reading from the DDRAM, or when writing to or reading
from the CGRAM. When S = logic 0 the display does not
shift.
Function set from I2C-bus interface: DL bit can not bet set
to logic 0 from the I2C-bus interface. If bit DL has been set
to logic 0 via the parallel bus, programming via the I2C-bus
interface is complicated.
9.6.2
N, M
9.4
Display on/off control
Sets number of display lines.
9.4.1
D
(1) In a 4-bit application DB3 to DB0 are left open (internal
pull-ups). Hence in the first function set instruction after
power-on G and H are set to 1. A second function set must
then be sent (2 nibbles) to set G and H to their required
values.
The display is on when D = logic 1 and off when
D = logic 0. Display data in the DDRAM is not affected and
can be displayed immediately by setting D to logic 1.
1997 Dec 16
22
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
9.7
Set CGRAM address
9.11 Read data from CGRAM or DDRAM
‘Set CGRAM address’ sets bits 0 to 5 of the CGRAM
address (ACG in Table 3) into the Address Counter
(binary A[5] to A[0]). Data can then be written to or read
from the CGRAM.
Reads binary 8-bit data D[7] to D[0] from the CGRAM or
DDRAM.
The most recent ‘Set address’ instruction determines
whether the CGRAM or DDRAM is to be read.
Only bits 0 to 5 of the CGRAM address are set by the
‘Set CGRAM address’ instruction. Bit 6 can be set using
the ‘Set DDRAM address’ instruction or by using the
auto-increment feature during CGRAM write. All bits 0 to 6
can be read using the ‘Read busy flag and address’
instruction.
The ‘Read data’ instruction gates the content of the data
register (DR) to the bus while E = HIGH. After E goes
LOW again, internal operation increments (or decrements)
the AC and stores RAM data corresponding to the new AC
into the DR.
Remark: the only three instructions that update the data
register (DR) are:
9.8
Set DDRAM address
• ‘Set CGRAM address’
Set DDRAM address sets the DDRAM address (ADD in
Table 3) into the Address Counter (binary A[6] to A[0).
Data can then be written to or read from the DDRAM.
• ‘Set DDRAM address’
• ‘Read data’ from CGRAM or DDRAM.
Other instructions (e.g. ‘Write data, ‘Cursor/display shift’,
‘Clear display’, ‘Return home’) will not modify the data
register content.
Table 5 Hexadecimal address ranges
ADDRESS
00 to 4F
FUNCTION
1-line by 24
00 to 0B and 0C to 4F
00 to 27 and 40 to 67
2-line by 12
2-line by 24
10 INTERFACE TO MICROCONTROLLER
(PARALLEL INTERFACE)
00 to 13, 20 to 33, 40 to 53 4-line by 12
and 60 to 73
The PCF2104x can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
9.9
Read busy flag and address
In the 8-bit mode data is transferred as 8-bit bytes using
the 8 data lines DB0 to DB7. Three further control lines E,
RS, and R/W are required.
‘Read busy flag and address’ reads the Busy Flag (BF).
When BF = logic 1 it indicates that an internal operation is
in progress. The next instruction will not be executed until
BF = logic 0, so BF should be checked before sending
another instruction.
In the 4-bit mode data is transferred in two cycles of 4-bits
each. The higher order bits (corresponding to DB4 to DB7
in 8-bit mode) are sent in the first cycle and the lower order
bits (DB0 to DB3 in 8-bit mode) in the second cycle.
Data transfer is complete after two 4-bit data transfers.
It should be noted that two cycles are also required for the
Busy Flag check. 4-bit operation is selected by instruction.
See Figs 15, 16 and 17 for examples of bus protocol.
At the same time, the value of the Address Counter
expressed in binary A[6] to A[0] is read out. The Address
Counter is used by both CGRAM and DDRAM and its
value is determined by the previous instruction.
9.10 Write data to CGRAM or DDRAM
In the 4-bit mode pins DB3 to DB0 must be left
open-circuit. They are pulled up to VDD internally.
Writes binary 8-bit data D[7] to D[0] to the CGRAM or the
DDRAM.
Whether the CGRAM or DDRAM is to be written to is
determined by the previous specification of CGRAM or
DDRAM address setting. After writing, the address
automatically increments or decrements by 1, in
accordance with the entry mode. Only bits D0 to D4 of
CGRAM data are valid, bits D5 to D7 are ‘don't care’.
1997 Dec 16
23
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
11 INTERFACE TO MICROCONTROLLER
(I2C-BUS INTERFACE)
11.5 Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
11.1 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL).
Both lines must be connected to a positive supply via a
pull-up resistor. Data transfer may be initiated only when
the bus is not busy.
11.2 Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
11.3 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
11.6 I2C-bus protocol
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I2C-bus configuration for the different
PCF2104x READ and WRITE cycles is illustrated in
Figs 22, 23 and 24.
11.4 System configuration
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.18 Bit transfer.
24
1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
MBC622
Fig.19 Definition of START and STOP conditions.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.20 System configuration.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
MASTER
1
2
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.21 Acknowledgement on the I2C-bus.
25
1997 Dec 16
acknowledgement
from PCF2104x
S
A
0
0
1
1
1
0
1
0
A
1
CONTROL BYTE
A
DATA
A
0
CONTROL BYTE
1 byte
A
DATA
A
P
S
slave address
2n 0 bytes
n
0 bytes
update
data pointer
R/W
Co
Co
S
A
0
0
1
1
1
0
1
0
MGC617
PCF2104x
slave address
R/W
Fig.22 Master transmits to slave receiver; WRITE mode.
ahdnbok,uflapegwidt
acknowledgement
from PCF2104x
S
A
0
(1)
0
1
1
1
0
1
1
CONTROL BYTE
DATA
0
1
1
CONTROL
DATA
0
A
A
A
A
A
S
slave address
2n 0 bytes
2 bytes
R/W
Co
Co
acknowledgement
from PCF2104x
no acknowledgement
from master
S
A
0
SLAVE
ADDRESS
1
A
DATA
A
DATA
1
P
S
n bytes
last byte
R/W
update
MGC618
data pointer
(1) Last data byte is a dummy byte (may be omitted).
Fig.23 Master reads after setting word address; write word address, set RS/RW; READ data.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
acknowledgement
from PCF2104x
acknowledgement
from master
no acknowledgement
from master
S
A
0
SLAVE
ADDRESS
1
A
DATA
A
DATA
1
S
P
last byte
n bytes
R/W
update
data pointer
MGC619
Fig.24 Master reads slave immediately after first byte; READ mode (RS previously defined).
1997 Dec 16
28
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 0
LSB
R/W
STOP
CONDITION
(P)
BIT 6
(A6)
ACKNOWLEDGE
(A)
PROTOCOL
SDA
t
t
t
r
BUF
LOW
SCL
t
t
HD;STA
f
t
SU;STO
t/f
SCL
MGA811 - 1
t
HIGH
Fig.25 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
12 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
UNIT
supply voltage
+8.0
V
VLCD
VI
LCD supply voltage
V
V
V
DD − 11
VDD
V
input voltage OSC, RS, R/W, E and DB0 to DB7
output voltage R1 to R32, C1 to C60 and VLCD
DC input current
SS − 0.5
VDD + 0.5
V
VO
II
LCD − 0.5 VDD + 0.5
V
−10
−10
−50
−
+10
+10
+50
400
100
+150
mA
mA
mA
IO
DC output current
IDD, ISS, ILCD VDD, VSS or VLCD current
Ptot
PO
Tstg
total power dissipation
power dissipation per output
storage temperature
mW
mW
°C
−
−65
13 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
14 DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
2.5
−
6.0
V
VLCD
IDD
LCD supply voltage
supply current external VLCD
supply current 1
V
−
−
−
DD − 9
−
V
DD − 3.5
V
note 1
−
−
IDD1
200
200
500
300
µA
µA
IDD2
supply current 2
VDD = 5 V; VOP = 9 V;
fosc = 150 kHz;
Tamb = 25 °C
IDD3
supply current 3
VDD = 3 V; VOP = 5 V;
fosc = 150 kHz;
−
150
200
µA
Tamb = 25 °C
ILCD
VLCD input current
notes 1 and 6
note 2
−
−
50
100
1.8
µA
VPOR
Power-on reset voltage level
1.3
V
1997 Dec 16
30
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
SYMBOL
Logic
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VIL1
LOW level input voltage pins E, RS,
R/W, DB0 to DB7 and SA0
VSS
−
0.3VDD
VDD
V
VIH1
HIGH level input voltage pins E, RS,
R/W, DB0 to DB7 and SA0
0.7VDD
VSS
−
V
VIL(osc)
VIH(osc)
Ipu
LOW level input voltage pin OSC
HIGH level input voltage pin OSC
−
VDD − 1.5
V
VDD − 0.1
−
VDD
V
pull-up current at pins DB0 to DB7, VI = VSS
RS and R/W
0.04
0.15
1.00
µA
IOL(DB)
IOH(DB)
IL1
LOW level output current pins
DB0 to DB7
VOL = 0.4 V; VDD = 5 V 1.6
−
−
−
−
mA
mA
µA
HIGH level output current pins
DB0 to DB7
VOH = 4 V; VDD = 5 V
VI = VDD or VSS
−1.0
−1
−
leakage current pins OSC, E, RS,
R/W, DB0 to DB7 and SA0
+1
I2C-bus
SDA, SCL
VIL2
VIH2
IL2
LOW level input voltage
HIGH level input voltage
leakage current
note 3
VSS
−
−
−
−
−
0.3VDD
V
note 3
0.7VDD
VDD
+1
7
V
VI = VDD or VSS
note 4
−1
−
µA
pF
mA
Ci
input capacitance
IOL(SDA)
LOW level output current (SDA)
VOL = 0.4 V; VDD = 5 V
3
−
LCD outputs
RROW
row output resistance pins
R1 to R32
note 5
note 5
note 6
−
−
−
1.5
3
3
kΩ
kΩ
mV
RCOL
Vtol1
column output resistance pins
C1 to C60
6
bias voltage tolerance pins
R1 to R32 and C1 to C60
±20
±130
Notes
1. LCD outputs are open-circuit; inputs at VDD or VSS; V0 = VDD; bus inactive; internal or external clock with duty cycle
50% (IDD1 only).
2. Resets all logic when VDD < VPOR
.
3. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow; this current must
not exceed ±0.5 mA.
4. Tested on sample basis.
5. Resistance of output terminals (R1 to R32 and C1 to C60) with load current Iload = 150 µA; VOP = VDD − VLCD = 9 V;
outputs measured one at a time.
6. LCD outputs open-circuit.
1997 Dec 16
31
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
15 AC CHARACTERISTICS
VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to + 85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
40
TYP.
65
MAX.
100
UNIT
Hz
fFR
fosc
LCD frame frequency (internal clock)
external clock frequency
note 1
90
150
225
kHz
Bus timing characteristics: Parallel Interface; notes 1 and 2
WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2104X)
Tcy
enable cycle time
enable pulse width
address set-up time
address hold time
data set-up time
data hold time
500
220
50
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
PWEH
tASU
tAH
25
tDSW
tHD
60
25
READ OPERATION (READING DATA FROM PCF2104X TO MICROCONTROLLER)
Tcy
enable cycle time
enable pulse width
address set-up time
address hold time
data delay time
500
220
50
25
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
PWEH
tASU
tAH
−
−
−
tDHD
tHD
150
100
data hold time
20
Timing characteristics: I2C-bus interface; note 2
fSCL
SCL clock frequency
tolerable spike width on bus
bus free time
−
−
−
−
−
−
−
−
−
−
−
−
−
100
100
−
kHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
tSW
−
tBUF
4.7
4.7
4
tSU;STA
tHD;STA
tLOW
tHIGH
tr
set-up time for a repeated START condition
start condition hold time
SCL LOW time
−
−
4.7
4
−
SCL HIGH time
−
SCL and SDA rise time
SCL and SDA fall time
data set-up time
−
1
tf
−
0.3
−
tSU;DAT
tHD;DAT
tSU;STO
250
0
data hold time
−
set-up time for STOP condition
4
−
Notes
1. VDD = 5.0 V.
2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD
.
1997 Dec 16
32
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
16 TIMING DIAGRAMS
RS
V
V
V
V
IH1
IL1
IH1
IL1
t
t
AH
V
AS
R/W
V
IL1
IL1
t
PW
EH
AH
V
V
IH1
IH1
E
V
V
V
IL1
IL1
IL1
t
H
t
DSW
IH1
V
V
V
V
IH1
IL1
Valid Data
DB0 to DB7
IL1
MLA798 - 1
T
cy
Fig.26 Parallel bus write operation sequence; writing data from microcontroller to PCF2104x.
V
V
V
V
IH1
IL1
t
IH1
IL1
RS
t
AS
AH
V
V
IH1
IH1
R/W
t
PW
AH
EH
V
V
IH1
IH1
V
E
V
IL1
V
IL1
IL1
t
t
DHR
DDR
V
V
V
V
OH1
OH1
OL1
DB0 to DB7
OL1
MLA799 - 1
T
cy
Fig.27 Parallel bus read operation sequence; reading data from PCF2104x to microcontroller.
33
1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
17 APPLICATION INFORMATION
handbook, 4 columns
P20
P21
P22
RS
R/W
E
32
60
R1 to R32
to
LCD
P80CL51
PCF2104x
C1 to C60
DB0 to DB7
8
P10 to P17
MGC620
Fig.28 Direct connection to 8-bit microcontroller; 8-bit bus.
handbook, 4 columns
RS
R/W
E
P10
P11
P12
32
60
R1 to R32
to
LCD
P80CL51
PCF2104x
C1 to C60
DB4 to DB7
4
P14 to P17
MGC621
Fig.29 Direct connection to 8-bit microcontroller; 4-bit bus.
R7 to R16
R25 to R32
V
V
LCD
16
LCD
100 nF
V
V
R1 to R8
DD
DD
2 x 24 CHARACTER
LCD DISPLAY
(SPLIT SCREEN)
R17 to R24
OSC
100
nF
16
PCF2104x
60
60
C1 to C60
V
V
SS
SS
MGC624
DB0 to DB7 E RS R/W
Fig.30 Typical application using parallel interface.
34
1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
V
V
V
16
LCD
100 nF
LCD
R1 to R16
V
DD
DD
2 x 24 CHARACTER
LCD DISPLAY
(SPLIT SCREEN)
R17 to R24
16
OSC
100
nF
PCF2104x
V
V
DD DD
60
60
C1 to C60
V
V
SS
SS
SA0
V
DD
V
V
LCD
LCD
100 nF
V
V
DD
DD
R1 to R16
16
2 x 12 CHARACTER
LCD DISPLAY
OSC
100
nF
PCF2104x
60
C1 to C60
V
V
SS
SS
SA0
MGC625
V
SS
SCL SDA
MASTER TRANSMITTER
PCF84C81
Fig.31 Application using I2C-bus interface.
1997 Dec 16
35
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
17.1 8-bit operation, 2 × 12 display using internal
17.3 8-bit operation, 2 × 24 display
reset
For a 2-line display, the cursor automatically moves from
the first to the second line after the 40th digit of the first line
has been written. Thus, if there are only 8 characters in the
first line, the DDRAM address must be set after the eighth
character is completed (see Table 8). It should be noted
that both lines of the display are always shifted together,
data does not shift from one line to the other.
Table 7 shows an example of a 1-line display in 8-bit
operation. The PCF2104x functions must be set by the
function set instruction prior to display. Since the display
data RAM can store data for 80 characters, the RAM can
be used for advertising displays when combined with
display shift operation. Since the display shift operation
changes the display position only and DDRAM contents
remain unchanged. Display data entered first can be
displayed when the ‘Return home’ instruction is
performed.
17.4 I2C operation, 2 × 12 display
A control byte is required with most instructions
(see Table 9).
17.2 4-bit operation, 2 × 12 display using internal
17.5 Initializing by instruction
reset
If the power supply conditions for correctly operating the
internal reset circuit are not met, the PCF2104x must be
initialized by instruction. Tables 10 and 11 show how this
may be performed for 8-bit and 4-bit operation.
The program must set functions prior to 4-bit operation.
Table 6 shows an example. When power is turned on, 8-bit
operation is automatically selected and the PCF2104x
attempts to perform the first write as an 8-bit operation.
Since nothing is connected to DB0 to DB3, a rewrite is
then required. However, since one operation is completed
in two accesses of 4-bit operation, a rewrite is required to
set the functions (see Table 6 step 3).
Thus, DB4 to DB7 of the function set are written twice.
1997 Dec 16
36
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
Table 6 4-bit operation, 1-line display example; using internal reset
STEP
INSTRUCTION
DISPLAY
OPERATION
Initialized. No display appears.
1
Power supply on (PCF2104x is
initialized by the internal reset circuit).
2
3
Function set:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0;
DB5 = 1; DB4 = 0
Sets to 4-bit operation. In this instance operation is
handled as 8-bits by initialization and only this
instruction completes with one write.
Function set:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0;
DB5 = 1; DB4 = 0
Sets to 4-bit operation, selects 2 × 12 display.
RS = 0; R/W = 0; DB7 = 0; DB6 = 0;
DB5 = 0; DB4 = 0
4-bit operation starts from this point and resetting is
needed.
4
5
6
Display on/off control:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0;
DB5 = 0; DB4 = 0
Turns on display and cursor.
RS = 0; R/W = 0; DB7 = 1; DB6 = 1;
DB5 = 1; DB4 = 0
Entire display is blank after initialization.
Entry mode set:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0;
DB5 = 0; DB4 = 0
_
Sets mode to increment the address by 1 and to shift the
cursor to the right at the time of write to the DD/CGRAM.
RS = 0; R/W = 0; DB7 = 0; DB6 = 1;
DB5 = 1; DB4 = 0
Display is not shifted.
Write data to CGRAM/DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; P_
DB5 = 0; DB4 = 1
Writes ‘P’. The DDRAM has already been selected by
initialization at power-on.
RS = 1; R/W = 0; DB7 = 0; DB6 = 1;
DB5 = 1; DB4 = 0
The cursor is incremented by 1 and shifted to the right.
1997 Dec 16
37
Table 7 8-bit operation, 1-line display example; using internal reset (character set ‘A’)
STEP
INSTRUCTION
DISPLAY
OPERATION
Initialized. No display appears.
1
Power supply on (PCF2104x is initialized by the internal
reset function).
2
3
Function set:
Sets to 8-bit operation, selects 2 × 12 display.
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1;
DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0
Display mode on/off control:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 0
_
Turns on display and cursor. Entire display is blank after
initialization.
4
Entry mode set:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 0
_
Sets mode to increment the address by 1 and to shift the
cursor to the right at the time of the write to the
DD/CGRAM. Display is not shifted.
5
Write data to CGRAM/DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1;
DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0
P_
Writes ‘P’. The DDRAM has already been selected by
initialization at power-on. The cursor is incremented by 1
and shifted to the right.
6
Write data to CGRAM/DDRAM:
PH_
Writes ‘H’.
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 1; DB4 = 1;
DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0
7
|
|
|
8
Write data to CGRAM/DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1;
DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1
PHILIPS_
PHILIPS_
HILIPS _
Writes ‘S’.
9
Entry mode set:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 1
Sets mode for display shift at the time of write.
10
11
12
Write data to CGRAM/DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0;
DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0
Writes space.
Writes ‘M’.
Write data to CGRAM/DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0;
DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1
ILIPS M_
|
|
|
STEP
INSTRUCTION
Write data to CGRAM/DDRAM:
DISPLAY
OPERATION
13
MICROKO
Writes ‘O’.
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0;
DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 1
14
15
16
17
18
19
20
21
Cursor or display shift:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1;
DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0
MICROKO
MICROKO
ICROCO
Shifts only the cursor position to the left.
Shifts only the cursor position to the left.
Writes ‘C’ correction. The display moves to the left.
Shifts the display and cursor to the right.
Shifts only the cursor to the right.
Writes ‘M’.
Cursor or display shift:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1;
DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0
Write data to CGRAM/DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0;
DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1
Cursor or display shift:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1;
DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 0
MICROCO
MICROCO_
ICROCOM_
Cursor or display shift:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1;
DB3 = 0; DB2 = 1; DB1 = 0; DB0 = 0
Write data to CGRAM/DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0;
DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1
|
|
|
Return home:
PHILIPS M
Returns both display and cursor to the original position
(address 0).
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 0
Table 8 8-bit operation, 2-line display example; using internal reset
STEP
INSTRUCTION
DISPLAY
OPERATION
Initialized. No display appears.
1
Power supply on (PCF2104x is initialized by the internal
reset function).
2
3
Function set:
Sets to 8-bit operation, selects 2 × 24 display
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1;
DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0
Display on/off control:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 0
_
Turns on display and cursor. Entire display is blank after
initialization.
4
Entry mode set:
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 0
_
Sets mode to increment the address by 1 and to shift the
cursor to the right at the time of write to the CG/DDRAM.
Display is not shifted.
5
Write data to CGRAM/DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1;
DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0
P_
Writes ‘P’. The DDRAM has already been selected by
initialization at power-on. The cursor is incremented by 1
and shifted to the right.
6
|
|
|
7
Write data to CGRAM/DDRAM:
PHILIPS_
Writes ‘S’.
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1;
DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1
8
Set DDRAM address:
RS = 0; R/W = 0; DB7 = 1; DB6 = 1; DB5 = 0; DB4 = 0;
DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0
PHILIPS
_
Sets DDRAM address to position the cursor at the head of
the 2nd line.
9
Write data to CGRAM/ DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0;
DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1
PHILIPS
M_
Writes ‘M’.
10
11
12
|
|
|
Write data to CGRAM/ DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0;
DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 1
PHILIPS
Writes ‘O’.
MICROCO_
Write data to CGRAM/ DDRAM:
PHILIPS
Sets mode for display shift at the time of write.
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 1
MICROCO_
STEP
INSTRUCTION
Write data to CGRAM/ DDRAM:
RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0;
DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1
DISPLAY
HILIPS
OPERATION
13
Writes ‘M’. Display is shifted to the left. The first and
second lines shift together.
ICROCOM_
14
15
|
|
|
Return home:
PHILIPS
Returns both display and cursor to the original position
(address 0).
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 0
MICROCOM
Table 9 Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1)
STEP
I2C-BUS BYTE
DISPLAY
OPERATION
Initialized. No display appears.
1
2
I2C-bus start
Slave address for write:
SA6 = 0; SA5 = 1; SA4 = 1; SA3 = 1; SA2 = 0; SA1 = 1;
SA0 = 0; R/W = 0; Ack = 1
During the acknowledge cycle SDA will be pulled-down by
the PCF2104x.
3
4
Send a control byte for function set:
Co = 0; RS = 0; R/W = 0; Ack = 1
Control byte sets RS and R/W for following data bytes.
Function set:
Selects 1-line display; SCL pulse during acknowledge
cycle starts execution of instruction.
DB7 = 0; DB6 = 0; DB5 = 1; DB4 = X; DB3 = 0; DB2 = 0;
DB1 = 0; DB0 = 0; Ack = 1
5
6
Display on/off control:
DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1;
DB1 = 1; DB0 = 0; Ack = 1
_
_
Turns on display and cursor. Entire display shows
character Hex 20 (blank in ASCII-like character sets).
Entry mode set:
DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1;
DB1 = 1; DB0 = 0; Ack = 1
Sets mode to increment the address by 1 and to shift the
cursor to the right at the time of write to the DDRAM or
CGRAM. Display is not shifted.
7
8
I2C-bus start
_
_
For writing data to DDRAM, RS must be set to 1.
Therefore a control byte is needed.
Slave address for write:
SA6 = 0; SA5 = 1; SA4 = 1; SA3 = 1; SA2 = 0; SA1 = 1;
SA0 = 0; R/W = 0; Ack = 1
9
Send a control byte for write data:
Co = 0; RS = 1; R/W = 0; Ack = 1
_
10
Write data to DDRAM:
DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0;
DB1 = 0; DB0 = 0; Ack = 1
P_
Writes ‘P’. The DDRAM has been selected at power-up.
The cursor is incremented by 1 and shifted to the right.
11
Write data to DDRAM:
PH_
Writes ‘H’.
DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0;
DB1 = 0; DB0 = 0; Ack = 1
12 to 15
|
|
|
|
16
Write data to DDRAM:
PHILIPS_
Writes ‘S’.
DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0;
DB1 = 1; DB0 = 1; Ack = 1
STEP
I2C-BUS BYTE
DISPLAY
OPERATION
17
(optional I2C-bus stop) I2C-bus start + slave address for write PHILIPS_
(as step 8)
18
19
Control byte:
Co = 1; RS = 0; R/W = 0; Ack = 1
PHILIPS_
PHILIPS
Return home:
Sets DDRAM address 0 in Address Counter. (Also returns
shifted display to original position. DDRAM contents
unchanged). This instruction does not update the Data
Register (DR).
DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0;
DB1 = 1; DB0 = 0; Ack = 1
20
Control byte for read:
Co = 0; RS = 1; R/W = 1; Ack = 1
PHILIPS
DDRAM content will be read from following instructions.
The R/W has to be set to 1 while still in I2C-bus write
mode.
21
22
I2C-bus start
PHILIPS
PHILIPS
Slave address for read:
SA6 = 0; SA5 = 1; SA4 = 1; SA3 = 1; SA2 = 0; SA1 = 1;
SA0 = 0; R/W = 1; Ack = 1
During the acknowledge cycle the content of the DR is
loaded into the internal I2C-bus interface to be shifted out.
In the previous instruction neither a ‘Set address’ nor a
‘Read data’ has been performed. Therefore the content of
the DR was unknown.
23
Read data: 8 × SCL + master acknowledge; note 2:
DB7 = X; DB6 = X; DB5 = X; DB4 = X; DB3 = X; DB2 = X;
DB1 = X; DB0 = X; Ack = 1
PHILIPS
8 × SCL; content loaded into interface during previous
acknowledge cycle is shifted out over SDA. MSB is DB7.
During master acknowledge content of DDRAM
address 01 is loaded into the I2C-bus interface.
24
25
Read data: 8 × SCL + master acknowledge; note 2:
DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0;
DB1 = 0; DB0 = 0; Ack = 0
PHILIPS
PHILIPS
8 × SCL; code of letter ‘H’ is read first. During master
acknowledge code of ‘I’ is loaded into the I2C-bus
interface.
No master acknowledge; After the content of the I2C-bus
interface register is shifted out no internal action is
performed. No new data is loaded to the interface register,
Data Register (DR) is not updated, Address Counter (AC)
is not incremented and cursor is not shifted.
Read data: 8 × SCL + no master acknowledge; note 2:
DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0;
DB1 = 0; DB0 = 1; Ack = 1
26
I2C stop
PHILIPS
Notes
1. X = don’t care.
2. SDA is left at high-impedance by the microcontroller during the READ acknowledge.
Table 10 Initialization by instruction, 8-bit interface (note 1)
STEP
DESCRIPTION
Power-on or unknown state
|
Wait 2 ms after VDD rises above VPOR
|
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1;
DB3 = X; DB2 = X; DB1 = X; DB0 = X
BF cannot be checked before this instruction. ‘Function set’
(interface is 8-bits long).
|
Wait 2 ms
|
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1;
DB3 = X; DB2 = X; DB1 = X; DB0 = X
BF cannot be checked before this instruction.‘Function set’
(interface is 8-bits long).
|
Wait more than 40 µs
|
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1;
DB3 = X; DB2 = X; DB1 = X; DB0 = X
BF cannot be checked before this instruction. ‘Function set’
(interface is 8-bits long).
|
|
BF can be checked after the following instructions. When BF is not checked, the
waiting time between instructions is the specified instruction time (see Table 3).
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1;
DB3 = N; DB2 = M; DB1 = X; DB0 = 0
‘Function set’ (interface is 8-bits long). Specify the number of display lines.
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0
‘Display off’.
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 1
‘Clear display’.
‘Entry mode set’.
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0;
DB3 = 0; DB2 = 1; DB1 = I/D; DB0 = S
|
Initialization ends
Note
1. X = don’t care.
Table 11 Initialization by instruction, 4-bit interface. Not applicable for I2C-bus operation
STEP
DESCRIPTION
Power-on or unknown state
|
Wait 2 ms after VDD rises above VPOR
|
BF cannot be checked before this instruction. ‘Function set’
(interface is 8-bits long).
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1
|
Wait 2 ms
|
BF cannot be checked before this instruction. ‘Function set’
(interface is 8-bits long).
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1
|
Wait 40 µs
|
BF cannot be checked before this instruction. ‘Function set’
(interface is 8-bits long).
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1
|
|
BF can be checked after the following instructions. When BF is not checked, the
waiting time between instructions is the specified instruction time (see Table 3).
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0
RS = 0; R/W = 0; DB7 = N; DB6 = M; DB5 = 0; DB4 = 0
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0
RS = 0; R/W = 0; DB7 = 1; DB6 = 0; DB5 = 0; DB4 = 0
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0
RS = 0; R/W = 0; DB7 = 1; DB6 = 0; DB5 = 0; DB4 = 0
RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0
RS = 0; R/W = 0; DB7 = 0; DB6 = 1; DB5 = I/D; DB4 = S
|
‘Function set’ (set interface to 4-bits long). Interface is 8-bits long.
‘Function set’ (interface is 4-bits long).
Specify number of display lines and voltage generator characteristic.
‘Display off’.
‘Clear display’.
‘Entry mode set’.
Initialization ends
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
DISPLAY LAYOUT: COLUMNS
15 46
PCF2104x column
output numbers
C1
60
LCD column
numbers
1
31
60
DOT MATRIX LCD
PCF2104x column
output numbers
C16
45
DISPLAY LAYOUT: ROWS
R8 to R1
R9 to R16
MGC623
R17 to R24
R32 to R25
Fig.32 Example of 4 × 12 display layout (PCF2104x).
1997 Dec 16
46
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
display glass
dot matrix
COLUMN LAYOUT
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ROW LAYOUT
1 to 8
16 to 9
MLB898
2
lines by 12 characters display
Fig.33 Display example (PCF2104x); 2 lines by 12 characters.
1997 Dec 16
47
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
R1
R8
PCF2104x
CHIP-ON-GLASS
4 LINE BY
R9
R16
R17
R24
R25
R32
12 CHARACTER
C1
2104
R9
C60
MGC626
SCL
SDA
V
SS
DD
LCD
V
V
Fig.34 Chip-on-glass application.
1997 Dec 16
48
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
18 BONDING PAD LOCATIONS
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
58
57
56
55
54
53
52
51
50
R15 87
R16 88
R25 89
R26 90
R27
R28
91
92
R1 93
R2
R3 95
R4
94
49
48
47
96
SCL 97
98
E
46 C35
45 C36
44 C37
43 C38
42 C39
41 C40
40 C41
39 C42
38 C43
37 C44
36 C45
35 C46
34 C47
33 C48
32 C49
31 C50
30 C51
29 C52
28 C53
RS 99
100
101
R/W
T1
x
≈ 5.63
mm
0
0
y
DB7 102
DB6 103
DB5
DB4
104
105
PCF2104x
DB3 106
DB2 107
DB1 108
DB0 109
SDA 110
V
111
LCD
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
MGC628
≈ 5.10 mm
Chip dimensions: approximately 5.10 × 5.63 mm.
Gold bump dimensions: approximately 89 × 89 × 25 µm.
Fig.35 Bonding pad locations.
49
1997 Dec 16
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
Table 12 Bonding pad locations (dimensions in µm).
All x/y coordinates are referenced to centre of chip,
see Fig.35
SYMBOL
OSC
PAD
x
y
SYMBOL
C42
PAD
x
y
1
−2184.5
−2024.5
−1864.5
−1704.5
−1339
−1179
−1019
−859
−699
−539
−379
−219
−59
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2637
−2445
−2285
−2125
−1965
−1805
−1645
−1485
−1325
−1165
−1005
−845
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2185
2025
1865
1705
1545
1385
1225
1065
905
−685
−525
VDD
SA0
VSS
R8
2
C41
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
3
−365
4
−205
5
−45
R7
6
115
R6
7
275
R5
8
435
R32
R31
R30
R29
R24
R23
R22
R21
R20
R19
R18
R17
C60
C59
C58
C57
C56
C55
C54
C53
C52
C51
C50
C49
C48
C47
C46
C45
C44
C43
9
595
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
755
915
1075
1235
101
1395
261
1555
421
1715
581
1875
741
2035
901
2195
1061
1221
1381
1541
1701
1861
2021
2181
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2350
2355
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
745
585
425
265
105
C8
−55
C7
−215
−375
−535
C6
C5
1997 Dec 16
50
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
SYMBOL
C4
PAD
x
y
77
78
−695
−855
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2637.5
2308
C3
C2
79
−1015
−1175
−1385
−1545
−1705
−1865
−2025
−2185
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2349
−2327.5
−2027.5
1982.5
C1
80
R9
81
R10
R11
82
83
R12
R13
R14
R15
R16
R25
R26
R27
R28
R1
84
85
86
87
88
2148
89
1988
90
1828
91
1668
92
1508
93
1348
R2
94
1188
R3
95
1028
R4
96
868
SCL
E
97
632
98
472
RS
99
312
R/W
T1
100
101
102
103
104
105
106
107
108
109
110
111
142
−34
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SDA
VLCD
RECPAT ‘F’
RECPAT ‘C’
RECPAT ‘C’
−233
−393
−668
−828
−1103
−1263
−1538
−1698
−1933
−2453
2427.5
−2512.5
2297.5
1997 Dec 16
51
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
19 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
20 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Dec 16
52
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
NOTES
1997 Dec 16
53
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
NOTES
1997 Dec 16
54
Philips Semiconductors
Product specification
LCD controller/driver
PCF2104x
NOTES
1997 Dec 16
55
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
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Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
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Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
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Tel. +7 095 755 6918, Fax. +7 095 755 6919
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Czech Republic: see Austria
Slovakia: see Austria
Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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Hungary: see Austria
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Tel. +1 800 234 7381
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Tel. +60 3 750 5214, Fax. +60 3 757 4880
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Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/04/pp56
Date of release: 1997 Dec 16
Document order number: 9397 750 02924
相关型号:
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