PCF2127T_技术文档

PCF2127

Accurate RTC with integrated quartz crystal for industrial

applications

Rev. 8 — 19 December 2014

Product data sheet

1. General description

The PCF2127 is a CMOS¹Real Time Clock (RTC) and calendar with an integrated

Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz

crystal optimized for very high accuracy and very low power consumption. The PCF2127

has 512 bytes of general-purpose static RAM, a selectable I²C-bus or SPI-bus, a backup

battery switch-over circuit, a programmable watchdog function, a timestamp function, and

many other features.

For a selection of NXP Real-Time Clocks, see Table 94 on page 89

2. Features and benefits

 UL Recognized Component

 Operating temperature range from 40 C to +85 C

 Temperature Compensated Crystal Oscillator (TCXO) with integrated capacitors

 Typical accuracy:

 PCF2127AT: 3 ppm from 15 C to +60 C

 PCF2127T: 3 ppm from 30 C to +80 C

 Integration of a 32.768 kHz quartz crystal and oscillator in the same package

 Provides year, month, day, weekday, hours, minutes, seconds, and leap year

correction

 512 bytes of general-purpose static RAM

 Timestamp function

 with interrupt capability

 detection of two different events on one multilevel input pin (for example, for tamper

detection)

 Two line bidirectional 400 kHz Fast-mode I²C-bus interface

 3 line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s)

 Battery backup input pin and switch-over circuitry

 Battery backed output voltage

 Battery low detection function

 Extra power fail detection function with input and output pins

 Power-On Reset Override (PORO)

 Oscillator stop detection function

 Interrupt output (open-drain)

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

 Programmable 1 second or 1 minute interrupt

 Programmable watchdog timer with interrupt

 Programmable alarm function with interrupt capability

 Programmable square wave output pin

 Programmable countdown timer with interrupt

 Clock operating voltage: 1.8 V to 4.2 V

 Low supply current: typical 0.70 A at V_DD= 3.3 V

3. Applications

 Electronic metering for electricity, water, and gas

 Precision timekeeping

 Access to accurate time of the day

 GPS equipment to reduce time to first fix

 Applications that require an accurate process timing

 Products with long automated unattended operation time

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCF2127AT

PCF2127T

SO20

plastic small outline package; 20 leads;

body width 7.5 mm

SOT163-1

SO16

plastic small outline package; 16 leads;

body width 7.5 mm

SOT162-1

4.1 Ordering options

Table 2.

Ordering options

Product type number Orderable part number Sales item

(12NC)

Delivery form

IC

revision

PCF2127AT/2

PCF2127T/2

PCF2127AT/2Y

PCF2127T/2Y

935299867518 tape and reel, 13 inch, dry pack

935299866518 tape and reel, 13 inch, dry pack

2

5. Marking

Table 3.

Marking codes

Product type number

PCF2127AT/2

PCF2127T/2

Marking code

PCF2127AT

PCF2127T

PCF2127

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Product data sheet

Rev. 8 — 19 December 2014

2 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

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Fig 1. Block diagram of PCF2127

PCF2127

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Product data sheet

Rev. 8 — 19 December 2014

3 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

7. Pinning information

7.1 Pinning

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Fig 2. Pin configuration for PCF2127AT (SO20)

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Fig 4. Position of the stubs from the package assembly process

PCF2127

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Product data sheet

Rev. 8 — 19 December 2014

4 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

After lead forming and cutting, there remain stubs from the package assembly process.

These stubs are present at the edge of the package as illustrated in Figure 4. The stubs

are at an electrical potential. To avoid malfunction of the PCF2127, it has to be ensured

that they are not shorted with another electrical potential (e.g. by condensation).

7.2 Pin description

Table 4.

Pin description of PCF2127

Input or input/output pins must always be at a defined level (V_SSor V_DD) unless otherwise specified.

Symbol

Description

PCF2127AT

PCF2127T

SCL

SDI

1

2

1

2

combined serial clock input for both I²C-bus and SPI-bus

serial data input for SPI-bus

connect to pin V_SSif I²C-bus is selected

SDO

3

4

3

4

serial data output for SPI-bus, push-pull

combined serial data input and output for the I²C-bus and

chip enable input (active LOW) for the SPI-bus

SDA/CE

IFS

5

interface selector input

connect to pin V_SSto select the SPI-bus

connect to pin BBS to select the I²C-bus

timestamp input (active LOW) with 200 k internal pull-up

TS

6

resistor (R_PU

)

CLKOUT

V_SS

7

clock output (open-drain)

8

ground supply voltage

n.c.

9 to 12

13

14

15

16

17

18

19

-

not connected; do not connect; do not use as feed through

do not connect; do not use as feed through

power fail output (open-drain; active LOW)

power fail input

TEST

PFO

PFI

9

10

11

12

13

14

15

RST

INT

reset output (open-drain; active LOW)

interrupt output (open-drain; active LOW)

output voltage (battery backed)

battery supply voltage (backup)

connect to V_SSif battery switch-over is not used

supply voltage

BBS

V_BAT

V_DD

20

16

PCF2127

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Product data sheet

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PCF2127

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Accurate RTC with integrated quartz crystal for industrial applications

8. Functional description

The PCF2127 is a Real Time Clock (RTC) and calendar with an on-chip Temperature

Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal integrated

into the same package (see Section 8.3.3).

Address and data are transferred by a selectable 400 kHz Fast-mode I²C-bus or a 3 line

SPI-bus with separate data input and output (see Section 9). The maximum speed of the

SPI-bus is 6.5 Mbit/s.

The PCF2127 has a backup battery input pin and backup battery switch-over circuit which

monitors the main power supply. The backup battery switch-over circuit automatically

switches to the backup battery when a power failure condition is detected (see

Section 8.6.1). Accurate timekeeping is maintained even when the main power supply is

interrupted.

A battery low detection circuit monitors the status of the battery (see Section 8.6.2). When

the battery voltage drops below a certain threshold value, a flag is set to indicate that the

battery must be replaced soon. This ensures the integrity of the data during periods of

battery backup.

8.1 Register overview

The PCF2127 contains an auto-incrementing address register: the built-in address

register will increment automatically after each read or write of a data byte up to the

register 1Bh. After register 1Bh, the auto-incrementing will wrap around to address 00h

(see Figure 5).

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Fig 5. Handling address registers

• The first three registers (memory address 00h, 01h, and 02h) are used as control

registers (see Section 8.2).

• The memory addresses 03h through to 09h are used as counters for the clock

function (seconds up to years). The date is automatically adjusted for months with

fewer than 31 days, including corrections for leap years. The clock can operate in

12-hour mode with an AM/PM indication or in 24-hour mode (see Section 8.9).

• The registers at addresses 0Ah through 0Eh define the alarm function. It can be

selected that an interrupt is generated when an alarm event occurs (see

Section 8.10).

PCF2127

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Product data sheet

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PCF2127

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Accurate RTC with integrated quartz crystal for industrial applications

• The register at address 0Fh defines the temperature measurement period and the

clock out mode. The temperature measurement can be selected from every 4 minutes

(default) down to every 30 seconds (see Table 14). CLKOUT frequencies of

32.768 kHz (default) down to 1 Hz for use as system clock, microcontroller clock, and

so on, can be chosen (see Table 15).

• The registers at addresses 10h and 11h are used for the watchdog and countdown

timer functions. The watchdog timer has four selectable source clocks allowing for

timer periods from less than 1 ms to greater than 4 hours (see Table 58). Either the

watchdog timer or the countdown timer can be enabled (see Section 8.11). For the

watchdog timer, it is possible to select whether an interrupt or a pulse on the reset pin

is generated when the watchdog times out. For the countdown timer, it is only

possible that an interrupt is generated at the end of the countdown.

• The registers at addresses 12h to 18h are used for the timestamp function. When the

trigger event happens, the actual time is saved in the timestamp registers (see

Section 8.12).

• The register at address 19h is used for the correction of the crystal aging effect (see

Section 8.4.1).

• The registers at addresses 1Ah and 1Bh define the RAM address. The register at

address 1Ch (RAM_wrt_cmd) is the RAM write command; register 1Dh

(RAM_rd_cmd) is the RAM read command. Data is transferred to or from the RAM by

the serial interface (see Section 8.5).

• The registers Seconds, Minutes, Hours, Days, Months, and Years are all coded in

Binary Coded Decimal (BCD) format to simplify application use. Other registers are

either bit-wise or standard binary.

When one of the RTC registers is written or read, the content of all counters is temporarily

frozen. This prevents a faulty writing or reading of the clock and calendar during a carry

condition (see Section 8.9.8).

PCF2127

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Product data sheet

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PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

8.2 Control registers

The first 3 registers of the PCF2127, with the addresses 00h, 01h, and 02h, are used as

control registers.

8.2.1 Register Control_1

Table 6.

Control_1 - control and status register 1 (address 00h) bit allocation

Bits labeled as T must always be written with logic 0.

Bit

7

6

5

4

3

2

1

0

Symbol

EXT_

TEST

T

STOP

TSF1

POR_

OVRD

12_24

MI

SI

Reset

value

0

1

0

Table 7.

Control_1 - control and status register 1 (address 00h) bit description

Bits labeled as T must always be written with logic 0.

Bit

Symbol

Value

Description

Reference

7

EXT_TEST

0

1

0

1

normal mode

Section 8.14

external clock test mode

unused

6

5

T

-

STOP

RTC source clock runs

RTC clock is stopped;

Section 8.15

RTC divider chain flip-flops are asynchronously

set logic 0;

CLKOUT at 32.768 kHz, 16.384 kHz, or

8.192 kHz is still available

4

3

2

TSF1

0

1

no timestamp interrupt generated

Section 8.12.1

flag set when TS input is driven to an intermediate

level between power supply and ground;

flag must be cleared to clear interrupt

POR_OVRD

12_24

0

1

Power-On Reset Override (PORO) facility disabled; Section 8.8.2

set logic 0 for normal operation

Power-On Reset Override (PORO) sequence

reception enabled

0

1

24-hour mode selected

12-hour mode selected

Table 33,

Table 49,

Table 74

1

0

MI

SI

0

1

0

1

minute interrupt disabled

minute interrupt enabled

second interrupt disabled

second interrupt enabled

Section 8.13.1

PCF2127

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Product data sheet

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PCF2127

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Accurate RTC with integrated quartz crystal for industrial applications

8.2.2 Register Control_2

Table 8.

Bit

Control_2 - control and status register 2 (address 01h) bit allocation

7

MSF

0

6

WDTF

0

5

TSF2

0

4

AF

0

3

CDTF

0

2

TSIE

0

1

AIE

0

CDTIE

0

Symbol

Reset

value

Table 9.

Control_2 - control and status register 2 (address 01h) bit description

Bit

Symbol

Value

Description

no minute or second interrupt generated

Reference

7

MSF

0

1

Section 8.13

flag set when minute or second interrupt generated;

flag must be cleared to clear interrupt

6

WDTF

0

1

no watchdog timer interrupt or reset generated

Section 8.13.4

flag set when watchdog timer interrupt or reset

generated;

flag cannot be cleared by command (read-only)

no timestamp interrupt generated

5

4

3

TSF2

AF

0

1

Section 8.12.1

Section 8.10.6

Section 8.11.4

flag set when TS input is driven to ground;

flag must be cleared to clear interrupt

no alarm interrupt generated

0

1

flag set when alarm triggered;

flag must be cleared to clear interrupt

no countdown timer interrupt generated

flag set when countdown timer interrupt generated;

flag must be cleared to clear interrupt

no interrupt generated from timestamp flag

interrupt generated when timestamp flag set

no interrupt generated from the alarm flag

interrupt generated when alarm flag set

no interrupt generated from countdown timer flag

interrupt generated when countdown timer flag set

CDTF

0

1

2

1

0

TSIE

AIE

0

1

0

1

0

1

Section 8.13.6

Section 8.13.5

Section 8.13.2

CDTIE

PCF2127

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Product data sheet

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Accurate RTC with integrated quartz crystal for industrial applications

8.2.3 Register Control_3

Table 10. Control_3 - control and status register 3 (address 02h) bit allocation

Bit

7

6

5

4

BTSE

0

3

BF

0

2

BLF

0

1

BIE

0

BLIE

0

Symbol

PWRMNG[2:0]

0

Reset

value

0

Table 11. Control_3 - control and status register 3 (address 02h) bit description

Bit

Symbol

Value

Description

Reference

7 to 5

PWRMNG[2:0]

see

control of the battery switch-over, battery low

Section 8.6

Table 25

detection, and extra power fail detection functions

no timestamp when battery switch-over occurs

time-stamped when battery switch-over occurs

no battery switch-over interrupt generated

flag set when battery switch-over occurs;

flag must be cleared to clear interrupt

battery status ok;

4

3

BTSE

BF

0

1

0

1

Section 8.12.4

Section 8.6.1

and

Section 8.12.4

2

BLF

0

1

Section 8.6.2

no battery low interrupt generated

battery status low;

flag cannot be cleared by command

no interrupt generated from the battery flag (BF)

interrupt generated when BF is set

1

0

BIE

0

1

0

1

Section 8.13.7

BLIE

no interrupt generated from battery low flag (BLF) Section 8.13.8

interrupt generated when BLF is set

8.3 Register CLKOUT_ctl

Table 12. CLKOUT_ctl - CLKOUT control register (address 0Fh) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

6

5

OTPR

X

4

-

3

-

2

1

COF[2:0]

0

Symbol

TCR[1:0]

Reset

value

0

-

0

Table 13. CLKOUT_ctl - CLKOUT control register (address 0Fh) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7 to 6

5

Symbol

TCR[1:0]

OTPR

Value

Description

see Table 14

temperature measurement period

no OTP refresh

0

1

OTP refresh performed

unused

4 to 3

2 to 0

-

COF[2:0]

see Table 15

CLKOUT frequency selection

PCF2127

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Product data sheet

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PCF2127

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Accurate RTC with integrated quartz crystal for industrial applications

8.3.1 Temperature compensated crystal oscillator

The frequency of tuning fork quartz crystal oscillators is temperature-dependent. In the

PCF2127, the frequency deviation caused by temperature variation is corrected by

adjusting the load capacitance of the crystal oscillator.

The load capacitance is changed by switching between two load capacitance values using

a modulation signal with a programmable duty cycle. In order to compensate the spread of

the quartz parameters every chip is factory calibrated.

The frequency accuracy can be evaluated by measuring the frequency of the square

wave signal available at the output pin CLKOUT. However, the selection of

f_CLKOUT= 32.768 kHz (default value) leads to inaccurate measurements. Accurate

frequency measurement occurs when f_CLKOUT= 16.384 kHz or lower is selected (see

Table 15).

8.3.1.1 Temperature measurement

The PCF2127 has a temperature sensor circuit used to perform the temperature

compensation of the frequency. The temperature is measured immediately after power-on

and then periodically with a period set by the temperature conversion rate TCR[1:0] in the

register CLKOUT_ctl.

Table 14. Temperature measurement period

TCR[1:0]

Temperature measurement period

[1]

00

01

10

11

4 min

2 min

1 min

30 seconds

[1] Default value.

8.3.2 OTP refresh

Each IC is calibrated during production and testing of the device. The calibration

parameters are stored on EPROM cells called One Time Programmable (OTP) cells. It is

recommended to process an OTP refresh once after the power is up and the oscillator is

operating stable. The OTP refresh takes less than 100 ms to complete.

To perform an OTP refresh, bit OTPR has to be cleared (set to logic 0) and then set to

logic 1 again.

8.3.3 Clock output

A programmable square wave is available at pin CLKOUT. Operation is controlled by the

COF[2:0] control bits in register CLKOUT_ctl. Frequencies of 32.768 kHz (default) down

to 1 Hz can be generated for use as system clock, microcontroller clock, charge pump

input, or for calibrating the oscillator.

CLKOUT is an open-drain output and enabled at power-on. When disabled, the output is

high-impedance.

PCF2127

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Product data sheet

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PCF2127

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Accurate RTC with integrated quartz crystal for industrial applications

Table 15. CLKOUT frequency selection

COF[2:0]

000

CLKOUT frequency (Hz)

Typical duty cycle^[1]

[2][3]

32768

60 : 40 to 40 : 60

50 : 50

-

001

16384

010

8192

011

4096

100

2048

101

1024

110

1

111

CLKOUT = high-Z

[1] Duty cycle definition: % HIGH-level time : % LOW-level time.

[2] Default value.

[3] The specified accuracy of the RTC can be only achieved with CLKOUT frequencies not equal to

32.768 kHz or if CLKOUT is disabled.

The duty cycle of the selected clock is not controlled, however, due to the nature of the

clock generation all but the 32.768 kHz frequencies are 50 : 50.

8.4 Register Aging_offset

Table 16. Aging_offset - crystal aging offset register (address 19h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read.

Bit

7

-

6

-

5

-

4

-

3

2

1

0

Symbol

AO[3:0]

Reset

value

-

1

0

Table 17. Aging_offset - crystal aging offset register (address 19h) bit description

Bit positions labeled as - are not implemented and return 0 when read.

Bit

Symbol

-

Value

Description

unused

7 to 4

3 to 0

-

AO[3:0]

see Table 18

aging offset value

8.4.1 Crystal aging correction

The PCF2127 has an offset register Aging_offset to correct the crystal aging effects².

The accuracy of the frequency of a quartz crystal depends on its aging. The aging offset

adds an adjustment, positive or negative, in the temperature compensation circuit which

allows correcting the aging effect.

At 25 C, the aging offset bits allow a frequency correction of typically 1 ppm per AO[3:0]

value, from 7 ppm to +8 ppm.

2. For further information, refer to the application note Ref. 3 “AN11266”.

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Table 18. Frequency correction at 25C, typical

AO[3:0]

ppm

Decimal

Binary

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

+8

+7

+6

+5

+4

+3

+2

+1

0

1

2

3

4

5

6

7

[1]

8

9

1

2

3

4

5

6

7

10

11

12

13

14

15

[1] Default value.

8.5 General purpose 512 bytes static RAM

The PCF2127 contains a general purpose 512 bytes static RAM. This integrated SRAM is

battery backed and can therefore be used to store data which is essential for the

application to survive a power outage.

9 bits, RA[8:0], define the RAM address pointer in registers RAM_addr_MSB and

RAM_addr_LSB. The register address pointer increments after each read or write

automatically up to 1Bh and then wraps around to address 00h (see Figure 5 on page 6).

Data is transferred to or from the RAM by the interface. To write to the RAM, the register

RAM_wrt_cmd, to read from the RAM the register RAM_rd_cmd must be addressed

explicitly.

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8.5.1 Register RAM_addr_MSB

Table 19. RAM_addr_MSB - RAM address MSB register (address 1Ah) bit allocation

Bit positions labeled as - are not implemented and return 0 when read.

Bit

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

RA8

0

Symbol

Reset

value

-

Table 20. RAM_addr_MSB - RAM address MSB register (address 1Ah) bit description

Bit positions labeled as - are not implemented and return 0 when read.

Bit

7 to 1

0

Symbol

Description

-

unused

RAM address, MSB (9^thbit)

RA8

8.5.2 Register RAM_addr_LSB

Table 21. RAM_addr_LSB - RAM address LSB register (address 1Bh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

RA[7:0]

Reset

value

0

Table 22. RAM_addr_LSB - RAM address LSB register (address 1Bh) bit description

Bit

Symbol

Description

7 to 0

RA[7:0]

RAM address, LSB (1^stto 8^thbit)

8.5.3 Register RAM_wrt_cmd

Table 23. RAM_wrt_cmd - RAM write command register (address 1Ch) bit description

Bit

Symbol

Description

7 to 0

-

data to be written into RAM

8.5.4 Register RAM_rd_cmd

Table 24. RAM_rd_cmd - RAM read command register (address 1Dh) bit description

Bit

Symbol

Description

7 to 0

-

data to be read from RAM

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8.5.5 Operation examples

8.5.5.1 Writing to the RAM

1. Set RAM address:

– Select register RAM_addr_MSB (send address 1Ah).

– Set value for bit RA8 (data byte of register 1Ah).

Note: register address will be incremented automatically to 1Bh.

– Set value for array RA[7:0] (data byte of register 1Bh).

2. Send RAM write command:

– Select register RAM_wrt_cmd (send address 1Ch).

3. Write data into the RAM:

– Write n data byte into RAM.

For details, see Figure 46 on page 69.

8.5.5.2 Reading from the RAM

1. Set RAM address:

– Select register RAM_addr_MSB (send address 1Ah).

– Set value for bit RA8 (data byte of register 1Ah).

Note: register address will be incremented automatically to 1Bh.

– Set value for array RA[7:0] (data byte of register 1Bh).

2. Send RAM read command:

– Select register RAM_rd_cmd (send address 1Dh).

3. Read from the RAM:

– Read n data byte from the RAM.

For details, see Figure 47 on page 70.

8.6 Power management functions

The PCF2127 has two power supplies:

V_DD— the main power supply

V_BAT— the battery backup supply

Internally, the PCF2127 is operating with the internal operating voltage V_oper(int)which is

also available as V_BBSon the battery backed output voltage pin, BBS. Depending on the

condition of the main power supply and the selected power management function,

V

_oper(int)is either on the potential of V_DDor V_BAT(see Section 8.6.4).

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Three power management functions are implemented:

Battery switch-over function. monitoring the main power supply V_DDand switching to

_BATin case a power fail condition is detected (see Section 8.6.1).

V

Battery low detection function. monitoring the status of the battery, V_BAT(see

Section 8.6.2).

Extra power fail detection function. monitoring the voltage at the power fail input pin,

PFI (see Section 8.6.3).

The power management functions are controlled by the control bits PWRMNG[2:0] (see

Table 25) in register Control_3 (see Table 11):

Table 25. Power management control bit description

PWRMNG[2:0]

Function

[1]

000

battery switch-over function is enabled in standard mode;

battery low detection function is enabled;

extra power fail detection function is enabled

battery switch-over function is enabled in standard mode;

battery low detection function is disabled;

001

010

011

100

101

110

extra power fail detection function is enabled

battery switch-over function is enabled in standard mode;

battery low detection function is disabled;

extra power fail detection function is disabled

battery switch-over function is enabled in direct switching mode;

battery low detection function is enabled;

extra power fail detection function is enabled

battery switch-over function is enabled in direct switching mode;

battery low detection function is disabled;

extra power fail detection function is enabled

battery switch-over function is enabled in direct switching mode;

battery low detection function is disabled;

extra power fail detection function is disabled

[2]

battery switch-over function is disabled - only one power supply

(V_DD);

battery low detection function is disabled;

extra power fail detection function is enabled

111

battery switch-over function is disabled - only one power supply

(V_DD);

battery low detection function is disabled;

extra power fail detection function is disabled

[1] Default value.

[2] When the battery switch-over function is disabled, the PCF2127 works only with the power supply V_DD

.

V_BATmust be put to ground and the battery low detection function is disabled.

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8.6.1 Battery switch-over function

The PCF2127 has a backup battery switch-over circuit which monitors the main power

supply V_DD. When a power failure condition is detected, it automatically switches to the

backup battery.

One of two operation modes can be selected:

Standard mode — the power failure condition happens when:

V_DD< V_BATAND V_DD< V_th(sw)bat

V_th(sw)batis the battery switch threshold voltage. Typical value is 2.5 V. The battery

switch-over in standard mode works only for V_DD> 2.5 V

Direct switching mode — the power failure condition happens when V_DD< V_BAT. Direct

switching from V_DDto V_BATwithout requiring V_DDto drop below V_th(sw)bat

When a power failure condition occurs and the power supply switches to the battery, the

following sequence occurs:

1. The battery switch flag BF (register Control_3) is set logic 1.

2. An interrupt is generated if the control bit BIE (register Control_3) is enabled

(see Section 8.13.7).

3. If the control bit BTSE (register Control_3) is logic 1, the timestamp registers store the

time and date when the battery switch occurred (see Section 8.12.4).

4. The battery switch flag BF is cleared by command; it must be cleared to clear the

interrupt.

The interface is disabled in battery backup operation:

• Interface inputs are not recognized, preventing extraneous data being written to the

device

• Interface outputs are high-impedance

For further information about I²C-bus communication and battery backup operation, see

Section 9.3 on page 70.

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8.6.1.1 Standard mode

If V_DD> V_BATOR V_DD> V_th(sw)bat: V_oper(int)is at V_DDpotential.

If V_DD< V_BATAND V_DD< V_th(sw)bat: V_oper(int)is at V_BATpotential.

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V_th(sw)batis the battery switch threshold voltage. Typical value is 2.5 V. In standard mode, the

battery switch-over works only for V_DD> 2.5 V.

V_DDmay be lower than V_BAT(for example V_DD= 3 V, V_BAT= 4.1 V).

Fig 6. Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled)

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8.6.1.2 Direct switching mode

If V_DD> V_BAT: V_oper(int)is at V_DDpotential.

If V_DD< V_BAT: V_oper(int)is at V_BATpotential.

The direct switching mode is useful in systems where V_DDis always higher than V_BAT

.

This mode is not recommended if the V_DDand V_BATvalues are similar (for example,

V_DD= 3.3 V, V_BAT 3.0 V). In direct switching mode, the power consumption is reduced

compared to the standard mode because the monitoring of V_DDand V_th(sw)batis not

performed.

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Fig 7. Battery switch-over behavior in direct switching mode with bit BIE set logic 1

(enabled)

8.6.1.3 Battery switch-over disabled: only one power supply (V_DD

)

When the battery switch-over function is disabled:

• The power supply is applied on the V_DDpin

• The V_BATpin must be connected to ground

• V_oper(int)is at V_DDpotential

• The battery flag (BF) is always logic 0

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8.6.1.4 Battery switch-over architecture

The architecture of the battery switch-over circuit is shown in Figure 8.

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Fig 8. Battery switch-over circuit, simplified block diagram

V_oper(int)is at V_DDor V_BATpotential.

Remark: It has to be assured that there are decoupling capacitors on the pins V_DD, V_BAT

,

and BBS.

8.6.2 Battery low detection function

The PCF2127 has a battery low detection circuit which monitors the status of the battery

V_BAT

.

When V_BATdrops below the threshold value V_th(bat)low(typically 2.5 V), the BLF flag

(register Control_3) is set to indicate that the battery is low and that it must be replaced.

Monitoring of the battery voltage also occurs during battery operation.

An unreliable battery cannot prevent that the supply voltage drops below V_low(typical

1.2 V) and with that the data integrity gets lost. (For further information about V_lowsee

Section 8.7.)

When V_BATdrops below the threshold value V_th(bat)low, the following sequence occurs (see

Figure 9):

1. The battery low flag BLF is set logic 1.

2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled

(see Section 8.13.8).

3. The flag BLF remains logic 1 until the battery is replaced. BLF cannot be cleared by

command. It is automatically cleared by the battery low detection circuit when the

battery is replaced or when the voltage rises again above the threshold value. This

could happen if a super capacitor is used as a backup source and the main power is

applied again.

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Fig 9. Battery low detection behavior with bit BLIE set logic 1 (enabled)

8.6.3 Extra power fail detection function

The PCF2127 has an extra power fail detection circuit which compares the voltage at the

power fail input pin PFI to an internal reference voltage equal to 1.25 V.

If V_PFI< 1.25 V, the power fail output PFO is driven LOW. PFO is an open-drain, active

LOW output which requires an external pull-up resistor in any application.

The extra power fail detection function is typically used as a low voltage detection for the

main power supply V_DD(see Figure 10).

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Usually R1 and R2 should be chosen such that the voltage at pin PFI

• is higher than 1.25 V at start-up

• falls below 1.25 V when V_DDfalls below a desired threshold voltage, V_th(uvp), defined

by Equation 1:

R₁







V_thuvp

=

+ 1  1.25V

(1)

-----



R₂

V

_th(uvp)value is usually set to a value that there are several milliseconds before V_DDfalls

below the minimum operating voltage of the system, in order to allow the microcontroller

to perform early backup operations, like terminating the communication with the

PCF2127.

The value of C is determined from Equation 2:

0.02 As

R₁//R₂ V

-------------------- -----

C =

(2)

If the extra power fail detection function is not used, pin PFI must be connected to V_SSand

pin PFO must be left open circuit.

8.6.3.1 Extra power fail detection when the battery switch-over function is enabled

• When the power switches to the backup battery supply V_BAT, the power fail

comparator is switched off and the power fail output at pin PFO goes (or remains)

LOW

• When the power switches back to the main V_DD, the pin PFO is not driven LOW

anymore. It is pulled HIGH through the external pull-up resistance for a certain time

(t_rec= 15.63 ms to 31.25 ms). Then the power fail comparator is enabled again

For illustration, see Figure 11 and Figure 12.

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V_th(uvp)> (V_BAT, V_th(sw)bat

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mode and V_th(uvp)< V_BAT

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8.6.3.2 Extra power fail detection when the battery switch-over function is disabled

If the battery switch-over function is disabled and the power fail comparator is enabled,

the power fail output at pin PFO depends only on the result of the comparison between

V

_PFIand 1.25 V:

• If V_PFI> 1.25 V, PFO = HIGH (through the external pull-up resistor)

• If V_PFI< 1.25 V, PFO = LOW

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8.6.4 Battery backup supply

The V_BBSvoltage on the output pin BBS is at the same potential as the internal operating

voltage V_oper(int), depending on the selected battery switch-over function mode:

Table 26. Output pin BBS

Battery switch-over function Conditions

mode

Potential of

V_oper(int)and

V_BBS

standard

V_DD> V_BATOR V_DD> V_th(sw)bat

V_DD

V_BAT

V_DD

V_BAT

V_DD

V_DD< V_BATAND V_DD< V_th(sw)bat

V_DD> V_BAT

direct switching

disabled

V_DD< V_BAT

only V_DDavailable,

V_BATmust be put to ground

The output pin BBS can be used as a supply for external devices with battery backup

needs, such as SRAM (see Ref. 3 “AN11266”). For this case, Figure 14 shows the typical

driving capability when V_BBSis driven from V_DD

.

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Fig 14. Typical driving capability of V_BBS: (V_BBS V_DD) with respect to the output load

current I_BBS

8.7 Oscillator stop detection function

The PCF2127 has an on-chip oscillator detection circuit which monitors the status of the

oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag OSF

(in register Seconds) is set logic 1.

• Power-on:

a. The oscillator is not running, the chip is in reset (OSF is logic 1).

b. When the oscillator starts running and is stable after power-on, the chip exits from

reset.

c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command.

• Power supply failure:

a. When the power supply of the chip drops below a certain value (V_low), typically

1.2 V, the oscillator stops running and a reset occurs.

b. When the power supply returns to normal operation, the oscillator starts running

again, the chip exits from reset.

c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command.

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(1) Theoretical state of the signals since there is no power.

(2) The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a reset has

occurred since the flag was last cleared (OSF set logic 0). In this case, the integrity of the clock

information is not guaranteed. The OSF flag is cleared by command.

Fig 15. Power failure event due to battery discharge: reset occurs

8.8 Reset function

The PCF2127 has a Power-On Reset (POR) and a Power-On Reset Override (PORO)

function implemented.

8.8.1 Power-On Reset (POR)

The POR is active whenever the oscillator is stopped. The oscillator is considered to be

stopped during the time between power-on and stable crystal resonance (see Figure 16).

This time may be in the range of 200 ms to 2 s depending on temperature and supply

voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set

logic 1).

The OTP refresh (see Section 8.3.2 on page 13) should ideally be executed as the first

instruction after start-up and also after a reset due to an oscillator stop.

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After POR, the following mode is entered:

• 32.768 kHz CLKOUT active

• Power-On Reset Override (PORO) available to be set

• 24-hour mode is selected

• Battery switch-over is enabled

• Battery low detection is enabled

• Extra power fail detection is enabled

The register values after power-on are shown in Table 5 on page 8.

8.8.2 Power-On Reset Override (PORO)

The POR duration is directly related to the crystal oscillator start-up time. Due to the long

start-up times experienced by these types of circuits, a mechanism has been built in to

disable the POR and therefore speed up the on-board test of the device.

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Fig 17. Power-On Reset (POR) system

The setting of the PORO mode requires that POR_OVRD in register Control_1 is set

logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as

illustrated in Figure 18. All timings shown are required minimum.

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Product data sheet

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PCF2127

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Fig 18. Power-On Reset Override (PORO) sequence, valid for both I²C-bus and SPI-bus

Once the override mode is entered, the device is immediately released from the reset

state and the set-up operation can commence.

The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be

logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0

during normal operation has no effect except to prevent accidental entry into the PORO

mode.

8.9 Time and date function

Most of these registers are coded in the Binary Coded Decimal (BCD) format.

8.9.1 Register Seconds

Table 27. Seconds - seconds and clock integrity register (address 03h) bit allocation

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

7

OSF

1

6

5

4

3

2

1

0

Symbol

SECONDS (0 to 59)

X

Reset

value

X

Table 28. Seconds - seconds and clock integrity register (address 03h) bit description

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

Symbol

Value

Place value Description

7

OSF

0

1

-

clock integrity is guaranteed

clock integrity is not guaranteed:

oscillator has stopped and chip reset has occurred

since flag was last cleared

6 to 4

3 to 0

SECONDS

0 to 5

0 to 9

ten’s place actual seconds coded in BCD format

unit place

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Table 29. Seconds coded in BCD format

Seconds Upper-digit (ten’s place)

Digit (unit place)

value in

decimal

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00

01

02

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

09

10

:

0

:

0

:

0

1

:

1

0

:

0

:

0

:

1

0

:

58

59

1

0

1

0

1

8.9.2 Register Minutes

Table 30. Minutes - minutes register (address 04h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

-

6

5

4

3

2

1

0

Symbol

MINUTES (0 to 59)

X

Reset

value

-

X

Table 31. Minutes - minutes register (address 04h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

-

Value

-

Place value Description

unused

7

-

6 to 4

3 to 0

MINUTES

0 to 5

0 to 9

ten’s place actual minutes coded in BCD format

unit place

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8.9.3 Register Hours

Table 32. Hours - hours register (address 05h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

6

5

4

3

2

1

0

Symbol

-

AMPM

HOURS (1 to 12) in 12-hour mode

HOURS (0 to 23) in 24-hour mode

Reset

value

-

X

Table 33. Hours - hours register (address 05h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

Place value Description

7 to 6

-

unused

12-hour mode^[1]

5

AMPM

0

-

indicates AM

indicates PM

1

4

HOURS

0 to 1

0 to 9

ten’s place actual hours coded in BCD format when in 12-hour

mode

3 to 0

unit place

24-hour mode^[1]

5 to 4

3 to 0

HOURS

0 to 2

0 to 9

ten’s place actual hours coded in BCD format when in 24-hour

mode

unit place

[1] Hour mode is set by the bit 12_24 in register Control_1 (see Table 7).

8.9.4 Register Days

Table 34. Days - days register (address 06h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

-

6

-

5

4

3

2

1

0

Symbol

DAYS (1 to 31)

Reset

value

-

X

Table 35. Days - days register (address 06h) bit description

Bit

Symbol

Value

-

Place value Description

- unused

7 to 6

5 to 4

3 to 0

-

DAYS^[1]

0 to 3

0 to 9

ten’s place actual day coded in BCD format

unit place

[1] If the year counter contains a value which is exactly divisible by 4, including the year 00, the RTC compensates for leap years by adding

a 29^thday to February.

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8.9.5 Register Weekdays

Table 36. Weekdays - weekdays register (address 07h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

-

6

-

5

-

4

-

3

-

2

1

0

Symbol

WEEKDAYS (0 to 6)

X

Reset

value

-

X

Table 37. Weekdays - weekdays register (address 07h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

-

Description

7 to 3

2 to 0

-

unused

WEEKDAYS

0 to 6

actual weekday value, see Table 38

Although the association of the weekdays counter to the actual weekday is arbitrary, the

PCF2127 assumes that Sunday is 000 and Monday is 001 for the purpose of determining

the increment for calendar weeks.

Table 38. Weekday assignments

Day^[1]

Bit

2

1

0

1

0

1

0

1

0

1

0

1

0

Sunday

0

Monday

Tuesday

Wednesday

Thursday

Friday

0

1

Saturday

1

[1] Definition may be reassigned by the user.

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8.9.6 Register Months

Table 39. Months - months register (address 08h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

-

6

-

5

-

4

3

2

1

0

Symbol

MONTHS (1 to 12)

X

Reset

value

-

X

Table 40. Months - months register (address 08h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

-

Value

-

Place value Description

- unused

7 to 5

4

MONTHS

0 to 1

0 to 9

ten’s place actual month coded in BCD format, see Table 41

unit place

3 to 0

Table 41. Month assignments in BCD format

Month

Upper-digit

(ten’s place)

Digit (unit place)

Bit 4

0

Bit 3

0

Bit 2

Bit 1

0

Bit 0

1

January

February

March

0

1

0

1

0

1

April

0

May

0

1

June

0

1

0

July

0

1

August

September

October

November

December

0

1

0

1

0

1

0

1

0

1

0

1

0

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8.9.7 Register Years

Table 42. Years - years register (address 09h) bit allocation

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

7

6

5

4

3

2

1

0

Symbol

YEARS (0 to 99)

Reset

value

X

Table 43. Years - years register (address 09h) bit description

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

Symbol

Value

0 to 9

Place value Description

7 to 4

3 to 0

YEARS

ten’s place actual year coded in BCD format

unit place

8.9.8 Setting and reading the time

Figure 19 shows the data flow and data dependencies starting from the 1 Hz clock tick.

During read/write operations, the time counting circuits (memory locations 03h through

09h) are blocked.

This prevents

• Faulty reading of the clock and calendar during a carry condition

• Incrementing the time registers during the read cycle

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Fig 19. Data flow of the time function

After this read/write access is completed, the time circuit is released again. Any pending

request to increment the time counters that occurred during the read/write access is

serviced. A maximum of 1 request can be stored; therefore, all accesses must be

completed within 1 second (see Figure 20).

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Fig 20. Access time for read/write operations

As a consequence of this method, it is very important to make a read or write access in

one go. That is, setting or reading seconds through to years should be made in one single

access. Failing to comply with this method could result in the time becoming corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in a

second access the date is set, it is possible that the time may increment between the two

accesses. A similar problem exists when reading. A roll-over may occur between reads

thus giving the minutes from one moment and the hours from the next. Therefore it is

advised to read all time and date registers in one access.

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8.10 Alarm function

When one or more of the alarm bit fields are loaded with a valid second, minute, hour, day,

or weekday and its corresponding alarm enable bit (AE_x) is logic 0, then that information

is compared with the actual second, minute, hour, day, and weekday (see Figure 21).

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(1) Only when all enabled alarm settings are matching.

Fig 21. Alarm function block diagram

The generation of interrupts from the alarm function is described in Section 8.13.5.

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8.10.1 Register Second_alarm

Table 44. Second_alarm - second alarm register (address 0Ah) bit allocation

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

7

AE_S

1

6

5

4

3

2

1

0

Symbol

SECOND_ALARM (0 to 59)

Reset

value

X

Table 45. Second_alarm - second alarm register (address 0Ah) bit description

Bit

Symbol

Value

0

Place value Description

7

AE_S

-

second alarm is enabled

second alarm is disabled

1

6 to 4

3 to 0

SECOND_ALARM

0 to 5

0 to 9

ten’s place second alarm information coded in BCD format

unit place

8.10.2 Register Minute_alarm

Table 46. Minute_alarm - minute alarm register (address 0Bh) bit allocation

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

7

AE_M

1

6

5

4

3

2

1

0

Symbol

MINUTE_ALARM (0 to 59)

Reset

value

X

Table 47. Minute_alarm - minute alarm register (address 0Bh) bit description

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

Symbol

Value

0

Place value Description

7

AE_M

-

minute alarm is enabled

minute alarm is disabled

1

6 to 4

3 to 0

MINUTE_ALARM

0 to 5

0 to 9

ten’s place minute alarm information coded in BCD format

unit place

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8.10.3 Register Hour_alarm

Table 48. Hour_alarm - hour alarm register (address 0Ch) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

6

5

4

3

2

1

0

Symbol

AE_H

-

AMPM

HOUR_ALARM (1 to 12) in 12-hour mode

HOUR_ALARM (0 to 23) in 24-hour mode

Reset

value

1

-

X

Table 49. Hour_alarm - hour alarm register (address 0Ch) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

Place value Description

7

AE_H

0

1

-

hour alarm is enabled

hour alarm is disabled

unused

6

-

12-hour mode^[1]

5

AMPM

0

-

indicates AM

indicates PM

1

4

HOUR_ALARM

0 to 1

0 to 9

ten’s place hour alarm information coded in BCD format when in

12-hour mode

3 to 0

unit place

24-hour mode^[1]

5 to 4

3 to 0

HOUR_ALARM

0 to 2

0 to 9

ten’s place hour alarm information coded in BCD format when in

24-hour mode

unit place

[1] Hour mode is set by the bit 12_24 in register Control_1.

8.10.4 Register Day_alarm

Table 50. Day_alarm - day alarm register (address 0Dh) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

AE_D

1

6

-

5

4

3

2

1

0

Symbol

DAY_ALARM (1 to 31)

Reset

value

-

X

Table 51. Day_alarm - day alarm register (address 0Dh) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

Place value Description

7

AE_D

0

-

day alarm is enabled

1

day alarm is disabled

unused

6

-

5 to 4

3 to 0

DAY_ALARM

0 to 3

0 to 9

ten’s place day alarm information coded in BCD format

unit place

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8.10.5 Register Weekday_alarm

Table 52. Weekday_alarm - weekday alarm register (address 0Eh) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

AE_W

1

6

-

5

-

4

-

3

-

2

1

0

Symbol

WEEKDAY_ALARM (0 to 6)

Reset

value

-

X

Table 53. Weekday_alarm - weekday alarm register (address 0Eh) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

Description

7

AE_W

0

weekday alarm is enabled

weekday alarm is disabled

unused

1

6 to 3

2 to 0

-

WEEKDAY_ALARM

0 to 6

weekday alarm information

8.10.6 Alarm flag

When all enabled comparisons first match, the alarm flag AF (register Control_2) is set.

AF remains set until cleared by command. Once AF has been cleared, it will only be set

again when the time increments to match the alarm condition once more. For clearing the

flags, see Section 8.11.6

Alarm registers which have their alarm enable bit AE_x at logic 1 are ignored.

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Example where only the minute alarm is used and no other interrupts are enabled.

Fig 22. Alarm flag timing diagram

8.11 Timer functions

The PCF2127 has two different timer functions, a watchdog timer and a countdown timer.

The timers can be selected by using the control bits WD_CD[1:0] in the register

Watchdg_tim_ctl.

• The watchdog timer has four selectable source clocks. It can, for example, be used to

detect a microcontroller with interrupt and reset capability which is out of control (see

Section 8.11.3)

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• The countdown timer has four selectable source clocks allowing for countdown

periods from less than 1 ms to more than 4 hours (see Section 8.11.4)

To control the timer functions and timer output, the registers Control_2, Watchdg_tim_ctl,

and Watchdg_tim_val are used.

8.11.1 Register Watchdg_tim_ctl

Table 54. Watchdg_tim_ctl - watchdog timer control register (address 10h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read.

Bit

7

6

5

TI_TP

0

4

-

3

-

2

-

1

0

Symbol

WD_CD[1:0]

TF[1:0]

Reset

value

0

-

1

Table 55. Watchdg_tim_ctl - watchdog timer control register (address 10h) bit description

Bit positions labeled as - are not implemented and return 0 when read.

Bit

Symbol

Value

Description

7 to 6

WD_CD[1:0]

00

Watchdog timer disabled;

countdown timer disabled

01

watchdog timer disabled;

countdown timer enabled

if CDTIE is set logic 1, the interrupt pin INT is

activated when the countdown timed out

10

11

watchdog timer enabled;

the interrupt pin INT is activated when timed out;

countdown timer not available

watchdog timer enabled;

the reset pin RST is activated when timed out;

countdown timer not available

5

TI_TP

0

1

-

the interrupt pin INT is configured to generate a

permanent active signal when MSF and/or CDTF is

set

the interrupt pin INT is configured to generate a

pulsed signal when MSF flag and/or CDTF flag is set

(see Figure 27)

4 to 2

1 to 0

-

unused

TF[1:0]

timer source clock for watchdog and countdown timer

00

01

10

11

4.096 kHz

64 Hz

1 Hz

1

⁄₆₀Hz

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8.11.2 Register Watchdg_tim_val

Table 56. Watchdg_tim_val - watchdog timer value register (address 11h) bit allocation

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

7

6

5

4

3

2

1

0

Symbol

WATCHDG_TIM_VAL[7:0]

Reset

value

X

Table 57. Watchdg_tim_val - watchdog timer value register (address 11h) bit description

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

Symbol

Value

Description

7 to 0

WATCHDG_TIM_

VAL[7:0]

00 to FF

timer period in seconds:

n

TimerPeriod =

--------------------------------------------------------------

SourceClockFrequency

where n is the timer value

Table 58. Programmable watchdog timer

TF[1:0] Timer source

clock frequency

Units

Minimum timer

period (n = 1)

Units

Maximum timer

period (n = 255)

Units

00

01

10

11

4.096

64

kHz

Hz

244

15.625

1

s

ms

s

62.256

3.984

255

ms

s

1

Hz

s

1

⁄

Hz

60

s

15300

s

60

8.11.3 Watchdog timer function

The watchdog timer function is enabled or disabled by the WD_CD[1:0] bits of the register

Watchdg_tim_ctl (see Table 55).

The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock

frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or ¹⁄₆₀Hz (see Table 58).

When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val

determines the watchdog timer period (see Table 58).

The watchdog timer counts down from the software programmed 8-bit binary value n in

register Watchdg_tim_val. When the counter reaches 1, the watchdog timer flag WDTF

(register Control_2) is set logic 1.

If WDTF is logic 1 and:

• if WD_CD[1:0] = 10 an interrupt will be generated

• if WD_CD[1:0] = 11 a reset will be generated

The counter does not automatically reload.

When WD_CD[1:0] = 10 or WD_CD[1:0] = 11 and the Microcontroller Unit (MCU) loads a

watchdog timer value n:

• the flag WDTF is reset

• INT or RST is cleared

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• the watchdog timer starts again

Loading the counter with 0 will:

• reset the flag WDTF

• clear INT or RST

• stop the watchdog timer

Remark: WDTF is read only and cannot be cleared by command. WDTF can be cleared

by:

• loading a value in register Watchdg_tim_val

• reading of the register Control_2

Writing a logic 0 or logic 1 to WDTF has no effect.

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Counter reached 1, WDTF is logic 1, and an interrupt is generated.

Fig 23. WD_CD[1:0] = 10: watchdog activates an interrupt when timed out

• When the watchdog timer counter reaches 1, the watchdog timer flag WDTF is set

logic 1

• When a minute or second interrupt occurs, the minute/second flag MSF is set logic 1

(see Section 8.13.1)

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to t_w(rst)

.

Fig 24. WD_CD[1:0] = 11: watchdog activates a reset pulse when timed out

Table 59. Specification of t_w(rst)

WD_CD[1:0]

TF[1:0]

00

t_w(rst)

11

244 s

01

15.625 ms

10

11

8.11.4 Countdown timer function

The countdown timer function is controlled by the WD_CD[1:0] bits in register

Watchdg_tim_ctl (see Table 55).

The timer counts down from the software programmed 8-bit binary value n in register

Watchdg_tim_val. When the counter reaches 1

• the countdown timer flag CDTF is set

• the counter automatically reloads

• and the next time period starts

Loading the counter with 0 effectively stops the timer.

Reading the timer returns the actual value of the countdown counter.

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In this example, it is assumed that the countdown timer flag (CDTF) is cleared before the next

countdown period expires and that INT is set to pulsed mode.

Fig 25. General countdown timer behavior

If a new value of n is written before the end of the actual timer period, this value takes

immediate effect. It is not recommended to change n without first disabling the counter by

setting WD_CD[1:0] = 00. The update of n is asynchronous to the timer clock. Therefore

changing it on the fly could result in a corrupted value loaded into the countdown counter.

This can result in an undetermined countdown period for the first period. The countdown

value n will, however, be correctly stored and correctly loaded on subsequent timer

periods.

If this mode is enabled and the countdown timer flag CDTF is set, an interrupt signal on

INT will be generated. See Section 8.13.2 for details on how the interrupt can be

controlled.

When starting the countdown timer for the first time, only the first period will not have a

fixed duration. The amount of inaccuracy for the first timer period depends on the chosen

source clock, see Table 60.

Table 60. First period delay for timer counter

Timer source clock

4.096 kHz

Minimum timer period

Maximum timer period

n

n + 1

64 Hz

n

n + 1

1 Hz

(n  1) + ¹⁄_{64 Hz}

n + ¹⁄_{64 Hz}

1

⁄₆₀Hz

At the end of every countdown, the timer sets the countdown timer flag (CDTF). CDTF

may only be cleared by command. The asserted CDTF can be used to generate an

interrupt (INT). The interrupt may be generated as a pulsed signal every countdown

period or as a permanently active signal which follows the condition of CDTF. TI_TP is

used to control this mode selection. The interrupt output may be disabled with the CDTIE

bit, see Table 9.

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When reading the timer, the actual countdown value is returned and not the initial value n.

Since it is not possible to freeze the countdown timer counter during read back, it is

recommended to read the register twice and check for consistent results.

8.11.5 Pre-defined timers: second and minute interrupt

PCF2127 has two pre-defined timers which are used to generate an interrupt either once

per second or once per minute (see Section 8.13.1). The pulse generator for the minute or

second interrupt operates from an internal 64 Hz clock. It is independent of the watchdog

or countdown timers. Each of these timers can be enabled by the bits SI (second interrupt)

and MI (minute interrupt) in register Control_1.

8.11.6 Clearing flags

The flags MSF, CDTF, AF and TSFx can be cleared by command. To prevent one flag

being overwritten while clearing another, a logic AND is performed during the write

access. A flag is cleared by writing logic 0 while a flag is not cleared by writing logic 1.

Writing logic 1 results in the flag value remaining unchanged.

Four examples are given for clearing the flags. Clearing the flags is made by a write

command:

• Bits labeled with - must be written with their previous values

• WDTF is read only and has to be written with logic 0

Repeatedly rewriting these bits has no influence on the functional behavior.

Table 61. Flag location in register Control_2

Register

Bit

7

6

5

4

3

2

1

0

Control_2

MSF

WDTF

TSF2

AF

CDTF

-

Table 62. Example values in register Control_2

Register

Bit

7

6

5

4

3

2

1

0

Control_2

1

0

1

0

The following tables show what instruction must be sent to clear the appropriate flag.

Table 63. Example to clear only CDTF (bit 3)

Register

Bit

7

6

5

4

3

2

1

0

[1]

Control_2

1

0

1

0

-

[1] The bits labeled as - have to be rewritten with the previous values.

Table 64. Example to clear only AF (bit 4)

Register

Bit

7

6

5

4

3

2

1

0

Control_2

1

0

1

0

1

0^[1]

[1] The bits labeled as - have to be rewritten with the previous values.

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Table 65. Example to clear only MSF (bit 7)

Register

Bit

7

6

5

4

3

2

1

0

Control_2

0

1

0^[1]

[1] The bits labeled as - have to be rewritten with the previous values.

Table 66. Example to clear both CDTF and MSF

Register

Bit

7

6

5

4

3

2

1

0

Control_2

0

1

0

0^[1]

[1] The bits labeled as - have to be rewritten with the previous values.

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8.12 Timestamp function

The PCF2127 has an active LOW timestamp input pin TS, internally pulled with an

on-chip pull-up resistor to V_oper(int). It also has a timestamp detection circuit which can

detect two different events:

1. Input on pin TS is driven to an intermediate level between power supply and ground.

2. Input on pin TS is driven to ground.

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(1) When using switches or push-buttons, it is recommended to connect a 1 nF capacitance to the TS

pin to ensure proper switching.

Fig 26. Timestamp detection with two push-buttons on the TS pin (for example, for

tamper detection)

The timestamp function is enabled by default after power-on and it can be switched off by

setting the control bit TSOFF (register Timestp_ctl).

A most common application of the timestamp function is described in Ref. 3 “AN11266”.

See Section 8.13.6 for a description of interrupt generation from the timestamp function.

8.12.1 Timestamp flag

1. When the TS input pin is driven to an intermediate level between the power supply

and ground, either on the falling edge from V_DDor on the rising edge from ground,

then the following sequence occurs:

a. The actual date and time are stored in the timestamp registers.

b. The timestamp flag TSF1 (register Control_1) is set.

c. If the TSIE bit (register Control_2) is active, an interrupt on the INT pin is

generated.

The TSF1 flag can be cleared by command. Clearing the flag clears the interrupt.

Once TSF1 is cleared, it will only be set again when a new negative or positive edge

on pin TS is detected.

2. When the TS input pin is driven to ground, the following sequence occurs:

a. The actual date and time are stored in the timestamp registers.

b. In addition to the TSF1 flag, the TSF2 flag (register Control_2) is set.

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c. If the TSIE bit is active, an interrupt on the INT pin is generated.

The TSF1 and TSF2 flags can be cleared by command; clearing both flags clears the

interrupt. Once TSF2 is cleared, it will only be set again when TS pin is driven to

ground once again.

8.12.2 Timestamp mode

The timestamp function has two different modes selected by the control bit TSM

(timestamp mode) in register Timestp_ctl:

• If TSM is logic 0 (default): in subsequent trigger events without clearing the timestamp

flags, the last timestamp event is stored

• If TSM is logic 1: in subsequent trigger events without clearing the timestamp flags,

the first timestamp event is stored

The timestamp function also depends on the control bit BTSE in register Control_3, see

Section 8.12.4.

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8.12.3 Timestamp registers

8.12.3.1 Register Timestp_ctl

Table 67. Timestp_ctl - timestamp control register (address 12h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

TSM

0

6

TSOFF

0

5

-

4

3

2

1

0

Symbol

1_O_16_TIMESTP[4:0]

X

Reset

value

-

X

Table 68. Timestp_ctl - timestamp control register (address 12h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

Description

7

TSM

0

in subsequent events without clearing the timestamp

flags, the last event is stored

1

in subsequent events without clearing the timestamp

flags, the first event is stored

6

TSOFF

0

1

-

timestamp function active

timestamp function disabled

5

-

unused

1

4 to 0

1_O_16_TIMESTP[4:0]

⁄₁₆second timestamp information coded in BCD

format

8.12.3.2 Register Sec_timestp

Table 69. Sec_timestp - second timestamp register (address 13h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

-

6

5

4

3

2

1

0

Symbol

SECOND_TIMESTP (0 to 59)

Reset

value

-

X

Table 70. Sec_timestp - second timestamp register (address 13h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

-

Place value Description

unused

7

-

6 to 4

3 to 0

SECOND_TIMESTP

0 to 5

0 to 9

ten’s place second timestamp information coded in BCD format

unit place

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8.12.3.3 Register Min_timestp

Table 71. Min_timestp - minute timestamp register (address 14h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

-

6

5

4

3

2

1

0

Symbol

MINUTE_TIMESTP (0 to 59)

Reset

value

-

X

Table 72. Min_timestp - minute timestamp register (address 14h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

-

Place value Description

unused

7

-

6 to 4

3 to 0

MINUTE_TIMESTP

0 to 5

0 to 9

ten’s place minute timestamp information coded in BCD format

unit place

8.12.3.4 Register Hour_timestp

Table 73. Hour_timestp - hour timestamp register (address 15h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

6

5

4

3

2

1

0

Symbol

-

AMPM

HOUR_TIMESTP (1 to 12) in 12-hour mode

HOUR_TIMESTP (0 to 23) in 24-hour mode

Reset

value

-

X

Table 74. Hour_timestp - hour timestamp register (address 15h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

Place value Description

7 to 6

-

unused

12-hour mode^[1]

5

AMPM

0

-

indicates AM

indicates PM

1

4

HOUR_TIMESTP

0 to 1

0 to 9

ten’s place hour timestamp information coded in BCD format

when in 12-hour mode

3 to 0

unit place

24-hour mode^[1]

5 to 4

3 to 0

HOUR_TIMESTP

0 to 2

0 to 9

ten’s place hour timestamp information coded in BCD format

when in 24-hour mode

unit place

[1] Hour mode is set by the bit 12_24 in register Control_1.

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8.12.3.5 Register Day_timestp

Table 75. Day_timestp - day timestamp register (address 16h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

-

6

-

5

4

3

2

1

0

Symbol

DAY_TIMESTP (1 to 31)

Reset

value

-

X

Table 76. Day_timestp - day timestamp register (address 16h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

-

Place value Description

- unused

7 to 6

5 to 4

3 to 0

-

DAY_TIMESTP

0 to 3

0 to 9

ten’s place day timestamp information coded in BCD format

unit place

8.12.3.6 Register Mon_timestp

Table 77. Mon_timestp - month timestamp register (address 17h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

-

6

-

5

-

4

3

2

1

0

Symbol

MONTH_TIMESTP (1 to 12)

Reset

value

-

X

Table 78. Mon_timestp - month timestamp register (address 17h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

-

Place value Description

- unused

7 to 5

4

-

MONTH_TIMESTP

0 to 1

0 to 9

ten’s place month timestamp information coded in BCD format

unit place

3 to 0

8.12.3.7 Register Year_timestp

Table 79. Year_timestp - year timestamp register (address 18h) bit allocation

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

7

6

5

4

3

2

1

0

Symbol

YEAR_TIMESTP (0 to 99)

Reset

value

X

Table 80. Year_timestp - year timestamp register (address 18h) bit description

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

Symbol

Value

0 to 9

Place value Description

7 to 4

3 to 0

YEAR_TIMESTP

ten’s place year timestamp information coded in BCD format

unit place

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8.12.4 Dependency between Battery switch-over and timestamp

The timestamp function depends on the control bit BTSE in register Control_3:

Table 81. Battery switch-over and timestamp

BTSE

BF

Description

[1]

0

-

the battery switch-over does not affect the

timestamp registers

1

If a battery switch-over event occurs:

0

1

the timestamp registers store the time and

date when the switch-over occurs;

after this event occurred BF is set logic 1

the timestamp registers are not modified;

in this condition subsequent battery

switch-over events or falling edges on pin TS

are not registered

[1] Default value.

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8.13 Interrupt output, INT

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When SI, MI, CDTIE, WD_CD[1:0], AIE, TSIE, BIE, BLIE are all disabled, INT remains high-impedance.

Fig 27. Interrupt block diagram

PCF2127 has an interrupt output pin INT which is open-drain, active LOW (requiring a

pull-up resistor if used). Interrupts may be sourced from different places:

• second or minute timer

• countdown timer

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• watchdog timer

• alarm

• timestamp

• battery switch-over

• battery low detection

The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the

interrupts generated from the second/minute timer (flag MSF in register Control_2) and

the countdown timer (flag CDTF in register Control_2) are pulsed signals or a

permanently active signal. All the other interrupt sources generate a permanently active

interrupt signal which follows the status of the corresponding flags. When the interrupt

sources are all disabled, INT remains high-impedance.

• The flags MSF, CDTF, AF, TSFx, and BF can be cleared by command.

• The flag WDTF is read only. How it can be cleared is explained in Section 8.11.6.

• The flag BLF is read only. It is cleared automatically from the battery low detection

circuit when the battery is replaced.

8.13.1 Minute and second interrupts

Minute and second interrupts are generated by predefined timers. The timers can be

enabled independently from one another by the bits MI and SI in register Control_1.

However, a minute interrupt enabled on top of a second interrupt cannot be

distinguishable since it occurs at the same time.

The minute/second flag MSF (register Control_2) is set logic 1 when either the seconds or

the minutes counter increments according to the enabled interrupt (see Table 82). The

MSF flag can be cleared by command.

Table 82. Effect of bits MI and SI on pin INT and bit MSF

MI

0

SI

0

Result on INT

Result on MSF

no interrupt generated

an interrupt once per minute

MSF never set

1

0

MSF set when minutes

counter increments

0

1

an interrupt once per second

MSF set when seconds

counter increments

MSF set when seconds

counter increments

When MSF is set logic 1:

• If TI_TP is logic 1, the interrupt is generated as a pulsed signal.

• If TI_TP is logic 0, the interrupt is permanently active signal that remains until MSF is

cleared.

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Fig 28. INT example for SI and MI when TI_TP is logic 1

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Fig 29. INT example for SI and MI when TI_TP is logic 0

The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock

and generates a pulse of ¹⁄₆₄seconds in duration.

8.13.2 Countdown timer interrupts

The generation of interrupts from the countdown timer is controlled by the CDTIE bit

(register Control_2).

The interrupt may be generated as a pulsed signal at every countdown period or as a

permanently active signal which follows the status of the countdown timer flag CDTF. Bit

TI_TP is used to control this bit.

8.13.3 INT pulse shortening

The pulse generator for the countdown timer interrupt also uses an internal clock, but this

time it is dependent on the selected source clock for the countdown timer and on the

countdown value n. As a consequence, the width of the interrupt pulse varies (see

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Table 83).

Table 83. INT operation (bit TI_TP = 1)

Source clock (Hz)

INT period (s)

n = 1^[1]

n > 1

1

4096

64

⁄

8192

4096

1

⁄

128

64

1

⁄

64

1

⁄

60

64

[1] n = loaded countdown value. Timer stopped when n = 0.

If the MSF or CDTF flag (register Control_2) is cleared before the end of the INT pulse,

then the INT pulse is shortened. This allows the source of a system interrupt to be cleared

immediately when it is serviced, that is, the system does not have to wait for the

completion of the pulse before continuing, see Figure 30 and Figure 31. Instructions for

clearing bit MSF and bit CDTF can be found in Section 8.11.6.

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The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode. That is, when

TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI logic 0.

Fig 30. Example of shortening the INT pulse by clearing the MSF flag

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(1) Indicates normal duration of INT pulse.

The timing shown for clearing CDTF is also valid for the non-pulsed interrupt mode. That is, when

TI_TP is logic 0, where the INT pulse may be shortened by setting CDTIE logic 0.

Fig 31. Example of shortening the INT pulse by clearing the CDTF flag

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8.13.4 Watchdog timer interrupts

The generation of interrupts from the watchdog timer is controlled using the WD_CD[1:0]

bits (register Watchdg_tim_ctl). The interrupt is generated as an active signal which

follows the status of the watchdog timer flag WDTF (register Control_2). No pulse

generation is possible for watchdog timer interrupts.

The interrupt is cleared when the flag WDTF is reset. WDTF is a read-only bit and cannot

be cleared by command. Instructions for clearing it can be found in Section 8.11.6.

8.13.5 Alarm interrupts

Generation of interrupts from the alarm function is controlled by the bit AIE (register

Control_2). If AIE is enabled, the INT pin follows the status of bit AF (register Control_2).

Clearing AF immediately clears INT. No pulse generation is possible for alarm interrupts.

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Example where only the minute alarm is used and no other interrupts are enabled.

Fig 32. AF timing diagram

8.13.6 Timestamp interrupts

Interrupt generation from the timestamp function is controlled using the TSIE bit (register

Control_2). If TSIE is enabled, the INT pin follows the status of the flags TSFx. Clearing

the flags TSFx immediately clears INT. No pulse generation is possible for timestamp

interrupts.

8.13.7 Battery switch-over interrupts

Generation of interrupts from the battery switch-over is controlled by the BIE bit (register

Control_3). If BIE is enabled, the INT pin follows the status of bit BF in register Control_3

(see Table 81). Clearing BF immediately clears INT. No pulse generation is possible for

battery switch-over interrupts.

8.13.8 Battery low detection interrupts

Generation of interrupts from the battery low detection is controlled by the BLIE bit

(register Control_3). If BLIE is enabled, the INT pin follows the status of bit BLF (register

Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0) or when

bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be cleared by

command.

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8.14 External clock test mode

A test mode is available which allows on-board testing. In this mode, it is possible to set

up test conditions and control the operation of the RTC.

The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then

pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz)

with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT

generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided

down by a 2⁶divider chain called prescaler (see Table 84). The prescaler can be set into a

known state by using bit STOP. When bit STOP is logic 1, the prescaler is reset to 0.

STOP must be cleared before the prescaler can operate again.

From a stop condition, the first 1 second increment will take place after 32 positive edges

on pin CLKOUT. Thereafter, every 64 positive edges cause a 1 second increment.

Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When

entering the test mode, no assumption as to the state of the prescaler can be made.

Operating example:

1. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).

2. Set bit STOP (register Control_1, STOP is logic 1).

3. Set time registers to desired value.

4. Clear STOP (register Control_1, STOP is logic 0).

5. Apply 32 clock pulses to CLKOUT.

6. Read time registers to see the first change.

7. Apply 64 clock pulses to CLKOUT.

8. Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

8.15 STOP bit function

The function of the STOP bit is to allow for accurate starting of the time circuits. STOP

causes the upper part of the prescaler (F₉to F₁₄) to be held in reset and thus no 1 Hz ticks

are generated. The time circuits can then be set and will not increment until the STOP bit

is released. STOP doesn't affect the CLKOUT signal but the output of the prescaler in the

range of 32 Hz to 1 Hz (see Figure 33).

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The lower stages of the prescaler, F₀to F₈, are not reset and because the I²C-bus and the

SPI-bus are asynchronous to the crystal oscillator, the accuracy of restarting the time

circuits is between 0 and one 64 Hz cycle (0.484375 s and 0.500000 s), see Table 84 and

Figure 34.

Table 84. First increment of time circuits after stop release

Bit

Prescaler bits^[1]

1 Hz tick

Time

Comment

STOP

F₀to F₈- F₉to F₁₄

hh:mm:ss

Clock is running normally

0

010000111-010100

12:45:12

prescaler counting normally

STOP bit is activated by user. F₀to F₈are not reset and values cannot be predicted externally

1

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prescaler is now running

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[1] F₀is clocked at 32.768 kHz.

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PCF2127

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Fig 34. STOP bit release timing

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9. Interfaces

The PCF2127 has an I²C-bus or SPI-bus interface using the same pins. The selection is

done using the interface selection pin IFS (see Table 85).

Table 85. Interface selection input pin IFS

Connection

V_SS

Bus interface

SPI-bus

I²C-bus

Reference

Section 9.1

Section 9.2

IFS

BBS

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To select the SPI-bus interface, pin IFS has to be

connected to pin V_SS

To select the I²C-bus interface, pin IFS has to be

connected to pin BBS.

.

a. SPI-bus interface selection

b. I²C-bus interface selection

Fig 35. Interface selection

9.1 SPI-bus interface

Data transfer to and from the device is made by a 3 line SPI-bus (see Table 86). The data

lines for input and output are split. The data input and output line can be connected

together to facilitate a bidirectional data bus (see Figure 36). The SPI-bus is initialized

whenever the chip enable line pin SDA/CE is inactive.

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Fig 36. SDI, SDO configurations

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Table 86. Serial interface

Symbol Function

Description

[1]

SDA/CE chip enable input;

active LOW

when HIGH, the interface is reset;

input may be higher than V_DD

when SDA/CE is HIGH, input may float;

input may be higher than V_DD

when SDA/CE is HIGH, input may float;

SCL

serial clock input

SDI

serial data input

input may be higher than V_DD

;

input data is sampled on the rising edge of

SCL

SDO

serial data output

push-pull output;

drives from V_SSto V_oper(int)(V_BBS);

output data is changed on the falling edge of

SCL

[1] The chip enable must not be wired permanently LOW.

9.1.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a

whole byte, with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal SDA/CE. The first

byte transmitted is the command byte. Subsequent bytes are either data to be written or

data to be read (see Figure 37).

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Fig 37. Data transfer overview

The command byte defines the address of the first register to be accessed and the

read/write mode. The address counter will auto increment after every access and will

reset to zero after the last valid register is accessed. The R/W bit defines if the following

bytes are read or write information.

Table 87. Command byte definition

Bit

Symbol

Value

Description

7

R/W

data read or write selection

write data

0

1

read data

6 to 5 SA

4 to 0 RA

01

subaddress;

other codes will cause the device to ignore

data transfer

00h to 1Dh

register address

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PCF2127

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In this example, the Seconds register is set to 45 seconds and the Minutes register to 10 minutes.

a. Writing seconds and minutes

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b. Writing to RAM address 02h

Fig 38. SPI-bus write examples

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PCF2127

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In this example, the registers Months and Years are read. The pins SDI and SDO are not connected together. For this

configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left

open, high I_DDcurrents may result.

a. Reading month and year

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Fig 39. SPI-bus read examples

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9.2 I²C-bus interface

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines are

connected to a positive supply by a pull-up resistor. Data transfer is initiated only when the

bus is not busy.

9.2.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line remains

stable during the HIGH period of the clock pulse as changes in the data line at this time

are interpreted as control signals (see Figure 40).

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9.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH, is defined as the START condition S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition P (see Figure 41).

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Fig 41. Definition of START and STOP conditions

Remark: For the PCF2127, a repeated START is not allowed. Therefore a STOP has to

be released before the next START.

9.2.3 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves.

The PCF2127 can act as a slave transmitter and a slave receiver.

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Fig 42. System configuration

9.2.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is illustrated in Figure 43.

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Fig 43. Acknowledgement on the I²C-bus

9.2.5 I²C-bus protocol

After a start condition, a valid hardware address has to be sent to a PCF2127 device. The

appropriate I²C-bus slave address is 1010001. The entire I²C-bus slave address byte is

shown in Table 88.

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Table 88. I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

1

0

1

0

1

The R/W bit defines the direction of the following single or multiple byte data transfer (read

is logic 1, write is logic 0).

For the format and the timing of the START condition (S), the STOP condition (P), and the

acknowledge (A) refer to the I²C-bus specification Ref. 13 “UM10204” and the

characteristics table (Table 93). In the write mode, a data transfer is terminated by sending

a STOP condition. A repeated START (Sr) condition is not applicable.

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Fig 45. Bus protocol, reading from registers

PCF2127

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PCF2127

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Fig 46. Bus protocol, writing to RAM

PCF2127

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PCF2127

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Fig 47. Bus protocol, reading from RAM

9.3 Bus communication and battery backup operation

To save power during battery backup operation (see Section 8.6.1), the bus interfaces are

inactive. Therefore the communication via I²C- or SPI-bus should be terminated before

the supply of the PCF2127 is switched from V_DDto V_BAT

.

The extra power fail detection function (see Section 8.6.3) of the PCF2127 allows early

detection of a dropping V_DD. The output on pin PFO indicates to the microcontroller to

terminate the bus communication properly. When the bus communication is not

terminated in a proper way, the time counters get corrupted.

Remark: If the I²C-bus communication was terminated uncontrolled, the I²C-bus has to

be reinitialized by sending a STOP followed by a START after the device switched back

from battery backup operation to V_DDsupply operation.

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10. Internal circuitry

9

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Fig 48. Device diode protection diagram of PCF2127

11. Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

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12. Limiting values

Table 89. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

0.5

50

0.5

10

0.5

10

0.5

-

Max

+6.5

+50

Unit

V

V_DD

I_DD

V_i

supply voltage

supply current

input voltage

input current

output voltage

output current

mA

V

+6.5

+10

I_I

mA

V

V_O

I_O

+6.5

+10

mA

V

at pin SDA/CE

+20

V_BAT

P_tot

battery supply voltage

total power dissipation

+6.5

300

mW

V

[1]

[2]

[3]

[4]

V_ESD

electrostatic

discharge voltage

HBM

CDM

-

4000

1250

200

-

V

I_lu

latch-up current

-

mA

C

T_stg

T_amb

storage temperature

55

40

+85

ambient temperature operating device

+85

[1] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”.

[2] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.

[3] Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (T_amb(max)).

[4] According to the store and transport requirements (see Ref. 14 “UM10569”) the devices have to be stored at a temperature of +8 C to

+45 C and a humidity of 25 % to 75 %.

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13. Static characteristics

Table 90. Static characteristics

V_DD= 1.8 V to 4.2 V; V_SS= 0 V; T_amb= 40 C to +85 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

[1]

supply voltage

1.8

-

4.2

-

V

V_BAT

battery supply voltage

-

V_DD(cal)

calibration supply

voltage

3.3

V_low

I_DD

low voltage

-

1.2

-

V

supply current

interface active;

supplied by V_DD

SPI-bus (f_SCL= 6.5 MHz)

I²C-bus (f_SCL= 400 kHz)

-

800

200

A

interface inactive (f_SCL= 0 Hz)^[2];

TCR[1:0] = 00 (see Table 13 on page 12)

PWRMNG[2:0] = 111 (see Table 25 on page 18);

TSOFF = 1 (see Table 68 on page 50);

COF[2:0] = 111 (see Table 15 on page 14)

V_DD= 1.8 V

V_DD= 3.3 V

V_DD= 4.2 V

-

470

700

800

-

nA

1500

-

PWRMNG[2:0] = 111 (see Table 25 on page 18);

TSOFF = 1 (see Table 68 on page 50);

COF[2:0] = 000 (see Table 15 on page 14)

V_DD= 1.8 V

V_DD= 3.3 V

V_DD= 4.2 V

-

560

-

nA

850

1050

PWRMNG[2:0] = 000 (see Table 25 on page 18);

TSOFF = 0 (see Table 68 on page 50);

COF[2:0] = 111 (see Table 15 on page 14)

[3]

V_DDor V_BAT= 1.8 V

V_DDor V_BAT= 3.3 V

V_DDor V_BAT= 4.2 V

-

1750

2150

2350

-

nA

[3]

-

3500

PWRMNG[2:0] = 000 (see Table 25 on page 18);

TSOFF = 0 (see Table 68 on page 50);

COF[2:0] = 000 (see Table 15 on page 14)

[3]

V_DDor V_BAT= 1.8 V

V_DDor V_BAT= 3.3 V

V_DDor V_BAT= 4.2 V

-

1840

2300

2600

50

-

nA

[3]

-

I_L(bat)

battery leakage

current

V_DDis active supply;

V_BAT= 3.0 V

100

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Table 90. Static characteristics …continued

V_DD= 1.8 V to 4.2 V; V_SS= 0 V; T_amb= 40 C to +85 C, unless otherwise specified.

Symbol

Power management

V_th(sw)batbattery switch

Parameter

Conditions

Min

Typ

Max

Unit

-

2.5

-

V

threshold voltage

V_th(bat)low

low battery threshold

voltage

-

2.5

-

V

T_amb= 25 C

2.25

-

2.85

-

V_th(PFI)

threshold voltage on

pin PFI

1.25

Inputs^[4]

V_I

input voltage

0.5

-

V_DD+ 0.5

0.25V_DD

0.3V_DD

V

V_IL

LOW-level input

voltage

-

T_amb= 20 C to +85 C;

V_DD> 2.0 V

V_IH

I_LI

HIGH-level input

voltage

0.7V_DD

-

V

input leakage current V_I= V_DDor V_SS

post ESD event

-

0

-

A

pF

1

-

+1

7

[5]

C_i

input capacitance

-

Outputs

V_O

output voltage

on pins CLKOUT, INT, RST and

PFO, referring to external pull-up

0.5

-

5.5

4.2

V

on pin BBS

1.8

-

V

on pin SDO

0.5

0.8V_DD

V_SS

V_DD+ 0.5

V_OH

V_OL

HIGH output voltage

LOW output voltage

on pin SDO

V_DD

on pins CLKOUT, INT, RST,

SDO, and PFO

0.2V_DD

I_OL

LOW-level output

current

output sink current;

V_OL= 0.4 V

[6]

on pin SDA/CE

3

17

-

mA

on all other outputs

1.0

I_OH

HIGH-level output

current

output source current;

on pin SDO;

-

V_OH= 3.8 V;

V

_DD= 4.2 V

I_LO

output leakage current V_O= V_DDor V_SS

post ESD event

-

0

-

A

1

+1

[1] For reliable oscillator start-up at power-on: V_DD(po)min= V_DD(min)+ 0.3 V.

[2] Timer source clock = ¹

₆₀Hz, level of pins SDA/CE, SDI, and SCL is V_DDor V_SS

⁄

.

[3] When the device is supplied by the V_BATpin instead of the V_DDpin, the current values for I_BATare as specified for I_DDunder the same

conditions.

[4] The I²C-bus and SPI-bus interfaces of PCF2127 are 5 V tolerant.

[5] Tested on sample basis.

[6] For further information, see Figure 49.

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13.1 Current consumption characteristics, typical

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Fig 49. I_OLon pin SDA/CE

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CLKOUT disabled; PWRMNG[2:0] = 111; TSOFF = 1; TS input floating.

Fig 50. I_DDas a function of temperature

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PCF2127

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Fig 51. I_DDas a function of V_DD

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PCF2127

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Interface inactive; T_amb= 25 C; V_BAT= 0 V; default configuration.

Description of the PWRMNG[2:0] settings, see Table 25 on page 18.

(1)

V_DD= 1.8 V.

(2) V_DD= 3.3 V.

(3) V_DD= 4.2 V.

(4)

V_DDor V_BAT= 1.8 V.

(5) V_DDor V_BAT= 3.3 V.

(6) V_DDor V_BAT= 4.2 V.

Fig 52. Typical I_DDas a function of the power management settings

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13.2 Frequency characteristics

Table 91. Frequency characteristics

V_DD= 1.8 V to 4.2 V; V_SS= 0 V; T_amb= +25 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_o

output frequency

on pin CLKOUT;

-

32.768

-

kHz

V

_DDor V_BAT= 3.3 V;

COF[2:0] = 000;

AO[3:0] = 1000

f/f

frequency stability

V_DDor V_BAT= 3.3 V

PCF2127AT

T_amb= 15 C to +60 C

-

3

5

ppm

T_amb= 25 C to 15 C

and

10

T_amb= +60 C to +65 C

PCF2127T

[1][2]

T

_amb= 30 C to +80 C

-

3

5

8

ppm

T_amb= 40 C to 30 C

and

15

T_amb= +80 C to +85 C

[3]

f_xtal/f_xtal

relative crystal

frequency variation

crystal aging

PCF2127AT

first year;

-

3

ppm

V_DDor V_BAT= 3.3 V

PCF2127T

first year

-

3

8

-

ppm

ten years

-

ppm

f/V

frequency variation

with voltage

on pin CLKOUT

1

ppm/V

[1] 1 ppm corresponds to a time deviation of 0.0864 seconds per day.

[2] Only valid if CLKOUT frequencies are not equal to 32.768 kHz or if CLKOUT is disabled.

[3] Not production tested. Effects of reflow soldering are included (see Ref. 3 “AN11266”).

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PCF2127

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(2) Uncompensated typical tuning-fork crystal frequency.

Fig 53. Typical characteristic of frequency with respect to temperature of PCF2127AT

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(1) Typical temperature compensated frequency response.

(2) Uncompensated typical tuning-fork crystal frequency.

Fig 54. Typical characteristic of frequency with respect to temperature of PCF2127T

PCF2127

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14. Dynamic characteristics

14.1 SPI-bus timing characteristics

Table 92. SPI-bus characteristics

_DD= 1.8 V to 4.2 V; V_SS= 0 V; T_amb= 40 C to +85 C, unless otherwise specified. All timing values are valid within the

V

operating supply voltage at ambient temperature and referenced to V_ILand V_IHwith an input voltage swing of V_SSto V_DD(see

Figure 55).

Symbol

Parameter

Conditions

V_DD= 1.8 V

V_DD= 4.2 V

Unit

Min

Max

Min

Max

Pin SCL

f_clk(SCL)

SCL clock frequency register read/write access

RAM write access

-

2.0

-

6.5

MHz

ns

-

2.0

-

6.5

RAM read access

-

1.11

-

6.25

t_SCL

SCL time

register read/write access

RAM write access

RAM read access

register read/write access

RAM write access

RAM read access

register read/write access

RAM write access

RAM read access

for SCL signal

800

900

100

450

400

450

-

140

160

70

80

70

80

-

ns

-

ns

t_clk(H)

clock HIGH time

clock LOW time

-

ns

-

ns

-

ns

t_clk(L)

-

ns

-

ns

-

ns

t_r

rise time

fall time

100

ns

t_f

for SCL signal

-

ns

Pin SDA/CE

t_{su(CE_N)}

t_{h(CE_N)}

t_{rec(CE_N)}

t_{w(CE_N)}

Pin SDI

t_su

CE_N set-up time

CE_N hold time

60

40

100

-

30

25

30

-

ns

s

-

CE_N recovery time

CE_N pulse width

-

0.99

set-up time

hold time

set-up time for SDI data

hold time for SDI data

70

-

20

-

ns

t_h

Pin SDO

t_d(R)SDO

SDO read delay time C_L= 50 pF

register read access

-

225

410

90

-

55

25

-

ns

RAM read access

-

[1]

t_dis(SDO)

SDO disable time

-

t_t(SDI-SDO)transition time from

SDI to SDO

to avoid bus conflict

0

[1] No load value; bus is held up by bus capacitance; use RC time constant with application values.

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

80 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

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PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

81 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

14.2 I²C-bus timing characteristics

Table 93. I²C-bus characteristics

All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %

and 70 % with an input voltage swing of V_SSto V_DD(see Figure 56).

Symbol

Parameter

Standard mode

Fast-mode (Fm)

Unit

Min

Max

Min

Max

Pin SCL

f_SCL

SCL clock frequency

0

100

0

400

kHz

s

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

4.7

4.0

-

1.3

0.6

-

t_HIGH

s

Pin SDA/CE

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

250

0

-

100

0

-

ns

Pins SCL and SDA/CE

t_BUF

bus free time between a STOP

4.7

-

1.3

-

s

and START condition

t_SU;STO

t_HD;STA

set-up time for STOP condition

4.0

-

0.6

-

s

hold time (repeated) START

condition

t_SU;STA

set-up time for a repeated START

condition

4.7

-

0.6

-

s

ns

[1][2][3]

t_r

t_f

rise time of both SDA and SCL

signals

-

1000

300

20 + 0.1C_b

300

fall time of both SDA and SCL

signals

[4]

[5]

[6]

t_VD;ACK

t_VD;DAT

t_SP

data valid acknowledge time

data valid time

0.1

300

-

3.45

-

0.1

75

-

0.9

-

s

ns

pulse width of spikes that must be

suppressed by the input filter

50

[1] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_ILof the SCL signal) in order to

bridge the undefined region of the falling edge of SCL.

[2] C_bis the total capacitance of one bus line in pF.

[3] The maximum t_ffor the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, t_fis 250 ns. This allows

series protection resistors to be connected between the SDA/CE pin, the SCL pin, and the SDA/SCL bus lines without exceeding the

maximum t_f.

[4]

t_VD;ACKis the time of the acknowledgement signal from SCL LOW to SDA (out) LOW.

[5] t_VD;DATis the minimum time for valid SDA (out) data following SCL LOW.

[6] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

82 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

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Fig 56. I²C-bus timing diagram; rise and fall times refer to 30 % and 70 %

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

83 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

15. Application information

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C_i: In case mechanical switches are used, a capacitor of 1 nF is recommended.

R1, R2: Voltage dividers for setting the power-fail level.

R_PU: For example, 10 k.

Fig 57. General application diagram

For information about application configuration, see Ref. 3 “AN11266” on page 92

16. Test information

16.1 Quality information

UL Component Recognition

This (component or material) is Recognized by UL. Representative samples of this

component have been evaluated by UL and meet applicable UL requirements.

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

84 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

17. Package outline

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Fig 58. Package outline SOT163-1 (SO20) of PCF2127AT

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

85 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

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Fig 59. Package outline SOT162-1 (SO16) of PCF2127T

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

86 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

18. Packing information

18.1 Tape and reel information

For tape and reel packing information, see

• Ref. 11 “SOT162-1_518” on page 92 for the PCF2127T.

• Ref. 12 “SOT163-1_518” on page 92 for the PCF2127AT.

19. Soldering

For information about soldering, see Ref. 3 “AN11266” on page 92.

19.1 Footprint information

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Fig 60. Footprint information for reflow soldering of SOT163-1 (SO20) of PCF2127AT

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

87 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

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ꢀꢁꢂꢈꢋ ꢀꢁꢇꢂꢋ ꢀꢀꢁꢂꢋꢋ ꢉꢁꢌꢋꢋ ꢂꢁꢌꢋꢋ ꢋꢁꢈꢋꢋ ꢋꢁꢊꢋꢋ ꢀꢋꢁꢋꢌꢋ ꢊꢁꢉꢋꢋ ꢀꢀꢁꢍꢋꢋ ꢀꢀꢁꢌꢃꢋ

%\

&

'ꢀ

'ꢂ

*[

*\

+[

+\

VRWꢂꢇꢆꢀꢂBIU

Fig 61. Footprint information for reflow soldering of SOT162-1 (SO16) of PCF2127T

PCF2127

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Product data sheet

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88 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

21. Abbreviations

Table 95. Abbreviations

Acronym

Description

ACK

AM

ACKnowledge (I²C-bus)

Ante Meridiem

BCD

CDM

CMOS

DC

Binary Coded Decimal

Charged Device Model

Complementary Metal-Oxide Semiconductor

Direct Current

GPS

HBM

I²C

Global Positioning System

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

LSB

MCU

MSB

PM

Least Significant Bit

Microcontroller Unit

Most Significant Bit

Post Meridiem

POR

PORO

PPM

RAM

RC

Power-On Reset

Power-On Reset Override

Parts Per Million

Random Access Memory

Resistance-Capacitance

Real Time Clock

RTC

SCL

SDA

SPI

Serial CLock line

Serial DAta line

Serial Peripheral Interface

Static Random Access Memory

Temperature Compensated Xtal Oscillator

crystal

SRAM

TCXO

Xtal

PCF2127

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Product data sheet

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91 of 100

PCF2127

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Accurate RTC with integrated quartz crystal for industrial applications

22. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN10853 — Handling precautions of ESD sensitive devices

[3] AN11266 — Application and soldering information for the PCF2127 industrial TCXO

RTC

[4] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[8] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[9] JESD78 — IC Latch-Up Test

[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[11] SOT162-1_518 — SO16; Reel pack; SMD, 13”, packing information

[12] SOT163-1_518 — SO20; Reel pack; SMD, 13”, packing information

[13] UM10204 — I²C-bus specification and user manual

[14] UM10569 — Store and transport requirements

[15] UM10762 — User manual for the accurate RTC demo board OM13513 containing

PCF2127T and PCF2129AT

PCF2127

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Accurate RTC with integrated quartz crystal for industrial applications

23. Revision history

Table 96. Revision history

Document ID

PCF2127 v.8

Modifications:

Release date

20141219

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCF2127 v.7

• Added V_OHand V_OLvalues in Table 90

• Enhanced ESD HBM values

• Corrected Figure 8

• Enhanced description of internal operating voltage

• Added register bit allocation tables

• Fixed typos

PCF2127 v.7

20141003

Product data sheet

-

PCF2127AT v.6

PCF2127 v.3

PCF2127AT

PCF2127AT v.6

PCF2127AT v.5

PCF2127AT v.4

PCF2127AT v.3

PCF2127A v.2

PCF2127A v.1

PCF2127T

20130711

20130128

20121207

20121004

20100507

20100121

Product data sheet

-

PCF2127AT v.5

PCF2127AT v.4

PCF2127AT v.3

PCF2127A v.2

PCF2127A v.1

-

PCF2127 v.3

PCF2127 v.2

PCF2127 v.1

20130711

20130422

20130212

Product data sheet

-

PCF2127 v.2

PCF2127 v.1

-

PCF2127

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PCF2127

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24. Legal information

24.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

24.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

24.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

PCF2127

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PCF2127

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Accurate RTC with integrated quartz crystal for industrial applications

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

24.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

25. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCF2127

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Product data sheet

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PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

26. Tables

Table 1. Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description of PCF2127 . . . . . . . . . . . . . . . .5

Table 5. Register overview . . . . . . . . . . . . . . . . . . . . . . .8

Table 6. Control_1 - control and status register 1 (address

00h) bit allocation . . . . . . . . . . . . . . . . . . . . . .10

Table 7. Control_1 - control and status register 1 (address

00h) bit description . . . . . . . . . . . . . . . . . . . . . .10

Table 8. Control_2 - control and status register 2 (address

01h) bit allocation . . . . . . . . . . . . . . . . . . . . . .11

Table 9. Control_2 - control and status register 2 (address

01h) bit description . . . . . . . . . . . . . . . . . . . . .11

Table 10. Control_3 - control and status register 3 (address

02h) bit allocation . . . . . . . . . . . . . . . . . . . . . .12

Table 11. Control_3 - control and status register 3 (address

02h) bit description . . . . . . . . . . . . . . . . . . . . . .12

Table 12. CLKOUT_ctl - CLKOUT control register (address

0Fh) bit allocation . . . . . . . . . . . . . . . . . . . . . .12

Table 13. CLKOUT_ctl - CLKOUT control register (address

0Fh) bit description. . . . . . . . . . . . . . . . . . . . . .12

Table 14. Temperature measurement period . . . . . . . . . .13

Table 15. CLKOUT frequency selection. . . . . . . . . . . . . .14

Table 16. Aging_offset - crystal aging offset register

(address 19h) bit allocation . . . . . . . . . . . . . . .14

Table 17. Aging_offset - crystal aging offset register

(address 19h) bit description . . . . . . . . . . . . . .14

Table 18. Frequency correction at 25 °C, typical . . . . . . .15

Table 19. RAM_addr_MSB - RAM address MSB register

(address 1Ah) bit allocation . . . . . . . . . . . . . . .16

Table 20. RAM_addr_MSB - RAM address MSB register

(address 1Ah) bit description . . . . . . . . . . . . . .16

Table 21. RAM_addr_LSB - RAM address LSB register

(address 1Bh) bit allocation . . . . . . . . . . . . . . .16

Table 22. RAM_addr_LSB - RAM address LSB register

(address 1Bh) bit description . . . . . . . . . . . . . .16

Table 23. RAM_wrt_cmd - RAM write command register

(address 1Ch) bit description . . . . . . . . . . . . . .16

Table 24. RAM_rd_cmd - RAM read command register

(address 1Dh) bit description . . . . . . . . . . . . . .16

Table 25. Power management control bit description . . .18

Table 26. Output pin BBS. . . . . . . . . . . . . . . . . . . . . . . . .26

Table 27. Seconds - seconds and clock integrity register

(address 03h) bit allocation . . . . . . . . . . . . . . .30

Table 28. Seconds - seconds and clock integrity register

(address 03h) bit description . . . . . . . . . . . . . .30

Table 29. Seconds coded in BCD format . . . . . . . . . . . .31

Table 30. Minutes - minutes register (address 04h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 31. Minutes - minutes register (address 04h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 32. Hours - hours register (address 05h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 33. Hours - hours register (address 05h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 34. Days - days register (address 06h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 35. Days - days register (address 06h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 36. Weekdays - weekdays register (address 07h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 37. Weekdays - weekdays register (address 07h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 38. Weekday assignments . . . . . . . . . . . . . . . . . . 33

Table 39. Months - months register (address 08h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 40. Months - months register (address 08h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 41. Month assignments in BCD format . . . . . . . . . 34

Table 42. Years - years register (address 09h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 43. Years - years register (address 09h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 44. Second_alarm - second alarm register (address

0Ah) bit allocation . . . . . . . . . . . . . . . . . . . . . . 38

Table 45. Second_alarm - second alarm register (address

0Ah) bit description . . . . . . . . . . . . . . . . . . . . . 38

Table 46. Minute_alarm - minute alarm register (address

0Bh) bit allocation . . . . . . . . . . . . . . . . . . . . . . 38

Table 47. Minute_alarm - minute alarm register (address

0Bh) bit description . . . . . . . . . . . . . . . . . . . . . 38

Table 48. Hour_alarm - hour alarm register (address 0Ch)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 49. Hour_alarm - hour alarm register (address 0Ch)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 50. Day_alarm - day alarm register (address 0Dh) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 51. Day_alarm - day alarm register (address 0Dh) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 52. Weekday_alarm - weekday alarm register

(address 0Eh) bit allocation . . . . . . . . . . . . . . 40

Table 53. Weekday_alarm - weekday alarm register

(address 0Eh) bit description . . . . . . . . . . . . . . 40

Table 54. Watchdg_tim_ctl - watchdog timer control register

(address 10h) bit allocation . . . . . . . . . . . . . . . 41

Table 55. Watchdg_tim_ctl - watchdog timer control register

(address 10h) bit description . . . . . . . . . . . . . . 41

Table 56. Watchdg_tim_val - watchdog timer value register

(address 11h) bit allocation . . . . . . . . . . . . . . . 42

Table 57. Watchdg_tim_val - watchdog timer value register

(address 11h) bit description . . . . . . . . . . . . . . 42

Table 58. Programmable watchdog timer . . . . . . . . . . . . 42

Table 59. Specification of t_w(rst). . . . . . . . . . . . . . . . . . . . 44

Table 60. First period delay for timer counter . . . . . . . . . 45

Table 61. Flag location in register Control_2 . . . . . . . . . . 46

Table 62. Example values in register Control_2 . . . . . . . 46

Table 63. Example to clear only CDTF (bit 3) . . . . . . . . . 46

Table 64. Example to clear only AF (bit 4). . . . . . . . . . . . 46

Table 65. Example to clear only MSF (bit 7) . . . . . . . . . . 47

Table 66. Example to clear both CDTF and MSF . . . . . . 47

Table 67. Timestp_ctl - timestamp control register (address

12h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 50

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Product data sheet

Rev. 8 — 19 December 2014

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PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

Table 68. Timestp_ctl - timestamp control register (address

12h) bit description . . . . . . . . . . . . . . . . . . . . . .50

Table 69. Sec_timestp - second timestamp register

(address 13h) bit allocation . . . . . . . . . . . . . . .50

Table 70. Sec_timestp - second timestamp register

(address 13h) bit description . . . . . . . . . . . . . .50

Table 71. Min_timestp - minute timestamp register (address

14h) bit allocation . . . . . . . . . . . . . . . . . . . . . .51

Table 72. Min_timestp - minute timestamp register (address

14h) bit description . . . . . . . . . . . . . . . . . . . . .51

Table 73. Hour_timestp - hour timestamp register (address

15h) bit allocation . . . . . . . . . . . . . . . . . . . . . .51

Table 74. Hour_timestp - hour timestamp register (address

15h) bit description . . . . . . . . . . . . . . . . . . . . . .51

Table 75. Day_timestp - day timestamp register (address

16h) bit allocation . . . . . . . . . . . . . . . . . . . . . .52

Table 76. Day_timestp - day timestamp register (address

16h) bit description . . . . . . . . . . . . . . . . . . . . . .52

Table 77. Mon_timestp - month timestamp register (address

17h) bit allocation . . . . . . . . . . . . . . . . . . . . . .52

Table 78. Mon_timestp - month timestamp register (address

17h) bit description . . . . . . . . . . . . . . . . . . . . . .52

Table 79. Year_timestp - year timestamp register (address

18h) bit allocation . . . . . . . . . . . . . . . . . . . . . .52

Table 80. Year_timestp - year timestamp register (address

18h) bit description . . . . . . . . . . . . . . . . . . . . . .52

Table 81. Battery switch-over and timestamp. . . . . . . . . .53

Table 82. Effect of bits MI and SI on pin INT and bit MSF55

Table 83. INT operation (bit TI_TP = 1) . . . . . . . . . . . . . .57

Table 84. First increment of time circuits after stop

release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 85. Interface selection input pin IFS . . . . . . . . . . . .62

Table 86. Serial interface . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 87. Command byte definition . . . . . . . . . . . . . . . . .63

Table 88. I²C slave address byte . . . . . . . . . . . . . . . . . . .68

Table 89. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 90. Static characteristics . . . . . . . . . . . . . . . . . . . .73

Table 91. Frequency characteristics . . . . . . . . . . . . . . . .78

Table 92. SPI-bus characteristics. . . . . . . . . . . . . . . . . . .80

Table 93. I²C-bus characteristics . . . . . . . . . . . . . . . . . . .82

Table 94. Selection of Real-Time Clocks . . . . . . . . . . . . .89

Table 95. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 96. Revision history . . . . . . . . . . . . . . . . . . . . . . . .93

PCF2127

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Product data sheet

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PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

27. Figures

Fig 1. Block diagram of PCF2127 . . . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration for PCF2127AT (SO20) . . . . . . .4

Fig 3. Pin configuration for PCF2127T (SO16) . . . . . . . .4

Fig 4. Position of the stubs from the package assembly

process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 5. Handling address registers . . . . . . . . . . . . . . . . . .6

Fig 6. Battery switch-over behavior in standard mode with

bit BIE set logic 1 (enabled). . . . . . . . . . . . . . . . .20

Fig 7. Battery switch-over behavior in direct switching

mode with bit BIE set logic 1 (enabled) . . . . . . . .21

Fig 8. Battery switch-over circuit, simplified block

diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 9. Battery low detection behavior with bit BLIE set logic

1 (enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 10. Typical application of the extra power fail detection

function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 11. PFO signal behavior when battery switch-over is

enabled in standard mode and

Fig 38. SPI-bus write examples . . . . . . . . . . . . . . . . . . . 64

Fig 39. SPI-bus read examples. . . . . . . . . . . . . . . . . . . . 65

Fig 40. Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Fig 41. Definition of START and STOP conditions . . . . . 66

Fig 42. System configuration. . . . . . . . . . . . . . . . . . . . . . 67

Fig 43. Acknowledgement on the I²C-bus. . . . . . . . . . . . 67

Fig 44. Bus protocol, writing to registers. . . . . . . . . . . . . 68

Fig 45. Bus protocol, reading from registers . . . . . . . . . . 68

Fig 46. Bus protocol, writing to RAM. . . . . . . . . . . . . . . . 69

Fig 47. Bus protocol, reading from RAM. . . . . . . . . . . . . 70

Fig 48. Device diode protection diagram of PCF2127 . . 71

Fig 49. I_OLon pin SDA/CE . . . . . . . . . . . . . . . . . . . . . . . 75

Fig 50. I_DDas a function of temperature . . . . . . . . . . . . . 75

Fig 51. I_DDas a function of V_DD. . . . . . . . . . . . . . . . . . . . 76

Fig 52. Typical I_DDas a function of the power management

settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Fig 53. Typical characteristic of frequency with respect to

temperature of PCF2127AT . . . . . . . . . . . . . . . . 79

Fig 54. Typical characteristic of frequency with respect to

temperature of PCF2127T . . . . . . . . . . . . . . . . . 79

Fig 55. SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Fig 56. I²C-bus timing diagram; rise and fall times refer to

30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Fig 57. General application diagram . . . . . . . . . . . . . . . . 84

Fig 58. Package outline SOT163-1 (SO20)

V_th(uvp)> (V_BAT, V_th(sw)bat). . . . . . . . . . . . . . . . . . .25

Fig 12. PFO signal behavior when battery switch-over is

enabled in direct switching mode

and V_th(uvp)< V_BAT. . . . . . . . . . . . . . . . . . . . . . . .25

Fig 13. PFO signal behavior when battery switch-over is

disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 14. Typical driving capability of V_BBS: (V_BBS- V_DD) with

respect to the output load current I_BBS. . . . . . . . .27

Fig 15. Power failure event due to battery discharge: reset

occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 16. Dependency between POR and oscillator . . . . . .29

Fig 17. Power-On Reset (POR) system. . . . . . . . . . . . . .29

Fig 18. Power-On Reset Override (PORO) sequence, valid

for both I²C-bus and SPI-bus. . . . . . . . . . . . . . . .30

Fig 19. Data flow of the time function. . . . . . . . . . . . . . . .35

Fig 20. Access time for read/write operations . . . . . . . . .36

Fig 21. Alarm function block diagram. . . . . . . . . . . . . . . .37

Fig 22. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .40

Fig 23. WD_CD[1:0] = 10: watchdog activates an interrupt

when timed out . . . . . . . . . . . . . . . . . . . . . . . . . .43

Fig 24. WD_CD[1:0] = 11: watchdog activates a reset pulse

when timed out . . . . . . . . . . . . . . . . . . . . . . . . . .44

Fig 25. General countdown timer behavior . . . . . . . . . . .45

Fig 26. Timestamp detection with two push-buttons on the

TS pin (for example, for tamper detection) . . . . .48

Fig 27. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .54

Fig 28. INT example for SI and MI when TI_TP is logic 156

Fig 29. INT example for SI and MI when TI_TP is logic 056

Fig 30. Example of shortening the INT pulse by clearing the

MSF flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Fig 31. Example of shortening the INT pulse by clearing the

CDTF flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Fig 32. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .58

Fig 33. STOP bit functional diagram . . . . . . . . . . . . . . . .60

Fig 34. STOP bit release timing. . . . . . . . . . . . . . . . . . . .61

Fig 35. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .62

Fig 36. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .62

Fig 37. Data transfer overview. . . . . . . . . . . . . . . . . . . . .63

of PCF2127AT. . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Fig 59. Package outline SOT162-1 (SO16)

of PCF2127T. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Fig 60. Footprint information for reflow soldering of

SOT163-1 (SO20) of PCF2127AT. . . . . . . . . . . . 87

Fig 61. Footprint information for reflow soldering of

SOT162-1 (SO16) of PCF2127T. . . . . . . . . . . . . 88

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

98 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

28. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.8

Reset function . . . . . . . . . . . . . . . . . . . . . . . . 28

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 28

Power-On Reset Override (PORO) . . . . . . . . 29

Time and date function. . . . . . . . . . . . . . . . . . 30

Register Seconds. . . . . . . . . . . . . . . . . . . . . . 30

Register Minutes . . . . . . . . . . . . . . . . . . . . . . 31

Register Hours. . . . . . . . . . . . . . . . . . . . . . . . 32

Register Days . . . . . . . . . . . . . . . . . . . . . . . . 32

Register Weekdays . . . . . . . . . . . . . . . . . . . . 33

Register Months. . . . . . . . . . . . . . . . . . . . . . . 34

Register Years . . . . . . . . . . . . . . . . . . . . . . . . 35

Setting and reading the time . . . . . . . . . . . . . 35

Alarm function . . . . . . . . . . . . . . . . . . . . . . . . 37

Register Second_alarm . . . . . . . . . . . . . . . . . 38

Register Minute_alarm. . . . . . . . . . . . . . . . . . 38

Register Hour_alarm . . . . . . . . . . . . . . . . . . . 39

Register Day_alarm . . . . . . . . . . . . . . . . . . . . 39

Register Weekday_alarm. . . . . . . . . . . . . . . . 40

Alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Timer functions. . . . . . . . . . . . . . . . . . . . . . . . 40

Register Watchdg_tim_ctl . . . . . . . . . . . . . . . 41

Register Watchdg_tim_val . . . . . . . . . . . . . . . 42

Watchdog timer function . . . . . . . . . . . . . . . . 42

Countdown timer function . . . . . . . . . . . . . . . 44

Pre-defined timers: second and minute

8.8.1

8.8.2

8.9

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

4

4.1

5

8.9.1

8.9.2

8.9.3

8.9.4

8.9.5

8.9.6

8.9.7

8.9.8

8.10

8.10.1

8.10.2

8.10.3

8.10.4

8.10.5

8.10.6

8.11

6

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8

8.1

8.2

Functional description . . . . . . . . . . . . . . . . . . . 6

Register overview. . . . . . . . . . . . . . . . . . . . . . . 6

Control registers . . . . . . . . . . . . . . . . . . . . . . . 10

Register Control_1 . . . . . . . . . . . . . . . . . . . . . 10

Register Control_2 . . . . . . . . . . . . . . . . . . . . . 11

Register Control_3 . . . . . . . . . . . . . . . . . . . . . 12

Register CLKOUT_ctl. . . . . . . . . . . . . . . . . . . 12

Temperature compensated crystal oscillator . 13

Temperature measurement . . . . . . . . . . . . . . 13

OTP refresh . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Register Aging_offset . . . . . . . . . . . . . . . . . . . 14

Crystal aging correction . . . . . . . . . . . . . . . . . 14

General purpose 512 bytes static RAM . . . . . 15

Register RAM_addr_MSB . . . . . . . . . . . . . . . 16

Register RAM_addr_LSB . . . . . . . . . . . . . . . . 16

Register RAM_wrt_cmd . . . . . . . . . . . . . . . . . 16

Register RAM_rd_cmd . . . . . . . . . . . . . . . . . . 16

Operation examples . . . . . . . . . . . . . . . . . . . . 17

Writing to the RAM . . . . . . . . . . . . . . . . . . . . . 17

Reading from the RAM. . . . . . . . . . . . . . . . . . 17

Power management functions . . . . . . . . . . . . 17

Battery switch-over function . . . . . . . . . . . . . . 19

Standard mode . . . . . . . . . . . . . . . . . . . . . . . . 20

Direct switching mode . . . . . . . . . . . . . . . . . . 21

Battery switch-over disabled: only one power

supply (V_DD) . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Battery switch-over architecture . . . . . . . . . . . 22

Battery low detection function. . . . . . . . . . . . . 22

Extra power fail detection function . . . . . . . . . 23

Extra power fail detection when the battery

8.2.1

8.2.2

8.2.3

8.3

8.3.1

8.3.1.1

8.3.2

8.3.3

8.4

8.11.1

8.11.2

8.11.3

8.11.4

8.11.5

8.4.1

8.5

interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Clearing flags. . . . . . . . . . . . . . . . . . . . . . . . . 46

Timestamp function . . . . . . . . . . . . . . . . . . . . 48

Timestamp flag. . . . . . . . . . . . . . . . . . . . . . . . 48

Timestamp mode . . . . . . . . . . . . . . . . . . . . . . 49

Timestamp registers. . . . . . . . . . . . . . . . . . . . 50

8.5.1

8.5.2

8.5.3

8.5.4

8.5.5

8.5.5.1

8.5.5.2

8.6

8.6.1

8.6.1.1

8.6.1.2

8.6.1.3

8.11.6

8.12

8.12.1

8.12.2

8.12.3

8.12.3.1 Register Timestp_ctl . . . . . . . . . . . . . . . . . . . 50

8.12.3.2 Register Sec_timestp. . . . . . . . . . . . . . . . . . . 50

8.12.3.3 Register Min_timestp . . . . . . . . . . . . . . . . . . . 51

8.12.3.4 Register Hour_timestp . . . . . . . . . . . . . . . . . . 51

8.12.3.5 Register Day_timestp. . . . . . . . . . . . . . . . . . . 52

8.12.3.6 Register Mon_timestp . . . . . . . . . . . . . . . . . . 52

8.12.3.7 Register Year_timestp . . . . . . . . . . . . . . . . . . 52

8.12.4

Dependency between Battery switch-over and

timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Interrupt output, INT. . . . . . . . . . . . . . . . . . . . 54

Minute and second interrupts. . . . . . . . . . . . . 55

Countdown timer interrupts . . . . . . . . . . . . . . 56

INT pulse shortening . . . . . . . . . . . . . . . . . . . 56

Watchdog timer interrupts . . . . . . . . . . . . . . . 58

Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 58

Timestamp interrupts . . . . . . . . . . . . . . . . . . . 58

Battery switch-over interrupts . . . . . . . . . . . . 58

8.6.1.4

8.6.2

8.6.3

8.13

8.13.1

8.13.2

8.13.3

8.13.4

8.13.5

8.13.6

8.13.7

8.6.3.1

switch-over function is enabled . . . . . . . . . . . 24

Extra power fail detection when the battery

switch-over function is disabled . . . . . . . . . . . 26

Battery backup supply . . . . . . . . . . . . . . . . . . 26

Oscillator stop detection function . . . . . . . . . . 27

8.6.3.2

8.6.4

8.7

continued >>

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

99 of 100

PCF2127

NXP Semiconductors

Accurate RTC with integrated quartz crystal for industrial applications

8.13.8

8.14

Battery low detection interrupts . . . . . . . . . . . 58

External clock test mode . . . . . . . . . . . . . . . . 59

8.15

STOP bit function . . . . . . . . . . . . . . . . . . . . . . 59

9

9.1

9.1.1

9.2

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.3

Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 62

Data transmission. . . . . . . . . . . . . . . . . . . . . . 63

I²C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 66

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

START and STOP conditions . . . . . . . . . . . . . 66

System configuration . . . . . . . . . . . . . . . . . . . 66

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 67

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 67

Bus communication and battery backup

operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

10

11

12

Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 71

Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 72

13

13.1

13.2

Static characteristics. . . . . . . . . . . . . . . . . . . . 73

Current consumption characteristics, typical . 75

Frequency characteristics. . . . . . . . . . . . . . . . 78

14

14.1

14.2

Dynamic characteristics . . . . . . . . . . . . . . . . . 80

SPI-bus timing characteristics . . . . . . . . . . . . 80

I²C-bus timing characteristics. . . . . . . . . . . . . 82

15

Application information. . . . . . . . . . . . . . . . . . 84

Test information. . . . . . . . . . . . . . . . . . . . . . . . 84

Quality information . . . . . . . . . . . . . . . . . . . . . 84

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 85

Packing information . . . . . . . . . . . . . . . . . . . . 87

Tape and reel information. . . . . . . . . . . . . . . . 87

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Footprint information. . . . . . . . . . . . . . . . . . . . 87

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Real-Time Clock selection . . . . . . . . . . . . . . . 89

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 91

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 93

16

16.1

17

18

18.1

19

19.1

20

20.1

21

22

23

24

Legal information. . . . . . . . . . . . . . . . . . . . . . . 94

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 94

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 95

24.1

24.2

24.3

24.4

25

26

27

28

Contact information. . . . . . . . . . . . . . . . . . . . . 95

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 December 2014

Document identifier: PCF2127


型号：	PCF2127T
厂家：	NXP
描述：	Accurate RTC with integrated quartz crystal for industrial applications
文件：	总100页 (文件大小：1077K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCF2127T [NXP]

相关型号：

PCF2128

PCF2128T

PCF2128T1

PCF2129(A)

PCF2129A

PCF2129AT

PCF2129AT-1

PCF2129AT/1

PCF2129AT/1,512

PCF2129AT/1,518

PCF2129AT/2

PCF2129AT/2,518