PCF5075TDK-T [NXP]
IC SPECIALTY TELECOM CIRCUIT, PDSO20, PLASTIC, SOT-266, SSOP-20, Telecom IC:Other;
| 型号： | PCF5075TDK-T |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY TELECOM CIRCUIT, PDSO20, PLASTIC, SOT-266, SSOP-20, Telecom IC:Other 电信 光电二极管 电信集成电路 |
| 文件： | 总30页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF5075
Power amplifier controller for GSM
and PCN systems
1997 Feb 27
Product specification
Supersedes data of 1996 Feb 15
File under Integrated Circuits, IC17
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
CONTENTS
1
2
3
4
5
6
FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
FUNCTIONAL DESCRIPTION
6.2
Primary start condition
Power-down (PD) HIGH
Power-down (PD) LOW
The analog integrating controller
Ramp generation
Description of signals
Stability
Clock influence
Serial bus programming
Data format
6.2.1
6.2.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.5
6.6
6.6.1
6.6.2
6.6.3
Vk bits
Vh bits
PL bits
7
LIMITING VALUES
8
OPERATING CHARACTERISTICS
10
11
11.2.1
13
14
TIMING CHARACTERISTICS
APPLICATION INFORMATION
Theoretical limit for correct down-ramping
APPENDIX B: BEHAVIOURAL MODELS
APPENDIX C: AC SIMULATIONS FOR OPERATIONAL AMPLIFIERS 2 AND 4
16.2
16.3
16.4
Reflow soldering
Wave soldering
Repairing soldered joints
17
18
DEFINITIONS
LIFE SUPPORT APPLICATIONS
1997 Feb 27
2
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
1
FEATURES
• CMOS low-voltage, low-power
• Can be used in burst mode with power-down
• Three-wire serial bus interface with the bus available in
power-down mode
• On-chip ramp generator for 256 different power levels
• Extendable dynamic range
• Two programmable regulator start conditions, VKICK and
VHOME
• Programmable analog output voltage limitation
• Ramping speed depending on the 13 MHz system
frequency clock for Global System for Mobile
communications (GSM) and Personnel
Communications Network (PCN)
• Low swing input buffer for the 13 MHz master clock
• Compatible with a large number of different RF power
modules
• Programmable temperature matching
• Quick restart option.
2
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
2.7
2.7
−
5.0
5.0
9
5.5
5.5
15
V
VDDA
IDD(tot)
Tamb
analog supply voltage
total supply current
V
mA
°C
operating ambient temperature
−40
−
+85
3
ORDERING INFORMATION
PACKAGE
DESCRIPTION
plastic shrink small outline package; 20 leads; body width 4.4 mm
TYPE NUMBER
NAME
VERSION
PCF5075
SSOP20
SOT266-1
1997 Feb 27
3
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
4
BLOCK DIAGRAM
2166
MHz
sensor RF input
voltage
control for
RF power module
C2
180 pF
D1
D2
1 kΩ
L1 100 µF
BAS70-07
V
C3
50 pF
C1
V
1 kΩ
INT(p)
D1
180 pF
V
V
V
I
BIAS
INT(n)
19 20
INT(o)
18
VS2
VS1
BVS1
SR
7
6
5
1
3
1.25 V
band gap
OP2
80 µA
R1
V
8.4 kΩ
BVS1
HPA
V
R3
R5
8.4 kΩ
OP4
DAC8
8.4 kΩ
HPA
KOMP
DACA KICKA QRSA
OP1
QRSA
R2
1
2
2.4
ADDER
1
1
8.4 kΩ
V
RAMPR
=100
mV
SLOPE GENERATOR
HPA
R4
R6
8.4 kΩ HPA
COMPARATOR
DAC6
DACA
KICKA
V
8.4 kΩ
HOMEIN
POWER LEVEL REG.
8-bit
V
V
REGISTER
REGISTER
6-bit
8-bit
2-bit
2-bit
KICK
HOME
LIMITER REGISTER
DF REGISTER
1/6
Control
10
SERIAL BUS INTERFACE
low swing
input
A
buffer
12
DF
15
14
13
8
16
2
17
11
CL13
9
4
MBE729
V
V
DATA
STROBE
TRIG DTX PD
SSD
SSA
CLK
V
V
DDD
DDA
Fig.1 Block diagram.
1997 Feb 27
4
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
5
PINNING
SYMBOL
PIN
DESCRIPTION
sensor signal input 1
VS1
VDDA
BVS1
PD
1
2
3
4
5
analog supply voltage
buffered sensor output signal
power-down input
handbook, halfpage
V
1
2
20
19
18
17
16
15
14
13
12
11
VS1
INT(n)
IBIAS
bias current output for external
rectifier
V
V
INT(p)
DDA
V
VS2
VSR
6
7
8
9
sensor signal input 2
BVS1
PD
3
INT(o)
bias voltage output for sensor
digital supply voltage
4
V
SSA
VDDD
DTX
5
I
V
BIAS
VS2
SSD
PCF5075
test, disable or stop TX burst
6
DATA
CLK
(has to be connected to VSSD
)
7
V
TRIG
CL13
10
11
trigger signal input
SR
8
V
STROBE
DF
13 MHz master clock pulse input
(LOW swing input)
DDD
DTX
9
DF
12
13
14
15
16
17
18
19
20
programmable 3-state output
serial bus strobe input signal
serial bus clock input signal
serial bus data input signal
digital ground
10
TRIG
CL13
STROBE
CLK
MBE728
DATA
VSSD
VSSA
analog ground
VINT(o)
VINT(p)
VINT(n)
integrator output voltage
integrator positive input voltage
integrator negative input voltage
Fig.2 Pin configuration.
1997 Feb 27
5
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
4. The temperature behaviour of the home position.
Bits Dvh1 and Dvh0 must be used to add 0, 1 or 2
internally generated diode voltages to VHOME. In this
manner it is possible to compensate for a possible
temperature dependence (−2 mV/°C or −4 mV/°C) of
the control curves of the power module.
6
FUNCTIONAL DESCRIPTION
General
6.1
This CMOS device integrates operational amplifiers, two
digital-to-analog converters and a serial interface to
implement an ‘Integrating-Controller’. It is designed to
control both the power level and the up and down-ramping
of GSM-transmit bursts.
5. The KICK voltage. The 6 bits of the KICK voltage
register (Vk5-to-Vk0) determine the differential
integrator input voltage just after a ramp-up starting
signal is detected.
The GSM/PCN power-up power-down ramping curves are
generated on-chip, using an internal clock frequency of
2.166 MHz (Tcy = 1/fclk), that is generated internally by
dividing the external 13 MHz clock by six.
The register information is written via a three-wire serial
bus (see Sections 6.5 and 6.6).
Generally, the power amplifier is ramped-up after a rising
edge on TRIG (pin 10) and ramped-down after a falling
edge. When TRIG goes LOW for less than two clock
periods (2Tcy), a special function for base station
applications is activated (see Chapter 12).
The DF output (pin 12) is a general purpose pin which can
have three different states, LOW, HIGH and 3-state,
depending on the values of DF0 and DF1 in the serial
register.
Separate power supply pins are provided for the analog
and digital blocks.
When DTX (pin 9) becomes active during a ramp-up,
ramping is stopped and a normal ramp-down is executed
thereby turning the power module off. To restart the ramp
generator, DTX and TRIG have to go LOW (TRIG has to
stay LOW for more than two clock periods). The next
LOW-to-HIGH transition will cause a ramp-up again.
6.2
Primary start condition
When the power supply is first switched on, the PCF5075
is in an undefined state because the chip has neither a
power-on-reset nor a reset pin. Initialisation of the digital
part is therefore necessary.
The contents of the power-level register (PL7-to-PL0)
determines which of 256 possible values the top of the
clock period burst will have.
The easiest way of doing this is to perform a short dummy
ramp-up/ramp-down sequence, apply the 13 MHz master
clock, make PD LOW and then toggle TRIG
LOW-HIGH-LOW for more than two clock periods in the
HIGH state. The chip will stay initialized as long as the
supplies are on. After this, recognition of the 13 MHz
master clock and TRIG will be influenced by PD.
To match the controller to different power modules and
sensors, several parameters must be adjusted:
1. The typical value of the external capacitors
C1 and C2. C1 determines the maximum bandwidth
of the power control loop, depending on the highest
steepness of the control curve of the power module
and on the sensor attenuation (see Fig.4).
6.2.1
POWER-DOWN (PD) HIGH
2. The upper voltage limit of VO(INT) (pin 18). To protect
the power module; the output of VO(INT) can be limited
to 3.75 V, 3.1 V or 2.35 V, depending on the contents
of the limiter register (lim1-to-lim0). The fourth limiter
register word can be used to switch the limiter option
off. This limiting results in a ringing at VO(INT)
(200 mV (p-p) typ.) but, because the power module is
in saturation, it will not transfer the ringing to the
antenna.
The serial bus interface is operating, and all registers can
be programmed, but no effect will be seen on any pin.
The contents of the registers are passed to the rest of the
circuit only during power-up and with the 13 MHz master
clock applied.
Also, because the LOW-input swing buffer at pin CL13 is
switched off, neither the adder nor the slope generator will
function. This means that after the chip is powered-up, the
outputs have to settle again to the programmed register
values. The settling time is dominated by the slow
power-up of the band gap of typically 250 µs.
3. The HOME VO(INT) position. The integrator output
voltage at home position (PD and TRIG LOW) must be
programmed with the VHOME register. Bits Vh5-to-Vh0
are fed into a 6-bit DAC that generates a part of
VHOME
.
1997 Feb 27
6
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
If the chip is used in the burst mode it is important to switch
on the PCF5075 before the power module or the
RF-power; otherwise it is possible that a positive spike at
V(INT)o will open the power module. A minimum period of
6.3
The analog integrating controller
The analog integrating controller consists of three
operational amplifiers (OP1, OP2 and OP4) and one
comparator. OP1 and OP2 are only used for buffering
purposes, OP4 is used to form a differential integrator.
The comparator is used to limit the integrator output
voltage to the value selected by the ‘lim’-bits in the serial
register.
tON = 400 µs should be allowed between activating the
PCF5075 (via PD) and activating the power module
(externally, generally via TRIG). See Fig.3.
6.2.2
POWER-DOWN (PD) LOW
A two (Schottky) diode external rectifier is connected to
pins VSR, VS2, IBIAS and VS1.
The whole chip is active. Pin CL13 clocks the internal state
machine as well as the adder and slope generator. Every
change at TRIG is recognized if the master clock is
running. The contents of the serial bus registers are
processed. If the master clock is switched off during
power-up, the state machine is stopped and the output of
the adder/slope generator becomes undefined.
Nevertheless, by reactivating the master clock, the output
of the adder/slope generator will settle to the old values
again.
The SC-Adder block basically generates the voltage
V
SR − 2VD1 + VPL.The differential integrator then
integrates the difference of this voltage and the voltage
SR − 2VD1 + VRFIN. The integrator output voltage VO(INT)
V
is used to control the power amplifier module.
Table 1 Definition of some voltages (see Fig.1)
SYMBOL
DESCRIPTION
VSR
VD1
VPL
bias voltage output for sensor (band gap voltage), typically 1.25 V
voltage over the (external) Schottky diode D1
voltage determining the power level; it is generated in the SC-Adder block if switch DACA is closed
(i.e. if the signal DACA is HIGH); equals 2.4 times the DAC8 output
VRFIN
voltage difference at pin VS1 when RF is rectified at the sensor diode D2
buffered voltage from pin VS1
VBVS1
VKICK
kick voltage; if KICKA is HIGH, DAC8 outputs this voltage
VKOMP
VRAMPR
voltage at R3 if the circuit is switched to the home position by HPA; VKOMP compensates VKICK at R2
buffered output voltage of the slope generator; steady state limits of some succeeding filtered voltage
steps (not 1:1 visible at pin VINT(p)
)
HPA/KICKA active: VSR − 2VD1 + VKICK
DACA active: VSR − 2VD1 + VPL
QRSA active: VSR − 2VD1 − VQRS
VHOMEIN
VQRS
if HPA is active, DAC6 outputs the value of the VHOME register which is directly visible only at pin 18;
VHOMEIN also contains the diode forward voltages nVF (with n = 0,1 or 2; VF ≈ 700 mV at Tamb = 27 oC)
0 or 100 mV; 0 V only if a ‘Quick Restart’ condition is detected; otherwise, if QRSA is active, DAC8
outputs 100 mV; this voltage is inverted by the adder and causes a ramp-down with a shortened tail
1997 Feb 27
7
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
because DACA becomes inactive and QRSA active.
6.4
Ramp generation (see Fig.3)
This additional subtraction of 100 mV causes a
The circuit is activated with the PD signal going LOW
before time mask ‘AS’ and deactivated after
ramping-down, by PD going HIGH between ‘GS’ and ‘HS’.
ramp-down with a shortened tail.The slope generator
again generates a smooth curve between the new adder
output voltage and the old adder output voltage. The slope
generator must have reached its final value 38Tcy after the
recognized falling edge of TRIG because the signal HPA
is activated again and by that turning the integrator into its
‘home position’ (‘G’).The integrator output voltage will be
regulated once more to the value defined in the VHOME
For the (usual) ‘power-down burst mode’ application in
GSM/PCN mobile stations, the RF input power at the
power module must be activated between ‘AS’ and ‘BS’
(when the home position at VO(INT) has already reached its
stable value) and deactivated between ‘GS’ and ‘HS’. This
is necessary for many types of power modules to meet the
−70 dB margin. For quick restart after ramping-down see
Chapter 12.
register. The adder output voltage is VSR − 2VD1 + VKICK
The voltage VKICK is subtracted at VINT(n) by VKOMP while
the home position is active (see Fig.1). Thus the resulting
.
voltage at VO(INT) has the programmed value VHOME
.
A ramp-up is started by a positive edge on TRIG. To be
able to detect a quick restart (base station applications
only) the TRIG signal is internally delayed by two clock
periods. Because of this, all other internal signals are
delayed by two clock periods with respect to the signal at
pin TRIG.
Figures 4, 5 and 6 show measurements of the circuit in
application.
6.4.2
STABILITY
Figure 6 shows the result of a special test. A static power
level was chosen where the steepness of the control curve
of a worst case power module sample has the highest
value. This value usually is approximately 6 to 10 dB less
than the maximum possible power. Capacitors C1 and C2
are now reduced to the point where the loop is close to the
limit of stability. A gain peaking at the critical frequency
occurs and noise increases. By this easy procedure the
critical frequency and the critical value for C1 = C2 can be
found. These capacitances must now be increased by a
factor of 2 to 4 for sufficient stability reserve.
Figure 3 shows a possible relationship between the chip
timing (points ‘B’, ‘C’, ‘E’ and ‘G’) and the GSM-mask
standard (points ‘AS’, ‘BS’, ‘CS’, ‘DS’, ‘ES’, ‘FS’, ‘GS’ and
‘HS’). However, the user is free to choose t1 and t2
independently so that the mask is not violated.
6.4.1
DESCRIPTION OF SIGNALS
Signals starting at a stable home position of VO(INT) at time
B − 2Tcy are considered.
The integrator output voltage is regulated to the value
defined in the VHOME register. The output of the slope
generator is VSR − 2VD1 + VKICK and is connected to the
positive input VINT(p) of operational amplifier OP4 (VKICK is
defined by the ‘Vk’-bits in the VKICK register). Two clock
periods after a positive edge on TRIG the integrator start
condition circuitry is turned off and OP4 is switched into an
integrator configuration (‘B’). Now the HPA switches are
6.4.3
CLOCK INFLUENCE
The resulting loop band width must be smaller than the
internal clock frequency fclk = 2.166 MHz. A gain peaking
effect at fclk must be avoided, low pass filters between
pin VO(INT) and the input of the power module will reduce
the stability margin and this can cause an unwanted gain
at fclk. As shown in the block diagram (see Fig.1) a
non-critical serial resonant circuit at pin VINT(p) is
recommended.
open. Due to the positive differential input voltage VKICK
,
the integrator output will start to rise. After 18Tcy (‘C’) the
output of DAC8 is connected to the adder and slope
generator block. The input of the 8-bit DAC comes from
PL7 to PL0 of the power level register. The slope
generator will generate a smooth curve between the
former and the new output value of the adder block.
The voltage VRAMPR at the end is VSR − 2VD1 + VPL, thus
the power amplifier is ramped-up via the integrator in
approximately 22Tcy.
This condition is stable providing TRIG remains HIGH.
Two clock periods after a negative edge at TRIG the
ramp-down is started (‘E’).The adder output voltage will
change to VSR − 2Vd1 − VQRS (VQRS = 100 mV typ.),
1997 Feb 27
8
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
AS
BS
CS
DS
)
ES
FS
GS
HS
22T
18T
22T
22T
18T
22T
cy
cy
cy
t
cy
cy
cy
dB
t
(8T
(2T
)
1
2
cy
cy
4
1
1
6
30
70
T
B
C
E
G
18T
38T
cy
cy
44T
2T
2T
cy
cy
400 µs
T
OFF
cy
ON
TRIG
PD
KICKA
HPA
QRSA
DACA
RFIN
(7)
(1)
(2)
V
INT(p)
(3)
(4)
(5)
(6)
MBE725
(OP4)
(1) tRFON = tON − 12Tcy to tON + 2Tcy
(2) tRFOFF = 44Tcy to 66Tcy
.
.
(3)
(4)
(5)
V
V
V
SR − 2Vd1 + VKICK (start integrator).
SR − 2Vd1 + VPL
SR − 2Vd1 − Vqrs
.
.
(6) (VSR − 2Vd1 + VKICK + VHOMEIN)/3.
(7) This timing to the RF input power of the power module ensures that the −70 dB margin is met, even if the isolation of the power module is bad.
Fig.3 Timing of a typical ramp-up/ramp-down curve.
1997 Feb 27
9
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
REF 42.4 dBm
GTSMP
ATTEN 30 dB
MGC567
LOG
10
dB/
OFFST
23.0
dB
ARFCN
1
TN 0
WA SB
SC EC
CORR
40
CENTER 890.200 MHz
# RES BW 300 kHz
28
18 10
0 µs
32
SPAN 0 Hz
# SWP 80 µs
# VBW 300 kHz
Fig.4 Ramp-up.
REF 41.8 dBm
GTSMP
ATTEN 30 dB
MGC570
LOG
10
dB/
OFFST
23.0
dB
ARFCN
1
TN 0
WA SB
SC EC
CORR
543 µs
553 561
571
591
SPAN 0 Hz
CENTER 890.200 MHz
# RES BW 300 kHz
# VBW 300 kHz
# SWP 80 µs
Fig.5 Ramp-down.
1997 Feb 27
10
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
25.7 dBm
# ATTEN 20 dB
MBE717
OUTPUT RF SPECTRUM
modulation
LOG
10
dB/
LIMIT PASS
OFFST
16.6
dB
ARFCN
62
TN 0
−2.166 MHz
2.166 MHz
WA SB
SC FC
CORR
CENTER 902.400 MHz
# RES BW 30 kHz
SPAN 5.000 MHz
# SWP 2.00 sec.
# VBW 30 kHz
Fig.6 Modulation spectrum.
6.5
Serial bus programming
6.6
Data format
A simple 3−wire unidirectional serial bus is used to
program the circuit. The 3 wires are Data, Clock and
Strobe. The data sent to the device is loaded in bursts
framed by Strobe. Programming clock edges and their
appropriate data bits are ignored until Strobe goes active
LOW. The programmed information is loaded into the
addressed latch when Strobe returns inactive HIGH. Only
the last 16 bits serially clocked into the device are retained
within the programming register. Additional leading bits
are ignored, and no check is made on the number of clock
pulses. The fully static CMOS design uses virtually no
current when the bus is inactive. The bus is also
programmable during power-down.
Data is entered with the most significant bit (MSB) first.
The leading bits make up the data field, while the trailing
four bits are an address field. The PCF5075 uses only one
of the available addresses. The format is given in Table 2.
The trailing address bits are decoded upon the inactive
Strobe edge. This produces an internal load pulse to store
the data in one of the addressed latches. To avoid
erroneous circuit operation, the strobe pulse is not allowed
during internal data reads by the rest of the circuit. This
condition is guaranteed by respecting a minimum Strobe
pulse width after data transfer (see Chapter 10).
1997 Feb 27
11
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
Table 2 Programming register bit usage
DATA BITS
SUBADDRESS
DEVICE ADDRESS
MSB
LSB
p15
pxx
p7
p6
p5
p4
p3
p2
p1
p0
data9
datax
data1
data0
Sadd1
Sadd0
add3
add2
add1
add0
The correspondence between data and address fields is given in Table 3.
Table 3 Register bit allocation
DATA FIELD (D9 TO D0)
MSB
SUB
ADDRESS
DEVICE ADDRESS
LSB
p15
Vk5
Vh5
p14
Vk4
Vh4
p13
Vk3
Vh3
p12
Vk2
Vh2
p11
Vk1
Vh1
p10
Vk0
Vh0
p9
p8
p7
p6
p5
p4
0
p3 p2 p1
0
0
0
0
Lim1 Lim0 nu(1)
DVh1 DVh0 nu(1)
nu(1)
nu(1)
0
0
1
1
1
1
0
0
0
1
1
1
1
PL7(2) PL6(2) PL5(2) PL4(2) PL3(2) PL2(2) PL1(2) PL0(2) DF1(4) DF0(3)
1
Notes
1. nu = not used.
2. PL = power level.
3. DF0 = data on DF output.
4. DF1 = enable of this output for DF1 = 0 pin DF is in 3-state mode.
Table 4 Limiter voltage
TOLERANCE AT
TOLERANCE AT
Tamb = 85 °C
LIM1
LIM0
LIMITER VOLTAGE
T
amb = 27 °C
±250 mV
±250 mV
±250 mV
−
0
0
1
1
0
1
0
1
2.35 V
3.10 V
±350 mV
±350 mV
±350 mV
−
3.75 V
limiter off
Table 5 DVh diode offset for VHOME
(1)(2)
DVH1
DVH0
VHOME
Vh
0
0
1
1
0
1
0
1
Vh+ VF
Vh + 2VF
VDD
Notes
1. Vh = voltage programmed into Vh5 to Vh0 generated by DAC6 (max. 2 V at VSR = 1.25 V).
2. VF = an internally generated diode voltage drop with 0.7 V ±50 mV at Tamb = 25 °C or 0.7 V +50 to −100 mV at
Tamb = 85 °C (TC ≈ −2 mV/°C).
1997 Feb 27
12
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
6.6.1
Vk BITS
The Vk bits control the kick voltage in 64 steps of 4.8 mV per step.
6.6.2
Vh BITS
The Vh bits control the home position voltage in 64 steps of 32 mV per step.
6.6.3
PL BITS
The PL bits control the ramp-up top level voltage (equal to power level) in 256 steps of 11.7 mV per step.
7
LIMITING VALUES
VDD = VDDD = VDDA; VSS = VSSD = VSSA; in accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
UNIT
supply voltage
7.0
7.0
V
VI
DC input voltage on all pins
DC current into any signal pin
total power dissipation
−0.5
−10
−
V
II
+10
83
mA
Ptot
Tstg
Tamb
mW
°C
storage temperature
−65
−40
150
85
operating ambient temperature
°C
8
OPERATING CHARACTERISTICS
Tamb = −40 to 85 °C; VDD = VDDA = VDDD; unless otherwise specified.
SYMBOL PARAMETER CONDITION
Operational amplifier (OP1)
MIN.
TYP.
MAX. UNIT
VDD
supply voltage
2.7
−
−
5.5
−
V
BG
gain bandwidth
positive slew rate
negative slew rate
at −3 dB
4
MHz
V/µs
V/µs
SR(p)
SR(n)
−
0.3
0.3
−
−
−
Operational amplifiers (OP2 and OP4)
VDD
BG
supply voltage
gain bandwidth
2.7
4
−
−
5.5
V
at −3 dB; unity gain;
−
MHz
CL = 120 pF; note 1
CMRR
PSRR
SR(p)
SR(n)
Vos
common mode rejection ratio
−
45
−
−
dB
dB
V/µs
V/µs
mV
V
power supply ripple rejection for unity gain
50
−
positive slew rate
negative slew rate
voltage offset
for unity gain; note 2
4.5
4.5
−7
−
−
for unity gain; note 2
no load at output
−
−
0
+7
0.5
−
CMil
common mode input low limit ± 5% tolerance; note 3
−
−
CMih
common mode input high
limit
± 5% tolerance;
notes 3 and 4
0.9VDD
−
V
Vo(min)
Vo(max)
minimum output voltage
maximum output voltage
for unity gain
−
−
−
0.3
V
V
for unity gain; note 4
0.85VDDD
−
1997 Feb 27
13
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
SYMBOL
RO
Resistors R1 and R2
PARAMETER
CONDITION
MIN.
TYP.
MAX. UNIT
small signal output resistance Iload = 2 mA at 1.9 V
−
5
10
Ω
R1
value of R1
Tamb = 25 °C
Tamb = 25 °C
6.7
6.7
−
8.4
8.4
2
10
10
−
kΩ
kΩ
%
R2
value of R2
Rmatch
matching between
R1 and R2
TC
temperature coefficient
−
0.13
−
%/°C
Programmability and accuracy of VPL
INLE
integral non-linearity error
differential non-linearity error
minimum output voltage
maximum output voltage
−
−
−
−
−
±10
±1
−
LSB
LSB
mV
V
DNLE
Vo(min)
Vo(max)
−
note 5
11.5
2.4VSR
notes 5 and 6
−
Programmability and accuracy of VKICK
INLE
integral non-linearity error
differential non-linearity error
minimum output voltage
maximum output voltage
−
−
−
−
−
±10
±1
−
LSB
LSB
mV
DNLE
Vo(min)
Vo(max)
−
note 5
note 5
4.8
312
−
mV
Programmability and accuracy of VHOME
INLE
integral non-linearity error
differential non-linearity error
minimum output voltage
−
−
−
−
±10
±1
−
LSB
LSB
mV
DNLE
Vo(min)
−
VSR = 1.25 V; Dvh1 = 0;
Dvh0 = 0; note 5
32
Vo(max)
maximum output voltage
VSR = 1.25 V; Dvh1 = 0;
Dvh0 = 0; note 5
−
2
−
V
Notes
1. Minimum specified frequency at Tamb = 27 °C; for Tamb = 85 °C a typical value of 4 MHz is specified.
2. Slew rates are measured between 10% and 90% of output voltage interval with a load of approximately 40 pF to
ground.
3. The tolerance band for the input range is defined as the interval where the output follows the input with ±5% tolerance
of the actual input value.
4. These values at Tamb = 25 °C are supply voltage and temperature dependent (TC = 3 mV/°C).
5. The value is dependent on VSR, for tolerance of VSR (see Chapter 9).
6. The maximum output is limited to VPL(max) = 0.85VDD
.
1997 Feb 27
14
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
9
DC CHARACTERISTICS
Tamb = −40 to 85 °C; VDD = VDDD = VDDA; VSS = VSSD = VSSA = 0 V; unless otherwise specified.
SYMBOL
PARAMETER
supply voltage
CONDITION
MIN.
2.7
TYP.
5.0
MAX.
5.5
UNIT
VDD
V
IDD(op)
IDD(idle)
total operating current
total idle current
fi = 13 MHz
−
−
9
2
15
20
mA
PD = HIGH
µA
Logic I/O’s (pins 4, 9, 10, 12 to 15)
IIL
LOW level input leakage current
VIL = 0.8 V
VIH = 2 V
−5
−5
−
−
5
5
−
µA
µA
pF
ILH
Ci
HIGH input leakage current
input capacitance
−
10
CL13, low-swing master clock input (pin 11)
IPD
input pull-down current in power-down Vi = 1 V; Tamb = 25 °C;
TC = −0.5%/°C; note 1
−
−
25
µA
Ci
input capacitance
−
10
5
−
pF
kΩ
V
Zi
input impedance
fi = 13 MHz; note 1
AC coupling = 33 pF
−
−
Vi(p−p)
input voltage (peak-to-peak value)
0.5
−
VDD
Sensor DC reference input voltage VS1 and VS2 (pins 1 and 6); note 2
VVS2
VVS1
input voltage
input voltage
0
−
−
VSR
V
−
0.9VDD
Bias current source IBIAS (pin 5)
IBIAS bias current source for D1 and D2
Vi = 1 V; Tamb = 25 °C;
TC = −0.22µA/°C
60
80
100
µA
VCM
voltage range
note 3
0.3
−
0.9VDD
V
Band gap voltage VSR (pin 7)
VSR
TC
bandgap voltage
Tamb = 25 °C
1.16
−
1.25
1.34
−
V
temperature coefficient for VSR
power-up time band gap
−0.175
250
mV/°C
µs
Tpu
note 4
−
−
Other analog I/O’s (pins 3, 18, 19 and 20)
IIL
Ci
input leakage current
input capacitance
Vi = 1 V
−15
−
15
µA
−
10
−
pF
Notes
1. In power down mode this input is inactive and switched to ground with more than 40 kΩ. An AC coupling with 33 pF
is recommended.
2. The voltage at pin VS2 = VSR − Vd1 with the forward voltage Vd1 ~ 250 mV of the DC reference diode D1 of the RF
sensor. Vd1 must not be influenced by RF because a voltage change at pin VS2 moves the input voltage of the adder
and slope generator.
3. Two 1 kΩ resistors close to the RF sensor diode D2 in the block diagram are necessary for RF decoupling.
4. The necessary start-up time TON = 400 µs (see Fig.3) between PD and TRIG is more than Tpd.
1997 Feb 27
15
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
10 TIMING CHARACTERISTICS
T
amb = −40 to +85 °C; VDD = VDDA = VDDD; VSS = VSSA = VSSD = 0 V; unless otherwise specified.
For timing see Fig.3; Tcy = 6⁄13 µs.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Controller timing
tqrs
negative pulse width on TRIG for quick restart recognition
negative pulse width on TRIG for no quick restart recognition
delay from positive TRIG edge to point B = 13⁄6Tcy
delay from point B to point C = 18Tcy
0.077
−
−
0.769 µs
tnoqrs
1.0
−
−
−
−
−
−
µs
µs
µs
µs
µs
td(TRIG-B)
td(B-C)
td(TRIG-E)
td(E-G)
1.0
−
8.31
1.0
delay from negative TRIG edge to point E = 13⁄6Tcy
−
delay from point E to point G = 38Tcy
−
17.54
Serial bus timing
SERIAL PROGRAMMING CLOCK (PIN 14)
tr
rise time
−
10
10
−
−
−
−
ns
ns
ns
tf
fall time
−
Tcy
clock period
100
ENABLE PROGRAMMING (PIN 13); note 1
tstart
tend
strobe set-up time to first clock edge
strobe hold time from first clock edge
40
20
−
−
−
−
ns
ns
REGISTER SERIAL INPUT DATA (PIN 15)
tsu
th
input data to CLK set-up time
input data to CLK hold time
20
20
−
−
−
−
ns
ns
Note
1. After rising edge of STROBE one more active CLK edge (LOW-to-HIGH transition) completes the transfer.
t
T
t
t
end
su
cy
h
CLK
Data
MSB
Ladrs
Strobe
t
t
t
end
start
start
MBE730
Fig.7 Serial bus timing diagram.
16
1997 Feb 27
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
The DF pin (pin 12) can be used to switch a 13 dB
11 APPLICATION INFORMATION
11.1 Switching the dynamic range
attenuator, right after the sensor, into the antenna
path.This has the advantage of not changing the
behaviour of the loop, however, the disadvantage is
introducing a certain amount of attenuation when switched
off. Alternatively, as shown in Fig.8, a gain stage can be
switched at the sensor. By doing this the loop gain and the
bandwidth of the loop will be switched. Consequently, at
least a 13 dB stability margin is needed if the switchable
gain stage has a range of 13 dB.
For GSM phase 2 and PCN, some very low power levels
are needed. The control voltage VPL can be as low as
30 mV. This equates approximately to the 3 LSB of the
power level register, giving minimum adjustments of
approximately 30⁄8 mV. This does not provide acceptable
accuracy and other methods must be employed to allow
the PCF5075 to be used.
antenna
sensor
RFIN
RF POWER
AMPLIFIER
900 MHz
4 to 9 dB
33 pF
33 pF
1 kΩ
1
kΩ
1 kΩ
10
9
8
7
6
5
4
3
2
1
PCF5075
11 12 13 14 15 16 17 18 19 20
C1
180
pF
13 MHz
C2
33 pF
180
pF
3-wire
serial
bus
100
µH
50 pF
MBE727
Fig.8 Application diagram for mobile stations.
17
1997 Feb 27
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
Therefore, only one diode is recommended for the
11.2 Additional application information
modules BGY20x. The fine temperature matching must be
done by software. Details about this matching are shown
in plot 3 of the PSPICE package.
An evaluation kit with software and demonstration boards
is available for the PCF5075 together with the power
modules BGY20x. Additionally, a package of PSPICE
models with several plots and descriptions is also
available which will provide help for applications.
Curve 1 in Fig.9 shows what happens if the home position
of VO(INT) has the highest usable value. This behaviour is
matched to meet the −6 dB margin and the −30 dB margin
at the power level −13 dBm. The −70 dB margin will be met
by optimizing the time where the RF input power of the
power module is activated.
Very little bus traffic is required for the PCF5075 because
the ramping curves are generated on-chip. VKICK and
VHOME define the start conditions for up-ramping. VPL
determines the power levels. TRIG is the trigger for up and
down-ramping.
Curve 2 in Fig.9 results if the home position has the lowest
usable value. Here the ramping curve seems to be optimal,
but the switching spectrum is at the limit. This behaviour
occurs when the regulator, which is integrating VKICK, has
not yet reached the active part of the power module control
curve and thus the step of the slope generator has the
highest steepness. In this situation the power ramps-up
with a delay and with increased steepness as can be seen
in the curve.
The non-linear behaviour of the control curves of the
power modules have a big influence on the loop. Start
conditions in the flat area of the control curve are critical
and need some attention. Initially VO(INT) will be at the
home position. The switches HPA release the regulator.
The integrator now must be moved into the active part of
the control curve. This is achieved by integrating VKICK
.
When VO(INT) has reached the active region of the control
curve the loop is closed and the circuit is able to follow the
ramping function generated by a voltage step to the slope
generator. The step height VPL determines the power of
the transmit burst. Down-ramping is started at the slope
generator input by a voltage step from VPL back to
−100 mV. The loop follows the leading function for
down-ramping until the RF sensor measures zero. The
sensor signal is not able to go to −100 mV because this
would represent a negative power. The reason for the
−100 mV in the leading function is to shorten the tail of
the slope.
For the power level −13 dBm the TRIG time may be shifted
a little by software. At all other power levels TRIG can be
kept constant.
11.2.1 THEORETICAL LIMIT FOR CORRECT DOWN-RAMPING
No loop is able to follow a leading value which is beyond a
physical limit. The power limit of any power module
depends on RF input power, transmit frequency, supply
voltage and load impedance. The maximum VPL must be
matched to the worst case output power and reduced by
1 dB. A distance of 1 dB is necessary because the
steepness of the control curve of the power module
decreases for higher output power. Incorrect behaviour is
shown in Fig.10. Curve 1 works correctly, but the module
is at the power limit. If the supply voltage is reduced now,
the theoretical principle of a loop design is violated. Thus
the down-ramping in curve 2 starts with a delay followed
by an increased steepness. The GSM margin for the
switching spectrum will only be met if the maximum value
of VPL is matched to the possibilities of the loop.
For VKICK a value of 60 mV is recommended, matched to
a kick power that is 8 dB below −13 dBm (see Fig.9).
Usually VKICK has a constant value for all power levels.
One of the highlights of the PCF5075 is that for matching
of the start behaviour only one parameter must be adapted
to the individual sample of the power module. This
parameter is the home position of VO(INT) that is set by
VHOMEIN. An optimized value must be chosen in production
for the life of the device. This value can be stored in an
EPROM. Software may help to adapt VHOMEIN to different
temperatures. The VO(INT) home position that has to be
programmed must be matched to the middle of the two
curves illustrated in Fig.9.
The programmable VO(INT) limiter (see Table 4) is foreseen
to protect the power module during error conditions such
as, for example, wrong antenna connection and not to
avoid the down-ramping behaviour of curve 2.
VHOMEIN is the sum of VHOME and of the diode forward
voltages with a typical negative temperature behaviour.
Two diodes are necessary for matching the behaviour of
the power module BGY20x. But if two diodes are chosen
(see Table 5), the absolute value of VO(INT) is so high that
there is not enough room for matching the start behaviour.
1997 Feb 27
18
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
REF 33.4 dBm
ATTEN 40 dB
+4 dB
MBE718
+1 dB
1 dB
LOG
10
6 dB
dB/
KICK
30 dB
1
2
70 dB
40
28
18
10
0 µs
32
# SWP 80 µs
CENTER 902.400 MHz
# RES BW 300 kHz
# VBW 300 kHz
(1) Curve 1: highest usable value.
(2) Curve 2: lowest usable value.
Fig.9 Power as a function of time; rising edge (behaviour at different worst case home positions of VO(INT)).
REF 34.8 dBm
ATTEN 40 dB
MBE719
LOG
10
dB/
2
6 dB
1
30 dB
70 dB
543 µs
553
561
571
591
# SWP 80 µs
CENTER 902.400 MHz
# RES BW 1.0 MHz
# VBW 300 kHz
(1) Curve 1: correct behaviour.
(2) Curve 2: unusable behaviour with wrong VPL value.
Fig.10 Power as a function of time, falling edge.
19
1997 Feb 27
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
(see Fig.11). It should be noted that at time ‘E’ the voltage
at the positive input of OP4 is now 100 mV higher than
without quick restart, which causes the slower and less
steep ramp-down. A normal ramp-up will restart after 38
clock periods. Burst 1 and Burst 2 can have different
power levels if the PL register is reprogrammed between
time ‘E’ and ‘G’.
12 APPENDIX A: BASE STATION FEATURES
In base station applications a so called ‘quick restart’ is
used and performs the following. When a quick restart
condition is detected, which means TRIG goes LOW for a
period of less than two clock periods, the integrating
controller is not totally turned off. This enables the
controller to ramp-up faster after a ramp-down
AS
BS
CS
DS
ES
FS
GS
HS
22T
18T
22T
22T
18T
22T
cy
cy
cy
t
cy
cy
cy
t
dB
1
2
4
1
1
6
BURST 1
BURST 2
30
70
B
C
E
G
18T
38T
cy
cy
2T
2T
cy
cy
TRIG
PD
KICKA
HPA
QRSA
DACA
V
INT(p)
(OP4)
(1)
(2)
(3)
(4)
MBE724
(1)
(2)
(3)
(4)
V
V
V
V
SR − 2Vd1 + VKICK (start integrator).
SR − 2Vd1 + VPL
SR − 2Vd1
SR − 2Vd1 + VPL
Fig.11 Base station features timing diagram.
20
1997 Feb 27
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
13 APPENDIX B: BEHAVIOURAL MODELS
2.4
0.5
2
-3E5
V
DAC
V
SR
VS2
K
B
-1.9E11
A
k.(A ± B)
=
-6E5
/
d
dt
MBE723
V
O
Fig.12 Schematic diagram.
In ESPICE syntax:
bm0 gain v(a0) = 2.4 * v(vdac)
bm1 sub v(a1) = 0.5 * (v(a0) − v(VSR))
bm2 add v(a2) = 2.0 * (v(a1) + v(VS2))
bm3 add v(v1) = (v(a2) + v(v2))
bm4 int v(v2) = −3e5 * INT v(v1)
bm5 dif v(v3) = −6e5 * DIF v(vout)
bm6 add v(v4) = −1.9e11 * (v(vout) + v(v2))
bm7 add v(v5) = (v(v3) + v(v4))
bm8 int v(v6) = INT v(v5)
bm9 int v(vout) = INT v(v6)
1997 Feb 27
21
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
R1
A1
R2
R3
A3
V
O
V
V
INT(p)
A2
C1
C2
INT(n)
MBE722
First pole at 1.7 kHz (typ.) → R1 = 1/2/pi/1700; C1 = 1.
Second pole at 7 MHz (typ.) → R2 = 1/2/pi/7000000; C1 = 1.
DC gain 72 dB → A1 = 3980; A2 = 1; A3 = 1.
RO = 5 Ω (typ.) → R3 = 5 Ω.
A1, A2 and A3 are the gains of voltage controlled voltage sources.
Fig.13 Operational amplifiers 2 and 4 schematic diagram.
14 APPENDIX C: AC SIMULATIONS FOR OPERATIONAL AMPLIFIERS 2 AND 4
100 µH
low pass
filter in the
power module
180 pF
10 pF
VS1
BGY203
50 pF
8.4 kΩ
10 pF
BVS1
180 pF
OP4
V
V
INT(n)
1 kΩ
LP
OP2
1 kΩ
V
INT(o)
8.4 kΩ
INT(p)
DC level
80 pF
DC level
MBE721
Fig.14 Operational amplifiers 2 and 4 circuit diagram.
22
1997 Feb 27
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
The simulation output illustrated in Fig.15 shows the worst and typical cases for the integrator configuration (TRIG HIGH).
The signals are drawn for node LP.
MBE720
100
60
nominal case
20
(phase)
(amplitude)
worst case
-20
-60
10
2
3
4
5
6
7
10
10
10
10
10
Fig.15 Simulation output.
1997 Feb 27
23
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
15 PACKAGE OUTLINE
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
D
E
A
X
c
y
H
v
M
A
E
Z
11
20
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
10o
0o
0.15
0
1.4
1.2
0.32
0.20
0.20
0.13
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.45
0.65
0.45
0.48
0.18
mm
1.5
0.65
1.0
0.2
0.25
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
90-04-05
95-02-25
SOT266-1
1997 Feb 27
24
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
If wave soldering cannot be avoided, the following
conditions must be observed:
16 SOLDERING
16.1 Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
16.2 Reflow soldering
Reflow soldering techniques are suitable for all SSOP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
16.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
16.3 Wave soldering
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Feb 27
25
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
17 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Feb 27
26
Philips Semiconductors
Product specification
Power amplifier controller for GSM and
PCN systems
PCF5075
NOTES
1997 Feb 27
27
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Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
437027/1200/03/pp28
Date of release: 1997 Feb 27
Document order number: 9397 750 01629
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Communications
l CMOS low-voltage, low-power
l Can be used in burst mode with power-down
l Three-wire serial bus interface with the bus available in power-down mode
l On-chip ramp generator for 256 different power levels
l Extendable dynamic range
PC/PC-peripherals
Cross reference
Models
Packages
l Two programmable regulator start conditions, VKICK and VHOME
l Programmable analog output voltage limitation
l Ramping speed depending on the 13 MHz system frequency clock for Global System for Mobile communications (GSM) and
Personnel Communications Network (PCN)
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
l Low swing input buffer for the 13 MHz master clock
l Compatible with a large number of different RF power modules
l Programmable temperature matching
l Quick restart option.
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PCF5075
PCF5075
Type nr. Title
Datasheet
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PCF5075 Power amplifier controller for GSM and 27-Feb-97
PCN systems
Product
Specification
24
216
Blockdiagram
Blockdiagram of PCF5075T
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
Partnumber
marking/packing
package device status buy online
SOT266 Full production
Standard Marking * Reel Dry Pack,
SMD, 13"
PCF5075T/F2 PCF5075TDK-T
9351 852 40518
Please read information about some discontinued variants of this product.
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