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PCF8535U [NXP]

65 x 133 pixel matrix driver; 65 X 133像素矩阵驱动器
PCF8535U
型号： PCF8535U
厂家： NXP    NXP
描述：

65 x 133 pixel matrix driver
65 X 133像素矩阵驱动器

显示驱动器 驱动程序和接口 接口集成电路
文件： 总52页 (文件大小：1041K)
中文：  中文翻译
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INTEGRATED CIRCUITS  
DATA SHEET  
PCF8535  
65 × 133 pixel matrix driver  
Objective specification  
1999 Aug 24  
File under Integrated Circuits, IC12  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
CONTENTS  
7.10  
Bias system  
7.10.1  
7.11  
7.11.1  
7.12  
7.12.1  
7.13  
7.13.1  
7.14  
7.14.1  
7.15  
7.15.1  
7.15.2  
7.16  
7.16.1  
7.16.2  
7.16.3  
7.16.4  
7.16.5  
7.16.6  
7.17  
Set bias system  
1
2
3
4
5
FEATURES  
Temperature measurement  
Temperature read back  
Temperature compensation  
Temperature coefficients  
VOP  
Set VOP value  
Voltage multiplier control  
S[1:0]  
Addressing  
Input addressing  
Output addressing  
Instruction set  
RAM read/write command page  
Function and RAM command page  
Display setting command page  
HV-gen command page  
Special feature command page  
Instruction set  
I2C-bus interface  
Characteristics of the I2C-bus  
I2C-bus protocol  
APPLICATIONS  
GENERAL DESCRIPTION  
ORDERING INFORMATION  
BLOCK DIAGRAM  
5.1  
Block diagram functions  
Oscillator  
Power-on reset  
I2C-bus controller  
Input filters  
Display data RAM  
Timing generator  
Address counter  
Display address counter  
5.1.1  
5.1.2  
5.1.3  
5.1.4  
5.1.5  
5.1.6  
5.1.7  
5.1.8  
6
PINNING  
6.1  
Pin functions  
R0 to R64  
C0 to C132  
6.1.1  
6.1.2  
6.1.3  
6.1.4  
6.1.5  
6.1.6  
6.1.7  
6.1.8  
6.1.9  
6.1.10  
6.1.11  
6.1.12  
6.1.13  
6.1.14  
7.17.1  
7.17.2  
VSS1 and VSS2  
VDD1 to VDD3  
VLCDOUT  
VLCDIN  
VLCDSENSE  
SDA  
SDAOUT  
SCL  
SA0 and SA1  
OSC  
8
LIMITING VALUES (PROVISIONAL)  
HANDLING  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
DC CHARACTERISTICS  
AC CHARACTERISTICS  
RESET TIMING  
APPLICATION INFORMATION  
BONDING PAD LOCATIONS  
DEVICE PROTECTION DIAGRAM  
TRAY INFORMATION  
RES  
T1, T2, T3, T4 and T5  
7
FUNCTIONAL DESCRIPTION  
DEFINITIONS  
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
7.7  
7.8  
7.9  
Reset  
Power-down  
LCD voltage selector  
Oscillator  
Timing  
Column driver outputs  
Row driver outputs  
Drive waveforms  
Set multiplex rate  
LIFE SUPPORT APPLICATIONS  
PURCHASE OF PHILIPS I2C COMPONENTS  
BARE DIE DISCLAIMER  
1999 Aug 24  
2
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
1
FEATURES  
• Single-chip LCD controller/driver  
• 65 row, 133 column outputs  
• Display data RAM 65 × 133 bits  
• 133 icons (last row is used for icons)  
• Fast mode I2C-bus interface (400 kbits/s)  
2
APPLICATIONS  
• Software selectable multiplex rates:  
• Automotive information systems  
• Telecommunication systems  
• Point-of-sale terminals  
• Instrumentation.  
1 : 17, 1 : 26, 1 : 34, 1 : 49 and 1 : 65  
• On-chip:  
– Generation of intermediate LCD bias voltages  
– Oscillator requires no external components  
(external clock also possible)  
– Generation of VLCD  
.
3
GENERAL DESCRIPTION  
• CMOS compatible inputs  
The PCF8535 is a low power CMOS LCD row/column  
driver, designed to drive dot matrix graphic displays at  
multiplex rates of 1 : 17, 1 : 26, 1 : 34, 1 : 49 and 1 : 65.  
Furthermore, it can drive up to 133 icons. All necessary  
functions for the display are provided in a single chip,  
including on-chip generation of LCD bias voltages,  
resulting in a minimum of external components and low  
power consumption. The PCF8535 is compatible with  
most microcontrollers and communicates via an industry  
standard two-line bidirectional I2C-bus serial interface.  
All inputs are CMOS compatible.  
• Software selectable bias configuration  
• Logic supply voltage range VDD1 to VSS1 4.5 to 5.5 V  
• Supply voltage range for high voltage part VDD2 and  
VDD3 to VSS2 and VSS3 4.5 to 5.5 V  
• Display supply voltage range VLCD to VSS  
:
– Mux rate 1 : 65: 8 to 16 V.  
• Low power consumption, suitable for battery operated  
systems  
• Internal Power-on reset and/or external reset  
• Temperature read back available  
• Manufactured in N-well silicon gate CMOS process.  
4
ORDERING INFORMATION  
TYPE NUMBER  
PACKAGE  
NAME  
DESCRIPTION  
chip with bumps in tray  
VERSION  
PCF8535U  
−
−
1999 Aug 24  
3
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
5
BLOCK DIAGRAM  
V
V
V
DD3  
R0 to R64  
65  
C0 to C132  
133  
DD1  
DD2  
V
V
ROW  
DRIVERS  
COLUMN  
DRIVERS  
SS1  
SS2  
POWER-ON RESET  
INTERNAL  
RESET  
T4, T5  
PCF8535  
RES  
OSC  
T1, T2, T3  
DATA LATCHES  
OSCILLATOR  
BIAS  
VOLTAGE  
GENERATOR  
MATRIX  
LATCHES  
V
LCDIN  
TIMING  
GENERATOR  
DISPLAY DATA RAM  
V
LCDSENSE  
DISPLAY  
ADDRESS  
COUNTER  
V
LCD  
MATRIX DATA  
RAM  
GENERATOR  
V
LCDOUT  
SCL  
SDA  
2
INPUT  
FILTERS  
I C-BUS  
COMMAND  
DECODER  
ADDRESS  
COUNTER  
CONTROL  
SDAOUT  
MGS669  
SA1 SA0  
Fig.1 Block diagram.  
4
1999 Aug 24  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
5.1  
Block diagram functions  
5.1.5  
DISPLAY DATA RAM  
5.1.1  
OSCILLATOR  
The PCF8535 contains a 65 × 133 bit static RAM which  
stores the display data. The RAM is divided into 9 banks of  
133 bytes. The last bank is used for icon data and is only  
one bit deep. During RAM access, data is transferred to  
the RAM via the I2C-bus interface. There is a direct  
correspondence between the X address and the column  
output number.  
The on-chip oscillator provides the display clock for the  
system; it requires no external components. Alternatively,  
an external display clock may be provided via the OSC  
input. The OSC input must be connected to VDD1 or VSS1  
when not in use. During power-down additional current  
saving can be made if the external clock is disabled.  
5.1.6  
TIMING GENERATOR  
5.1.2  
POWER-ON RESET  
The timing generator produces the various signals  
required to drive the internal circuitry. Internal chip  
operation is not disturbed by operations on the data bus.  
The on-chip Power-on reset initializes the chip after  
power-on or power failure.  
5.1.3  
I2C-BUS CONTROLLER  
5.1.7  
ADDRESS COUNTER  
The I2C-bus controller detects the I2C-bus protocol, slave  
address, commands and display data bytes. It performs  
the conversion of the data input (serial-to-parallel).  
The PCF8535 acts as an I2C-bus slave and therefore  
cannot initiate bus communication.  
The Address Counter (AC) sends addresses to the Display  
Data RAM (DDRAM) for writing.  
5.1.8  
DISPLAY ADDRESS COUNTER  
The display is generated by continuously shifting rows of  
RAM data to the dot matrix LCD via the column outputs.  
The display status (all dots on or off, normal or inverse  
video) is set via the I2C-bus.  
5.1.4  
INPUT FILTERS  
Input filters are provided to enhance noise immunity in  
electrically adverse environments; RC low-pass filters are  
provided on the SDA, SCL and RES lines.  
1999 Aug 24  
5
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
6
PINNING  
SYMBOL  
PAD  
DESCRIPTION  
1
dummy pad  
2
bump/alignment mark 1  
LCD row driver outputs  
LCD column driver outputs  
LCD row driver outputs  
bump/alignment mark 2  
dummy pad  
R0 to R15  
3 to 18  
C0 to C132  
R47 to R33  
19 to 151  
152 to 166  
167  
168  
R48 to R64  
169 to 185  
186  
LCD row driver outputs; R64 is icon row  
bump/alignment mark 3  
dummy pad  
187 to 189  
190  
OSC  
oscillator  
VLCDIN  
191 to 196  
197 to 203  
204  
LCD supply voltage  
voltage multiplier output  
VLCDOUT  
VLCDSENSE  
voltage multiplier regulation input (VLCD  
)
205 and 206  
207  
dummy pad  
RES  
T3  
external reset input (active LOW)  
test output 3  
208  
T2  
209  
test output 2  
T1  
210  
test output 1  
VDD2  
VDD3  
VDD1  
211 to 218  
219 to 222  
223 to 228  
229  
supply voltage 2  
supply voltage 3  
supply voltage 1  
dummy pad  
SDA  
SDAOUT  
SA1  
SA0  
VSS2  
VSS1  
T5  
230 and 231  
232  
I2C-bus serial data inputs  
I2C-bus serial data output  
I2C-bus slave address input  
I2C-bus slave address input  
ground 2  
233  
234  
235 to 242  
243 to 250  
251  
ground 1  
test input 5  
T4  
252  
test input 4  
253  
dummy pad  
SCL  
254 and 255  
256  
I2C-bus serial clock inputs  
bump/alignment mark 4  
LCD row driver outputs  
R32 to R16  
257 to 273  
6.1  
6.1.1  
Pin functions  
R0 TO R64  
These pads output the display row signals.  
1999 Aug 24  
6
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
6.1.2  
C0 TO C132  
and the Indium Tin Oxide (ITO) track resistance. It is  
possible that during the acknowledge cycle the PCF8535  
will not be able to create a valid logic 0 level. By splitting  
the SDA input from the SDAOUT output the device could  
be used in a mode that ignores the acknowledge bit.  
In COG applications where the acknowledge cycle is  
required or where read back is required, it is necessary to  
minimize the track resistance from the SDAOUT pad to the  
system SDA line to guarantee a valid LOW level.  
These pads output the display column signals.  
6.1.3  
VSS1 AND VSS2  
VSS1 and VSS2 must be connected together.  
6.1.4  
VDD1 TO VDD3  
VDD1 is the logic supply. VDD2 and VDD3 are for the voltage  
multiplier. For split power supplies VDD2 and VDD3 must be  
connected together. If only one supply voltage is available,  
all three supplies must be connected together.  
6.1.10 SCL  
I2C-bus serial clock input.  
6.1.11 SA0 AND SA1  
6.1.5  
VLCDOUT  
Least significant bits of the I2C-bus slave address.  
If, in the application, an external VLCD is used, VLCDOUT  
must be left open-circuit; otherwise (if the internal voltage  
multiplier is enabled) the chip may be damaged. VLCDOUT  
should not be driven when VDD1 is below its minimum  
allowed value otherwise a low impedance path between  
VLCDOUT and VSS1 will exist.  
Table 1 Slave address; see note 1  
SA1 AND SA0  
MODE  
write  
read  
write  
read  
write  
read  
write  
read  
SLAVE ADDRESS  
0 and 0  
78H  
79H  
7AH  
7BH  
7CH  
7DH  
7EH  
7FH  
6.1.6  
VLCDIN  
0 and 1  
1 and 0  
1 and 1  
This is the VLCD supply for when an external VLCD is used.  
If the internal VLCD generator is used, then VLCDOUT and  
VLCDIN must be connected together. VLCDIN should not be  
driven when VDD1 is below its minimum allowed value,  
otherwise a low impedance path between VLCDIN and VSS1  
will exist.  
Note  
6.1.7  
VLCDSENSE  
1. The slave address is a concatination of the following  
bits {01111, SA1, SA0 and R/W}.  
This is the input to the internal voltage multiplier regulator.  
It must be connected to VLCDOUT when the internal voltage  
generator is used otherwise it may be left open-circuit.  
VLCDSENCE should not be driven when VDD1 is below its  
minimum allowed value, otherwise a low impedance path  
between VLCDSENCE and VSS1 will exist.  
6.1.12 OSC  
If the on-chip oscillator is used this input must be  
connected to VDD1 or VSS1  
.
6.1.13 RES  
6.1.8  
SDA  
I2C-bus serial data input.  
External reset pad: when this pad is LOW the chip will be  
reset; see Section 7.1. If an external reset is not required,  
this pad must be tied to VDD1. Timing for the RES pad is  
given in Chapter 12.  
6.1.9  
SDAOUT  
SDAOUT is the serial data acknowledge for the I2C-bus.  
By connecting SDAOUT to SDA externally, the SDA line  
becomes fully I2C-bus compatible. Having the  
acknowledge output separated from the serial data line is  
advantageous in Chip-On-Glass (COG) applications.  
In COG applications where the track resistance from the  
SDAOUT pad to the system SDA line can be significant, a  
potential divider is generated by the bus pull-up resistor  
6.1.14 T1, T2, T3, T4 AND T5  
In applications T4 and T5 must be connected to VSS  
T1, T2 and T3 are to be left open-circuit.  
.
1999 Aug 24  
7
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
7
FUNCTIONAL DESCRIPTION  
The PCF8535 is a low power LCD driver designed to interface with microprocessors/microcontrollers and a wide variety  
of LCDs.  
The host microprocessor/microcontroller and the PCF8535 are both connected to the I2C-bus. The SDA and SCL lines  
must be connected to the positive power supply via pull-up resistors. The internal oscillator requires no external  
components. The appropriate intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip.  
The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and suitable  
capacitors for decoupling VLCD and VDD  
.
V
LCD  
V
to V  
DD3  
DD1  
V
DD(I2C)  
133 column drivers  
65 row drivers  
HOST  
LCD PANEL  
MICROPROCESSOR/  
MICROCONTROLLER  
R
R
PCF8535  
pu  
pu  
V
SS  
RES  
SA0  
SA1  
SCL  
SDA  
V
V
SS1, SS2  
MGS670  
Fig.2 Typical system configuration.  
1999 Aug 24  
8
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
7.1  
Reset  
7.3  
LCD voltage selector  
The PCF8535 has two reset modes; internal Power-on  
reset or external reset. Reset initiated from either the RES  
pad or the internal Power-on reset block will initialize the  
chip to the following starting condition:  
The practical value for VOP is determined by equating  
Voff(rms) with defined LCD threshold voltage (Vth), typically  
when the LCD exhibits approximately 10% contrast.  
7.4  
Oscillator  
• Power-down mode (PD = 1)  
The internal logic operation and the multi-level drive  
signals of the PCF8535 are clocked by the built-in RC  
oscillator. No external components are required.  
• Horizontal addressing (V = 0); no mirror X or Y  
(MX = 0 and MY = 0)  
• Display blank (D = 0 and E = 0)  
• Address counter X[6:0] = 0, Y[2:0] = 0 and XM0 = 0  
• Bias system BS[2:0] = 0  
7.5  
Timing  
The timing of the PCF8535 organizes the internal data flow  
of the device. The timing also generates the LCD frame  
frequency which is derived from the clock frequency  
generated in the internal clock generator.  
• Multiplex rate M[2:0] = 0 (Mux rate 1 : 17)  
• Temperature control mode TC[2:0] = 0  
• HV-gen control, HVE = 0 the HV generator is switched  
off, PRS = 0 and S[1:0] = 00  
7.6  
Column driver outputs  
• VLCDOUT is equal to 0 V  
The LCD drive section includes 133 column outputs  
(C0 to C132) which should be connected directly to the  
LCD. The column output signals are generated in  
accordance with the multiplexed row signals and with the  
data in the display latch. When less than 133 columns are  
required the unused column outputs should be left  
open-circuit.  
• RAM data is unchanged (Note: RAM data is undefined  
after power-up)  
• All row and column outputs are set to VSS (display off)  
• TRS and BRS are set to zero  
• Direct mode is disabled (DM = 0)  
• Internal oscillator is selected, but not running (EC = 0)  
• Bias current set to low current mode (IB = 0).  
7.7  
Row driver outputs  
The LCD drive section includes 65 row outputs  
(R0 to R64) which should be connected directly to the  
LCD. The row output signals are generated in accordance  
with the selected LCD drive mode. If lower Mux rates or  
less than 65 rows are required, the unused outputs should  
be left open-circuit.  
7.2  
Power-down  
During power-down all static currents are switched off (no  
internal oscillator, no timing and no LCD segment drive  
system) and all LCD outputs are internally connected to  
VSS. The serial bus function remains active.  
1999 Aug 24  
9
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
7.8  
Drive waveforms  
frame n  
frame n + 1  
V
V
V
V
V
(t)  
(t)  
LCD  
2
3
state1  
state2  
ROW 0  
R0 (t)  
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
ROW 1  
R1 (t)  
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
COL 0  
C0 (t)  
V
V
V
4
5
SS  
V
V
V
LCD  
2
3
COL 1  
C1 (t)  
V
V
V
4
5
SS  
V
V
− V  
LCD  
SS  
− V  
3
SS  
V
V
− V  
V
− V  
LCD  
0 V  
3
2
4
5
V
(t)  
0 V  
V
state1  
− V  
− V  
SS  
SS  
5
V
− V  
4
LCD  
− V  
V
SS  
LCD  
V
V
− V  
LCD  
SS  
− V  
3
SS  
V
V
− V  
V
0 V  
V
− V  
LCD  
0 V  
3
2
4
5
V
(t)  
state2  
− V  
− V  
SS  
SS  
5
V
− V  
4
LCD  
− V  
V
SS  
LCD  
0 1 2 3 4 5 6 7 8...  
... 64 0 1 2 3 4 5 6 7 8...  
... 64  
MGS671  
Vstate1(t) = C1(t) − R0(t).  
Vstate2(t) = C1(t) − R1(t).  
Fig.3 Typical LCD driver waveforms.  
10  
1999 Aug 24  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
7.9  
Set multiplex rate  
The PCF8535 can be used to drive displays of varying sizes. The multiplex mode selected controls which rows are used.  
In all cases, the last row is always driven and is intended for icons. If Top Row Swap (TRS) is at logic 1 then the icon row  
will be output on pad R48. M[2:0] selects the multiplex rate (see Table 2).  
Table 2 Multiplex rates  
M[2]  
M[1]  
M[0]  
MULTIPLEX RATE  
ACTIVE ROWS  
0
0
0
0
1
0
0
1
0
1
0
1 : 17  
1 : 26  
R0 to R15 and R64  
R0 to R24 and R64  
R0 to R32 and R64  
R0 to R47 and R64  
R0 to R64  
0
1
1 : 34  
1
0
1 : 49  
1 : 65  
101 − 111  
do not use  
−
7.10 Bias system  
7.10.1 SET BIAS SYSTEM  
The bias voltage levels are set in the ratio of R − R − nR − R − R. Different multiplex rates require different factors n. This  
is programmed by BS[2:0]. For optimum bias values, n can be calculated from: n = Mux rate – 3  
Changing the bias system from the optimum will have a consequence on the contrast and viewing angle. One reason to  
come away from the optimum would be to reduce the required VOP. A compromise between contrast and VOP must be  
found for any particular application.  
Table 3 Programming the required bias system  
BS[2]  
BS[1]  
BS[0]  
n
BIAS MODE  
TYPICAL MUX RATES  
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
6
5
4
3
2
1
0
/
1 : 100  
1 : 80  
1 : 65  
1 : 49  
1 : 33  
1 : 26  
1 : 17  
1 : 9  
11  
1
/
10  
1
/
9
1
/
1
8
/
7
1
/
1
6
/
5
1
/
4
1999 Aug 24  
11  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
Table 4 Example of LCD bias voltage for 1/7bias, n = 3  
For calibrating the temperature read-out a measurement  
must be taken at a defined temperature. The offset  
between the ideal read-out and the actual result has to be  
stored into a non-volatile register (e.g. EEPROM);  
SYMBOL  
V1  
BIAS VOLTAGE FOR 1/7BIAS  
VLCD  
6/7 × VLCD  
5/7 × VLCD  
2/7 × VLCD  
1/7 × VLCD  
VSS  
Offset = TRideal – TRmeas  
(2)  
V2  
V3  
where TRmeas is the actual temperature read-out of the  
PCF8535.  
V4  
V5  
The calibrated temperature read-out can be calculated for  
each measurement as follows:  
V6  
TRcal = TRmeas + Offset  
(3)  
7.11 Temperature measurement  
The accuracy after the calibration is ±6.7% (plus ±1 lsb) of  
the difference between the current temperature and the  
calibration temperature. For this reason a calibration at or  
near the most sensitive temperature for the display is  
recommended.  
7.11.1 TEMPERATURE READ BACK  
The PCF8535 has an in-built temperature sensor.  
For power saving, the sensor should only be enabled  
when a measurement is required. It will not operate in  
power-down mode. The temperature read back requires a  
clock to operate. Normally the internal clock is used but, if  
the device is operating from an external clock, then this  
must be present for the measurement to work. VDD2 and  
VDD3 must also be applied. A measurement is initialized by  
setting the SM bit. Once started the SM bit will be  
automatically cleared. An internal oscillator will be  
initialized and allowed to warm-up for approximately  
2 frame periods. After this the measurement starts and  
lasts for a maximum of 2 frame periods.  
E.g. for a calibration at 25 °C with the current temperature  
at −20 °C, the absolute error may be calculated as:  
Absolute error = 0.067 × (25 °C − −20 °C)  
= ±3 °C + ±1 lsb = ±4.17 °C.  
7.12 Temperature compensation  
7.12.1 TEMPERATURE COEFFICIENTS  
Due to the temperature dependency of the liquid crystals  
viscosity the LCD controlling voltage, V must be increased  
at lower temperatures to maintain optimum contrast.  
Figure 4 shows VLCD as a function of temperature for a  
typical high multiplex rate liquid.  
Temperature data is returned via a status register. During  
the measurement the register will contain zero. Once the  
measurement is completed the register will be updated  
with the current temperature (non zero value). Because  
the I2C-bus interface is asynchronous to the temperature  
measurement, read back prior to the end of the  
In the PCF8535 the temperature coefficient of VLCD can be  
selected from 8 values by setting bits TC[2:0],  
see Table 5.  
measurement is not guaranteed. If this mode is required  
the register should be read twice to validate the data.  
The ideal temperature read-out can be calculated as  
follows;  
1
c
TRideal = 128 + (T – 27 °C) ×  
(1)  
--  
where T is the on-chip temperature in °C and c is the  
conversion constant; c = 1.17 °C/lsb.  
To improve the accuracy of the temperature measurement  
a calibration is recommended during the assembly of the  
final product.  
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PCF8535  
handbook, halfpage  
MGS473  
V
LCD  
0 °C  
T
Fig.4 VLCD as function of liquid crystal temperature (typical values).  
Table 5 Selectable temperature coefficients  
The low range offers programming from 4.5 to 10.215 V,  
with the high range from 10.215 to 15.93 V at the cut point  
temperature, Tcut. Care must be taken, when using  
temperature coefficients, that the programmed voltage  
does not exceed the maximum allowed VLCD voltage,  
see Chapter 10.  
TC[2]  
TC[1]  
TC[0]  
TC VALUE  
0
UNIT  
1/°C  
1/°C  
1/°C  
1/°C  
1/°C  
1/°C  
1/°C  
1/°C  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
−0.44 × 10−3  
−1.10 × 10−3  
−1.45 × 10−3  
−1.91 × 10−3  
−2.15 × 10−3  
−2.32 × 10−3  
−2.74 × 10−3  
For a particular liquid, the optimum VLCD can be calculated  
for a given multiplex rate. For a Mux rate of 1 : 65, the  
optimum operating voltage of the liquid can be calculated  
as:  
1 + 65  
VLCD  
=
× V = 6.85 × V  
(6)  
---------------------------------------  
1
th  
th  
2 × 1 –  
----------  
65  
7.13 VOP  
where Vth is the threshold voltage of the liquid crystal  
material used.  
7.13.1 SET VOP VALUE  
The voltage at the reference temperature can be  
calculated as: [VLCD (T = Tcut)]  
Table 6 Values for parameters of the HV generator  
programming  
VLCD  
= (a + VOP × b)  
(4)  
(Tcut)  
SYMBOL  
BITS  
VALUE  
UNIT  
The operating voltage, VOP, can be set by software.  
a
b
PRS = 0  
PRS = 1  
4.5  
10.215  
0.045  
27  
V
V
The generated voltage is dependent on the temperature,  
programmed Temperature Coefficient (TC) and the  
programmed voltage at the reference temperature (Tcut):  
V
VLCD = (a + VOP × b) × (1 + ((T – Tcut) × TC))  
(5)  
Tcut  
°C  
The values for Tcut, a and b are given in Table 6.  
The maximum voltage that can be generated is dependent  
on the voltage VDD2 and the display load current.  
Two overlapping VOP ranges are selectable via the  
command page “Hv-gen control”, see Fig.5.  
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V
LCD  
b
a
00 01 02 03 04 05 06 . . . 5F 6F 7F 00 01 02 03 04 05 06 . . . 5F 6F 7F  
LOW  
HIGH  
MGS472  
VOP[6:0] programming (00H to 7FH, programming range LOW and HIGH).  
Fig.5 VOP programming of PCF8535.  
7.14 Voltage multiplier control  
Table 7 HV generator multiplication factor  
7.14.1 S[1:0]  
S[1]  
0
S[0]  
0
MULTIPLICATION FACTOR  
2 × VDD2  
The PCF8535 incorporates a software configurable  
voltage multiplier. After reset (RES) the voltage multiplier  
is set to 2 × VDD2. Other voltage multiplier factors are set  
via the HV-gen command page. Before switching on the  
charge pump, the charge pump has to be pre-charged  
using the following sequence.  
0
1
3 × VDD2  
1
0
4 × VDD2  
1
1
5 × VDD2  
A starting state of HVE = 0, DOF = 0, PD = 1 and DM = 0  
is assumed. A small delay between steps is indicated.  
The recommended wait period is 20 µs per 100 nF of  
capacitance on VLCD1  
.
1. Set DM = 1 and PD = 0  
2. Delay  
3. Set the multiplication factor to 2 by setting S[1:0] = 00  
4. Set the required VOP and PRS.  
5. Set HVE = 1 to switch-on the charge pump with a  
multiplication factor of 2  
6. Delay  
7. Increase the number of stages, one at a time, with a  
delay between each until the required level is  
achieved.  
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7.15 Addressing  
The display RAM has a matrix of 65 × 133 bits.  
The columns are addressed by a combination of the  
X address pointer and the X-RAM page pointer, whilst the  
rows addressed in groups of 8 by the Y address pointer.  
The X address pointer has a range of 0 to 127 (7FH).  
Its range can be extended by the X-RAM page pointer,  
XM0. The Y address pointer has a range of 0 to 8 (08H).  
The PCF8535 is limited to 133 columns by 65 rows,  
addressing the RAM outside of this area is not allowed.  
Addressing of the RAM can be split into two parts; input  
addressing and output addressing. Input addressing is  
concerned with writing data into the RAM. Output  
addressing is almost entirely automatic and taken care of  
by the device, however, it is possible to affect the output  
mode.  
7.15.1 INPUT ADDRESSING  
Data is down loaded byte wise into the RAM matrix of the  
PCF8535 as indicated in Figs 6 to 10.  
Table 8 Effect of X-RAM page pointer  
X-RAM PAGE POINTER  
ADDRESSED COLUMN  
MX = 0  
ADDRESSED COLUMN  
MX = 1  
X ADDRESS POINTER  
XM0  
0
1
0
0
0
:
C0  
C1  
C132  
C131  
C130  
:
2
C2  
:
:
125  
126  
127  
0
0
0
0
1
1
:
C125  
C126  
C127  
C128  
C129  
:
C7  
C6  
C5  
C4  
C3  
:
1
:
4
1
C132  
C0  
Banks 1 to 7 use  
the entire byte  
MSB  
XM = 0  
XM = 1  
0
0
0
1
2
3
4
5
6
7
8
LSB  
Bank 8 is only  
1 bit deep and  
uses the MSB  
MSB  
icon data  
.. ..  
.. ..  
LSB  
X address  
MGS673  
Fig.6 RAM format, input addressing.  
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bank 0  
bank 1  
bank 2  
bank 3  
bank 7  
bank 8  
MSB  
top of LCD  
R0  
Data byte in location  
X = 0, Y = 0, MX = 0  
0
(MX = 0, MY = 0)  
LSB  
R8  
R16  
LCD  
R24  
MSB  
Data byte in location  
R56  
Y = 7, X = 0, MX = 0  
0
(MX = 0, MY = 0)  
LSB  
R64  
MGS674  
Fig.7 DDRAM to display mapping.  
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Two automated addressing modes are available; vertical  
addressing (V = 1) and horizontal addressing (V = 0).  
These modes change the way in which the  
auto-incrementing of the address pointers is handled and  
are independent of multiplex rate. The auto-incrementing  
works in a way so as to aid filling of the entire RAM. It is  
not a prerequisite of operation that the entire RAM is filled;  
in lower multiplex modes not all of the RAM will be needed.  
For these multiplex rates, use of horizontal addressing  
mode (V = 0) is recommended.  
The addressing modes may be further modified by the  
mirror X bit MX. This bit causes the data to be written into  
the RAM from right to left instead of the normal left to right.  
This effectively flips the display about the Y axis. The MX  
bit affects the mode of writing into the RAM, changing the  
MX bit after RAM data is written will not flip the display.  
7.15.1.1 Vertical addressing: non-mirrored;  
V = 1 and MX = 0  
In the vertical addressing mode data is written top to  
bottom and left to right. Here, the Y counter will  
Addressing the icon row is a special case as these RAM  
locations are not automatically accessed. These locations  
must be explicitly addressed by setting the Y address  
pointer to 8.  
auto-increment from 0 to 7 and then wrap around to 0 (see  
Fig.8). On each wrap over, the X counter will increment to  
address the next column. When the X counter wraps over  
from 127 to 0, the XM0 bit will be set. The last address  
accessible is Y = 7, X = 4 and XM0 = 1; after this access  
the counter will wrap around to Y = 0, X = 0 and XM0 = 0.  
The Y address pointer does not auto-increment when the  
X address over or underflows, it stays set to 8. Writing  
icon data is independent of the vertical and horizontal  
addressing mode, but is effected by the mirror X bit as  
described in Sections 7.15.1.2 and 7.15.1.3.  
XM = 0  
XM = 1  
0
0
byte number  
0
1
2
3
4
5
6
7
byte order for  
icon data  
8
icon data  
....  
....  
X address  
MGS675  
Fig.8 Sequence of writing data bytes into the RAM with normal vertical addressing (V = 1 and MX = 0).  
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7.15.1.2 Vertical addressing: mirrored; V = 1 and MX = 1  
It is also possible to write data from right to left, instead of from the normal left to right, still going top to bottom. In the  
mirrored vertical addressing mode the Y counter will auto-increment from 0 to 7 and then wrap around to 0 (see Fig.9).  
On each wrap-over, the X counter will decrement to address the preceding column. The XM0 bit will be automatically  
toggled each time the X address counter wraps over from 0. The last address accessible is Y = 7, X = 0 and XM0 = 0;  
after this access the counter will wrap around to Y = 0, X = 4 and XM0 = 1.  
XM = 0  
XM = 1  
0
0
byte number  
0
1
2
3
4
5
6
7
byte order for  
icon data  
8
icon data  
....  
....  
X address  
MGS676  
Fig.9 Sequence of writing data bytes into the RAM with mirrored vertical addressing (V = 1 and MX = 1).  
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7.15.1.3 Horizontal addressing: non-mirrored; V = 0 and MX = 0  
In horizontal addressing mode data is written from left to right and top to bottom. Here, the X counter will auto-increment  
from 0 to 127, set the XM0, then count 0 to 4 before wrapping around to 0 and clearing the XM0 bit (see Fig.10). On each  
wrap-over, the Y counter will increment. The last address accessible is Y = 7, X = 4 and XM0 = 1; after this access the  
counter will wrap around to Y = 0, X = 0 and XM0 = 0.  
XM = 0  
XM = 1  
0
0
byte number  
0
1
2
3
4
5
6
7
byte order for  
icon data  
8
icon data  
....  
....  
X address  
MGS677  
Fig.10 Sequence of writing data bytes into the RAM with normal horizontal addressing (V = 0 and MX = 0).  
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7.15.1.4 Horizontal addressing: mirrored; V = 0 and MX = 1  
It is also possible to write data from right to left, instead of from the normal left to right, still going top to bottom. In the  
mirrored horizontal addressing mode the X counter will auto-decrement from 4 to 0, clear the XM0, then count 127 to 0  
before wrapping around to 4 and setting the XM0 bit (see Fig.10). On each wrap-over, the Y counter will increment.  
The last address accessible is Y = 7, X = 0 and XM0 = 0; after this access the counter will wrap around to Y = 0, X = 4  
and XM0 = 1.  
XM = 0  
XM = 1  
0
0
byte number  
0
1
2
3
4
5
6
7
byte order for  
icon data  
8
icon data  
....  
....  
X address  
MGS678  
Fig.11 Sequence of writing data bytes into the RAM with mirrored horizontal addressing (V = 0 and MX = 1).  
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7.15.2 OUTPUT ADDRESSING  
The output addressing of the RAM is done automatically in accordance with the currently selected multiplex rate.  
Normally the user would not need to make any alterations to the addressing. There are, however, circumstances  
pertaining to various connectivity of the device on a glass that would benefit from some in-built functionality. Three modes  
exist that enable the user to modify the output addressing, namely:  
1. MY, mirror the Y axis. This mode effectively flips the display about the X axis, resulting in an upside down display.  
The effect is observable immediately the bit is modified. This is useful if the device is to be mounted above the display  
area instead of below.  
2. Bottom Row Swap (BRS). This mode swaps the order of the rows on the bottom(1) edge of the chip. This is useful to  
aide routing to the display when it is not possible to pass tracks under the device; a typical example would be in tape  
carrier package. This mode is often used in conjunction with TRS.  
3. Top Row Swap (TRS). As with BRS, but swaps the order of rows on the top(1) edge of the chip.  
7.15.2.1 Mirror Y, MY  
As described above, the Y axis is mirrored in the X axis.  
..  
R0  
R1  
R2  
R3  
R4  
R5  
MY = 0  
R6  
R7  
R8  
Y axis  
R64  
... icons ...  
Mirror  
Y axis  
R55  
R56  
R57  
R58  
R59  
R60  
R61  
R62  
R63  
R64  
MY = 1  
... icons ...  
MGS679  
Fig.12 Mirror Y behaviour (Mux rate 1 : 65).  
(1) The top edge is defined as the edge containing the user interface connections. The bottom edge is the opposing edge.  
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7.15.2.2 Bottom Row Swap  
Here the order of the row pads is modified. Each block of rows is swapped about its local Y axis.  
R16  
R32  
R64  
R48  
INTERFACE  
COLUMNS  
R15  
R0  
R33  
R47  
MGS680  
Fig.13 Bottom row swap.  
7.15.2.3 Top Row Swap  
Here the order of the row pads is modified. Each block of rows is swapped about its local Y axis.  
R32  
R16  
R48  
R64  
INTERFACE  
COLUMNS  
R0  
R15  
R47  
R33  
MGS681  
Fig.14 Top row swap.  
22  
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7.15.2.4 Output row order  
The order in which the rows are activated is a function of bits MY, TRS, BRS and the selected multiplex mode.  
Tables 9 to 12 give the order in which the rows are activated. In all cases, the RAM is accessed in a linear fashion,  
starting at zero with a jump to the last row for the icon data.  
Table 9 Row order for BRS = 0 and TRS = 0  
MULTIPLEX MODE  
MY = 0  
R0 to R15 and R64  
MY = 1  
R15 to R0 and R64  
1 : 17  
1 : 26  
1 : 33  
1 : 49  
1 : 65  
R0 to R24 and R64  
R0 to R31 and R64  
R0 to R47 and R64  
R0 to R64  
R24 to R0 and R64  
R31 to R0 and R64  
R47 to R0 and R64  
R63 to R0 and R64  
Table 10 Row order for BRS = 1 and TRS = 0  
MULTIPLEX MODE  
MY = 0  
MY = 1  
1 : 17  
1 : 26  
1 : 33  
1 : 49  
R15 to R0 and R64  
R0 to R15 and R64  
R15 to R0, R16 to R24 and R64  
R15 to R0, R16 to R31 and R64  
R24 to R16, R0 to R15 and R64  
R31 to R16, R0 to R15 and R64  
R15 to R0, R16 to R32, R47 to R33  
and R64  
R33 to R47, R32 to R16, R0 to R15  
and R64  
1 : 65  
R15 to R0, R16 to R32, R47 to R33  
and R48 to R64  
R63 to R48, R33 to R47, R32 to R16,  
R0 to R15 and R64  
Table 11 Row order for BRS = 0 and TRS = 1  
MULTIPLEX MODE  
MY = 0  
MY = 1  
1 : 17  
1 : 26  
1 : 33  
1 : 49  
R0 to R15 and R48  
R15 to R0 and R48  
R0 to R15, R32 to R24 and R48  
R0 to R15, R32 to R17 and R48  
R24 to R32, R15 to R0 and R48  
R17 to R32, R15 to R0 and R48  
R0 to R15, R32 to R16, R33 to R47  
and R48  
R47 to R33, R16 to R32, R15 to R0  
and R48  
1 : 65  
R0 to R15, R32 to R16, R33 to R47  
and R64 to R48  
R49 to R64, R47 to R33, R16 to R32,  
R15 to R0 and R48  
Table 12 Row order for BRS = 1 and TRS = 1  
MULTIPLEX MODE  
MY = 0  
MY = 1  
1 : 17  
1 : 26  
1 : 33  
1 : 49  
R15 to R0 and R48  
R0 to R15 and R48  
R15 to R0, R32 to R24 and R48  
R15 to R0, R32 to R17 and R48  
R0 to R15, R32 to R24 and R48  
R0 to R15, R17 to R32 and R48  
R15 to R0, R32 to R16, R47 to R33  
and R48  
R0 to R15, R16 to R32, R33 to R47  
and R48  
1 : 65  
R15 to R0, R32 to R16, R47 to R33  
and R64 to R48  
R0 to R15, R16 to R32, R33 to R47,  
R47 to R64 and R48  
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7.16 Instruction set  
• Oscillator off  
• VLCDIN may be disconnected  
• I2C-bus interface accesses are possible  
Data accesses to the PCF8535 can be broken down into  
two areas, those that define the operating mode of the  
device and those that fill the display RAM; the distinction  
being the D/C bit. When the D/C bit is at logic 0, the chip  
will respond to instructions as defined in Table 16. When  
the D/C bit is at logic 1, the chip will store data into the  
RAM. Data may be written to the chip that is independent  
to the presence of the display clock.  
• RAM contents are not cleared; RAM data can be written  
• Register settings remain unchanged.  
V
When V = 0, horizontal addressing is selected. When  
V = 1, vertical addressing is selected. The behaviour is  
described in Section 7.15.  
There are 4 instruction types. Those which:  
1. Define PCF8535 functions such as display  
configuration, etc.  
7.16.2.3 RAM page  
2. Set internal RAM addresses  
3. Perform data transfer with internal RAM  
4. Others.  
The XM0 bit extends the RAM into a second page. The bit  
may be considered to be the Most Significant Bit (MSB) of  
an 8-bit X address. The behaviour is described in  
Section 7.15.  
In normal use, category 3 instructions are the most  
frequently used. To lessen the MPU program load,  
automatic incrementing by one of the internal RAM  
address pointers after each data write is implemented.  
7.16.2.4 Set Yaddress  
The Y address is used as a pointer to the RAM for RAM  
writing. The range is 0 to 8. Each bank corresponds to a  
set of 8 rows, the only exception being bank 8, which  
contains the icon data and is only 1-bit deep; see Table 13.  
The instruction set is broken down into several pages,  
each command page being individually addressed via the  
H[2:0] bits.  
Table 13 Yaddress pointer  
7.16.1 RAM READ/WRITE COMMAND PAGE  
Y[3]  
0
Y[2]  
0
Y[1]  
0
Y[0]  
0
BANK  
ROWS  
This page is special in that it is accessible independently  
of the H bits. This page is mainly used as a stepping stone  
to other pages. Sending the ‘Default H[2:0]’ command will  
cause an immediate step to the ‘Function and RAM  
command page’ which will allow the H[2:0] bits to be set.  
bank 0 R0 to R7  
0
0
0
1
bank 1 R8 to R15  
bank 2 R16 to R23  
bank 3 R24 to R31  
bank 4 R32 to R39  
bank 5 R40 to R47  
bank 6 R48 to R55  
bank 7 R56 to R63  
0
0
1
0
0
0
1
1
0
1
0
0
7.16.2 FUNCTION AND RAM COMMAND PAGE  
7.16.2.1 Command page  
0
1
0
1
0
1
1
0
Setting H[2:0] will move the user immediately to the  
required command page. Pages not listed should not be  
accessed as the behaviour is not defined.  
0
1
1
1
1
0
0
0
bank 8 R64  
(icons)  
7.16.2.2 Function set  
PD  
When PD = 1, the LCD driver is in power-down mode:  
• All LCD outputs at VSS  
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7.16.2.5 Set X address  
7.16.3.3 Bias system  
The X address is used as a pointer to the RAM for RAM  
writing. The range of X is 0 to 127 (7FH) and may be  
extended by the XM0 bit. The combined value of XM0 and  
X address directly corresponds to the display column  
number when MX = 0 and corresponds to the inverse  
display column number when MX = 1; see Table 14.  
BS[2:0] sets the bias system; see Section 7.10.  
7.16.3.4 Display size  
Physically large displays require stronger drivers. Bit IB  
enables the user to select a stronger driving mode and  
should be used if suitable display quality can not be  
achieved with the default setting.  
Table 14 X address pointer  
7.16.3.5 Multiplex rate  
ADDRESSED  
COLUMN, MX = 0 COLUMN, MX = 1  
ADDRESSED  
XM0, X[6:0]  
M[2:0] sets the multiplex rate; see Section 7.9.  
0
1
C0  
C1  
C132  
C131  
C130  
C129  
:
7.16.4 HV-GEN COMMAND PAGE  
7.16.4.1 HV-gen control  
PRS  
2
C2  
3
C3  
:
:
Programmable charge pump range select. This bit defines  
whether the programmed voltage for VOP is in the low or  
the high range. The behaviour of this bit is further  
described in Section 7.13.  
129  
130  
131  
132  
C129  
C130  
C131  
C132  
C3  
C2  
C1  
C0  
HVE  
High voltage generator enable. When set to logic 0, the  
charge pump is disabled. When set to logic 1, the charge  
pump is enabled.  
7.16.3 DISPLAY SETTING COMMAND PAGE  
7.16.3.1 Display control  
The D and E bits set the display mode as given in  
Table 15.  
7.16.4.2 HV-gen stages  
S[1:0] set the multiplication factor of the charge pump  
ranging from times 2 to times 5. The behaviour of these  
bits is further described in Section 7.14.  
Table 15 Display control  
D
0
1
0
1
E
0
0
1
1
MODE  
display blank  
7.16.4.3 Temperature coefficients  
normal mode  
TC[2:0] set the required temperature coefficient.  
The behaviour of these bits is further described in  
Section 7.12.  
all display segments on  
inverse video  
7.16.4.4 Temperature measurement control  
7.16.3.2 External display control  
The SM bit is used to initiate a temperature measurement.  
The SM bit is automatically cleared at the end of the  
measurement. The behaviour of this bit is further  
described in Section 7.11.  
Mirror X and mirror Y have the effect of flipping the display  
left to right or top to bottom respectively. MX works by  
changing the order data that is written into the RAM.  
As such, the effects of toggling MX will only be seen after  
data is written into the RAM. MY works by reversing the  
order that column data is accessed relative to the row  
outputs. The effect of toggling MY will be seen  
7.16.4.5 VLCD control  
VOP[6:0] sets the required operating voltage for the  
display.  
immediately. The behaviour of both of these bits is further  
described in Section 7.15.  
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65 × 133 pixel matrix driver  
PCF8535  
7.16.5 SPECIAL FEATURE COMMAND PAGE  
When using an external clock and disabling it during  
power-down mode will further reduce the standby current.  
If it is not possible to disable it externally then it is worth  
noting that by selecting the internal clock, which is disabled  
during power-down mode, the same effect may be  
achieved.  
7.16.5.1 State control  
DM  
Direct mode allows VLCDOUT to be sourced directly from  
VDD2. This may be useful in systems where VDD is to be  
used for VLCD  
.
7.16.5.3 COG/TCP  
DOF  
The chip may be mounted on either a glass, foil or tape  
carrier package. For these applications, different  
organizations of the row pads are required to negate the  
necessity of routing under the device. The TRS and BRS  
allow for this swapping. The behaviour of both of these bits  
is further described in Section 7.15.  
Display off will turn off all internal analog circuitry that is not  
required for temperature measurement.  
As a consequence the display will be turned off. This  
mode is only required if temperature measurements are  
required whilst in power-down mode.  
7.16.5.2 Oscillator setting  
The internal oscillator may be disabled and the source  
clock for the display derived from the OSC pad. It is  
important to remember that LCDs are damaged by DC  
voltages and that the clock, whether derived internally or  
externally, should never be disabled whilst the display is  
active. The internal oscillator is switched off during  
power-down mode.  
7.16.6 INSTRUCTION SET  
Table 16 Instruction set  
I2C-BUS COMMAND BYTE  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
H[2:0] = XXX; RAM read/write command page  
INSTRUCTION  
D/C R/W(1)  
I2C-BUS COMMANDS  
Write data  
1
0
0
1
D7  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
writes data to display RAM  
Read status  
returns result of  
temperature measurement  
NOP  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
no operation  
Default H[2:0]  
jump to H[2:0] = 111  
H[2:0] = 111; function and RAM command page  
Command page  
Function set  
0
0
0
0
0
0
0
0
0
0
0
1
1
0
H2  
H1  
V
H0  
0
select command page  
PD  
power-down control, data  
entry mode  
RAM page  
0
0
0
0
0
0
0
1
1
0
0
0
0
XM0  
Y2  
0
0
set RAM page for X address  
Set Yaddress of  
RAM  
Y3  
Y1  
Y0  
sets Yaddress of RAM  
0 ≤ Y ≤ 8  
Set X address of  
RAM  
0
0
1
X6  
X5  
X4  
X3  
X2  
X1  
X0  
sets X address of RAM  
0 ≤ X ≤ 127  
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65 × 133 pixel matrix driver  
PCF8535  
I2C-BUS COMMAND BYTE  
INSTRUCTION  
D/C R/W(1)  
I2C-BUS COMMANDS  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
H[2:0] = 110; display setting command page  
Display control  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
D
E
0
sets display mode  
mirror X, mirror Y  
External display  
control  
MX MY  
Bias system  
Display size  
Multiplex rate  
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
BS2 BS1 BS0 set bias system  
IB  
0
0
set current for bias system  
set multiplex rate  
M2  
M1  
M0  
H[2:0] = 101; HV-gen command page  
HV-gen control  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
PRS HVE VLCD range, enable/disable  
HV-gen  
HV-gen stages  
S1  
S0  
# of HV-gen voltage  
multiplication  
Temperature  
coefficients  
TC2 TC1 TC0 set temperature coefficient  
Temperature  
measurement  
control  
0
0
SM start temperature  
measurement  
VLCD control  
0
0
1
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 set VLCD register  
0 ≤ VLCD ≤ 127  
H[2:0] = 011; special feature command page  
State control  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
DOF DM display off, direct mode  
Oscillator setting  
EC  
0
enable/disable the internal  
oscillator  
COG/TCP  
0
0
0
1
0
TRS BRS 0  
0
0
top row swap, bottom row  
swap  
Note  
1. R/W is set in the slave address.  
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PCF8535  
Table 17 Description of the symbols used in Table 16  
BIT  
PD  
0
1
chip is active  
chip is in power-down mode  
vertical addressing  
voltage multiplier enabled  
VLCD programming range HIGH  
start measurement  
mirror X  
V
horizontal addressing  
HVE  
PRS  
SM  
MX  
MY  
TRS  
BRS  
EC  
voltage multiplier disabled  
VLCD programming range LOW  
no measurement  
no X mirror  
no Y mirror  
mirror Y  
top row swap inactive  
bottom row swap inactive  
internal oscillator enabled; OSC pad ignored  
top row swap active  
bottom row swap active  
internal oscillator disabled; OSC pad enabled for  
input  
DM(1)  
direct mode disabled  
direct mode enabled  
DOF(1) display off mode disabled  
display off mode enabled  
high current mode for larger displays  
IB  
low current mode for smaller displays  
Note  
1. Conditional on other bits.  
Table 18 Priority behaviour of bits PD, DOF, HVE and DM; note 1  
PD  
1
DOF  
HVE  
X
DM  
X
MODE  
X
1
0
0
0
chip is in power-down mode as defined under PD  
0
X
X
all analog blocks except those required for temperature measurement are off  
chip is active and using the internal VLCD generator  
0
1
X
0
0
1
chip is active and using VDD as VLCD  
0
0
0
chip is active and using an external VLCD generator attached to VLCDIN  
Note  
1. X = don’t care state.  
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PCF8535  
7.17 I2C-bus interface  
• Slave: the device addressed by a master  
• Multi-master: more than one master can attempt to  
control the bus at the same time without corrupting the  
message  
7.17.1 CHARACTERISTICS OF THE I2C-BUS  
The I2C-bus is for bidirectional, two-line communication  
between different ICs or modules. The two lines are a  
serial data line (SDA) and a serial clock line (SCL). Both  
lines must be connected to a positive supply via a pull-up  
resistor. Data transfer may be initiated only when the bus  
is not busy.  
• Arbitration: procedure to ensure that, if more than one  
master simultaneously tries to control the bus, only one  
is allowed to do so and the message is not corrupted  
• Synchronization: procedure to synchronize the clock  
signals of two or more devices.  
7.17.1.1 Bit transfer  
7.17.1.4 Acknowledge  
One data bit is transferred during each clock pulse.  
The data on the SDA line must remain stable during the  
HIGH period of the clock pulse as changes in the data line  
at this time will be interpreted as a control signal.  
Bit transfer is illustrated in Fig.15.  
Each byte of 8 bits is followed by an acknowledge bit.  
The acknowledge bit is a HIGH signal put on the bus by  
the transmitter during which time the master generates an  
extra acknowledge related clock pulse. A slave receiver  
which is addressed must generate an acknowledge after  
the reception of each byte. Also a master receiver must  
generate an acknowledge after the reception of each byte  
that has been clocked out of the slave transmitter.  
The device that acknowledges must pull-down the SDA  
line during the acknowledge clock pulse, so that the SDA  
line is stable LOW during the HIGH period of the  
acknowledge related clock pulse (set-up and hold times  
must be taken into consideration). A master receiver must  
signal an end of data to the transmitter by not generating  
an acknowledge on the last byte that has been clocked out  
of the slave. In this event the transmitter must leave the  
data line HIGH to enable the master to generate a STOP  
condition. Acknowledgement on the I2C-bus is illustrated  
in Fig.18.  
7.17.1.2 START and STOP conditions  
Both data and clock lines remain HIGH when the bus is not  
busy. A HIGH-to-LOW transition of the data line, while the  
clock is HIGH is defined as the START condition (S).  
A LOW-to-HIGH transition of the data line while the clock  
is HIGH is defined as the STOP condition (P). The START  
and STOP conditions are illustrated in Fig.16.  
7.17.1.3 System configuration  
The system configuration is illustrated in Fig.17.  
• Transmitter: the device which sends the data to the bus  
• Receiver: the device which receives the data from the  
bus  
• Master: the device which initiates a transfer, generates  
clock signals and terminates a transfer  
SDA  
SCL  
data line  
stable;  
data valid  
change  
of data  
allowed  
MBC621  
Fig.15 Bit transfer.  
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65 × 133 pixel matrix driver  
PCF8535  
SDA  
SDA  
SCL  
SCL  
S
P
STOP condition  
START condition  
MBC622  
Fig.16 Definition of START and STOP conditions.  
MASTER  
TRANSMITTER/  
RECEIVER  
SLAVE  
TRANSMITTER/  
RECEIVER  
MASTER  
TRANSMITTER/  
RECEIVER  
SLAVE  
RECEIVER  
MASTER  
TRANSMITTER  
SDA  
SCL  
MGA807  
Fig.17 System configuration.  
DATA OUTPUT  
BY TRANSMITTER  
not acknowledge  
DATA OUTPUT  
BY RECEIVER  
acknowledge  
8
SCL FROM  
MASTER  
1
2
9
S
clock pulse for  
acknowledgement  
START  
condition  
MBC602  
Fig.18 Acknowledgement on the I2C-bus.  
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65 × 133 pixel matrix driver  
PCF8535  
7.17.2 I2C-BUS PROTOCOL  
After the acknowledgement cycle of a write, a control byte  
follows which defines the destination for the forthcoming  
data byte and the mode for subsequent bytes. For a read,  
the PCF8535 will immediately start to output the requested  
data until a NOT acknowledge is transmitted by the  
master. The sequence should be terminated by a STOP in  
the event that no further access is required for the time  
being, or by a RE-START, should further access be  
required.  
The PCF8535 is a slave receiver/transmitter. If data is to  
be read from the device the SDAOUT pad must be  
connected, otherwise SDAOUT is unused.  
Before any data is transmitted on the I2C-bus, the device  
which should respond is addressed. Four slave  
addresses, 0111100, 0111101, 0111110 and 0111111 are  
reserved for the PCF8535. The Least Significant Bits  
(LSBs) of the slave address is set by connecting  
SA1 and SA0 to either logic 0 (VSS) or logic 1 (VDD).  
For ease of operation a continuation bit, Co, has been  
included. This bit allows the user to set-up the chip  
configuration and transmit RAM data in one access. A data  
selection bit, D/C, defines the destination for data. These  
bits are contained in the control byte. DB5 to DB0 should  
be set to logic 0. These bits are reserved for future  
expansion.  
A sequence is initiated with a START condition (S) from  
the I2C-bus master which is followed by the slave address.  
All slaves with the corresponding address acknowledge in  
parallel, all the others will ignore the I2C-bus transfer.  
Table 19 Co and D/C definitions  
BIT  
Co  
0/1 R/W  
ACTION  
0
n.a. last control byte to be sent: only a stream of data bytes are allowed to follow; this stream may  
only be terminated by a STOP or RE-START condition  
1
0
another control byte will follow the data byte unless a STOP or RE-START condition is received  
D/C  
0
1
0
1
data byte will be decoded and used to set up the device  
data byte will return the contents of the currently selected status register  
data byte will be stored in the display RAM  
1
no provision for RAM read back is provided  
An example of a write access is given in Fig.19. Here, multiple instruction data is sent, followed by multiple display bytes.  
An example of a read access is given in Fig.20.  
acknowledgement  
from PCF8535  
acknowledgement  
from PCF8535  
acknowledgement  
from PCF8535  
acknowledgement  
from PCF8535  
acknowledgement  
from PCF8535  
S S  
control byte  
control byte  
S 0  
1
1
1
1
0 A 1 D/C  
A
data byte  
A 0 D/C  
Co  
A
data byte  
A P  
A A  
1 0  
slave address  
2n ≥ 0 bytes  
1 byte  
n ≥ 0 bytes  
MSB . . . . . . . . . . . LSB  
R/W Co  
update  
data pointer  
MGS682  
Fig.19 Master transmits to slave receiver; write mode.  
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PCF8535  
acknowledgement  
from PCF8535  
NOT acknowledgement  
from master  
S S  
temp. read out value  
S 0  
1
1
1
1
1 A  
A P  
A A  
1
0
slave address  
STOP condition  
R/W  
MGS683  
Fig.20 Master reads a slaves’ status register.  
8
LIMITING VALUES (PROVISIONAL)  
In accordance with the Absolute Maximum Rating System (IEC 134); notes 1, 2 and 3.  
SYMBOL  
PARAMETER  
MIN.  
−0.5  
MAX.  
+7.0  
UNIT  
VDD  
IDD  
supply voltage  
V
supply current  
−50  
−0.5  
−50  
−50  
−0.5  
−10  
−10  
−
+50  
mA  
V
VLCD  
ILCD  
ISS  
LCD supply voltage  
LCD supply current  
+17.0  
+50  
mA  
mA  
V
negative supply current  
+50  
VI/VO  
II  
input/output voltage (any input/output)  
DC input current  
VDD + 0.5  
+10  
mA  
mA  
mW  
mW  
°C  
IO  
DC output current  
+10  
Ptot  
total power dissipation per package  
power dissipation per output  
ambient temperature  
300  
P/out  
Tamb  
Tstg  
Tj(max)  
−
30  
−40  
−65  
−
+85  
storage temperature  
+150  
150  
°C  
maximum junction temperature  
°C  
Notes  
1. Stresses above these values listed may cause permanent damage to the device.  
2. Parameters are valid over the operating temperature range unless otherwise specified. All voltages are referenced  
to VSS unless otherwise specified.  
3. VSS = 0 V.  
9
HANDLING  
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is  
recommended to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).  
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PCF8535  
10 DC CHARACTERISTICS  
VDD = 4.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 16.0 V; Tamb = −40 to +85 °C; unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Supplies  
VLCDIN  
LCD supply voltage  
Mux mode 1 : 65  
8.0  
−
−
−
−
−
16.0  
16.0  
16.0  
16.0  
16.0  
90  
V
Mux mode 1 : 49  
8.0  
−
V
Mux mode 1 : 34  
V
Mux mode 1 : 26  
−
V
Mux mode 1 : 17  
−
V
ILCDIN  
LCD supply current  
normal mode; notes 1 and 2  
normal mode; notes 1 and 4  
−
40  
18  
−
µA  
µA  
V
−
40  
VLCDOUT  
generated supply voltage  
supply voltage  
LCD voltage generator  
enabled  
−
16.0  
VDD1  
VDD2  
VDD3  
,
,
4.5  
−
5.5  
V
IDD  
supply current  
power-down mode;  
notes 1, 3 and 5  
−
−
2
10  
µA  
µA  
display off mode;  
notes 1 and 5  
−
−
normal mode; notes 1 and 6  
normal mode; notes 1 and 2  
−
−
160  
40  
350  
90  
µA  
µA  
Logic  
VIL  
VIH  
IOL  
IL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level output current (SDA)  
leakage current  
VSS  
0.7VDD  
3.0  
−
−
−
−
0.3VDD  
VDD  
−
V
V
VOL = 0.4 V; VDD = 5 V  
VI = VDD or VSS  
mA  
µA  
−1  
+1  
Column and row outputs  
Ro(col)  
column output resistance C0 to C132 VLCD = 12 V; note 7  
−
−
−
0
0
10  
kΩ  
kΩ  
mV  
mV  
Ro(row)  
row output resistance R0 to R33  
bias tolerance C0 to C132  
bias tolerance R0 to R64  
VLCD = 12 V; note 7  
−
3.0  
Vbias(col)  
Vbias(row)  
−100  
−100  
+100  
+100  
Temperature coefficient  
tcut  
cut point temperature  
Tamb = −20 to +70 °C  
−
27  
−
°C  
Notes  
1. LCD outputs are open-circuit, inputs at VDD or VSS, bus inactive, fOSC = typical internal oscillator frequency.  
2. Conditions are: VDD1 to VDD3 = 5.0 V, VLCD = 12.0 V and external VLCD  
3. Power-down mode. During power-down all static currents are switched off.  
4. Conditions are: VDD1 to VDD3 = 5.0 V, VLCD = VDD2 and external VLCD  
5. Internal VLCD generation or external VLCD  
.
.
.
6. Conditions are: VDD1 to VDD3 = 5.0 V, VLCD = 12.0 V and voltage multiplier = 3VDD  
.
7. ILCD = 10 µA. Outputs tested one at a time.  
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PCF8535  
11 AC CHARACTERISTICS  
VDD = 4.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 16.0 V; Tamb = −40 to +85 °C; unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
80  
MAX.  
165  
UNIT  
Hz  
ffr(LCD)  
LCD frame frequency (internal clock)  
external clock frequency  
48  
fclk(ext)  
see Table 20 120  
−
−
−
−
−
410  
−
kHz  
µs  
tW(RESL)  
tW(RESH)  
tSU;RESL  
tR(op)  
reset LOW pulse width  
1
5
reset HIGH pulse width  
−
µs  
reset LOW pulse set-up time after power-on  
end of reset pulse to interface being operational  
notes 1 and 2  
−
−
30  
3
µs  
µs  
Serial-bus interface; note 3  
fSCL  
SCL clock frequency  
0
−
−
−
−
−
−
−
−
−
−
−
−
−
400  
−
kHz  
µs  
µs  
ns  
µs  
ns  
ns  
pF  
µs  
µs  
µs  
ns  
µs  
tLOW  
tHIGH  
tSU;DAT  
tHD;DAT  
tr  
SCL clock LOW period  
1.3  
SCL clock HIGH period  
data set-up time  
0.6  
−
100  
−
data hold time  
0
0.9  
300  
300  
400  
−
SCL, SDA rise time  
note 4  
note 4  
20 + 0.1Cb  
tf  
SCL, SDA fall time  
20 + 0.1Cb  
Cb  
capacitive load represented by each bus line  
set-up time for a repeated START condition  
START condition hold time  
set-up time for STOP condition  
tolerable spike width on bus  
−
tSU;STA  
tHD;STA  
tSU;STO  
tSP  
0.6  
0.6  
0.6  
−
−
−
50  
−
tBUF  
bus free time between a STOP and START  
condition  
1.3  
Notes  
1. VDD1 to VDD3 = 5 V.  
2. Decoupling capacitor VLCD and VSS = 100 nF (higher capacitor size increases tSU;RESL and higher VDD1 to VDD3  
reduces tSU;RESL).  
3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to  
VIL and VIH with an input voltage swing of VSS to VDD  
.
4. Cb = total capacitance of one bus line in pF.  
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PCF8535  
SDA  
t
t
t
LOW  
f
BUF  
SCL  
t
t
t
SU;DAT  
t
HD;STA  
r
t
HIGH  
HD;DAT  
SDA  
t
SU;STA  
MGA728  
t
SU;STO  
Fig.21 I2C-bus timing diagram.  
Table 20 External clock frequency  
EXTERNAL CLOCK FREQUENCY FOR AN 80 Hz FRAME  
MUX MODE  
DIVISION RATIO  
FREQUENCY (DIVISION RATIO × 80 Hz)  
1 : 65  
1 : 48  
1 : 33  
1 : 26  
1 : 17  
3168  
3136  
2720  
2592  
2592  
253 kHz  
251 kHz  
218 kHz  
207 kHz  
207 kHz  
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PCF8535  
12 RESET TIMING  
V
DD  
t
t
t
W(RESL)  
W(RESL)  
W(RESH)  
RES  
V
DD  
t
t
t
t
W(RESL)  
SU;RESL  
W(RESL)  
W(RESH)  
RES  
RES  
t
R(op)  
SDA,  
SCL  
MGS684  
Fig.22 Reset timing.  
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PCF8535  
13 APPLICATION INFORMATION  
Table 21 Programming example for PCF8535  
STEP  
SERIAL BUS BYTE  
START condition  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
SA1 SA0  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
DISPLAY(1)  
BLANK  
OPERATION  
1
2
start  
slave address, R/W = 0  
0
1
1
1
1
0
3
4
control byte, Co = 0, D/C = 0  
0
0
0
0
0
0
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
H[2:0] independent command;  
select function and RAM command  
page H[1:0] = 111  
0
0
0
0
0
0
0
1
5
6
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
function and RAM command page;  
PD = 0, V = 0  
0
0
0
1
0
0
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
function and RAM command page;  
select display setting command  
page H[1:0] = 110  
0
0
0
0
1
1
1
0
7
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
display setting command page; set  
bias system to 1/9BS[2:0] = 010  
0
0
0
1
0
0
1
0
8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
display setting command page; set  
normal mode (D = 1, E = 0)  
0
0
0
0
0
1
1
0
9
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
select Mux rate 1 : 65  
1
0
0
0
0
1
0
0
10  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
H[2:0] independent command;  
select function and RAM command  
page H[1:0] = 111  
0
0
0
0
0
0
0
1
11  
12  
13  
14  
15  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
function and RAM command page;  
select Hv-gen command page  
H[1:0] = 101  
0
0
0
0
1
1
0
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
Hv-gen command page; select  
voltage multiplication factor 3  
S[1:0] = 01  
0
0
0
0
1
0
0
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
Hv-gen command page; select  
temperature coefficient 2  
TC[2:0] = 010  
0
0
0
1
0
0
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
Hv-gen command page; set  
VLCD = 12.02 V;  
VOP[6:0] = 0101000  
1
0
1
0
1
0
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
Hv-gen command page; select high  
VLCD programming range  
(PRS = 1), voltage multiplier on  
(HVE = 1)  
0
0
0
0
0
1
1
1
16  
17  
START condition  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
SA1 SA0  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK  
BLANK  
repeat start  
slave address, R/W = 0  
0
1
1
1
1
0
18  
control byte, Co = 0, D/C = 1  
0
1
0
0
0
0
0
0
1999 Aug 24  
37  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
STEP  
SERIAL BUS BYTE  
DISPLAY(1)  
OPERATION  
19  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
data write; Y, X are initialized to  
logic 0 by default, so they are not  
set here  
0
0
0
1
1
1
1
1
MGS405  
20  
21  
22  
23  
24  
25  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
data write  
data write  
data write  
data write  
data write  
0
0
0
0
0
1
0
1
MGS406  
MGS407  
MGS408  
MGS409  
MGS410  
MGS411  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
0
0
1
1
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
0
0
0
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
1
1
1
1
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
0
0
0
0
0
1
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
data write, last data, stop  
transmission  
0
0
0
1
1
1
1
1
26  
27  
START condition  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
SA1 SA0  
repeat start  
slave address, R/W = 0  
0
1
1
1
1
0
MGS411  
1999 Aug 24  
38  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
STEP  
SERIAL BUS BYTE  
DISPLAY(1)  
OPERATION  
28  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
control byte, Co = 1, D/C = 0  
1
0
0
0
0
0
0
0
MGS411  
29  
30  
31  
32  
33  
34  
35  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
H[1:0] independent command;  
select function and RAM command  
page H[1:0] = 111  
0
0
0
0
0
0
0
1
MGS411  
MGS411  
MGS411  
MGS411  
MGS412  
MGS412  
MGS412  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
control byte, Co = 1, D/C = 0  
1
0
0
0
0
0
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
function and RAM command page;  
select display setting command  
page H[1:0] = 110  
0
0
0
0
1
1
1
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
control byte, Co = 1, D/C = 0  
1
0
0
0
0
0
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
display control; set inverse video  
mode (D = 1, E = 1)  
0
0
0
0
1
1
0
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
control byte, Co = 1, D/C = 0  
1
0
0
0
0
0
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
set X address of RAM; set address  
to ‘0000000’  
1
0
0
0
0
0
0
0
1999 Aug 24  
39  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
STEP  
SERIAL BUS BYTE  
DISPLAY(1)  
OPERATION  
36  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
control byte, Co = 0, D/C = 1  
0
1
0
0
0
0
0
0
MGS412  
37  
38  
39  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
data write  
0
0
0
0
0
0
0
0
MGS414  
MGS685  
MGS686  
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
data write  
0
0
0
0
0
0
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
data write  
0
0
0
0
0
0
0
0
40  
STOP condition  
end of transfer  
Note  
1. Assumes the display RAM was previously empty.  
The pinning of the PCF8535 is optimized for single plane wiring e.g. for chip-on-glass display modules.  
Display size: 65 × 133 pixels.  
1999 Aug 24  
40  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
DISPLAY 65 × 133 PIXELS  
33  
133  
32  
PCF8535  
R
R
R
I/O  
supply  
common  
C
ext  
3
V
SS1,  
V
V
V
V
LCD  
I/O  
DD1  
to  
SS2  
MGS687  
DD3  
Fig.23 Application diagram (COG).  
The required minimum value for the external capacitors in an application with the PCF8535 are:  
Cext for VLCD, VSS1 and VSS2 = 100 nF (min.) (recommended 470 nF to 1 µF); Cext for VDD1 to VDD3, VSS1 and  
VSS2 = 470 nF (recommended capacitor larger than the capacitor for VLCD, VSS1 and VSS2).  
Higher capacitor values are recommended for ripple reduction.  
For COG applications the recommended ITO track resistance is to be minimized for the I/O and supply connections.  
Maximum values for supply tracks (Rsupply) are 120 Ω. Maximum values for the common resistance to the source,  
(Rcommon) are 120 Ω. Higher track resistance reduces performance and increases current consumption.  
Three I/O lines are required for the COG module; SDA, SCL and RES (optional). Other signals may be fixed on the  
module to appropriate levels. RI/O should also be minimized. In particular, if the I2C-bus acknowledge or temperature  
read back is required, the RI/O for the SDA line must be carefully considered in conjunction with the value of the external  
pull-up resistor.  
1999 Aug 24  
41  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
14 BONDING PAD LOCATIONS  
SYMBOL  
C19  
PAD  
x
y
Table 22 Bonding pad locations  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
+1050  
−3325  
All x and y coordinates are referenced to the centre of the  
chip (dimensions in µm; see Fig.27).  
C20  
C21  
C22  
C23  
C24  
C25  
C26  
C27  
C28  
C29  
C30  
C31  
C32  
C33  
C34  
C35  
C36  
C37  
C38  
C39  
C40  
C41  
C42  
C43  
C44  
C45  
C46  
C47  
C48  
C49  
C50  
C51  
C52  
C53  
C54  
C55  
C56  
C57  
C58  
C59  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
−3255  
−3185  
−3115  
−3045  
−2975  
−2905  
−2835  
−2765  
−2695  
−2625  
−2555  
−2485  
−2415  
−2345  
−2275  
−2205  
−2135  
−1995  
−1925  
−1855  
−1785  
−1715  
−1645  
−1575  
−1505  
−1435  
−1365  
−1295  
−1225  
−1155  
−1085  
−1015  
−945  
SYMBOL  
PAD  
x
y
dummy  
1
−1050  
−6156  
bump/align 1 2  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
−6081  
−5985  
−5915  
−5845  
−5775  
−5705  
−5635  
−5565  
−5495  
−5425  
−5355  
−5285  
−5215  
−5145  
−5075  
−5005  
−4935  
−4725  
−4655  
−4585  
−4515  
−4445  
−4305  
−4235  
−4165  
−4095  
−4025  
−3955  
−3885  
−3815  
−3745  
−3675  
−3605  
−3535  
−3465  
−3395  
R0  
3
R1  
4
R2  
5
R3  
6
R4  
7
R5  
8
R6  
9
R7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
R8  
R9  
R10  
R11  
R12  
R13  
R14  
R15  
C0  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
−875  
−805  
−735  
−665  
−595  
−525  
−455  
1999 Aug 24  
42  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
SYMBOL  
C60  
PAD  
x
y
SYMBOL  
C101  
PAD  
x
y
79  
+1050  
−385  
−315  
−245  
−175  
−105  
−35  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
+1050  
+2625  
C61  
C62  
C63  
C64  
C65  
C66  
C67  
C68  
C69  
C70  
C71  
C72  
C73  
C74  
C75  
C76  
C77  
C78  
C79  
C80  
C81  
C82  
C83  
C84  
C85  
C86  
C87  
C88  
C89  
C90  
C91  
C92  
C93  
C94  
C95  
C96  
C97  
C98  
C99  
C100  
80  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
C102  
C103  
C104  
C105  
C106  
C107  
C108  
C109  
C110  
C111  
C112  
C113  
C114  
C115  
C116  
C117  
C118  
C119  
C120  
C121  
C122  
C123  
C124  
C125  
C126  
C127  
C128  
C129  
C130  
C131  
C132  
R47  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
+2695  
+2765  
+2835  
+2905  
+2975  
+3045  
+3115  
+3185  
+3255  
+3325  
+3395  
+3465  
+3535  
+3605  
+3675  
+3745  
+3815  
+3885  
+3955  
+4025  
+4095  
+4165  
+4235  
+4305  
+4375  
+4445  
+4515  
+4585  
+4655  
+4725  
+4795  
+5005  
+5075  
+5145  
+5215  
+5285  
+5355  
+5425  
+5495  
+5565  
81  
82  
83  
84  
85  
+35  
86  
+105  
+175  
+315  
+385  
+455  
+525  
+595  
+665  
+735  
+805  
+875  
+945  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
+1015  
+1085  
+1155  
+1225  
+1295  
+1365  
+1435  
+1505  
+1575  
+1645  
+1715  
+1785  
+1855  
+1925  
+1995  
+2065  
+2135  
+2205  
+2275  
+2345  
+2415  
+2485  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
R46  
R45  
R44  
R43  
R42  
R41  
R40  
R39  
1999 Aug 24  
43  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
SYMBOL  
R38  
PAD  
x
y
SYMBOL  
PAD  
x
y
161  
162  
163  
164  
165  
166  
+1050  
+5635  
VLCDOUT  
VLCDOUT  
VLCDSENCE  
dummy  
dummy  
RES  
202  
203  
204  
205  
206  
207  
208  
209  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
241  
242  
−1050  
+2034  
R37  
R36  
R35  
R34  
R33  
+1050  
+1050  
+1050  
+1050  
+1050  
+1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
+5705  
+5775  
+5845  
+5915  
+5985  
+6081  
+6094  
+5954  
+5884  
+5814  
+5744  
+5674  
+5604  
+5534  
+5464  
+5394  
+5324  
+5254  
+5184  
+5114  
+5044  
+4974  
+4904  
+4834  
+4414  
+4274  
+3996  
+3574  
+3154  
+2874  
+2804  
+2734  
+2664  
+2594  
+2524  
+2384  
+2314  
+2244  
+2174  
+2104  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
+1964  
+1894  
+1544  
+1264  
+914  
+704  
+494  
+284  
+144  
+74  
bump/align 2 167  
T3  
dummy  
R48  
R49  
R50  
R51  
R52  
R53  
R54  
R55  
R56  
R57  
R58  
R59  
R60  
R61  
R62  
R63  
R64  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
T2  
T1  
VDD2  
VDD2  
VDD2  
VDD2  
VDD2  
VDD2  
VDD2  
VDD2  
VDD3  
VDD3  
VDD3  
VDD3  
VDD1  
VDD1  
VDD1  
VDD1  
VDD1  
VDD1  
dummy  
SDA  
+4  
−66  
−136  
−206  
−276  
−346  
−416  
−486  
−556  
−626  
−696  
−766  
−836  
−906  
bump/align 3 186  
−976  
dummy  
dummy  
dummy  
OSC  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
−1046  
−1186  
−1466  
−1536  
−1886  
−2166  
−2376  
−2586  
−2656  
−2726  
−2796  
−2866  
−2936  
−3006  
−3076  
SDA  
VLCDIN  
SDAOUT  
SA1  
VLCDIN  
VLCDIN  
SA0  
VLCDIN  
VSS2  
VLCDIN  
VSS2  
VLCDIN  
VSS2  
VLCDOUT  
VLCDOUT  
VLCDOUT  
VLCDOUT  
VLCDOUT  
VSS2  
VSS2  
VSS2  
VSS2  
VSS2  
1999 Aug 24  
44  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
Table 23 Alignment marks  
SYMBOL  
VSS1  
PAD  
x
y
MARKS  
x
y
243  
244  
245  
246  
247  
248  
249  
250  
251  
252  
253  
254  
255  
−1050  
−3146  
Alignment mark 1  
Alignment mark 2  
Alignment mark 3  
Alignment mark 4  
−1045  
−4720  
+4620  
+6196  
−6196  
−6081  
VSS1  
VSS1  
VSS1  
VSS1  
VSS1  
VSS1  
VSS1  
T5  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−1050  
−3216  
−3286  
−3356  
−3426  
−3496  
−3566  
−3636  
−3846  
−4056  
−4126  
−4406  
−4476  
−4605  
−4826  
−4896  
−4966  
−5036  
−5106  
−5176  
−5246  
−5316  
−5386  
−5456  
−5526  
−5596  
−5666  
−5736  
−5806  
−5876  
−5946  
−1045  
+1045  
+1045  
Dummy bump/alignment +1050  
mark 1  
Dummy bump/alignment +1050  
mark 2  
+6081  
+4414  
−4605  
Dummy bump/alignment −1050  
mark 3  
T4  
dummy  
SCL  
SCL  
Dummy bump/alignment −1050  
mark 4  
Bottom left  
Top right  
−1180  
−6330  
bump/align 4 256  
+1180  
+6330  
R32  
R31  
R30  
R29  
R28  
R27  
R26  
R25  
R24  
R23  
R22  
R21  
R20  
R19  
R18  
R17  
R16  
257  
258  
259  
260  
261  
262  
263  
264  
265  
266  
267  
268  
269  
270  
271  
272  
273  
Table 24 Bonding pads  
PAD  
Pad pitch  
SIZE  
UNIT  
µm  
minimum 70  
62 × 100  
Pad size; Al  
µm  
CBB opening  
Bump dimensions  
36 × 76  
µm  
50 × 90 × 17.5 (± 5)  
maximum 381  
µm  
Wafer thickness  
(including bumps)  
µm  
1999 Aug 24  
45  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
handbook, halfpage  
handbook, halfpage  
80  
µm  
100  
µm  
y centre  
y centre  
x centre  
x centre  
MGS689  
MGS688  
Fig.24 Shape of alignment mark.  
Fig.25 Shape of dummy bump/alignment mark.  
12.66 mm  
handbook, halfpage  
2.36  
mm  
PCF8535  
pitch  
MGS690  
Fig.26 Bonding pads.  
1999 Aug 24  
46  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
R33  
R48  
.
.
.
.
.
.
.
.
.
.
.
.
R47  
C132  
R64  
.
.
.
OSC  
V
LCDIN  
V
LCDOUT  
V
LCDSENSE  
RES  
T3  
T2  
T1  
y
V
DD2  
x
V
0,0  
DD3  
V
DD1  
SDA  
SDAOUT  
SA1  
SA0  
V
SS2  
V
SS1  
T5  
T4  
.
.
.
SCL  
C0  
R32  
.
.
.
R15  
.
.
.
.
.
.
.
.
.
R16  
R0  
PAD ONE  
Dummy bump  
MGS693  
Alignment mark  
The position of the bonding pads is not to scale.  
Fig.27 Bonding pad location (viewed from bump side).  
47  
1999 Aug 24  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
15 DEVICE PROTECTION DIAGRAM  
PADS 223 to 228  
PADS 219 to 222  
PADS 211 to 218  
V
V
DD3  
V
DD2  
DD1  
PADS 243 to 250  
V
V
SS1  
SS1  
V
SS1  
PADS 235 to 242  
V
SS2  
PADS  
PADS 197 to 203  
V
V
SS2  
LCDOUT  
PADS 191 to 196, 204  
V
V
,
LCDIN  
LCDSENSE  
V
V
SS1  
SS1  
V
SS1  
V
DD1  
V
LCDIN  
PADS 254, 255, 230 to 232  
PADS 3 to 166, 169 to 185,  
257 to 273  
SCL, SDA, SDAOUT  
V
SS1  
V
SS1  
V
V
DD1  
DD1  
PADS 190, 233, 234, 252, 251, 207  
PADS 208 to 210  
T1, T2, T3  
OSC, SA0, SA1, T4, T5, RES  
V
V
SS1  
SS1  
MGS672  
Fig.28 Device diode protection diagram.  
48  
1999 Aug 24  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
16 TRAY INFORMATION  
x
A
C
y
D
B
F
E
MGS691  
The dimensions are given in Table 25.  
Fig.29 Tray details.  
Table 25 Dimensions  
DIM.  
DESCRIPTION  
VALUE  
A
pocket pitch in x direction  
pocket pitch in y direction  
pocket width in x direction  
pocket width in y direction  
tray width in x direction  
tray width in y direction  
14.88 mm  
4.06 mm  
12.76 mm  
2.46 mm  
50.8 mm  
50.8 mm  
B
C
D
E
F
x
handbook, halfpage  
P C 8 5 3 5 - 1  
number of pockets in x direction  
number of pockets in y direction  
3
y
11  
MGS692  
The orientation of the IC in a pocket is indicated by the  
position of the IC type name on the die surface with  
respect to the chamfer on the upper left corner of the tray.  
Refer to the bonding pad location diagram for the  
orientating and position of the type name on the die  
surface.  
Fig.30 Tray alignment.  
1999 Aug 24  
49  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
17 DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
18 LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
19 PURCHASE OF PHILIPS I2C COMPONENTS  
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the  
components in the I2C system provided the system conforms to the I2C specification defined by  
Philips. This specification can be ordered using the code 9398 393 40011.  
20 BARE DIE DISCLAIMER  
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of  
ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately  
indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern  
processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no  
control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors  
assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of  
the die. It is the responsibility of the customer to test and qualify their application in which the die is used.  
1999 Aug 24  
50  
Philips Semiconductors  
Objective specification  
65 × 133 pixel matrix driver  
PCF8535  
NOTES  
1999 Aug 24  
51  
Philips Semiconductors – a worldwide company  
Argentina: see South America  
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,  
Tel. +31 40 27 82785, Fax. +31 40 27 88399  
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,  
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139  
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,  
Tel. +64 9 849 4160, Fax. +64 9 849 7811  
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,  
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210  
Norway: Box 1, Manglerud 0612, OSLO,  
Tel. +47 22 74 8000, Fax. +47 22 74 8341  
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,  
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773  
Pakistan: see Singapore  
Belgium: see The Netherlands  
Brazil: see South America  
Philippines: Philips Semiconductors Philippines Inc.,  
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,  
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474  
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,  
51 James Bourchier Blvd., 1407 SOFIA,  
Tel. +359 2 68 9211, Fax. +359 2 68 9102  
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,  
Tel. +48 22 612 2831, Fax. +48 22 612 2327  
Portugal: see Spain  
Romania: see Italy  
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,  
Tel. +1 800 234 7381, Fax. +1 800 943 0087  
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,  
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,  
Tel. +852 2319 7888, Fax. +852 2319 7700  
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,  
Tel. +7 095 755 6918, Fax. +7 095 755 6919  
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,  
Colombia: see South America  
Czech Republic: see Austria  
Tel. +65 350 2538, Fax. +65 251 6500  
Slovakia: see Austria  
Slovenia: see Italy  
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,  
Tel. +45 33 29 3333, Fax. +45 33 29 3905  
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,  
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,  
Tel. +27 11 471 5401, Fax. +27 11 471 5398  
Finland: Sinikalliontie 3, FIN-02630 ESPOO,  
Tel. +358 9 615 800, Fax. +358 9 6158 0920  
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,  
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427  
South America: Al. Vicente Pinzon, 173, 6th floor,  
04547-130 SÃO PAULO, SP, Brazil,  
Tel. +55 11 821 2333, Fax. +55 11 821 2382  
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,  
Tel. +49 40 2353 60, Fax. +49 40 2353 6300  
Spain: Balmes 22, 08007 BARCELONA,  
Tel. +34 93 301 6312, Fax. +34 93 301 4107  
Hungary: see Austria  
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,  
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745  
India: Philips INDIA Ltd, Band Box Building, 2nd floor,  
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,  
Tel. +91 22 493 8541, Fax. +91 22 493 0966  
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,  
Tel. +41 1 488 2741 Fax. +41 1 488 3263  
Indonesia: PT Philips Development Corporation, Semiconductors Division,  
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,  
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080  
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,  
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874  
Ireland: Newstead, Clonskeagh, DUBLIN 14,  
Tel. +353 1 7640 000, Fax. +353 1 7640 200  
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,  
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,  
Tel. +66 2 745 4090, Fax. +66 2 398 0793  
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,  
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007  
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,  
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813  
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),  
Tel. +39 039 203 6838, Fax +39 039 203 6800  
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,  
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461  
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,  
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057  
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,  
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421  
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,  
Tel. +82 2 709 1412, Fax. +82 2 709 1415  
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,  
Tel. +1 800 234 7381, Fax. +1 800 943 0087  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,  
Tel. +60 3 750 5214, Fax. +60 3 757 4880  
Uruguay: see South America  
Vietnam: see Singapore  
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,  
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Middle East: see Italy  
Tel. +381 11 62 5344, Fax.+381 11 63 5777  
For all other countries apply to: Philips Semiconductors,  
Internet: http://www.semiconductors.philips.com  
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,  
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825  
67  
SCA  
© Philips Electronics N.V. 1999  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
465006/01/pp52  
Date of release: 1999 Aug 24  
Document order number: 9397 750 06201  

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