PCF85363ATT1/AJ_技术文档

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm

function, battery switch-over time stamp input, and I²C-bus

Rev. 3.1 — 18 June 2021

Product data sheet

1 General description

The PCF85363A is a CMOS¹Real-Time Clock (RTC) and calendar optimized for low

power consumption and with automatic switching to battery on main power loss. The

RTC can also be configured as a stop-watch (elapsed time counter). Three time log

registers triggered from battery switch-over as well as input driven events. Featuring

clock output and two independent interrupt signals, two alarms, I²C interface and quartz

crystal calibration, 64 byte battery backed-up RAM.

For a selection of NXP Real-Time Clocks, see Table 71.

2 Features and benefits

• UL Recognized Component (PCF85363ATL)

• Provides year, month, day, weekday, hours, minutes, seconds and 100th seconds

based on a 32.768 kHz quartz crystal

• Stop-watch mode for elapsed time counting. From 100th seconds to 999ꢀ999 hours

• Two independent alarms

• Battery back-up circuit

• WatchDog timer

• Three timestamp registers

• Two independent interrupt generators plus predefined interrupts at every second,

minute, or hour

• 64 byte battery backed-up RAM

• Frequency adjustment via programmable offset register

• Clock operating voltage: 0.9 V to 5.5 V

• Low current; typical 0.28 μA at V_DD= 3.0 V and T_amb= 25 °C

• 400 kHz two-line I²C-bus interface (at V_DD= 1.8 V to 5.5 V)

• Programmable clock output for peripheral devices (32.768 kHz, 16.384 kHz, 8.192 kHz,

4.096 kHz, 2.048 kHz, 1.024 kHz, and 1 Hz)

• Configurable oscillator circuit for a wide variety of quartzes: C_L= 6 pF, C_L= 7 pF, and

C_L= 12.5 pF

3 Applications

• Elapsed time counter

• Network powered devices

• Printers and copiers

• Battery backed up systems

• Digital voice recorders

1 The definition of the abbreviations and acronyms used in this data sheet can be found in Section 23.

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

• Data loggers

• Mobile equipment

• White goods

• Digital cameras

• Accurate high duration timer

4 Ordering information

Table 1.ꢀOrdering information

Topside

marking

Package

Name

Type number

Description

Version

PCF85363ATL/A

363A

DFN2626-10 plastic thermal enhanced extremely thin small outline

SOT1197-1

package; no leads; 10 terminals; body 2.6 x 2.6 x 0.5

mm

PCF85363ATT/A

363A

TSSOP8

plastic thin shrink small outline package; 8 leads; body

width 3 mm

SOT505-1

PCF85363ATT1/A 363A

TSSOP10

plastic thin shrink small outline package; 10 leads; body SOT552-1

width 3 mm

4.1 Ordering options

Table 2.ꢀOrdering options

Type number

Orderable part

number

Package

Packing method

Minimum

order quantity range

Temperature

PCF85363ATL/A

PCF85363ATT/A

PCF85363ATT1/A PCF85363ATT1/AJ ^[1]TSSOP10

PCF85363ATL/AX

PCF85363ATT/AJ

DFN2626-10

TSSOP8

REEL 7" Q1 NDP

REEL 13" Q1 NDP

4000

2500

-40 °C to +85 °C

REEL 13" Q1 NDP

2500

PCF85363ATT1/AZ TSSOP10

[1] Will be discontinued in 2021; drop in replacement is PCF85363ATT1/AZ. Refer to PCN 202104008A.

PCF85363A

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Product data sheet

Rev. 3.1 — 18 June 2021

2 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

5 Block diagram

Alarm control

64 byte RAM

100TH seconds

Seconds

SDA

SCL

2

Minutes

Alarm 1

Alarm 2

I C interface

Stopwatch

Hours xxxx00

Hours xx00xx

Hours 00xxxx

RTC

Hours

Weekdays

Days

Time stamp 1

Time stamp 2

Time stamp 3

Months

Years

-

Time stamp control

VSS

V

DD(int)

Mechanical

switch detec.

batt_mode

V

DD

Stopwatch

control

VDD

VBAT

V

/V

BAT TH

V

DD(int)

Battery switch over

batt_mode

(1)

TS

(CLK/INTB)

INTA

(CLK)

Alarms

Time stamps

Periodic interrupt

Offset calibration

WatchDog

Pulse/

level

Pulse/

level

Battery mode

Interrupt

generation

(1)

CLK

32768 Hz

quartz

oscillator

OSCI

CLK

generation

OSCO

PCF85363A

Offset

calibration

WatchDog

aaa-011044

1. Not available on all package types.

Figure 1.ꢀBlock diagram of PCF85363A

PCF85363A

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Product data sheet

Rev. 3.1 — 18 June 2021

3 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

6 Pinning information

6.1 Pinning

terminal 1

index area

OSCI

OSCO

1

2

3

4

5

10 VDD

9

8

7

6

INTA (CLK)

VBAT

CLK

SCL

SDA

PCF85363ATL

TS (CLK/INTB)

VSS

aaa-011064

Transparent top view

For mechanical details, see Figure 43.

Figure 2.ꢀPin configuration for PCF85363ATL (DFN2626-10)

OSCI 1

OSCO 2

VBAT 3

VSS 4

8 VDD

7 INTA(CLK)

6 SCL

PCF85363ATT

5 SDA

aaa-011063

For mechanical details, see Figure 44.

Figure 3.ꢀPin configuration for PCF85363ATT (TSSOP8)

OSCI

OSCO

1

2

3

4

5

10 VDD

9

8

7

6

INTA (CLK)

VBAT

CLK

SCL

SDA

PCF85363ATT

TS (CLK/INTB)

VSS

aaa-011065

For mechanical details, see Figure 45.

Figure 4.ꢀPin configuration for PCF85363ATT1 (TSSOP10)

PCF85363A

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Product data sheet

Rev. 3.1 — 18 June 2021

4 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

6.2 Pin description

Table 3.ꢀPin description

Input or input/output pins must always be at a defined level (V_SSor V_DD) unless otherwise specified.

Symbol

PCF85363ATL

(DFN2626-10)

PCF85363ATT

(TSSOP8)

PCF85363ATT1

(TSSOP10)

Type

Description

Primary use

Secondary use

OSCI

1

2

3

4

1

2

3

-

1

2

3

4

input

oscillator input

-

OSCO

output

supply

oscillator output

VBAT

battery backup supply voltage ^[1]

can be configured with TSPM[1:0] ^[2]

timestamp input

TS (CLK/INTB)

input/

output

INTB and CLK output (push-

pull); stop-watch control

VSS

SDA

5 ^[3]

6

4

5

6

supply

ground supply voltage

serial data line

-

input/

output

SCL

7

8

9

6

-

7

8

9

input

serial clock input

CLK (push-pull)

-

CLK

output

INTA (CLK)

7

can be configured with INTAPM[1:0] ^[2]

interrupt output (open-drain)

CLK output (open-drain)

VDD

10

8

10

supply

supply voltage

-

[1] Connect to V_DDif not used.

[2] See Table 6 and Table 46.

[3] The die paddle (exposed pad) is connected to V_SSthrough high ohmic (non-conductive) silicon attach and should be electrically isolated. It is good

engineering practice to solder the exposed pad to an electrically isolated PCB copper pad as shown in Figure 43 for better heat transfer but it is not

required as the RTC doesn’t consume much power. In no case should traces be run under the package exposed pad.

7 Functional description

The PCF85363A contains 8-bit registers for time information, for timestamp information

and registers for system configuration. Included is an auto-incrementing register address,

an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider which

provides the source clock for the Real-Time Clock (RTC) and calender, and an I²C-bus

interface with a maximum data rate of 400 kbit/s.

The built-in address register will increment automatically after each read or write of a

data byte. After register 2Fh, the auto-incrementing will wrap around to address 00h.

When the RAM is accessed, the wrap around will happen after address 7Fh, (see

Figure 5).

address register

00h

01h

02h

03h

...

40h

41h

42h

43h

...

auto-increment

2Dh

2Eh

2Fh

7Dh

7Eh

7Fh

wrap around

Time and configuration

registers

RAM registers

aaa-011066

Figure 5.ꢀAddress register incrementing

PCF85363A

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Product data sheet

Rev. 3.1 — 18 June 2021

5 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

00h

:

1st RAM byte

2nd RAM byte

3rd RAM byte

40h

:

Time registers

42h

:

07h

08h

:

Alarm registers

:

10h

11h

:

Timestamp registers

:

23h

24h

25h

:

Offset register

:

Control registers

:

2Bh

Single RAM byte

Watchdog

2Ch

2Dh

62nd RAM byte

63rd RAM byte

64th RAM byte

7Dh

:

2Eh

2Fh

Stop and reset

7Fh

Time and configuration

registers

RAM registers

aaa-011067

Figure 6.ꢀRegister map

All registers (see Table 4, Table 5, and Table 6) are designed as addressable 8-bit

parallel registers although not all bits are implemented. Figure 6 gives an overview of the

address map.

The 100th seconds, seconds, minutes, hours, days, months, and years as well as the

corresponding alarm registers are all coded in Binary Coded Decimal (BCD) format.

When one of the RTC registers is read, the contents of all time counters are frozen.

Therefore, faulty reading of the clock and calendar during a carry condition is prevented.

7.1 Registers organization overview

7.1.1 Time mode registers

The PCF85363A has two time mode register sets, one for the real-time clock mode and

one for the stopwatch clock mode. The access to these registers can be switched by the

RTCM bit in the Function control register (28h), see Table 6 and Table 53.

PCF85363A

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Product data sheet

Rev. 3.1 — 18 June 2021

6 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

real-time clock mode

RTCM

0

register set

1

stopwatch mode

register set

aaa-009600

Figure 7.ꢀTime mode register set selection

7.1.1.1 RTC mode time registers overview (RTCM = 0)

Table 4.ꢀRTC mode time registers

Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61.

Address

Register name

Bit

7

Reference

6

5

4

3

2

1

0

RTC time and date registers

00h

01h

02h

03h

100th_seconds

Seconds

Minutes

100TH_SECONDS (0 to 99)

Section 7.2

OS

SECONDS (0 to 59)

MINUTES (0 to 59)

EMON

-

Hours

-

AMPM

HOURS (1 to 12) in 12 hour mode

HOURS (0 to 23) in 24 hour mode

04h

Days

-

DAYS (1 to 31)

05h

Weekdays

Months

Years

-

WEEKDAYS (0 to 6)

06h

MONTHS (1 to 12)

07h

YEARS (0 to 99)

RTC alarm1

08h

Second_alarm1

Minute_alarm1

Hour_alarm1

-

SEC_ALARM1 (0 to 59)

MIN_ALARM1 (0 to 59)

AMPM

Section 7.4

09h

0Ah

-

HR_ALARM1 (1 to 12) in 12 hour mode

HR_ALARM1 (0 to 23) in 24 hour mode

DAY_ALARM1 (1 to 31)

0Bh

Day_alarm1

-

0Ch

Month_alarm1

-

MON_ALARM1 (1 to 12)

RTC alarm2

0Dh

Minute_alarm2

Hour_alarm2

-

MIN_ALARM2 (0 to 59)

Section 7.4

0Eh

-

AMPM

-

HR_ALARM2 (1 to 12) in 12 hour mode

0Fh

Weekday_alarm2

-

WDAY_ALARM2 (0 to 6)

RTC alarm enables

10h

Alarm_enables

WDAY_A2E

HR_A2E

MIN_A2E

MON_A1E

DAY_A1E

HR_A1E

MIN__A1E

SEC__A1E

Section 7.4

Section 7.7

RTC timestamp1 (TSR1)

11h

12h

13h

TSR1_seconds

TSR1_minutes

TSR1_hours

-

TSR1_SECONDS (0 to 59)

TSR1_MINUTES (0 to 59)

-

AMPM

TSR1_HOURS (1 to 12) in 12 hour mode

TSR1_HOURS (0 to 23) in 24 hour mode

TSR1_DAYS (1 to 31)

14h

15h

16h

TSR1_days

TSR1_months

TSR1_years

-

TSR1_MONTHS (1 to 12)

TSR1_YEARS (0 to 99)

RTC timestamp2 (TSR2)

PCF85363A

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Product data sheet

Rev. 3.1 — 18 June 2021

7 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Table 4.ꢀRTC mode time registers...continued

Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61.

Address

Register name

Bit

Reference

7

-

6

5

4

3

2

1

0

17h

18h

19h

TSR2_seconds

TSR2_minutes

TSR2_hours

TSR2_SECONDS (0 to 59)

TSR2_MINUTES (0 to 59)

Section 7.7

-

AMPM

TSR2_HOURS (1 to 12) in 12 hour mode

TSR2_HOURS (0 to 23) in 24 hour mode

TSR2_DAYS (1 to 31)

1Ah

1Bh

1Ch

TSR2_days

TSR2_months

TSR2_years

-

TSR2_MONTHS (1 to 12)

TSR2_YEARS (0 to 99)

RTC timestamp3 (TSR3)

1Dh

1Eh

1Fh

TSR3_seconds

TSR3_minutes

TSR3_hours

-

TSR3_SECONDS (0 to 59)

TSR3_MINUTES (0 to 59)

Section 7.7

-

AMPM

TSR3_HOURS (1 to 12) in 12 hour mode

TSR3_HOURS (0 to 23) in 24 hour mode

TSR3_DAYS (1 to 31)

20h

21h

22h

TSR3_days

TSR3_months

TSR3_years

-

TSR3_MONTHS (1 to 12)

TSR3_YEARS (0 to 99)

RTC timestamp mode control

23h TSR_mode

TSR3M[1:0]

-

TSR2M[2:0]

TSR1M[1:0]

Section 7.7

7.1.1.2 Stop-watch mode time registers (RTCM = 1)

Table 5.ꢀStop-watch mode time registers

Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61.

Address

Register name

Bit

7

Reference

6

5

4

3

2

1

0

Stop-watch time registers

00h

01h

02h

03h

04h

05h

06h

07h

100th_seconds

Seconds

100TH_SECONDS (0 to 99)

Section 7.3

OS

SECONDS (0 to 59)

MINUTES (0 to 59)

Minutes

EMON

Hours_xx_xx_00

Hours_xx_00_xx

Hours_00_xx_xx

not used

HR_XX_XX_00 (0 to 99)

HR_XX_00_XX (0 to 99)

HR_00_XX_XX (0 to 99)

-

not used

Stop-watch alarm1

08h

09h

0Ah

0Bh

0Ch

Second_alm1

-

SEC_ALM1 (0 to 59)

MIN_ALM1 (0 to 59)

Section 7.4

Minute_alm1

Hr_xx_xx_00_alm1

Hr_xx_00_xx_alm1

Hr_00_xx_xx_alm1

HR_XX_XX_00_ALM1 (0 to 99)

HR_XX_00_XX_ALM1 (0 to 99)

HR_00_XX_XX_ALM1 (0 to 99)

Stop-watch alarm2

0Dh

0Eh

0Fh

Minute_alm2

-

MIN_ALM2 (0 to 59)

Section 7.4

Hr_xx_00_alm2

Hr_00_xx_alm2

HR_XX_00_ALM2 (0 to 99)

HR_00_XX_ALM2 (0 to 99)

Stop-watch alarm enables

10h Alarm_enables

HR_00_XX_

A2E

HR_XX_00_

A2E

MIN_A2E

HR_00_XX_

XX_A1E

HR_XX_00_

XX_A1E

HR_XX_XX_ MIN_A1E

00_A1E

SEC_A1E

Section 7.4

Section 7.7

Stop-watch timestamp1 (TSR1)

11h

12h

13h

TSR1_seconds

TSR1_minutes

-

TSR1_SECONDS (0 to 59)

TSR1_MINUTES (0 to 59)

TSR1_hr_xx_xx_00

TSR1_HR_XX_XX_00 (0 to 99)

PCF85363A

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Product data sheet

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8 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Table 5.ꢀStop-watch mode time registers...continued

Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61.

Address

Register name

Bit

7

Reference

6

5

4

3

2

1

0

14h

15h

16h

TSR1_hr_xx_00_xx

TSR1_hr_00_xx_xx

not used

TSR1_HR_XX_00_XX (0 to 99)

TSR1_HR_00_XX_XX (0 to 99)

-

Stop-watch timestamp2 (TSR2)

17h

18h

19h

1Ah

1Bh

1Ch

TSR2_seconds

TSR2_minutes

TSR2_hr_xx_xx_00

TSR2_hr_xx_00_xx

TSR2_hr_00_xx_xx

not used

-

TSR2_SECONDS (0 to 59)

TSR2_MINUTES (0 to 59)

Section 7.7

TSR2_HR_XX_XX_00 (0 to 99)

TSR2_HR_XX_00_XX (0 to 99)

TSR2_HR_00_XX_XX (0 to 99)

-

Stop-watch timestamp3 (TSR3)

1Dh

1Eh

1Fh

20h

21h

22h

TSR3_seconds

TSR3_minutes

TSR3_hr_xx_xx_00

TSR3_hr_xx_00_xx

TSR3_hr_00_xx_xx

not used

-

TSR3_SECONDS (0 to 59)

TSR3_MINUTES (0 to 59)

Section 7.7

TSR3_HR_XX_XX_00 (0 to 99)

TSR3_HR_XX_00_XX (0 to 99)

TSR3_HR_00_XX_XX (0 to 99)

-

Stop-watch timestamp mode control

23h TSR_mode

TSR3M[1:0]

TSR2M[2:0]

TSR1M[1:0]

Section 7.7

7.1.2 Control registers overview

Table 6.ꢀControl and function registers overview

Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 61.

Address

Register name

Bit

7

Reference

6

5

4

3

2

1

0

Offset register

24h

Offset

OFFSET[7:0]

Section 7.8

Control registers

25h

26h

27h

28h

29h

2Ah

2Bh

Oscillator

CLKIV

-

OFFM

-

12_24

-

LOWJ

BSOFF

TSIM

OSCD[1:0]

BSRR

CL[1:0]

Section 7.10

Section 7.11

Section 7.12

Section 7.13

Section 7.9

Section 7.14

Battery_switch

Pin_IO

BSM[1:0]

BSTH

CLKPM

100TH

ILPA

ILPB

PIF

TSPULL

PI[1:0]

PIEA

PIEB

A2F

TSL

TSPM[1:0]

STOPM

A2IEA

INTAPM[1:0]

Function

RTCM

A1IEA

A1IEB

WDF

COF[2:0]

TSRIEA

TSRIEB

TSR3F

INTA_enable

INTB_enable

Flags

OIEA

OIEB

A1F

BSIEA

BSIEB

TSR2F

WDIEA

WDIEB

TSR1F

A2IEB

BSF

Single RAM byte

2Ch

RAM_byte

B[7:0]

WDM

-

Section 7.6

Section 7.5

Section 7.16

Section 7.15

Section 7.17

WatchDog registers

2Dh

WatchDog

WDR[4:0]

WDS[1:0]

Stop

2Eh

Stop_enable

Resets

-

STOP

CTS

Reset

2Fh

CPR

B[7:0]

0

1

0

SR

1

0

RAM (64 byte)

40h to 7Fh RAM

PCF85363A

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Product data sheet

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

7.2 RTC mode time and date registers

RTC mode is enabled by setting RTCM = 0. These registers are coded in the BCD format

to simplify application use.

Default state is:

Time

00:00:00.00

Date

2000 01 01

Weekday

Saturday

Monitor bits

OS = 1, EMON = 0

Table 7.ꢀTime and date registers in RTC mode (RTCM = 0)

Bit positions labeled as - are not implemented and return 0 when read.

Address

Register name

Upper-digit (ten’s place)

Digit (unit place)

Bit 7

0 to 9

OS

Bit 6

Bit 5

Bit 4

Bit 3

0 to 9

-

Bit 2

Bit 1

Bit 0

00h

01h

02h

03h

100th_seconds ^[1]

Seconds

0 to 5

-

Minutes

Hours ^[2]

EMON

-

AMPM

0 to 1

0 to 2

04h

05h

06h

07h

Days ^[3]

Weekdays

Months

Years

-

0 to 3

-

0 to 6

-

0 to 1

0 to 9

[1] The 100th_seconds register is only available when the 100TH mode is enabled, see Section 7.13.1. When the 100TH mode is disabled, this register

always returns 0.

[2] Hour mode is set by the 12_24 bit in the Oscillator register, see Section 7.10.

[3] If the year counter contains a value, which is exactly divisible by 4, the PCF85363A compensates for leap years by adding a 29th day to February.

7.2.1 Definition of BCD

The Binary-Coded Decimal (BCD) is an encoding of numbers where each digit is

represented by a separate bit field. Each bit field may only contain the values 0 to 9. In

this way, decimal numbers and counting is implemented.

Example: 59 encoded as an entire number is represented by 3Bh or 11ꢀ1011. In BCD the

5 is represented as 5h or 0101 and the 9 as 9h or 1001 which combines to 59h.

PCF85363A

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Product data sheet

Rev. 3.1 — 18 June 2021

10 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Table 8.ꢀBCD coding

Value in

decimal

Upper-digit (ten’s place)

Digit (unit place)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00

01

02

:

0

:

0

:

0

1

:

0

1

0

:

0

:

0

:

0

1

:

0

1

0

:

09

10

:

1

0

:

0

:

0

:

1

0

:

1

0

:

0

:

0

:

1

0

:

98

99

1

0

1

0

1

7.2.2 OS: Oscillator stop

When the oscillator of the PCF85363A is stopped, the OS status bit is set. The oscillator

can be stopped, for example, by connecting one of the oscillator pins OSCI or OSCO to

ground. The oscillator is considered to be stopped during the time between power-on and

stable crystal resonance. This time can be in the range of 200 ms to 2 s depending on

crystal type, temperature, and supply voltage.

The status bit remains set until cleared by command (see Figure 8). If the bit cannot

be cleared, then the oscillator is not running. This method can be used to monitor the

oscillator and to determine if the supply voltage has reduced to the point where oscillation

fails.

OS = 1 and bit can not be cleared

OS = 1 and bit can be cleared

V

DD

oscillation

OS flag

OS bit set when

oscillation stops

OS bit cleared

by software

t

oscillation now stable

aaa-009576

Figure 8.ꢀOS status bit

7.2.3 EMON: event monitor

The EMON can be used to monitor the status of all the flags in the Flags register, see

Section 7.14. When one or more of the flags is set, then the EMON bit returns a logic 1.

The EMON bit cannot be cleared. EMON returns a logic 0 when all flags are cleared.

See Figure 21 for a pictorial representation.

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7.2.4 Definition of weekdays

Definition may be reassigned by the user.

Table 9.ꢀWeekday assignments

Day

Bit

2

1

0

1

0

1

0

1

0

1

0

1

0

Sunday

0

Monday

Tuesday

Wednesday

Thursday

Friday

0

1

Saturday

1

7.2.5 Definition of months

Table 10.ꢀMonth assignments in BCD format

Month

Upper-digit

(ten’s place)

Digit (unit place)

Bit 4

0

Bit 3

0

Bit 2

Bit 1

0

Bit 0

1

January

February

March

0

1

0

1

0

1

April

0

May

0

1

June

0

1

0

July

0

1

August

September

October

November

December

0

1

0

1

0

1

0

1

0

1

0

1

0

7.2.6 Setting and reading the time in RTC mode

Figure 9 shows the data flow and data dependencies starting from the 100 Hz clock tick.

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100 Hz tick

100TH_SECOND

1 Hz tick

100TH

SECONDS

MINUTES

12_24

HOURS

DAYS

LEAP YEAR

CALCULATION

WEEKDAY

MONTHS

YEARS

aaa-009580

Figure 9.ꢀData flow for the time function

During read operations, the time counting circuits (memory locations 00h through 07h)

are copied into an output register. The RTC continues counting in the background.

When reading or writing the time it is very important to make a read or write access in

one go, that is, setting or reading 100th seconds through to years should be made in

one single access. Failing to comply with this method could result in the time becoming

corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in

a second access the date is set, it is possible that the time increments between the two

accesses. A similar problem exists when reading. A roll-over may occur between reads

thus giving the minutes from one moment and the hours from the next.

Before setting the time, the STOP bit should be set and the prescalers should be cleared

(see Section 7.16).

An example of setting the time: 14 hours, 23 minutes and 19 seconds.

• I²C START condition

• I²C slave address + write (A2h)

• register address (2Eh)

• write data (set STOP, 01h)

• write data (clear prescaler, A4h)

• write data (100th seconds, 00h)

• write data (Hours, 14h)

• write data (Minutes, 23h)

• write data (Seconds, 19h)

• I²C START condition

• I²C slave address + write (A2h)

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• register address (2Eh)

• write data (clear STOP, 00h). Time starts counting from this point

• I²C STOP condition

7.3 Stop-watch mode time registers

These registers are coded in the BCD format to simplify application use.

Stop-watch mode is enabled by setting RTCM = 1. In stop-watch mode, the PCF85363A

counts from 100th seconds to 999ꢀ999 hours. There are no days, weekdays, months or

year registers.

Default state is:

Time

00ꢀ00ꢀ00:00:00.00

Monitor bits

OS = 1, EMON = 0 (see Section 7.2.2 and Section 7.2.3)

Table 11.ꢀTime registers in stop-watch mode (RTCM = 1)

Bit positions labeled as - are not implemented and return 0 when read.

Address Register name Upper-digit (ten’s place)

Digit (unit place)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

0 to 9

-

Bit 2

Bit 1

Bit 0

00h

01h

02h

03h

04h

05h

06h

07h

100th_seconds^[1]0 to 9

Seconds

Minutes

OS

0 to 5

EMON 0 to 5

Hours_xx_xx_00 0 to 9

Hours_xx_00_xx 0 to 9

Hours_00_xx_xx 0 to 9

not used

-

[1] The 100th_seconds register is only available when the 100TH mode is enabled, see Section 7.13.1. When the 100TH

mode is disabled, this register always returns 0.

1. The 100th_seconds register is only available when the 100TH mode is enabled, see

Section 7.13.1. When the 100TH mode is disabled, this register always returns 0.

7.3.1 Setting and reading the time in stop-watch mode

Figure 10 shows the data flow and data dependencies starting from the 100 Hz clock tick.

During read operations, the time counting circuits (memory locations 00h through 07h)

are copied into an output register. The RTC continues counting in the background.

When reading or writing the time it is very important to make a read or write access in

one go, that is, setting or reading 100th_seconds through to HR_00_xx_xx should be

made in one single access. Failing to comply with this method could result in the time

becoming corrupted.

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As an example, if the seconds value is set in one access and then in a following

access the minutes value is set, it is possible that the time increments between the two

accesses. A similar problem exists when reading. A roll-over may occur between reads

thus giving the seconds from one moment and the minutes from the next.

100 Hz tick

100TH_SECONDS

1 Hz tick

100TH

SECONDS

MINUTES

HR_XX_XX_00

HR_XX_00_XX

HR_00_XX_XX

aaa-009581

Figure 10.ꢀData flow for the stop-watch function

7.4 Alarms

There are two independent alarms. Each is separately configured and may be used

to generate an interrupt. In RTC mode, an alarm is configured for time and date. In

stop-watch mode when the RTC is functioning as an elapsed time counter, an alarm is

configured for time only.

7.4.1 Alarms in RTC mode

In RTC mode, Alarm 1 can be configured from seconds to months. Alarm 2 operates

on minutes, hours and weekday. Each segment of the time is independently enabled.

Alarms can be output on the INTA and INTB pins.

7.4.1.1 Alarm1 and alarm2 registers in RTC mode

Setting the time for alarm1: Only the information which is relevant for the alarm condition

must to be programmed. The unused parts are ignored.

Table 12.ꢀAlarm1 and alarm2 registers in RTC mode coded in BCD (RTCM = 0)

Bit positions labeled as - are not implemented.

Address Register name

Upper-digit (ten’s place)

Digit (unit place)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RTC alarm1 registers

08h

Second_alarm1

-

0 to 5

0 to 9

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Table 12.ꢀAlarm1 and alarm2 registers in RTC mode coded in BCD (RTCM = 0)...continued

Bit positions labeled as - are not implemented.

Address Register name

Upper-digit (ten’s place)

Digit (unit place)

Bit 7

Bit 6

0 to 5

-

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

09h

0Ah

Minute_alarm1

Hour_alarm1

-

0 to 9

AMPM 0 to 1 0 to 9

0 to 2

0 to 3

-

0 to 9

0Bh

0Ch

Day_alarm1

-

Month_alarm1

0 to 1 0 to 9

RTC alarm2 registers

0Dh

0Eh

Minute_alarm2

Hour_alarm2

-

0 to 5

-

0 to 9

AMPM 0 to 1 0 to 9

0 to 2

-

0 to 9

-

0Fh

Weekday_alarm2 -

-

0 to 6

7.4.1.2 Alarm1 and alarm2 control in RTC mode

Table 13.ꢀAlarm_enables- alarm enable control register (address 10h) bit

description

Bit

Symbol

Value

Description

RTC alarm2

7

6

5

WDAY_A2E

weekday alarm2 enable

disabled

0^[1]

1

enabled

HR_A2E

MIN_A2E

hour alarm2 enable

disabled

0^[1]

1

enabled

minute alarm2 enable

disabled

0^[1]

1

enabled

RTC alarm1

4

3

2

MON_A1E

month alarm1 enable

disabled

0^[1]

1

enabled

DAY_A1E

HR_A1E

day alarm1 enable

disabled

0^[1]

1

enabled

hour alarm1 enable

disabled

0^[1]

1

enabled

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Table 13.ꢀAlarm_enables- alarm enable control register (address 10h) bit

description...continued

Bit

Symbol

Value

Description

minute alarm1 enable

disabled

1

MIN_A1E

0^[1]

1

enabled

0

SEC_A1E

second alarm1 enable

disabled

0^[1]

1

enabled

[1] Default value.

7.4.1.3 Alarm1 and alarm2 function in RTC mode

The registers at addresses 08h through 0Ch contain alarm1 information. When one

or more of these registers is loaded with second, minute, hour, day, or month, and

its corresponding alarm enable bit (SEC_A1E to MON_A1E) is set logic 1, then that

information is compared with the current second, minute, hour, day, and month.

The registers at addresses 0Dh through 0Fh contain alarm2 information. When one or

more of these registers is loaded with minute, hour or weekday, and its corresponding

alarm enable bit (MIN_A2E to WDAY_A2E) is set logic 1, then that information is

compared with the current minute, hour and weekday.

Alarm registers which have their alarm enable bit at logic 0 are ignored.

When the time increments to match the enabled alarms, the alarm flag in the Flags

register (Section 7.14) is set. A1F for alarm1 and A2F for alarm2. The alarm flag is

cleared by command.

When the time increments to match the enabled alarms, an interrupt can be generated.

See Section 7.4.3.

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and I²C-bus

example

check now signal

SEC_A1E

SEC_A1E = 0

SECOND ALARM1

=

0

1

SECOND TIME

MIN_A1E

MINUTE ALARM1

=

MINUTE TIME

HR_A1E

HOUR ALARM1

(1)

set alarm flag A1F

=

HOUR TIME

DAY_A1E

MON_A1E

DAY ALARM1

DAY TIME

MONTH ALARM1

MONTH TIME

example

check now signal

MINUTE ALARM2

MIN_A2E

HR_A2E

MIN_A2E = 0

=

0

1

MINUTE TIME

HOUR ALARM2

HOUR TIME

(1)

set alarm flag A2F

WDAY_A2E

WEEKDAY ALARM2

WEEKDAY TIME

aaa-009582

1. Only when all enabled alarm settings are matching.

The flag is set only on increment to a matched case (and not all the time it is equal).

Figure 11.ꢀAlarm1 and alarm2 function block diagram (RTC mode)

7.4.2 Alarms in stop-watch mode

In stop-watch mode, Alarm 1 can be configured from seconds to 999ꢀ999 hours. Alarm 2

operates on minutes up to 9ꢀ999 hours.

7.4.2.1 Alarm1 and alarm2 registers in stop-watch mode

Setting the time for alarm1 and alarm2: Only the information which is relevant for the

alarm condition must to be programmed. The unused parts are ignored.

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Table 14.ꢀAlarm1 and alarm2 registers in stop-watch mode coded in BCD (RTCM =

1)

Bit positions labeled as - are not implemented.

Address Register name

Upper-digit (ten’s place)

Digit (unit place)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Stop-watch alarm1 registers

08h

09h

0Bh

0Ch

Second_alm1

Minute_alm1

-

0 to 5

0 to 9

Hr_xx_xx_00_alm1 0 to 9

Hr_xx_00_xx_alm1 0 to 9

Hr_00_xx_xx_alm1 0 to 9

Stop-watch alarm2 registers

0Dh

0Eh

0Fh

Minute_alm2

-

0 to 5

0 to 9

Hr_xx_00_alm2

Hr_00_xx_alm2

0 to 9

7.4.2.2 Alarm1 and alarm2 control in stop-watch mode

Table 15.ꢀAlarm_enables- alarm enable control register (address 10h) bit

description

Bit

Symbol

Value

Description

Stop-watch alarm2

7

6

5

HR_00_XX_A2E

thousands of hours alarm2 enable

0^[1]

1

disabled

enabled

HR_XX_00_A2E

MIN_A2E

tens of hours alarm2 enable

disabled

0^[1]

1

enabled

minute alarm2 enable

disabled

0^[1]

1

enabled

Stop-watch alarm1

4

3

2

HR_00_XX_XX_A1E

100 thousands of hours alarm1 enable

0^[1]

1

disabled

enabled

HR_XX_00_XX_A1E

HR_XX_XX_00_A1E

thousands of hours alarm1 enable

0^[1]

1

disabled

enabled

tens of hour alarm1 enable

disabled

0^[1]

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Table 15.ꢀAlarm_enables- alarm enable control register (address 10h) bit

description...continued

Bit

Symbol

Value

Description

enabled

1

MIN_A1E

minute alarm1 enable

disabled

0^[1]

1

enabled

0

SEC_A1E

second alarm1 enable

disabled

0^[1]

1

enabled

[1] Default value.

7.4.2.3 Alarm1 and alarm2 function in stop-watch mode

The registers at addresses 08h through 0Ch contain alarm1 information. When one or

more of these registers is loaded with second, minute, and hours, and its corresponding

alarm enable bit (SEC_A1E to HR_00_XX_XX_A1E) is set logic 1, then that information

is compared with the current second, minute, and hours.

The registers at addresses 0Dh through 0Fh contain alarm2 information. When one

or more of these registers is loaded with minute and hours, and its corresponding

alarm enable bit (MIN_A2E to HR_00_XX_A2E) is set logic 1, then that information is

compared with the current minute and hours.

Alarm registers which have their alarm enable bit at logic 0 are ignored.

When the time increments to match the enabled alarms, the alarm flag in the Flags

register (Section 7.14) is set. A1F for alarm1 and A2F for alarm2. The alarm flag is

cleared by command.

When the time increments to match the enabled alarms, an interrupt can be generated.

See Section 7.4.3.

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and I²C-bus

example

check now signal

SEC_A1E

SEC_A1E = 0

SECOND ALARM1

=

0

1

SECOND TIME

MIN_A1E

MINUTE ALARM1

=

MINUTE TIME

HR_xx_xx_00_A1E

HR_xx_xx_00 ALARM1

(1)

set alarm flag A1F

=

xx_xx_00 HOUR TIME

HR_xx_00_xx_A1E

HR_00_xx_xx_A1E

HR_xx_00_xx ALARM1

xx_00_xx HOUR TIME

HR_00_xx_xx ALARM1

00_xx_xx HOUR TIME

example

check now signal

MINUTE ALARM2

MIN_A2E

MIN_A2E = 0

=

0

1

MINUTE TIME

HR_xx_00_A2E

HR_00_xx_A2E

HR_xx_00 ALARM2

(1)

set alarm flag A2F

xx_xx_00 HOUR TIME

HR_00_xx ALARM2

xx_00_xx HOUR TIME

aaa-009583

1. Only when all enabled alarm settings are matching.

The flag is set only on increment to a matched case (and not all the time it is equal).

Figure 12.ꢀAlarm1 and alarm2 function block diagram (stop-watch mode)

7.4.3 Alarm interrupts

The generation of interrupts from the alarm functions is controlled via the alarm interrupt

enable bits; A1IEA, A1IEB, A2IEA, A2IEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

The assertion of flags A1F or A2F can be used to generate an interrupt at the pins

INTA and INTB. The interrupt may be generated as a pulse signal every time the time

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increments to match the alarm setting or as a permanently active signal which follows the

condition of bit A1F and/or A2F. See Section 7.9 for interrupt control.

A1F and A2F remain set until cleared by command. Once an alarm flag has been

cleared, it will only be set again when the time increments to match the alarm condition

once more.

When an interrupt pin is configured to pulse mode and if an alarm flag is not cleared and

the time increments to match the alarm condition again, then a repeated interrupt pulse

will be generated.

7.5 WatchDog

Table 16.ꢀWatchDog - WatchDog control and register (address 2Dh) bit description

Bit

Symbol

Value

Description

7

WDM

WatchDog mode

0^[1]

1

single shot

repeat mode

6 to 2

1 to 0

WDR[4:0]

WDS[1:0]

WatchDog register bits

Write: WatchDog counter load value

Read: current counter value

WatchDog step size (source clock)

4 seconds (0.25 Hz)

1 second (1 Hz)

0h^[1]to 1Fh

0h to 1Fh

00^[1]

01

10

¹⁄₄second (4 Hz)

1

11

⁄₁₆second (16 Hz)

[1] Default value.

7.5.1 WatchDog functions

The WatchDog has four selectable step sizes allowing for periods in the range from 62.5

ms to 124 seconds. For periods greater than 2 minutes, the alarm function can be used.

Table 17.ꢀWatchDog durations

WDS[1:0] WatchDog step Delay

size ^[1]

Minimum WatchDog duration Maximum WatchDog duration

WDR = 1

WDR = 31

00

01

10

11

4 s

1 s

¹⁄₄s

4 s

124 s

1 s

31 s

0.25 s

0.0625 s

7.75 s

1

⁄₁₆s

1.9375 s

[1] Time periods can be affected by correction pulses.

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Remark: Note that all timings are generated from the 32.768 kHz oscillator and are

based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency

results in deviation in timings. This is not applicable to interface timing.

The WatchDog counts down from a software-loaded 5-bit binary value, WDR[4:0], in

register WatchDog. Loading the counter with 0 stops the WatchDog. Loading the counter

with a non-0 value starts the counter. Values from 1 to 31 are allowed.

countdown value, WDR

WatchDog clock

counter

00

03

02

01

03

02

01

03

02

01

03

WDF

INTA or INTB

WDR counts

duration of first WatchDog period after start

may range from WDR to WDR -1 counts

aaa-009584

In this example, it is assumed that the WatchDog flag (WDF) is cleared before the next

WatchDog period expires and that the interrupt output is set to pulsed mode.

Figure 13.ꢀWatchDog repeat mode

If a new value of WDR[4:0] is written before the end of the current WatchDog period, then

this value takes immediate effect.

When starting the timer for the first time or when reloading WDR[4:0] before the

end of the current period, the first period has an uncertainty of maximum one count.

The uncertainty is a result of loading the WDR[4:0] from the interface clock which is

asynchronous from the WatchDog source clock. Subsequent WatchDog periods do not

have such variation.

Reading the WatchDog register returns the current value of the WatchDog counter

(see Figure 13) and not the initial value WDR[4:0]. Since it is not possible to freeze the

WatchDog counter during read back, it is recommended to read the register twice and

check for consistent results.

7.5.1.1 WatchDog repeat mode

In repeat mode, at the end of every WatchDog period, the WatchDog flag (bit WDF in the

Flags register, Section 7.14) is set and the counter automatically reloads and starts the

next WatchDog period. An example is given in Figure 13. The asserted bit WDF can be

used to generate an interrupt. Bit WDF can only be cleared by command.

7.5.1.2 WatchDog single shot mode

In single shot mode, at the end of the countdown period, the WatchDog flag (bit WDF

in the Flags register, Section 7.14) is set and the counter stops with the value 0. The

WatchDog register must be reloaded to start another WatchDog period.

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Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

countdown value, WDR

WatchDog clock

counter

00

06

05

04

03

02

01

00

06

WDF

INTA or INTB

duration of WatchDog period after start

may range from WDR to WDR -1 counts

aaa-009585

Figure 14.ꢀWatchDog single shot mode

7.5.1.3 WatchDog interrupts

The generation of interrupts from the WatchDog functions is controlled via the WatchDog

interrupt enable bits; WDIEA and WDIEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

The assertion of the flag WDF can be used to generate an interrupt at pins INTA and

INTB. The interrupt may be generated as a pulsed signal every time the WatchDog

counter reaches the end of the countdown period. Alternatively as a permanently

active signal which follows the condition of bit WDF. WDF remains set until cleared by

command.

When enabled, interrupts are triggered every time the WatchDog counter reaches the

end of the countdown period and even if the WDF is not cleared, an interrupt pulse can

be generated.

See Section 7.9 for interrupt control.

7.6 Single RAM byte

Table 18.ꢀRAM_byte - 8-bit RAM register (address 2Ch) bit description

Bit

Symbol

Value

Description

7 to 0

B[7:0]

0000ꢀ0000^[1]to single RAM byte content

1111ꢀ1111

[1] Default value.

The PCF85363A provides a free single RAM byte, which can be used for any purpose,

for example, status bits of the system.

7.7 Timestamps

There are three timestamp registers which can be independently configured to record the

time for battery switch-over events and/or transitions on the TS pin.

Each timestamp register has an associated flag. It is also possible to generate an

interrupt signal for every timestamp register update.

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Timestamps work in both RTC and stop-watch mode. During battery operation, the

mechanical switch detector may also be used to trigger the timestamp.

The timestamp registers are read only and cannot be written. It is possible to set all three

registers to 0 with the CTS instruction in the Resets register (Section 7.15).

mode

flag

mode

flag

mode

flag

TSR1M[1:0]

TSR1F

TSR2M[2:0]

TSR2F

TSR3M[1:0]

TSR3F

timer registers

RTC mode

seconds

minutes

:

timestamp

register

timestamp

register

timestamp

register

years

TSR1

TSR2

TSR3

stopwatch mode

seconds

minutes

:

999999 hours

load

TS pin

battery

switchover

aaa-009595

Figure 15.ꢀTimestamp

The mode for each register is controlled by the TSR_mode register.

Table 19.ꢀTSR_mode - timestamp mode control register (address 23h) bit

description

Bit

Timestamp3 (TSR3)

7 to 6 TSR3M[1:0]

Symbol

Value

Description

timestamp register 3 mode

00^[1]

01

10

11

no timestamp

FB, record First time switch to Battery event

LB, record Last time switch to Battery event

LV, record Last time switch to V_DDevent

5

Timestamp2 (TSR2)

4 to 2 TSR2M[2:0]

-

0

not used

timestamp register 2 mode

000^[1]

001

no timestamp

FB, record First time switch to Battery event

LB, record Last time switch to Battery event

010

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Table 19.ꢀTSR_mode - timestamp mode control register (address 23h) bit

description...continued

Bit

Symbol

Value

011

Description

LV, record Last time switch to V_DDevent

100

FE, record First TS pin Event

LE, record Last TS pin Event

no timestamp

101

110 to 111

Timestamp1 (TSR1)

1 to 0 TSR1M[1:0]

timestamp register 1 mode

no timestamp

00^[1]

01

FE, record First TS pin Event

LE, record Last TS pin Event

no timestamp

10

11

[1] Default value.

First event means that the time is only stored on the first event and not recorded for

subsequent events. When the first event occurs, the associated timestamp flag is

set. When the flag is cleared, then a new ‘first’ event is recorded. See Figure 16 and

Figure 17.

Last event means that the time is stored on every event. When an event occurs, the

associated timestamp flag is set. It is not necessary to clear the flag before a new event

is recorded.

Interrupts can be generated in INTA pin and/or INTB pin. Interrupts are generated every

time a timestamp register is updated. Interrupt generation is not conditional on the state

of the timestamp flags. See Section 7.7.1.

source of

power

V

power

battery power

V

power

battery power

V

power

DD

event time

event type

t1

FB, LB

t2

t3

FB, LB

t4

t5

LV

LB

timestamp3 flag,

TSR3F

flag cleared by interface

TSR3 set to first time

switch to battery, FB

TSR3 = t1

no change

TSR2 = t2

TSR3 = t3

no change

TSR2 = t4

no change

TSR2 set to last time

no change

switch to V , LV

DD

aaa-009596

Figure 16.ꢀExample battery switch-over timestamp

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(1)

TS pin

event time

event type

t1

t2

t3

t4

t5

FE, LE

LE

FE, LE

LE

timestamp1 flag, TSR1F

flag cleared by interface

TSR2 set to last

TS pin event, LE

TSR2 = t1

TSR2 = t2

TSR2 = t3

no change

TSR2 = t4

TSR2 = t5

TSR1 set to first

TS pin event, FE

TSR3 = t1

no change

TSR3 = t4

no change

aaa-009604

1. TS pin set to active HIGH (TSL = 0), see register Pin_IO (address 27h), Section 7.12.

Figure 17.ꢀExample TS pin driven timestamp

The recorded time is stored in the associated timestamp register. The time format

depends on the RTC mode. The timestamp registers follows the time format of the time

registers.

Table 20.ꢀTimestamp registers in RTC mode (RTCM = 0)

Bit positions labeled as - are not implemented and return 0 when read.

Address Register name Upper-digit (ten’s place)

Digit (unit place)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RTC timestamp1 (TSR1)

11h

12h

13h

TSR1_seconds

TSR1_minutes

TSR1_hours

-

0 to 5

-

0 to 9

AMPM 0 to 1 0 to 9

0 to 2

0 to 3

-

0 to 9

14h

15h

16h

TSR1_days

TSR1_months

TSR1_years

-

0 to 1 0 to 9

0 to 9

RTC timestamp2 (TSR2)

17h

18h

19h

TSR2_seconds

TSR2_minutes

TSR2_hours

-

0 to 5

-

0 to 9

AMPM 0 to 1 0 to 9

0 to 2

0 to 3

-

0 to 9

1Ah

1Bh

1Ch

TSR2_days

TSR2_months

TSR2_years

-

0 to 1 0 to 9

0 to 9

RTC timestamp3 (TSR3)

1Dh TSR3_seconds

-

0 to 5

0 to 9

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Table 20.ꢀTimestamp registers in RTC mode (RTCM = 0)...continued

Bit positions labeled as - are not implemented and return 0 when read.

Address Register name Upper-digit (ten’s place)

Digit (unit place)

Bit 7

Bit 6

0 to 5

-

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1Eh

1Fh

TSR3_minutes

TSR3_hours

-

0 to 9

AMPM 0 to 1 0 to 9

0 to 2

0 to 3

-

0 to 9

20h

21h

22h

TSR3_days

TSR3_months

TSR3_years

-

0 to 1 0 to 9

0 to 9

Table 21.ꢀtimestamp registers in stop-watch mode (RTCM = 1)

Bit positions labeled as - are not implemented and return 0 when read.

Address Register name

Upper-digit (ten’s place)

Digit (unit place)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Stop-watch timestamp1 (TSR1)

11h

12h

13h

14h

15h

16h

TSR1_seconds

TSR1_minutes

-

0 to 5

0 to 9

-

TSR1_hr_xx_xx_00 0 to 9

TSR1_hr_xx_00_xx 0 to 9

TSR1_hr_00_xx_xx 0 to 9

not used

-

Stop-watch timestamp2 (TSR2)

17h

18h

19h

1Ah

1Bh

1Ch

TSR2_seconds

TSR2_minutes

-

0 to 5

0 to 9

-

TSR2_hr_xx_xx_00 0 to 9

TSR2_hr_xx_00_xx 0 to 9

TSR2_hr_00_xx_xx 0 to 9

not used

-

Stop-watch timestamp3 (TSR3)

1Dh

1Eh

1Fh

20h

21h

22h

TSR3_seconds

TSR3_minutes

-

0 to 5

0 to 9

-

TSR3_hr_xx_xx_00 0 to 9

TSR3_hr_xx_00_xx 0 to 9

TSR3_hr_00_xx_xx 0 to 9

not used

-

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7.7.1 Timestamps interrupts

The generation of interrupts from the timestamp functions is controlled via the timestamp

interrupt enable bits; TSRIEA and TSRIEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

The loading of new information into one of the timestamp registers can be used to

generate an interrupt at pins INTA and INTB. The interrupt may be generated as a pulsed

signal every time a timestamp register updates or as a permanently active signal which

follows the condition of timestamp flags, TSR1F to TSR3F. The timestamp flags remain

set until cleared by command.

When enabled, interrupts are triggered every time a timestamp register updates and

even if the associated flag is not cleared, an interrupt pulse can be generated.

See Section 7.9 for interrupt control.

7.8 Offset register

The PCF85363A incorporates an offset register (address 24h) which can be used to

implement several functions, such as:

• Accuracy tuning

• Aging adjustment

• Temperature compensation

Table 22.ꢀOffset - offset register (address 24h) bit description

Bit

Symbol

Value

Description

offset value

7 to 0

OFFSET[7:0]

see Table 24

There are two modes which define the correction period, normal mode and fast mode.

The normal mode is suitable for offset trimming. The fast mode is suitable for dynamic

offset correction e.g. implementing a temperature correction. The fast mode consumes

more current. Offset mode is defined by bit OFFM in the Oscillator register (Section 7.10).

Table 23.ꢀOFFM bit - oscillator control register (address 25h)

See Section 7.10.

Bit

Symbol

Value

Description

6

OFFM

offset mode bit

0^[1]

1

normal mode: correction is made every 4

hours; 2.170 ppm/step

fast mode: correction is made once every 8

minutes;2.0345 ppm/step

[1] Default value.

For OFFM = 0, each LSB introduces an offset of 2.170 ppm. For OFFM = 1, each LSB

introduces an offset of 2.0345 ppm. The offset value is coded in two’s complement giving

a range of +127 LSB to -128 LSB, see Table 24.

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Table 24.ꢀOffset values

OFFSET[7:0]

Offset value in

decimal

Offset value in ppm

Normal mode

OFFM = 0

Fast mode

OFFM = 1

011ꢀ1ꢀ1111

011ꢀ1ꢀ1110

:

+127

+126

:

+275.590

+273.420

:

+258.3815

+256.3470

:

0000ꢀ0010

0000ꢀ0001

0000ꢀ0000^[1]

1111ꢀ1111

1111ꢀ1110

:

+2

+1

0

+4.340

+2.170

0^[1]

+4.0690

+2.0345

0^[1]

-1

-2.170

-4.340

:

-2.0345

-4.0690

:

-2

:

1000ꢀ0001

1000ꢀ0000

-127

-128

-275.590

-277.760

-258.3815

-260.416

[1] Default value.

The correction is made by adding or subtracting clock correction pulses, thereby

changing the period of a single second but not by changing the oscillator frequency.

It is possible to monitor when correction pulses are applied. See Section 7.8.4.

7.8.1 Correction when OFFM = 0

The correction is triggered once every four hours and then correction pulses are applied

once per minute until the programmed correction values have been implemented.

Table 25.ꢀCorrection pulses for OFFM = 0

Correction value

+1 or -1

Every n^thhour

Actual minute

00

4

+2 or -2

4

00 and 01

00, 01, and 02

:

+3 or -3

4

:

+59 or -59

+60 or -60

+61 or -61

4

00 to 58

00 to 59

00

4

4 + 1

+62 or -62

4

00 to 59

00 and 01

:

4 + 1

:

+123 or -123

4

00 to 59

4 + 1

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Table 25.ꢀCorrection pulses for OFFM = 0...continued

Correction value

Every n^thhour

Actual minute

00, 01, and 02

00 to 59

4 + 2

4

-128

4 + 1

4 + 2

00 to 59

00 to 07

7.8.2 Correction when OFFM = 1

The correction is triggered once every eight minutes and then correction pulses

are applied once per second until the programmed correction values have been

implemented.

Clock correction is made more frequently in OFFM = 1; however, this can result in higher

power consumption.

Table 26.ꢀCorrection pulses for OFFM = 1

Correction value

+1 or -1

Every n^thminute

Actual second

00

8

+2 or -2

8

00 and 01

00, 01, and 02

:

+3 or -3

8

:

+59 or -59

+60 or -60

+61 or -61

8

00 to 58

00 to 59

00

8

8 + 1

8

+62 or -62

00 to 59

00 and 01

:

8 + 1

:

+123 or -123

8

00 to 59

00, 01, and 02

00 to 59

00 to 07

8 + 1

8 + 2

8

-128

8 + 1

8 + 2

7.8.3 Offset calibration workflow

The calibration offset has to be calculated based on the time. Figure 18 shows the

workflow how the offset register values can be calculated:

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sample calculation:

Measure the frequency on pin CLKOUT:

f

meas

32768.28 Hz

30.517320 µs

Convert to time:

t

= 1 / f

meas

Calculate the difference to the ideal

period of 1 / 32768.00:

0.000260 µs

8.51975 ppm

D

= 1 / 32768 - t

meas

Calculate the ppm deviation compared

to the measured value:

E

= 1000000 × D

meas

/ t

meas

ppm

Calculate the offset register value:

OFFM = 0 (low power):

Offset value = E

/ 2.17

3.926

4.188

4 correction pulses

are needed

ppm

OFFM = 1 (fast correction)

Offset value = E / 2.0345

4 correction pulses

are needed

ppm

aaa-009636

Figure 18.ꢀOffset calibration calculation workflow

(1)

(2)

(3)

-2

-1

0

1

2

3

4

5

6

7

8

9

deviation after

correction in

OFFM = 0

deviation after

correction in

OFFM = 1

measured/calculated

deviation 8.51975 ppm

-0.160 ppm

+0.382 ppm

aaa-009637

With the offset calibration an accuracy of ±1 ppm (0.5 × offset per LSB) can be reached (see

Table 24).

±1 ppm corresponds to a time deviation of 0.0864 seconds per day.

1. 4 correction pulses in OFFM = 0 correspond to -8.680 ppm.

2. 4 correction pulses in OFFM = 1 correspond to -8.138 ppm.

3. Reachable accuracy zone.

Figure 19.ꢀResult of offset calibration

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7.8.4 Offset interrupts

The generation of interrupts from the offset functions is controlled via the offset interrupt

enable bits; OIEA and OIEB. These bits are in registers INTA_enable (address 29h) and

INTB_enable (address 2Ah).

Every time a correction pulse is made an interrupt pulse can be generated at pins INTA

and INTB. As there are is no offset calibration flag, it is only possible to generate pulse

interrupts.

See Section 7.9 for interrupt control.

7.9 Interrupts

There are two interrupt output pins, INTA and INTB. Both pins have the same possible

sources and a dedicated register to control what is output. The pins can be used

independently from each other.

INTA data is output on the INTA pin. INTA is an interrupt output pin with open-drain drive.

INTA pin mode is controlled by INTAPM[1:0] bits in the Pin_IO register (Section 7.12).

INTB data is output on TS pin with push-pull drive. The TS pin must first be configured as

INTB output by setting TSIO[1:0] bits in the Pin_IO register (Section 7.12).

Interrupts will only be output when the pin mode is correctly defined. Interrupts are output

from the IC as active LOW signals.

The registers INTA_enable (address 29h) and INTB_enable (address 2Ah) are used to

select which interrupts should be output on which pin.

Table 27.ꢀINTA and INTB interrupt control bits

Bit

INTA_enable - INTA pin enable control (address 29h)

Symbol ILPA PIEA OIEA A1IEA

INTB_enable - INTB pin enable control (address 2Ah)

Symbol ILPB PIEB OIEB A1IEB

7

6

5

4

3

2

1

0

A2IEA

A2IEB

TSRIEA

TSRIEB

BSIEA

BSIEB

WDIEA

WDIEB

Table 28.ꢀDefinition of interrupt control bits

Bit

Symbol

INTA

Value

Description

INTB

7

ILPA

ILPB

level or pulse mode

interrupt generates a pulse

0^[1]

1

interrupt follows flags (permanent signal)

periodic interrupt enable

6

5

PIEA

OIEA

PIEB

OIEB

0^[1]

1

no periodic interrupt generated

periodic interrupt generated

offset correction interrupt enable

no correction interrupt generated

interrupt generated from correction

0^[1]

1

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Table 28.ꢀDefinition of interrupt control bits...continued

Bit

Symbol

INTA

Value

Description

INTB

4

A1IEA

A1IEB

alarm1 interrupt enable

0^[1]

1

no alarm interrupt generated

alarm interrupt generated

3

2

1

0

A2IEA

A2IEB

alarm2 interrupt enable

0^[1]

1

no alarm interrupt generated

alarm interrupt generated

TSRIEA

BSIEA

WDIEA

TSRIEB

BSIEB

WDIEB

timestamp register interrupt enable

no timestamp register interrupt generated

timestamp register interrupt generated

battery switch interrupt enable

no battery switch interrupt generated

battery switch interrupt generated

WatchDog interrupt enable

no WatchDog interrupt generated

WatchDog interrupt generated

0^[1]

1

0^[1]

1

0^[1]

1

[1] Default value.

7.9.1 ILPA/ILPB: interrupt level or pulse mode

Interrupts can be configured to generate a pulse or to send a continuous level

(permanent signal) which follows the state of the flag.

In pulse mode, an interrupt pulse is generated every time that the selected source

triggers.

Triggered means

• for periodic interrupts, every time a period has elapsed

• for offset correction, every time a correction pulse is initiated

• for alarms, every time the time increments to match the alarm time

• for timestamps, every time a register updates

• for battery switch, every time the IC switches to or from battery

• for WatchDog, every time the counter reaches the end of its count

The interrupt signal goes active coincident with the triggering event. The signal is cleared

by an internal 128 Hz clock. The internal clock is asynchronous to the triggering event

and so the pulse duration has a minimum period of one 128 Hz cycle and a maximum of

two 128 Hz cycles. Interrupt pulses may be shortened by clearing the flag before the end

of the pulse period.

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Flag does not need to be cleared

for interrupts to be generated

trigger event

flag

interrupt

128 Hz clock

Maximum

interrupt

period

Minimum

interrupt

period

aaa-009638

Figure 20.ꢀInterrupt pulse width

In level mode, the interrupt signal follows the state of the flag. Only interrupts which are

enabled will affect the pin state. All enabled flags must be cleared for the interrupt signal

to be cleared.

The EMON is used only for monitoring all flags and can be read back in the minutes

register. See Section 7.2.3.

7.9.2 Interrupt enable bits

The remainder of the bits in register INTA_enable (address 29h) and register

INTB_enable (address 2Ah) are used to select which interrupt data goes where. See

Figure 21

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7.10 Oscillator register

Table 29.ꢀOscillator - oscillator control register (address 25h) bit description

Bit

7

6

5

4

3

2

1

0

Symbol

Section

CLKIV

OFFM

12_24

LOWJ

OSCD[1:0]

CL[1:0]

Section 7.10.6

Section 7.16

Section 7.8

Section 7.10.3

Section 7.10.4

Section 7.10.5

7.10.1 CLKIV: invert the clock output

Table 30.ꢀCLKIV bit - oscillator control register (address 25h)

Bit

Symbol

Value

Description

7

CLKIV

output clock inversion

0^[1]

1

non-inverting; LOWJ mode will affect rising

edge

inverted; LOWJ mode will affect falling edge

[1] Default value.

The clock selected with the COF[2:0] bits (register Function, address 28h) can be

inverted. This is intended for use in conjunction with the low jitter mode, LOWJ. The low

jitter mode reduces the jitter for the rising edge of the output clock. If the reduced jitter

needs to be on the falling edge, for example when using an open-drain clock output, then

the CLKIV bit can be used to implement this.

7.10.2 OFFM: offset calibration mode

See Section 7.8 for a full description of offset calibration.

7.10.3 12_24: 12 hour or 24 hour clock

Table 31.ꢀ12_24 bit - oscillator control register (address 25h)

Bit

Symbol

Value

Description

5

12_24

12 hour or 24 hour mode

24 hour mode is selected

12 hour mode is selected

0^[1]

1

[1] Default value.

In RTC mode, time counting can be configured for 24 hour clock or 12 hour clock with the

AMPM flag.

This bit is ignored in stop-watch mode.

7.10.4 LOWJ: low jitter mode

Table 32.ꢀLOWJ bit - oscillator control register (address 25h)

Bit

Symbol

Value

Description

4

LOWJ

low jitter CLK output bit

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Table 32.ꢀLOWJ bit - oscillator control register (address 25h)...continued

Bit

Symbol

Value

0^[1]

1

Description

normal

reduced CLK output jitter; increase I_DD

[1] Default value.

Oscillator circuits suffer from jitter. In particular, ultra low-power oscillators like the one

used in the PCF85363A are optimized for power and not jitter. By setting the LOWJ bit,

the jitter performance can be improved at the cost of power consumption.

7.10.5 OSCD[1:0]: quartz oscillator drive control

Table 33.ꢀOSCD[1:0] bits - oscillator control register (address 25h)

Bit

Symbol

Value

Description

3 to 2

OSCD[1:0]

oscillator drive bits

00^[1]

01

normal drive; R_S(max): 100 kΩ

low drive; R_S(max): 60 kΩ; reduced I_DD

high drive; R_S(max): 500 kΩ; increased I_DD

10, 11

[1] Default value.

The oscillator is designed to be used with quartz with a series resistance up to 100 kΩ.

This covers the typical range of 32.768 kHz quartz crystals. Series resistance is also

referred to as: ESR, motional resistance, or R_S.

A low drive mode is available for low series resistance quartz. This reduces the current

consumption.

For very high series resistance quartz, there is a high drive mode. Current consumption

increases substantially in this mode.

7.10.6 CL[1:0]: quartz oscillator load capacitance

Table 34.ꢀCL[1:0] bits - oscillator control register (address 25h)

Bit

Symbol

Value

Description

1 to 0

CL[1:0]

internal oscillator capacitor selection for

quartz crystals with the corresponding load

capacitance of C_L:

00^[1]

01

7.0 pF

6.0 pF

12.5 pF

10

11

[1] Default value.

C_Lrefers to the load capacitance of the oscillator circuit and allows for a certain amount

of package and PCB parasitic capacitance. When the oscillator circuit matches the C_L

parameter of the quartz, then the frequency offset is zero.

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The PCF85363A is designed to operate with quartz with C_Lvalues of 6.0 pF, 7.0 pF and

12.5 pF.

12.5 pF are generally the cheapest and most widely available, but also require the most

power to drive. The circuit also operates with 9.0 pF quartz, however the offset calibration

would be needed to compensate. If a 9.0 pF quartz is used, then it is recommended to

set C_Lto 7.0 pF.

7.11 Battery switch register

This register configures the battery switch-over mode.

Associated with the battery switch-over is the battery switch flag (BSF) in the Flags

register (Section 7.14). Whenever the IC switches to battery operation, the flag is set.

The flag can only be read when operating from V_DDpower, however an interrupt pulse or

static LOW signal can be generated whenever switching to battery. An interrupt pulse can

also be generated when switching back to V_DDpower. Examples are given in Figure 23

and Figure 24.

When switched to battery, the V_DDpower domain is disabled. This means that I²C pins

are ignored, CLK output is disabled and Hi-Z, TS pin output mode is disabled and Hi-Z,

TS digital input is ignored and may be left floating. TS pin mechanical switch detector

is active. INTA output is still active for interrupt output and battery switch indication, but

disabled for clock output.

Table 35.ꢀIO pin behavior in battery mode

IO pin (mode)

V_DDoperation

active input

V_BAToperation

SCL

disabled; may be left floating

disabled; Hi-Z

SDA

active input/output

active output

active input

CLK

TS (output mode)

TS (digital input)

TS (mechanical switch input)

INTA

disabled; Hi-Z

disabled; may be left floating

active input

active output

active interrupt output

Table 36.ꢀBattery_switch - battery switch control (address 26h) bit description

Bit

7

-

6

-

5

-

4

3

2

1

0

Symbol

Section

BSOFF

BSRR

BSM[1:0]

Section 7.11.3

BSTH

-

Section 7.11.1

Section 7.11.2

Section 7.11.4

7.11.1 BSOFF: battery switch on/off control

Table 37.ꢀBSOFF bit - battery switch control (address 26h) bit description

Bit

Symbol

Value

Description

4

BSOFF

battery switch on/off

enable battery switch feature

disable battery switch feature

0^[1]

1

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and I²C-bus

[1] Default value.

The battery switch circuit may be disabled when not used. This disables all the circuit and

save power consumption. When disabled connect V_BATand V_DDtogether.

7.11.2 BSRR: battery switch internal refresh rate

Table 38.ꢀBSRR bit - battery switch control (address 26h) bit description

Bit

Symbol

Value

Description

3

BSRR

battery switch refresh rate

0^[1]

1

low

high

[1] Default value.

Non-user bit. Recommended to leave set at default.

7.11.3 BSM[1:0]: battery switch mode

Table 39.ꢀBSM[1:0] bits - battery switch control (address 26h) bit description

Bit

Symbol

Value

Description

2 to 1

BSM[1:0]

battery switch mode bits

switching at the V_thlevel

00^[1]

01

switching at the V_BATlevel

switching at the higher level of V_thor V_BAT

switching at the lower level of V_thor V_BAT

10

11

[1] Default value.

Switching is automatic and controlled by the voltages on the VBAT and VDD pins. There

are three modes:

• Compare V_DDwith an internal reference (V_th)

• Compare V_DDwith V_BAT

• Compare V_DDwith an internal reference (V_th) and V_BAT

The last mode is useful when a rechargeable battery is employed.

Table 40.ꢀBattery switch-over modes

BSM[1:0]

Condition

Internal power

V_DD

00

V_DD> V_th

V_DD< V_th

V_BAT

01

10

11

V_DD> V_BAT

V_DD

V_DD< V_BAT

V_BAT

V_DD> the higher of V_thor V_BAT

V_DD< the higher of V_thor V_BAT

V_DD> the lower of V_thor V_BAT

V_DD< the lower of V_thor V_BAT

V_DD

V_BAT

V_DD

V_BAT

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Due to the nature of the power switch circuit there is a switching hysteresis (see

Figure 22 and Table 67).

V

DD

switching point

hysteresis

V

increasing

DD

V

decreasing

DD

max

typ

V

th(low)

V

th(high)

min

t

battery operation

RTC power

supply

switch to V

switch to battery

operation

DD

V

DD

operation

DD

aaa-010665

Figure 22.ꢀThreshold voltage switching hysteresis

7.11.3.1 Switching at the V_thlevel, BSM[1:0] = 00

V

DD

V

BAT

internal power supply

V

th

V

DD

(= 0 V)

cleared via interface

BSF

INTA

battery mode indication

interface inactive

2

I C

interface active

aaa-010423

Figure 23.ꢀSwitching at V_th

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and I²C-bus

7.11.3.2 Switching at the V_BATlevel, BSM[1:0] = 01

V

DD

V

BAT

internal power supply

V

th

V

DD

(= 0 V)

cleared via interface

BSF

INTA

battery mode indication

interface inactive

2

I C

interface active

aaa-010425

Figure 24.ꢀSwitching at V_BAT

7.11.3.3 Switching at the higher of V_BATor V_thlevel, BSM[1:0] = 10

With this mode switching takes place when V_DDfalls below the higher of V_thor V_BAT

.

In Figure 25, an example is given where the threshold is set to 1.5 V and a single cell

battery is connected to VBAT. In this example, switching to the battery voltage takes

place when V_DDfalls below V_th.

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

V

DD

V

= 1.5 V

= 1.2 V

th

internal power supply

V

BAT

V

(= 0 V)

BSF

DD

cleared via interface

INTA

battery mode indication

interface inactive

2

I C

interface active

aaa-010426

Figure 25.ꢀSwitching at the higher of V_BATor V_th

7.11.3.4 Switching at the lower of V_BATand V_thlevel, BSM[1:0] = 11

With this mode switching takes place when V_DDfalls below the lower of V_thor V_BAT

.

In Figure 26, an example is given where the threshold is set to 1.5 V and a single cell

battery is connected to VBAT. In this example, switching to the battery voltage takes

place when V_DDfalls below V_BAT

.

V

DD

V

= 1.5 V

= 1.2 V

th

V

BAT

internal power supply

V

(= 0 V)

BSF

DD

cleared via interface

INTA

battery mode indication

interface inactive

2

I C

interface active

aaa-010429

Figure 26.ꢀSwitching at the lower of V_BATor V_th

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and I²C-bus

7.11.4 BSTH: threshold voltage control

Table 41.ꢀBSTH - battery switch control (address 26h) bit description

Bit

Symbol

Value

Description

0

BSTH

battery switch threshold voltage, V_th

0^[1]

1

V_th= 1.5 V

V_th= 2.8 V

[1] Default value.

The threshold for battery switch-over is selectable between two voltages, 1.5 V and 2.8 V.

7.11.5 Battery switch interrupts

The generation of interrupts from the battery switch function is controlled via the battery

switch interrupt enable bits; BSIEA and BSIEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

The assertion of the flag BSF (register Flags, address 2Bh) can be used to generate an

interrupt at pins INTA and INTB. The interrupt may be generated as a pulsed signal or

alternatively as a permanently active signal which follows the condition of bit BSF. BSF

remains set until cleared by command.

When enabled, interrupts are triggered every time the battery switch circuit switches

to either battery or to V_DDand even if the BSF is not cleared, an interrupt pulse can be

generated.

In addition, the INTA pin can be configured as a battery mode indicator (INTAPM[1:0] =

00). See Section 7.12.6. This mode differs from a general interrupt signal in that it is only

controlled by the current battery switch status.

See Section 7.9 for interrupt control.

Remark: INTB pin is only active when the IC is operating from V_DD

.

7.12 Pin_IO register

Table 42.ꢀPin_IO- pin input output control register (address 27h) bit description

Bit

7

6

5

4

3

2

1

0

Symbol

Section

CLKPM

TSPULL

TSL

TSIM

TSPM[1:0]

INTAPM[1:0]

Section 7.12.1

Section 7.12.2

Section 7.12.3

Section 7.12.5

Section 7.12.4

Section 7.12.6

This register is used to define the input and output modes of the IC.

7.12.1 CLKPM: CLK pin mode control

Table 43.ꢀCLKPM bit - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

7

CLKPM^[1]

CLK pin mode

enable CLK pin

disable CLK pin

0^[2]

1

[1] CLK pin is not available on all package types.

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and I²C-bus

[2] Default value.

Setting the CLKPM bit disables the CLK output and force the pin to drive out a logic

0. Clearing this bit enables the pad to output the selected clock frequency (see bits

COF[2:0] in the Function register, see Table 50).

7.12.2 TSPULL: TS pin pull-up resistor value

Table 44.ꢀTSPULL bit - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

6

TSPULL

TS pin pull-up resistor value

0^[1]

1

80 kΩ

40 kΩ

[1] Default value.

Controls the pull-up resistor value used in the mechanical switch detector. For

applications where there is a large capacitance on the TS pin e.g. from a long connecting

cable to the mechanical switch, the pull-up resistor value can be halved to improve switch

detection.

Using the low-resistance value increases current consumption when the switch is closed

i.e. shorting to V_SS

.

7.12.3 TSL: TS pin level sense

Table 45.ꢀTSL bit - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

5

TSL

TS pin input sense

active HIGH

0^[1]

1

active LOW

[1] Default value.

The active state of the TS pin can be defined for use as a timestamp trigger and/or as

stop control for the time counting. Active HIGH implies a transition from logic 0 to logic 1

is active. Active LOW implies a transition from logic 1 to logic 0 is active.

7.12.4 TSPM[1:0]: TS pin I/O control

Table 46.ꢀTSPM[1:0] bits - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

3 to 2

TSPM[1:0]

TS pin IO mode

00^[1]

01

disabled; input can be left floating

INTB output; push-pull

CLK output; push-pull

input mode

10

11

[1] Default value.

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and I²C-bus

These bits control the operation of the TS pin.

mechanical

switch detector

vdd_int

sample clock

TSL

sample

80 kΩ/

40 kΩ

invert

input data

(1)

TS (CLK/INTB) pin

INTB data

clock data

aaa-010443

1. Not available on all package types.

Figure 27.ꢀTS pin

TSIM is only considered when the TS pin is in input mode.

7.12.4.1 TS pin output mode; INTB

It is possible to output INTB data on the TS pin. The output is push-pull. No output is

available when on V_BAT. When on V_BATthe output is Hi-Z.

7.12.4.2 TS pin output mode; CLK

It is possible to output a clock frequency on the TS pin. Clock frequency is selected with

the COF[2:0] bits in the Function register (Section 7.13). The output is push-pull. No

output is available when on V_BAT. When on V_BATthe output is Hi-Z.

7.12.4.3 TS pin disabled

When disabled the pin is Hi-Z and can be left floating.

7.12.5 TSIM: TS pin input type control

Table 47.ꢀTSIM bit - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

4

TSIM

TS pin input mode

0^[1]

1

CMOS input; reference to V_DD; disabled

when on V_BAT

mechanical switch mode; active pull-up

sampled at 16 Hz; operates on V_DDand

V_BAT

[1] Default value.

In CMOS input mode (TSIM = 0), input is taken directly from the TS pin. The input is

conditioned by the setting of TSL. When operating on the battery voltage (V_BAT), the input

is disabled and is allowed to float.

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and I²C-bus

In mechanical switch detector mode (TSIM = 1), the TS pin is sampled at a rate of 16 Hz

for a period of 30.5 μs. At the same time as the sample a pull-up resistor is activated to

detect an open pin or a pin shorted to V_SS. The input is referenced to the internal power

supply. This mode operates when on V_DDor V_BAT. The pull-up resistor value can be

controlled by TSPULL bit in the Pin_IO register (see Section 7.12).

7.12.5.1 TS pin input mode

There are two input types which are controlled by the TSIM bit. The TS input can be used

to generate a timestamp event by configuring the timestamp mode bits; TSR2M[2:0] and

TSR1M[1:0] bits in TSR_mode register (see Table 19).

Also it is possible to use the TS pin to control counting of time. This is typically for use

with the stop-watch mode where an elapsed time counter function can be implemented.

Using the STOPM bit in the Function register (see Table 50) it is possible to control the

STOP bit by the TS pin.

7.12.6 INTAPM[1:0]: INTA pin mode control

Table 48.ꢀINTAPM[1:0] bits - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

1 to 0

INTAPM[1:0]

INTA pin mode

CLK output mode

battery mode indication

INTA output

00^[1]

01

10

11

Hi-Z

[1] Default value.

The INTA pin can be used to output three different signals.

battery mode

INTA (CLK)

clock data

INTA data

aaa-010464

Figure 28.ꢀINTA pin

7.12.6.1 INTAPM[1:0]: INTA

The primary function of the INTA pin is to output INTA data. INTA data is controlled by the

bits of the INTA_enable register (see Table 28).

The output is active LOW with an open-drain output. The output is available during V_DD

and V_BAToperation.

7.12.6.2 INTAPM[1:0]: clock data

It is possible to output a clock frequency on the INTA pin. Clock frequency is selected

with the COF[2:0] bits in the Function register (Section 7.13). The output is active LOW

with an open-drain output. The output is available only during V_DDoperation. The output

is Hi-Z when operating from V_BAT

.

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Remark: Clock output is the default state. To save power, it is recommended to disable

the clock when not being used. If no clock is required, then set COF[2:0] in the Function

register (Section 7.13) to CLK disabled. If clock output is only required on the CLK pin,

then set the INTA pin to either INTA data or battery mode.

7.12.6.3 INTAPM[1:0]: battery mode indication

It is possible to output the state of the power switch on the INTA pin. The output has an

open-drain output. The output is available during V_DDand V_BAToperation.

Table 49.ꢀINTA battery mode

Power supply

V_DD

INTA pin state

INTA = Hi-Z

V_BAT

INTA = logic 0

7.13 Function register

Table 50.ꢀFunction - chip function control register (address 28h) bit description

Bit

7

6

5

4

3

2

1

0

Symbol

Section

100TH

PI[1:0]

Section 7.13.2

RTCM

STOPM

COF[2:0]

Section 7.13.1

Section 7.13.3

Section 7.13.4

Section 7.13.5

7.13.1 100TH: 100th seconds mode

Table 51.ꢀ100TH bit - Function control register (address 28h)

Bit

Symbol

Value

Description

7

100TH

100th second mode

0^[1]

1

100th second disabled

100th second enabled

[1] Default value.

The PCF85363A can be configured to count at a resolution of 1 second or 0.01 seconds.

In 100th mode, the 100th_seconds register becomes available and the RTC counts at a

resolution of 0.01 seconds.

The 256 Hz clock signal is divided by 3 for fourteen 100 Hz periods and then by 2 for

eleven 100 Hz periods. This produces an effective division ratio of 2.56 with a maximum

jitter of 3.91 ms. Over twenty-five 100 Hz cycles the jitter is 0 ns.

7.13.2 PI[1:0]: Periodic interrupt

Table 52.ꢀPI[1:0] bits - Function control register (address 28h)

Bit

Symbol

Value

Description

6 to 5

PI[1:0]

periodic interrupt

no periodic interrupt

once per second

once per minute

00^[1]

01

10

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Table 52.ꢀPI[1:0] bits - Function control register (address 28h)...continued

Bit

Symbol

Value

Description

once per hour

11

[1] Default value.

The periodic interrupt mode can be used to enable pre-defined timers for generating

pulses on the interrupt pin. Interrupts once per second, once per minute or once per hour

can be generated.

When disabled, the timers are reset. When enabled, the time to the first pulse is between

the chosen period and the chosen period minus 1 seconds.

The timers are not affected by STOP.

When the periodic interrupt triggers, the PIF (PI flag) in the Flags register (Section 7.14)

is set.

The flag does not have to be cleared to allow another INTA or INTB pulse.

The duration of the periodic interrupt is unaffected by offset calibration.

See Section 7.9 for a description of interrupt pulse control and output pins.

7.13.3 RTCM: RTC mode

Table 53.ꢀRTCM bit - Function control register (address 28h)

Bit

Symbol

Value

Description

RTC mode

4

RTCM

0^[1]

1

real-time clock mode

stop-watch mode

[1] Default value.

The RTC mode is used to control how the time is counted. When configured as a classic

RTC, then time is counted from 100th seconds to years. In stop-watch mode, time is

counted from 100th seconds to 999ꢀ999 hours.

Table 54.ꢀRTC time counting modes

RTCM Mode

Time counting

0

1

RTC

100th seconds^[1], seconds, minutes, hours, days, weekdays, months, years

stop-watch 100th seconds^[1], seconds, minutes, hours (0 hours to 999ꢀ999 hours)

[1] Enabled with 100TH bit in the Function register (Section 7.13).

7.13.4 STOPM: STOP mode control

Table 55.ꢀSTOPM bit - Function control register (address 28h)

Bit

Symbol

Value

Description

STOP mode

3

STOPM

0^[1]

1

RTC stop is controlled by STOP bit only

RTC stop is controlled by STOP bit or TS

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and I²C-bus

[1] Default value.

The STOP register bit in the Oscillator register (Section 7.10) is used to stop the counting

of time in both RTC mode and stop-watch mode. Stopping of the oscillator can also

be controlled from the TS pin. The TS pin must first be configured as an input by the

TSPM[1:0] bits, then selected for active HIGH or active LOW by the TSL bits.

Table 56.ꢀOscillator stop control when STOPM = 1

STOP bit^[1]

TSL

TS pin^[2]

Oscillator state

running

Description

0

1

0

1

-

TS pin active HIGH

stopped

1

-

stopped

TS pin active LOW

TS pin ignored

running

1

stopped

[1] In the Oscillator register (Section 7.10).

[2] TSPM[1:0] = 11.

7.13.5 COF[2:0]: Clock output frequency

Table 57.ꢀCOF[2:0] bits - Function control register (address 28h)

Bit

Symbol

Value

Frequency selection (Hz)

CLK pin

32ꢀ768

16ꢀ384

8ꢀ192

TS pin

32ꢀ768

16ꢀ384

8ꢀ192

INTA pin

32ꢀ768

16ꢀ384

8ꢀ192

4ꢀ096

2ꢀ048

1ꢀ024

1

2 to 0

COF[2:0]

000^[1]

001

010

011

100

101

110

111

4ꢀ096

2ꢀ048

1ꢀ024

1

static LOW

Hi-Z

[1] Default value.

A programmable square wave is available at pin CLK. Operation is controlled by the

COF[2:0] bits. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for

use as a system clock, microcontroller clock, input to a charge pump, or for calibration of

the oscillator.

Pin CLK is a push-pull output and enabled at power-on. Pin CLK can be disabled by

setting CLKPM = 1 in the Pin_IO register (Section 7.12). When disabled, the CLK pin is

LOW.

The selected clock frequency may also be output on the TS pin and the INTA pin. The

CLKIV bit may be used to invert the clock output. CLKIV does not invert for the setting

COF[2:0] = 111.

The duty cycle of the selected clock is not controlled. However, due to the nature of the

clock generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50.

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and I²C-bus

Table 58.ꢀClock duty cycles

COF[2:0]

000^[2]

001

Frequency (Hz)

32ꢀ768

16ꢀ384

8ꢀ192

Typical duty cycle^[1]

60 : 40 to 40 : 60

50 : 50

-

010

011

4ꢀ096

100

2ꢀ048

101

1ꢀ024

110

1^[3]

111

static

[1] Duty cycle definition: % HIGH-level time : % LOW-level time.

[2] Default values. The duty cycle of the CLKOUT when outputting 32,768 Hz could change from 60:40 to 40:60 depending

on the detector since the 32,768 Hz is derived from the oscillator output which is not perfect. It could change from device

to device and it depends on the silicon diffusion. There is nothing that can be done from outside the chip to influence the

duty cycle.

[3] 1 Hz clock pulses are not affected by offset correction pulses.

7.14 Flags register

Table 59.ꢀFlags - Flag status register (address 2Bh) bit description

Bit

Symbol Flag name

Value

Description

7

PIF

Periodic Interrupt Flag

0^[1]

read: periodic interrupt flag inactive

write: periodic interrupt flag is cleared

read: periodic interrupt flag active

write: periodic interrupt flag remains unchanged

read: alarm2 flag inactive

Section 7.13.2

1

6

5

4

3

A2F

A1F

WDF

BSF

Alarm2 Flag

Section 7.4

0^[1]

write: alarm2 flag is cleared

1

read: alarm2 flag active

write: alarm2 flag remains unchanged

read: alarm1 flag inactive

Alarm1 Flag

Section 7.4

0^[1]

write: alarm1 flag is cleared

1

read: alarm1 flag active

write: alarm1 flag remains unchanged

read: WatchDog flag inactive

write: WatchDog flag is cleared

read: WatchDog flag active

WatchDog Flag

Section 7.5

0^[1]

1

write: WatchDog flag remains unchanged

read: battery switch flag inactive

write: battery switch flag is cleared

read: battery switch flag active

write: battery switch flag remains unchanged

Battery Switch Flag

Section 7.11

0^[1]

1

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and I²C-bus

Table 59.ꢀFlags - Flag status register (address 2Bh) bit description...continued

Bit

Symbol Flag name

Value

Description

2

TSR3F

TSR2F

TSR1F

Timestamp Register 3

event Flag

0^[1]

read: timestamp register 3 flag inactive

write: timestamp register 3 flag is cleared

read: timestamp register 3 flag active

write: timestamp register 3 flag remains unchanged

read: timestamp register 2 flag inactive

write: timestamp register 2 flag is cleared

read: timestamp register 2 flag active

write: timestamp register 2 flag remains unchanged

read: timestamp register 1 flag inactive

write: timestamp register 1 flag is cleared

read: timestamp register 1 flag active

write: timestamp register 1 flag remains unchanged

Section 7.7

1

0

Timestamp Register 2

event Flag

0^[1]

Section 7.7

1

Timestamp Register 1

event Flag

0^[1]

Section 7.7

1

[1] Default value.

The flags are set by their respective function. A full description can be found there. All

flags behave the same way. They are set by some function of the IC and remain set until

overwritten by command. It is possible to clear flags individually. To prevent one flag

being overwritten while clearing another, a logic AND is performed during a write access.

All flags are combined to generate an event monitoring signal called EMON. EMON is

described in Section 7.2.3 and can be read as the MSB of minutes register.

7.15 Reset register

Table 60.ꢀReset - software reset control (address 2Fh) bit description

Bit

7

6

5

4

3

SR

2

1

0

Symbol

Section

CPR

0

1

0

1

0

CTS

Section 7.15.2

Section 7.15.1

Section 7.15.3

For a

• software reset (SR), 0010ꢀ1100 (2Ch) must be sent to register Reset (address 2Fh). A

software reset also triggers CPR and CTS

• clear prescaler (CPR), 1010ꢀ0100 (A4h) must be sent to register Reset (address 2Fh)

• clear timestamp (CTS),0010ꢀ0101 (25h) must be sent to register Reset (address 2Fh)

It is possible to combine CPR and CTS by sending 1010ꢀ0101 (A5h).

Remark: Any other value sent to this register is ignored.

7.15.1 SR - Software reset

A reset is automatically generated at power-on. A reset can also be initiated with the

software reset command.

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

slave address

address 2Fh

software reset 2Ch

R/W

0

s

1

0

1

0

1

A

0

1

0

1

A

0

1

0

1

0

A P/S

SDA

SCL

internal

reset signal

aaa-010473

Figure 29.ꢀSoftware reset command

The PCF85363A resets to:

Mode

real-time clock, 100th second off

Time

00:00:00.00

Date

2000.01.01

Weekday

Saturday

Battery switch

on, switching on the lower threshold voltage

Oscillator

C_L= 7 pF

Pins

INTA = 32 kHz output, CLK = 32 kHz output, TS = disabled

In the reset state, all registers are set according to Table 61.

Table 61.ꢀRegisters reset values

Registers labeled as - remain unchanged.

Address

Register name

Bit

7

6

0

5

0

4

0

3

0

2

0

1

0

1

0

1

0

1

0

1

00h

01h

02h

03h

04h

05h

06h

100TH_seconds

Seconds

Minutes

0

1

0

Hours

0

Days

0

Weekdays

Months

0

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Table 61.ꢀRegisters reset values...continued

Registers labeled as - remain unchanged.

Address

Register name

Bit

7

6

0

-

5

0

-

4

0

-

3

0

-

2

0

-

1

0

-

0

-

07h

08h

Years

0

Second_alarm1

Second_alm1

Minute_alarm1

Minute_alm1

-

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

-

Hour_alarm1

Hr_xx_xx_00_alm1

Day_alarm1

Hr_xx_00_xx_alm1

Month_alarm1

Hr_00_xx_xx_alm1

Minute_alarm2

Minute_alm2

Hour_alarm2

Hr_xx_00_alm2

Weekday_alarm2

Hr_00_xx_alm2

Alarm enables

0

11h to 16h Timestamp 1

17h to 1Ch Timestamp 2

1Dh to 22h Timestamp 3

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Fh

Timestamp_mode

Offset

Oscillator

Battery_switch

Pin_IO

Function

INTA_enable

INTB_enable

Flags

RAM_byte

WatchDog

Reset

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

7.15.2 CPR: clear prescaler

To set the time for RTC mode accurately or to clear the time in stop-watch mode, the

clear prescaler instruction is needed.

Before sending this instruction, it is recommended to first set stop either by the STOP bit

or by the TS pin (see STOPM bit).

See STOP definition for an explanation on using this instruction.

7.15.3 CTS: clear timestamp

The timestamp registers (address 11h to 22h) can be set to all 0 with this instruction.

7.16 Stop_enable register

Table 62.ꢀStop_enable - control of STOP bit (address 2Eh)

Bit

Symbol

-

Value

Description

not used

7 to 1

0

0000ꢀ000

STOP

STOP bit

0^[1]

1

RTC clock runs

RTC clock is stopped

[1] Default value.

The STOP bit stops the time from counting in both RTC mode and stop-watch mode. For

RTC mode STOP is useful to set the time accurately. For stop-watch mode it is the start/

stop control for the watch.

The counter can also be controlled from the TS pin by configuring STOPM in the

Function register (Section 7.13). The internal stop signal is a combination of STOP and

the TS pin state.

Table 63.ꢀCounter stop signal

STOP bit

TS pin^[1][2]

stop signal

Counter

stopped

running

1

-

1

0

1

0

[1] Requires STOPM and TSPM[1:0] to be configured.

[2] TSL = 0 (active HIGH) (Pin_IO register, address 27h).

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

OSCILLATOR STOP

setting the OS flag

DETECTOR

100 Hz tick

1 Hz tick

0

1

32768 Hz

8192 Hz

PRESCALER

RESET

div 4

OSCILLATOR

CPR

(1)

stop

aaa-010477

1. stop is a combination of STOP register bit and the TS pin when programmed for stop control.

Figure 30.ꢀCPR and STOP bit functional diagram

The stop signal blocks the 8.192 kHz clock from generating system clocks and freezes

the time. In this state, the prescaler can be cleared with the CPR command in the Resets

register (Section 7.15).

Remark: The output of clock frequencies is not affected.

The time circuits can then be set and do not increment until the STOP bit is released.

The stop acts on the 8.192 kHz signal. And because the I²C-bus or TS pin input is

asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is

between zero and one 8.192 kHz cycle (see Figure 31).

8192 Hz

stop released

0 µs to 122 µs

aaa-004417

Figure 31.ꢀSTOP release timing

The first increment of the time circuits is between 0 s and 122 μs after STOP is released.

The flow for accurately setting the time in RTC mode is:

• start an I²C access at register 2Eh

• set STOP bit

• send CPR instruction

• address counter rolls over to address 00h

• set time (100th seconds, seconds to years)

• end I²C access

• wait for external time reference to indicate that time counting should start

• start an I²C access at register 2Eh

• clear STOP bit (time starts counting from now)

• end I²C access

The flow for resetting time in stop-watch mode is:

• start an I²C access at register 2Eh

• set STOP bit

• send CPR instruction

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

• address counter will roll over to address 00h

• set time to 000000:00:00.00

• end I²C access

7.17 64 byte RAM

In addition to the single RAM byte, there is a 64 byte RAM available from address 40h to

7Fh. The RAM can be written and read when the device is powered from V_DD. The RAM

content is backed-up when the device is powered from V_BAT, but cannot be accessed as

the interface is disabled.

The address pointer is set during interface initiation and will auto increment after each

byte access. The pointer will wrap around from address 7Fh to 40h after the last byte is

accessed, (see Figure 5).

8 I²C-bus interface

The I²C-bus is for bidirectional, two-line communication between different ICs. The two

lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy. Both data and clock lines remain HIGH when the bus is not

busy. The PCF85363A acts as a slave receiver when being written to and as a slave

transmitter when being read from.

Remark: When on V_BATpower, the interface is not accessible.

A

Write

Read

S

slave address + 0

A

write data

A

P

ACK from

slave

ACK from

slave

ACK from

slave

ACK from

slave

slave address + 1

A

read data

A

P

read data

A

ACK from

master

ACK from

slave

ACK from

slave

ACK from

master

aaa-010487

Figure 32.ꢀI²C read and write protocol

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

2

I C write example

SCL

SDA

bit7

bit0 ACK bit7

bit0 ACK

P

S

1st byte, slave address with R/W = 0

write 2nd byte

START

STOP

ACK of 2nd byte

from slave

condition

ACK of 1st byte

from slave

2

I C read example

SCL

SDA

bit7

read 2nd byte

0

bit

bit7

bit0 ACK

ACK

P

S

1st byte, slave address with R/W = 1

START

condition

STOP

condition

ACK of 1st byte

from slave

ACK of 2nd byte

from slave

aaa-010489

Figure 33.ꢀI²C read and write signaling

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must

remain stable during the HIGH period of the clock pulse, as changes in the data line at

this time are interpreted as STOP or START conditions.

8.2 START and STOP conditions

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the

START condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 33).

8.3 Acknowledge

Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as

logic 0. A not-acknowledge is defined as logic 1.

When written to, the slave will generate an acknowledge after the reception of each byte.

After the acknowledge, another byte may be transmitted. It is also possible to send a

STOP or START condition.

When read from, the master receiver must generate an acknowledge after the reception

of each byte. When the master receiver no longer requires bytes to be transmitter, it

must generate a not-acknowledge. After the not-acknowledge, either a STOP or START

condition must be sent.

A detailed description of the I²C-bus specification is given in [4].

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

9 Interface protocol

The PCF85363A uses the I²C interface for data transfer. Interpretation of the data is

determined by the interface protocol.

9.1 Write protocol

After the I²C slave address is transmitted, the PCF85363A requires that the register

address pointer is defined. It can take the value 00h to 2Fh. Values outside of that

range will result in the transfer being ignored, however the slave will still respond with

acknowledge pulses.

After the register address is transmitted, write data is transmitted. The minimum number

of data write bytes is 0 and the maximum number is unlimited. After each write, the

address pointer increments by one. After address 2Fh, the address pointer will roll over

to 00h.

• I²C START condition

• I²C slave address + write

• register address

• write data

• :

• write data

• I²C STOP condition; an I²C RE-START condition is also possible.

9.2 Read protocol

When reading the PCF85363A, reading starts at the current position of the address

pointer. The address pointer for read data should first be defined by a write sequence.

• I²C START condition

• I²C slave address + write

• register address

• I²C STOP condition; an I²C RE-START condition is also possible.

After setting the address pointer, a read can be executed. After the I²C slave address

is transmitted, the PCF85363A will immediately output read data. After each read, the

address pointer increments by one. After address 2Fh, the address pointer will roll over

to 00h.

• I²C START condition

• I²C slave address + read

• read data (master sends acknowledge bit)

• :

• read data (master sends not-acknowledge bit)

• I²C STOP condition. An I²C RE-START condition is also possible.

The master must indicate that the last byte has been read by generating a not-

acknowledge after the last read byte.

9.3 Slave addressing

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

9.3.1 Slave address

One I²C-bus slave address (1010ꢀꢀ001) is reserved for the PCF85363A. The entire I²C-

bus slave address byte is shown in Table 64.

Table 64.ꢀI²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

1

0

1

0

1

After a START condition, the I²C slave address has to be sent to the PCF85363A device.

Slave address can also be written in a hexadecimal format:

• A2h - Write slave address

• A3h - Read slave address

10 Application design-in information

In this application, stop-watch mode is used to implement an elapsed time counter. The

TS pin is used with a mechanical switch to start and stop the time. Each time the time is

stopped, timestamp2 is loaded with the current time and an interrupt is generated on the

INTA pin.

Time

counter

stop

STOP

control

mechanical

switch detector

vdd_int

STOPM

sample

clock, 16 Hz

TSL

TSR2

load

TS pin

sample

invert

TSR2

flag

V

SS

INTA

gen.

aaa-010560

Figure 34.ꢀApplication example

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

The RTC must be configured correctly for this mode of operation. Outlined in Table 65

are the settings needed for this mode.

In addition, the time must be set and any other configurations like battery switch-over,

quartz oscillator driving mode, etc., which are dependent on the application.

The sampler circuit shown in Figure 34 will hold invalid data until the mechanical switch

detector mode is enabled. It then requires a minimum of one sample period to initialize

to the current TS pin level. It is recommended to enable the mechanical detector mode

on the TS pin at least 62.5 ms before enabling the TS event mode. Failure to do so can

result in a false first event.

Table 65.ꢀApplication configuration

Register

Pin_IO

Section

Bit(s)

State

Comment

Section 7.12

Section 7.13

TSPM[1:0]

TSIM

11

1

TS pin in input mode

Pin_IO

select mechanical switch mode

TS pin input is active LOW

allow TS pin to control STOP

allow timestamps to create interrupts

generate interrupt pulses

last event mode for timestamp2

output interrupt on INTA

Pin_IO

TSL

1

Function

STOPM

TSRIEA

ILPA

1

0

TSR_mode Section 7.12

Pin_IO Section 7.12

TSR2M[2:0]

101

INTAPM[1:0] 10

Figure 35 shows the waveforms that can be expected. sample clock, vdd_int and stop

are internal nodes. vdd_int is supply which operates the IC and will be either V_DDor V_BAT

depending on the state of the battery switch-over.

,

sample clock, 16 Hz

vdd_int

floating

TS pin

V

SS

TS pin sampled

open

closed

switch SW 1

stop

stopwatch

running

stopped

running

TSR2 = t4

TSR2

INTA

t1

t2

t3

t4

t5 t6

aaa-010561

Figure 35.ꢀApplication example timing

• At and before t1, SW1 is open (TS pin floating). The TS pin is sampled and the internal

pull-up resistor will pull the pin HIGH to vdd_int. No actions are taken by the IC.

• At t2, SW1 is still open. No action is taken by the IC.

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

• At t3, SW1 closes. The TS pin is now shorted to V_SS. The TS pin has not been sampled

yet, so no action is taken by the IC.

• At t4, SW1 is closed. The internal pull-up resistor is enabled, but TS pin remains LOW.

The pin is then sampled and the LOW level detected. As the TSL bit was set for active

LOW detection, the HIGH-LOW transition of TS pin sampled triggers an event.

STOPM mode was configured to allow the TS pin to stop the time counting. As the TSL

bit was set for active LOW, time counting stops when the TS pin is LOW.

Timestamp register 2 was configured to take a copy of the time on an event of the TS

pin, hence TSR2 loads the time t4. TSR2F is also set.

INTA was configured to generate an interrupt when TSR2 loads a new time, hence an

interrupt pulse is seen on INTA.

• At t5, SW1 is opened. No action is taken by the IC.

• At t6, SW1 is open. The internal pull-up is active and the TS pin raises to vdd_int level.

The HIGH level is sampled and causes the stop signal to be released and time starts

counting again.

11 Internal circuitry

PCF85363A

VDD

OSCI

OSCO

INTA

CLK

SCL

SDA

VBAT

TS

VSS

aaa-011071

Figure 36.ꢀDevice diode protection diagram of PCF85363A

12 Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe

precautions for handling electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,

JESD625-A or equivalent standards.

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

13 Limiting values

Table 66.ꢀLimiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

I_DD

Parameter

Conditions

Min

-0.5

-50

-0.5

-50

-0.5

-10

-

Max

+6.5

+50

Unit

V

supply voltage

supply current

mA

V

V_BAT

I_BAT

V_I

battery supply voltage

battery supply current

input voltage

+6.5

+50

mA

V

on pins SCL, SDA, OSCI, TS

+6.5

+10

V_O

output voltage

V

I_I

input current

at any input

mA

mW

V

I_O

output current

at any output

+10

P_tot

V_ESD

total power dissipation

300

[1]

[2]

electrostatic discharge HBM

voltage

-

±3ꢀ500

CDM

PCF85363ATL

-

±1ꢀ750

±1ꢀ000

±2ꢀ000

200

V

PCF85363ATT

PCF85363ATT1

-

V

-

V

[3]

[4]

I_lu

latch-up current

-

mA

°C

T_stg

T_amb

storage temperature

-65

-40

+150

+85

ambient temperature operating device

[1] Pass level; Human Body Model (HBM) according to [1].

[2] Pass level; Charged-Device Model (CDM), according to [2].

[3] Pass level; latch-up testing, according to [3] at maximum ambient temperature (T_amb(max)).

[4] According to the store and transport requirements (see [5]) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to

75 %.

14 Characteristics

Table 67.ꢀStatic characteristics

V_DD= 0.9 V to 5.5 V; V_SS= 0 V; T_amb= -40 °C to +85 °C; f_osc= 32.768 kHz; quartz R_s= 60 kΩ; C_L= 7 pF; all registers in

reset state; unless otherwise specified.

Symbol

Supplies

V_DD

Parameter

Conditions

Min

Typ

Max

Unit

[1]

[2]

[1]

[3]

supply voltage

interface inactive; f_SCL= 0 Hz

interface active; f_SCL= 400 kHz

0.9

1.8

0.9

-

5.5

V

V_BAT

I_DD

battery supply voltage

supply current

CLKOUT disabled;

V_DD= 3.3 V;

interface inactive; f_SCL= 0 Hz

battery switch enabled

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Table 67.ꢀStatic characteristics...continued

V_DD= 0.9 V to 5.5 V; V_SS= 0 V; T_amb= -40 °C to +85 °C; f_osc= 32.768 kHz; quartz R_s= 60 kΩ; C_L= 7 pF; all registers in

reset state; unless otherwise specified.

Symbol

Parameter

Conditions

T_amb= 25 °C

Min

Typ

320

370

590

Max

480

550

885

Unit

nA

-

T_amb= 50 °C

nA

T_amb= 85 °C

nA

[4]

battery switch disabled

T_amb= 25 °C

-

280

330

550

10

420

500

825

-

nA

μA

T_amb= 50 °C

T_amb= 85 °C

CLKOUT disabled;

V_DD= 3.3 V;

interface active;

f_SCL= 400 kHz

Reference voltage

V_th

threshold voltage

HIGH falling V_DD

2.4

2.5

1.3

1.37

-

2.6

2.8

2.95

1.5

1.6

-

V

HIGH rising V_DD

2.7

V

LOW falling V_DD

1.4

V

LOW rising V_DD

1.47

±50

V

reference voltage hysteresis

mV

Inputs ^[5]

V_I

input voltage

-0.5

-

+5.5

V

V_IL

LOW-level input

voltage

+0.3V_DD

V_IH

I_LI

HIGH-level input

voltage

0.7V_DD

-

5.5

V

input leakage current V_I= V_SSor V_DD

post ESD event

-

0

-

μA

pF

kΩ

-0.5

-

+0.5

7

[6]

C_i

input capacitance

-

R_PU(TS)

pull-up resistance on 80 kΩ mode

pin TS

68

36

80

40

92

64

40 kΩ mode

Outputs

V_OH

HIGH-level output

voltage

on pin CLK, TS

0.8V_DD

V_SS

1

-

V_DD

V

V_OL

I_OH

LOW-level output

voltage

on pins SDA, INTA, CLK, TS

-

0.2V_DD

-

V

HIGH-level output

current

output source current;

V_OH= 2.9 V;

3

mA

V_DD= 3.3 V;

on pin CLK, TS

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PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Table 67.ꢀStatic characteristics...continued

V_DD= 0.9 V to 5.5 V; V_SS= 0 V; T_amb= -40 °C to +85 °C; f_osc= 32.768 kHz; quartz R_s= 60 kΩ; C_L= 7 pF; all registers in

reset state; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I_OL

LOW-level output

current

output sink current; V_OL= 0.4 V;

V_DD= 3.3 V

on pin SDA

on pin INTA

on pin CLK

on pin TS

3

2

1

8.5

6

-

mA

3

Oscillator

Δf_osc/f_osc

relative oscillator

ΔV_DD= 200 mV; T_amb= 25 °C

-

0.075

-

ppm

frequency variation

t_jit

jitter time

LOWJ = 0

LOWJ = 1

-

50

25

-

ns

[7]

C_L(itg)

integrated load

capacitance

on pins OSCO, OSCI;

V_DD= 3.3 V

C_L= 6 pF

C_L= 7 pF

4.8

5.6

10

-

6

7.2

8.4

15

pF

kΩ

7

C_L= 12.5 pF

normal mode

12.5

-

R_s

series resistance

100

[1] For reliable oscillator start-up at power-on use V_DDgreater than 1.2 V. If powered up at 0.9 V the oscillator will start but it might be a bit slow, especially if

at high temperature. Normally the power supply is not 0.9 V at start-up and only comes at the end of battery discharge. V_DDmin of 0.9 V is specified so

that the customer can calculate how large a battery or capacitor they need for their application. V_DDmin of 1.2 V or greater is needed to ensure speedy

oscillator start-up time.

[2] 400 kHz I2C operation is production tested at 1.8 V. Design methodology allows I2C operation at 1.8 V - 5 % (1.71 V) which has been verified during

product characterization on a limited number of devices.

[3] Measured after reset and CLK disabled, level of inputs is V_DDor V_SS

.

[4] Measured after reset, CLK disabled, battery switch disabled and level of inputs is V_DDor V_SS

[5] The I²C-bus interface of PCF85363A is 5 V tolerant.

[6] Implicit by design.

.

[7]

Integrated load capacitance, C_L(itg), is a calculation of C_OSCIand C_OSCOin series:

.

PCF85363A

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Product data sheet

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

aaa-010605

30

I

DD

(µA)

25

20

15

10

5

0

100

200

300

400

F

500

(kHz)

SCL

T_amb= 25 °C; CLKOUT disabled.

1. V_DD= 5.0 V.

2. V_DD= 3.3 V.

Figure 37.ꢀTypical I_DDwith respect to f_SCL

aaa-010602

900

I

DD

(nA)

750

600

450

300

150

0

(1)

(2)

-60

-40

-20

0

20

40

60

80

(ºC)

100

T

amb

C_L(itg)= 7 pF; CLKOUT disabled; battery switched on.

1. V_DD= 5 V.

2. V_DD= 3.3 V.

Figure 38.ꢀTypical I_DDas a function of temperature

PCF85363A

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

aaa-010603

18

I

DD

(µA)

15

12

9

(1)

6

(2)

(3)

3

0

1

2

3

4

5

6

V

DD

(V)

T_amb= 25 °C; f_CLKOUT= 32ꢀ768 Hz.

1. 47 pF CLKOUT load.

2. 22 pF CLKOUT load.

3. 0 pF CLKOUT load.

aaa-010604

600

I

DD

(nA)

500

400

300

200

100

0

(1)

(2)

(3)

0

1

2

3

4

5

6

V

DD

(V)

T_amb= 25 °C; CLKOUT disabled.

1. C_L(itg)= 12.5 pF.

2. C_L(itg)= 7 pF.

3. C_L(itg)= 6 pF.

Figure 39.ꢀTypical I_DDwith respect to V_DD

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Product data sheet

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

aaa-010607

0.4

Δf /f

osc osc

(ppm)

0.2

0

-0.2

-0.4

(1)

(2)

(3)

0

1

2

3

4

5

6

V

DD

(V)

T_amb= 25 °C.

1. C_L(itg)= 12.5 pF.

2. C_L(itg)= 6 pF.

3. C_L(itg)= 7 pF.

Figure 40.ꢀOscillator frequency variation with respect to V_DD

Table 68.ꢀI²C-bus characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; T_amb= -40 °C to +85 °C; f_osc= 32.768 kHz; quartz R_s= 60 kΩ; C_L= 7 pF; unless otherwise

specified. All timing values are valid within the operating supply voltage and temperature range and referenced to V_ILand

[1]

V_IHwith an input voltage swing of V_SSto V_DD

.

Symbol

Parameter

Conditions

Min

Max

Unit

C_b

capacitive load for

each bus line

-

400

pF

[2]

f_SCL

SCL clock frequency

0

400

-

kHz

μs

t_HD;STA

hold time (repeated)

START condition

0.6

t_SU;STA

set-up time for a

repeated START

condition

0.6

-

μs

t_LOW

t_HIGH

t_r

LOW period of the

SCL clock

1.3

0.6

20

-

μs

ns

μs

HIGH period of the

SCL clock

-

rise time of both SDA

and SCL signals

300

[3] [4]

t_f

fall time of both SDA

and SCL signals

20 × (V_DD/ 5.5 V) 300

t_BUF

bus free time between

a STOP and START

condition

1.3

-

t_SU;DAT

data set-up time

100

ns

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Product data sheet

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Table 68.ꢀI²C-bus characteristics...continued

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; T_amb= -40 °C to +85 °C; f_osc= 32.768 kHz; quartz R_s= 60 kΩ; C_L= 7 pF; unless otherwise

specified. All timing values are valid within the operating supply voltage and temperature range and referenced to V_ILand

[1]

V_IHwith an input voltage swing of V_SSto V_DD

.

Symbol

t_HD;DAT

t_SU;STO

Parameter

Conditions

Min

0

Max

Unit

ns

data hold time

-

set-up time for STOP

condition

0.6

μs

t_VD;DAT

t_VD;ACK

data valid time

0

0.9

μs

data valid

acknowledge time

t_SP

pulse width of

0

50

ns

spikes that must be

suppressed by the

input filter

[1] A detailed description of the I²C-bus specification is given in [4].

[2] I²C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min)of the SCL signal) to bridge the undefined

region of the falling edge of SCL.

[4] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at 250 ns. This

allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum

specified t_f.

START

condition

(S)

bit 7

MSB

(A7)

STOP

condition

(P)

bit 6

(A6)

bit 0 acknowledge

(R/W) (A)

protocol

t

HIGH

SU;STA

LOW

1

/f

SCL

SDA

t

BUF

f

t

r

t

VD;DAT

t

HD;DAT

VD;ACK

SU;STO

013aaa417

SU;DAT

HD;STA

Figure 41.ꢀI²C-bus timing diagram; rise and fall times refer to 30 % and 70 %

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Product data sheet

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

15 Application information

V

DD

100 nF

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

100 nF

VBAT

CLK

INTA

SCL

VDD

OSCI

V

DD

PCF85363A

OSCO

SDA

R

R: pull-up resistor

VSS

TS

t

r

R =

C

b

SDA SCL

2

(I C-bus)

aaa-011078

Figure 42.ꢀApplication diagram for PCF85363A

The data sheet values were obtained using a crystal with an ESR of 60 kΩ. If a crystal

with an ESR of 70 kΩ is used then the power consumption would increase by a few nA

and the start-up time will increase slightly.

16 Test information

16.1 Quality information

UL Component Recognition

This (component or material) is Recognized by UL. Representative

samples of this component have been evaluated by UL and meet

applicable UL requirements.

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Product data sheet

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

17 Package outline

DFN2626-10: plastic thermal enhanced extremely thin small outline package; no leads;

10 terminals; body 2.6 x 2.6 x 0.5 mm

SOT1197-1

X

B

A

D

E

A

1

A

3

terminal 1

index area

detail X

e

1

C

terminal 1

index area

B

A

v

w

C

e

b

y

1

y

C

1

5

L

k

E

h

10

6

D

h

0

1

2 mm

scale

Dimensions

(1)

Unit

A

b

D

h

E

e

1

k

L

v

w

y

1

3

h

max 0.5 0.05

nom

0.30 2.7 2.20 2.7 1.30

0.25 2.6 2.15 2.6 1.25

0.20 2.5 2.10 2.5 1.20

0.40

0.35

0.30

mm

0.127

0.5

2

0.1 0.05 0.05 0.05

min

0.00

0.2

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot1197-1_po

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

- - -

JEITA

- - -

11-01-20

12-09-16

SOT1197-1

Figure 43.ꢀPackage outline SOT1197-1 (DFN2626-10), PCF85363ATL

PCF85363A

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm

SOT505-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

A

(A )

2

A

3

A

1

pin 1 index

θ

L

p

L

1

4

detail X

e

w M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

E

L

p

UNIT

v

w

y

Z

θ

1

2

3

p

max.

0.15

0.05

0.95

0.80

0.45

0.25

0.28

0.15

3.1

2.9

3.1

2.9

5.1

4.7

0.7

0.4

0.70

0.35

6°

0°

mm

1.1

0.65

0.94

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-04-09

03-02-18

SOT505-1

Figure 44.ꢀPackage outline SOT505-1 (TSSOP8), PCF85363ATT

PCF85363A

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Product data sheet

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72 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm

SOT552-1

D

E

A

X

c

y

H

v

M

A

E

Z

6

10

A

(A )

2

A

3

A

1

pin 1 index

θ

L

p

L

1

5

detail X

e

w M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

L

UNIT

v

w

y

Z

θ

1

2

3

p

E

p

max.

0.15

0.05

0.95

0.80

0.30

0.15

0.23

0.15

3.1

2.9

3.1

2.9

5.0

4.8

0.7

0.4

0.67

0.34

6°

0°

mm

1.1

0.5

0.95

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-07-29

03-02-18

SOT552-1

Figure 45.ꢀPackage outline SOT552-1 (TSSOP10), PCF85363ATT1

PCF85363A

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Product data sheet

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73 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

18 Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IECꢀꢀ61340-5 or equivalent

standards.

19 Packing information

For tape and reel packing information, please see

• [6]

• [7]

• [8]

20 Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

20.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached

to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides

both the mechanical and the electrical connection. There is no single soldering method

that is ideal for all IC packages. Wave soldering is often preferred when through-hole

and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is

not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

20.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming

from a standing wave of liquid solder. The wave soldering process is suitable for the

following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

PCF85363A

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Product data sheet

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

20.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

20.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads

to higher minimum peak temperatures (see Figure 46) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board

is heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder

paste characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 69 and Table 70

Table 69.ꢀSnPb eutectic process (from J-STD-020D)

Package thickness (mm)

Package reflow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

< 2.5

≥ 2.5

220

Table 70.ꢀLead-free process (from J-STD-020D)

Package thickness (mm)

Package reflow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

PCF85363A

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Product data sheet

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 46.

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Figure 46.ꢀTemperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

21 Footprint information

3.600

2.950

0.725

0.125

5.750 3.600

3.200 5.500

1.150

0.600

0.450

0.650

sot505-1_fr

solder lands

occupied area

Dimensions in mm

Figure 47.ꢀFootprint information for reflow soldering of SOT505-1 (TSSOP8), PCF85363ATT

PCF85363A

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Product data sheet

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Footprint information for reflow soldering of DFN2626-10 package

SOT1197-1

Hx

Gx

D

P

0.025

Hy Ay Gy By

SPy

SLy

nSPx

SPx

SLx

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

solder paste deposit

solder land plus solder paste

occupied area

solder resist

DIMENSIONS in mm

P

Ay

By

D

SLx SLy SPx SPy

2.2 1.3 0.8 0.4

Gx

Gy

Hx

Hy

0.5

3.05 1.9 0.25

11-07-27

2.5 2.85 2.85

3.3

Issue date

sot1197-1_fr

12-09-16

Figure 48.ꢀFootprint information for reflow soldering of SOT1197-1 (DFN2626-10),PCF85363ATL

PCF85363A

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Footprint information for reflow soldering of TSSOP10 package

SOT552 -1

Hx

P1

Hy Gy

solder land

occupied area

Dimensions in mm

Gy

3.1

Hy

Hx

P1

11-04-19

13-05-02

5.0

3.1

0.5

Issue date

sot552-1_fr

Figure 49.ꢀFootprint information for reflow soldering of SOT552-1 (TSSOP10), PCF85363ATT1

PCF85363A

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Product data sheet

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

22 Appendix

22.1 Real-Time Clock selection

Table 71.ꢀSelection of Real-Time Clocks

Type name

Alarm, Timer,

Interrupt

Interface

I_DD

,

Battery

backup

Timestamp,

tamper input

AEC-Q100

compliant

Special features

Packages

Watchdog

output

typical (nA)

PCF8563

X

1

I²C

250

-

SO8, TSSOP8,

HVSON10

PCF8564A

PCA8565

X

1

I²C

250

600

-

integrated oscillator caps

WLCSP

grade 1

high robustness,

TSSOP8, HVSON10

T_amb= -40 °C to 125 °C

PCA8565A

X

1

I²C

600

-

integrated oscillator caps,

T_amb= -40 °C to 125 °C

WLCSP

PCF85063

-

1

2

I²C

SPI

I²C

220

230

-

basic functions only, no alarm HXSON8

PCF85063A

PCF85063B

PCF85263A

X

-

tiny package

SO8, DFN2626-10

-

tiny package

DFN2626-10

X

time stamp, battery backup,

SO8, TSSOP10,

TSSOP8, DFN2626-10

stopwatch ¹

⁄₁₀₀s

PCF85263B

PCF85363A

X

2

SPI

I²C

230

X

-

time stamp, battery backup,

TSSOP10, DFN2626-10

stopwatch ¹

₁₀₀s

⁄

time stamp, battery backup,

stopwatch ¹

RAM

⁄₁₀₀s, 64 Byte

PCF85363B

X

2

SPI

230

X

-

time stamp, battery backup,

TSSOP10, DFN2626-10

stopwatch ¹

RAM

⁄₁₀₀s, 64 Byte

PCF8523

PCF2123

PCF2127

X

2

1

I²C

150

100

500

X

-

lowest power 150 nA in

operation, FM+ 1 MHz

SO8, HVSON8,

TSSOP14, WLCSP

SPI

-

lowest power 100 nA in

operation

TSSOP14, HVQFN16

SO16

I²C and

SPI

X

temperature compensated,

quartz built in, calibrated, 512

Byte RAM

PCF2127A

X

1

I²C and

SPI

500

X

-

temperature compensated,

quartz built in, calibrated, 512

Byte RAM

SO20

PCF2129

PCF2129A

PCA2129

PCA21125

X

1

I²C and

SPI

500

820

X

-

X

-

temperature compensated,

quartz built in, calibrated

SO16

I²C and

SPI

-

temperature compensated,

quartz built in, calibrated

SO20

I²C and

SPI

grade 3

grade 1

temperature compensated,

quartz built in, calibrated

SO16

SPI

high robustness,

TSSOP14

T_amb= -40 °C to 125 °C

23 Abbreviations

Table 72.ꢀAbbreviations

Acronym

BCD

CMOS

ESD

HBM

I²C

Description

Binary Coded Decimal

Complementary Metal Oxide Semiconductor

ElectroStatic Discharge

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

LSB

Least Significant Bit

PCF85363A

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Product data sheet

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79 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Table 72.ꢀAbbreviations...continued

Acronym

MSB

MSL

Description

Most Significant Bit

Moisture Sensitivity Level

Printed-Circuit Board

Power-On Reset

PCB

POR

RTC

Real-Time Clock

SCL

Serial CLock line

Serial DAta line

SDA

SMD

Surface Mount Device

24 References

[1] JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model

(HBM)

[2] JESD22-C101 Field-Induced Charged-Device Model Test Method for Electrostatic-

Discharge-Withstand Thresholds of Microelectronic Components

[3] JESD78 IC Latch-Up Test

[4] UM10204 I²C-bus specification and user manual

[5] UM10569 Store and transport requirements

[6] SOT505-1_118 TSSOP8; Reel pack; SMD, 13", packing information

[7] SOT552-1_118 TSSOP10; Reel pack; SMD, 13", packing information

[8] SOT1197-1_115 DFN2626-10; Reel pack; SMD, 7", packing information

25 Revision history

Table 73.ꢀRevision history

Document ID

Release date

20210618

Data sheet status

Change notice

Supersedes

PCF85363A v.3.1

Modifications:

Product data sheet

202104008A

PCF85363A v.3

• Section 4: Added replacement information for SOT552-1.

20151118

PCF85363A v.3

PCF85363A v.2

PCF85363A v.1

Product data sheet

-

PCF85363A v.2

20150115

20140710

PCF85363A v.1

-

PCF85363A

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

26 Legal information

26.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

26.2 Definitions

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

26.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

PCF85363A

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Product data sheet

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81 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Security — Customer understands that all NXP products may be subject

to unidentified or documented vulnerabilities. Customer is responsible

for the design and operation of its applications and products throughout

their lifecycles to reduce the effect of these vulnerabilities on customer’s

applications and products. Customer’s responsibility also extends to other

open and/or proprietary technologies supported by NXP products for use

in customer’s applications. NXP accepts no liability for any vulnerability.

Customer should regularly check security updates from NXP and follow up

appropriately. Customer shall select products with security features that best

meet rules, regulations, and standards of the intended application and make

the ultimate design decisions regarding its products and is solely responsible

for compliance with all legal, regulatory, and security related requirements

concerning its products, regardless of any information or support that may

be provided by NXP. NXP has a Product Security Incident Response Team

(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,

reporting, and solution release to security vulnerabilities of NXP products.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor

tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of non-

automotive qualified products in automotive equipment or applications. In

the event that customer uses the product for design-in and use in automotive

applications to automotive specifications and standards, customer (a) shall

use the product without NXP Semiconductors’ warranty of the product for

such automotive applications, use and specifications, and (b) whenever

customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own

risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,

damages or failed product claims resulting from customer design and use

of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

26.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

NXP — wordmark and logo are trademarks of NXP B.V.

PCF85363A

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Product data sheet

Rev. 3.1 — 18 June 2021

82 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Tab. 6.

Tab. 7.

Ordering information ..........................................2

Ordering options ................................................2

Pin description ...................................................5

RTC mode time registers ..................................7

Stop-watch mode time registers ........................8

Control and function registers overview ............ 9

Time and date registers in RTC mode

(RTCM = 0) .....................................................10

BCD coding .....................................................11

Weekday assignments .................................... 12

Tab. 37. BSOFF bit - battery switch control (address

26h) bit description ..........................................39

Tab. 38. BSRR bit - battery switch control (address

26h) bit description ..........................................40

Tab. 39. BSM[1:0] bits - battery switch control

(address 26h) bit description ...........................40

Tab. 40. Battery switch-over modes ..............................40

Tab. 41. BSTH - battery switch control (address

26h) bit description ..........................................44

Tab. 42. Pin_IO- pin input output control register

(address 27h) bit description ...........................44

Tab. 43. CLKPM bit - Pin_IO control register

Tab. 8.

Tab. 9.

Tab. 10. Month assignments in BCD format ..................12

Tab. 11. Time registers in stop-watch mode (RTCM

= 1) ..................................................................14

Tab. 12. Alarm1 and alarm2 registers in RTC mode

coded in BCD (RTCM = 0) ..............................15

Tab. 13. Alarm_enables- alarm enable control

register (address 10h) bit description ..............16

Tab. 14. Alarm1 and alarm2 registers in stop-watch

mode coded in BCD (RTCM = 1) ....................19

Tab. 15. Alarm_enables- alarm enable control

register (address 10h) bit description ..............19

Tab. 16. WatchDog - WatchDog control and register

(address 2Dh) bit description .......................... 22

Tab. 17. WatchDog durations ........................................22

Tab. 18. RAM_byte - 8-bit RAM register (address

2Ch) bit description .........................................24

Tab. 19. TSR_mode - timestamp mode control

register (address 23h) bit description ..............25

Tab. 20. Timestamp registers in RTC mode (RTCM

= 0) ..................................................................27

Tab. 21. timestamp registers in stop-watch mode

(RTCM = 1) .....................................................28

Tab. 22. Offset - offset register (address 24h) bit

description ....................................................... 29

Tab. 23. OFFM bit - oscillator control register

(address 25h) ..................................................29

Tab. 24. Offset values ................................................... 30

Tab. 25. Correction pulses for OFFM = 0 ......................30

Tab. 26. Correction pulses for OFFM = 1 ......................31

Tab. 27. INTA and INTB interrupt control bits ................33

Tab. 28. Definition of interrupt control bits .....................33

Tab. 29. Oscillator - oscillator control register

(address 25h) bit description ...........................37

Tab. 30. CLKIV bit - oscillator control register

(address 25h) ..................................................37

Tab. 31. 12_24 bit - oscillator control register

(address 27h) ..................................................44

Tab. 44. TSPULL bit - Pin_IO control register

(address 27h) ..................................................45

Tab. 45. TSL bit - Pin_IO control register (address

27h) ................................................................. 45

Tab. 46. TSPM[1:0] bits - Pin_IO control register

(address 27h) ..................................................45

Tab. 47. TSIM bit - Pin_IO control register (address

27h) ................................................................. 46

Tab. 48. INTAPM[1:0] bits - Pin_IO control register

(address 27h) ..................................................47

Tab. 49. INTA battery mode .......................................... 48

Tab. 50. Function - chip function control register

(address 28h) bit description ...........................48

Tab. 51. 100TH bit - Function control register

(address 28h) ..................................................48

Tab. 52. PI[1:0] bits - Function control register

(address 28h) ..................................................48

Tab. 53. RTCM bit - Function control register

(address 28h) ..................................................49

Tab. 54. RTC time counting modes ...............................49

Tab. 55. STOPM bit - Function control register

(address 28h) ..................................................49

Tab. 56. Oscillator stop control when STOPM = 1 .........50

Tab. 57. COF[2:0] bits - Function control register

(address 28h) ..................................................50

Tab. 58. Clock duty cycles ............................................ 51

Tab. 59. Flags - Flag status register (address 2Bh)

bit description ..................................................51

Tab. 60. Reset - software reset control (address

2Fh) bit description ......................................... 52

Tab. 61. Registers reset values .....................................53

Tab. 62. Stop_enable - control of STOP bit (address

2Eh) .................................................................55

Tab. 63. Counter stop signal .........................................55

Tab. 64. I2C slave address byte ................................... 60

Tab. 65. Application configuration ................................. 61

Tab. 66. Limiting values ................................................ 63

Tab. 67. Static characteristics ....................................... 63

Tab. 68. I2C-bus characteristics ....................................68

Tab. 69. SnPb eutectic process (from J-STD-020D) ..... 75

Tab. 70. Lead-free process (from J-STD-020D) ............75

Tab. 71. Selection of Real-Time Clocks ........................ 79

Tab. 72. Abbreviations ...................................................79

(address 25h) ..................................................37

Tab. 32. LOWJ bit - oscillator control register

(address 25h) ..................................................37

Tab. 33. OSCD[1:0] bits - oscillator control register

(address 25h) ..................................................38

Tab. 34. CL[1:0] bits - oscillator control register

(address 25h) ..................................................38

Tab. 35. IO pin behavior in battery mode ......................39

Tab. 36. Battery_switch - battery switch control

(address 26h) bit description ...........................39

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NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Tab. 73. Revision history ...............................................80

Figures

Fig. 1.

Fig. 2.

Block diagram of PCF85363A ...........................3

Pin configuration for PCF85363ATL

(DFN2626-10) ....................................................4

Pin configuration for PCF85363ATT

(TSSOP8) ..........................................................4

Pin configuration for PCF85363ATT1

(TSSOP10) ........................................................4

Address register incrementing ...........................5

Register map .....................................................6

Time mode register set selection ...................... 7

OS status bit ................................................... 11

Data flow for the time function ........................ 13

Fig. 28. INTA pin .......................................................... 47

Fig. 29. Software reset command ................................ 53

Fig. 30. CPR and STOP bit functional diagram ............56

Fig. 31. STOP release timing .......................................56

Fig. 32. I2C read and write protocol .............................57

Fig. 33. I2C read and write signaling ........................... 58

Fig. 34. Application example ........................................ 60

Fig. 35. Application example timing ............................. 61

Fig. 36. Device diode protection diagram of

PCF85363A .....................................................62

Fig. 37. Typical IDD with respect to fSCL .....................66

Fig. 38. Typical IDD as a function of temperature ........ 66

Fig. 39. Typical IDD with respect to VDD .....................67

Fig. 40. Oscillator frequency variation with respect

to VDD ............................................................ 68

Fig. 41. I2C-bus timing diagram; rise and fall times

refer to 30 % and 70 % .................................. 69

Fig. 42. Application diagram for PCF85363A ............... 70

Fig. 43. Package outline SOT1197-1

(DFN2626-10), PCF85363ATL ........................71

Fig. 44. Package outline SOT505-1 (TSSOP8),

PCF85363ATT .................................................72

Fig. 45. Package outline SOT552-1 (TSSOP10),

PCF85363ATT1 ...............................................73

Fig. 46. Temperature profiles for large and small

components .....................................................76

Fig. 47. Footprint information for reflow soldering of

SOT505-1 (TSSOP8), PCF85363ATT .............76

Fig. 48. Footprint information for reflow soldering of

SOT1197-1 (DFN2626-10),PCF85363ATL ......77

Fig. 49. Footprint information for reflow soldering of

SOT552-1 (TSSOP10), PCF85363ATT1 .........78

Fig. 3.

Fig. 4.

Fig. 5.

Fig. 6.

Fig. 7.

Fig. 8.

Fig. 9.

Fig. 10. Data flow for the stop-watch function .............. 15

Fig. 11.

Alarm1 and alarm2 function block diagram

(RTC mode) .................................................... 18

Fig. 12. Alarm1 and alarm2 function block diagram

(stop-watch mode) ...........................................21

Fig. 13. WatchDog repeat mode .................................. 23

Fig. 14. WatchDog single shot mode ........................... 24

Fig. 15. Timestamp .......................................................25

Fig. 16. Example battery switch-over timestamp ..........26

Fig. 17. Example TS pin driven timestamp .................. 27

Fig. 18. Offset calibration calculation workflow .............32

Fig. 19. Result of offset calibration ...............................32

Fig. 20. Interrupt pulse width ........................................35

Fig. 21. Interrupt selection ............................................36

Fig. 22. Threshold voltage switching hysteresis ...........41

Fig. 23. Switching at Vth .............................................. 41

Fig. 24. Switching at VBAT .......................................... 42

Fig. 25. Switching at the higher of VBAT or Vth ........... 43

Fig. 26. Switching at the lower of VBAT or Vth .............43

Fig. 27. TS pin ..............................................................46

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Product data sheet

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84 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

Contents

1

2

3

4

General description ............................................ 1

Features and benefits .........................................1

Applications .........................................................1

Ordering information .......................................... 2

Ordering options ................................................ 2

Block diagram ..................................................... 3

Pinning information ............................................ 4

Pinning ...............................................................4

Pin description ...................................................5

Functional description ........................................5

Registers organization overview ........................6

Time mode registers ..........................................6

RTC mode time registers overview (RTCM

7.10

Oscillator register .............................................37

CLKIV: invert the clock output ......................... 37

OFFM: offset calibration mode ........................ 37

12_24: 12 hour or 24 hour clock ......................37

LOWJ: low jitter mode ..................................... 37

OSCD[1:0]: quartz oscillator drive control ........38

CL[1:0]: quartz oscillator load capacitance ...... 38

Battery switch register ..................................... 39

BSOFF: battery switch on/off control ............... 39

BSRR: battery switch internal refresh rate .......40

BSM[1:0]: battery switch mode ........................40

7.10.1

7.10.2

7.10.3

7.10.4

7.10.5

7.10.6

7.11

7.11.1

7.11.2

7.11.3

4.1

5

6

6.1

6.2

7

7.1

7.1.1

7.1.1.1

7.11.3.1 Switching at the Vth level, BSM[1:0] = 00 ........41

7.11.3.2 Switching at the VBAT level, BSM[1:0] = 01 .... 42

7.11.3.3 Switching at the higher of VBAT or Vth

level, BSM[1:0] = 10 ........................................42

7.11.3.4 Switching at the lower of VBAT and Vth

level, BSM[1:0] = 11 ........................................ 43

7.11.4

7.11.5

7.12

7.12.1

7.12.2

7.12.3

7.12.4

7.12.4.1 TS pin output mode; INTB ...............................46

7.12.4.2 TS pin output mode; CLK ................................46

7.12.4.3 TS pin disabled ................................................46

7.12.5

7.12.5.1 TS pin input mode ...........................................47

7.12.6 INTAPM[1:0]: INTA pin mode control ...............47

7.12.6.1 INTAPM[1:0]: INTA .......................................... 47

7.12.6.2 INTAPM[1:0]: clock data .................................. 47

7.12.6.3 INTAPM[1:0]: battery mode indication ............. 48

7.13

7.13.1

7.13.2

7.13.3

7.13.4

7.13.5

7.14

7.15

7.15.1

7.15.2

7.15.3

7.16

7.17

8

= 0) .................................................................... 7

Stop-watch mode time registers (RTCM =

7.1.1.2

1) ........................................................................8

Control registers overview .................................9

RTC mode time and date registers ..................10

Definition of BCD .............................................10

OS: Oscillator stop .......................................... 11

EMON: event monitor ......................................11

Definition of weekdays .....................................12

Definition of months .........................................12

Setting and reading the time in RTC mode ......12

Stop-watch mode time registers ...................... 14

Setting and reading the time in stop-watch

mode ................................................................14

Alarms ..............................................................15

Alarms in RTC mode .......................................15

Alarm1 and alarm2 registers in RTC mode ......15

Alarm1 and alarm2 control in RTC mode .........16

Alarm1 and alarm2 function in RTC mode .......17

Alarms in stop-watch mode ............................. 18

Alarm1 and alarm2 registers in stop-watch

7.1.2

7.2

BSTH: threshold voltage control ......................44

Battery switch interrupts .................................. 44

Pin_IO register .................................................44

CLKPM: CLK pin mode control ........................44

TSPULL: TS pin pull-up resistor value .............45

TSL: TS pin level sense .................................. 45

TSPM[1:0]: TS pin I/O control ......................... 45

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.3

7.3.1

7.4

7.4.1

7.4.1.1

7.4.1.2

7.4.1.3

7.4.2

TSIM: TS pin input type control .......................46

7.4.2.1

Function register ..............................................48

100TH: 100th seconds mode .......................... 48

PI[1:0]: Periodic interrupt .................................48

RTCM: RTC mode ...........................................49

STOPM: STOP mode control .......................... 49

COF[2:0]: Clock output frequency ................... 50

Flags register ...................................................51

Reset register .................................................. 52

SR - Software reset .........................................52

CPR: clear prescaler ....................................... 55

CTS: clear timestamp ......................................55

Stop_enable register ........................................55

64 byte RAM ................................................... 57

I2C-bus interface ...............................................57

Bit transfer ....................................................... 58

START and STOP conditions .......................... 58

Acknowledge ....................................................58

Interface protocol ..............................................59

Write protocol ...................................................59

Read protocol .................................................. 59

Slave addressing ............................................. 59

Slave address ..................................................60

Application design-in information ...................60

mode ................................................................18

Alarm1 and alarm2 control in stop-watch

mode ................................................................19

Alarm1 and alarm2 function in stop-watch

7.4.2.2

7.4.2.3

mode ................................................................20

Alarm interrupts ............................................... 21

WatchDog ........................................................ 22

WatchDog functions .........................................22

WatchDog repeat mode ...................................23

WatchDog single shot mode ............................23

WatchDog interrupts ........................................ 24

Single RAM byte ..............................................24

Timestamps ......................................................24

Timestamps interrupts ..................................... 29

Offset register .................................................. 29

Correction when OFFM = 0 .............................30

Correction when OFFM = 1 .............................31

Offset calibration workflow ...............................31

Offset interrupts ............................................... 33

Interrupts ..........................................................33

ILPA/ILPB: interrupt level or pulse mode ......... 34

Interrupt enable bits .........................................35

7.4.3

7.5

7.5.1

7.5.1.1

7.5.1.2

7.5.1.3

7.6

7.7

7.7.1

7.8

7.8.1

7.8.2

7.8.3

7.8.4

7.9

8.1

8.2

8.3

9

9.1

9.2

9.3

9.3.1

10

7.9.1

7.9.2

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 18 June 2021

85 / 86

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I²C-bus

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16.1

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Internal circuitry ................................................62

Safety notes .......................................................62

Limiting values ..................................................63

Characteristics .................................................. 63

Application information ....................................70

Test information ................................................ 70

Quality information ...........................................70

Package outline .................................................71

Handling information ........................................74

Packing information ..........................................74

Soldering of SMD packages .............................74

Introduction to soldering .................................. 74

Wave and reflow soldering .............................. 74

Wave soldering ................................................75

Reflow soldering .............................................. 75

Footprint information ........................................76

Appendix ............................................................79

Real-Time Clock selection ...............................79

Abbreviations .................................................... 79

References .........................................................80

Revision history ................................................ 80

Legal information ..............................................81

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20.2

20.3

20.4

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Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 June 2021

Document identifier: PCF85363A


型号：	PCF85363ATT1/AJ
厂家：	NXP
描述：	Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input, and I2C-bus
文件：	总86页 (文件大小：966K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCF85363ATT1/AJ [NXP]

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