PCF85363ATL/AX_技术文档

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm

function, battery switch-over time stamp input, and I²C-bus

Rev. 3 — 18 November 2015

Product data sheet

1. General description

The PCF85363A is a CMOS¹Real-Time Clock (RTC) and calendar optimized for low

power consumption and with automatic switching to battery on main power loss. The RTC

can also be configured as a stop-watch (elapsed time counter). Three time log registers

triggered from battery switch-over as well as input driven events. Featuring clock output

and two independent interrupt signals, two alarms, I²C interface and quartz crystal

calibration, 64 byte battery backed-up RAM.

For a selection of NXP Real-Time Clocks, see Table 72 on page 86.

2. Features and benefits

 UL Recognized Component (PCF85363ATL)

 Provides year, month, day, weekday, hours, minutes, seconds and 100th seconds

based on a 32.768 kHz quartz crystal

 Stop-watch mode for elapsed time counting. From 100th seconds to 999999 hours

 Two independent alarms

 Battery back-up circuit

 WatchDog timer

 Three timestamp registers

 Two independent interrupt generators plus predefined interrupts at every second,

minute, or hour

 64 byte battery backed-up RAM

 Frequency adjustment via programmable offset register

 Clock operating voltage: 0.9 V to 5.5 V

 Low current; typical 0.28 A at V_DD= 3.0 V and T_amb= 25 C

 400 kHz two-line I²C-bus interface (at V_DD= 1.8 V to 5.5 V)

 Programmable clock output for peripheral devices (32.768 kHz, 16.384 kHz,

8.192 kHz, 4.096 kHz, 2.048 kHz, 1.024 kHz, and 1 Hz)

 Configurable oscillator circuit for a wide variety of quartzes: C_L= 6 pF, C_L= 7 pF, and

C_L= 12.5 pF

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 24.

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

3. Applications

 Elapsed time counter

 Printers and copiers

 Network powered devices

 Battery backed up systems

 Data loggers

 Digital voice recorders

 Mobile equipment

 Digital cameras

 White goods

 Accurate high duration timer

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCF85363ATL

DFN2626-10

plastic thermal enhanced extremely

thin small outline package; no leads;

10 terminals; body 2.6  2.6  0.5 mm

SOT1197-1

PCF85363ATT

PCF85363ATT1

TSSOP8

plastic thin shrink small outline

package; 8 leads; body width 3 mm

SOT505-1

SOT552-1

TSSOP10

plastic thin shrink small outline

package; 10 leads; body width 3 mm

4.1 Ordering options

Table 2.

Ordering options

Product type number Orderable part number Sales item

(12NC)

Delivery form

IC

revision

PCF85363ATL/A

PCF85363ATT/A

PCF85363ATT1/A

PCF85363ATL/AX

PCF85363ATT/AJ

PCF85363ATT1/AJ

935304648115 tape and reel, 7 inch

1

935304751118 tape and reel, 13 inch

935304752118 tape and reel, 13 inch

5. Marking

Table 3.

Marking codes

Product type number

PCF85363ATL/A

PCF85363ATT/A

PCF85363ATT1/A

Marking code

363A

PCF85363A

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Product data sheet

Rev. 3 — 18 November 2015

2 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

6. Block diagram

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Fig 1. Block diagram of PCF85363A

PCF85363A

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Product data sheet

Rev. 3 — 18 November 2015

3 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

7. Pinning information

7.1 Pinning

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For mechanical details, see Figure 43 on page 78.

Fig 2. Pin configuration for PCF85363ATL (DFN2626-10)

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For mechanical details, see Figure 44 on page 79.

Fig 3. Pin configuration for PCF85363ATT (TSSOP8)

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For mechanical details, see Figure 45 on page 80.

Fig 4. Pin configuration for PCF85363ATT1 (TSSOP10)

PCF85363A

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Product data sheet

Rev. 3 — 18 November 2015

4 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

8. Functional description

The PCF85363A contains 8-bit registers for time information, for timestamp information

and registers for system configuration. Included is an auto-incrementing register address,

an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider which

provides the source clock for the Real-Time Clock (RTC) and calender, and an I²C-bus

interface with a maximum data rate of 400 kbit/s.

The built-in address register will increment automatically after each read or write of a data

byte. After register 2Fh, the auto-incrementing will wrap around to address 00h. When the

RAM is accessed, the wrap around will happen after address 7Fh, (see Figure 5).

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Fig 6. Register map

PCF85363A

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Product data sheet

Rev. 3 — 18 November 2015

6 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

All registers (see Table 5 on page 8, Table 6 on page 10, and Table 7 on page 12) are

designed as addressable 8-bit parallel registers although not all bits are implemented.

Figure 6 gives an overview of the address map.

The 100th seconds, seconds, minutes, hours, days, months, and years as well as the

corresponding alarm registers are all coded in Binary Coded Decimal (BCD) format. When

one of the RTC registers is read, the contents of all time counters are frozen. Therefore,

faulty reading of the clock and calendar during a carry condition is prevented.

8.1 Registers organization overview

8.1.1 Time mode registers

The PCF85363A has two time mode register sets, one for the real-time clock mode and

one for the stopwatch clock mode. The access to these registers can be switched by the

RTCM bit in the Function control register (28h), see Table 7 on page 12 and Table 54 on

page 54.

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Fig 7. Time mode register set selection

PCF85363A

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Product data sheet

Rev. 3 — 18 November 2015

7 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

8.2 RTC mode time and date registers

RTC mode is enabled by setting RTCM = 0. These registers are coded in the BCD format

to simplify application use.

Default state is:

Time — 00:00:00.00

Date — 2000 01 01

Weekday — Saturday

Monitor bits — OS = 1, EMON = 0

Table 8.

Time and date registers in RTC mode (RTCM = 0)

Bit positions labeled as - are not implemented and return 0 when read.

Address Register name Upper-digit (ten’s place) Digit (unit place)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00h

01h

02h

03h

100th_seconds^[1]0 to 9

0 to 9

Seconds

Minutes

Hours^[2]

OS

0 to 5

EMON 0 to 5

-

AMPM 0 to 1 0 to 9

0 to 2

0 to 9

-

04h

05h

06h

07h

Days^[3]

Weekdays

Months

Years

-

0 to 3

-

0 to 6

-

0 to 1 0 to 9

0 to 9

[1] The 100th_seconds register is only available when the 100TH mode is enabled, see Section 8.13.1. When

the 100TH mode is disabled, this register always returns 0.

[2] Hour mode is set by the 12_24 bit in the Oscillator register, see Section 8.10 on page 41.

[3] If the year counter contains a value, which is exactly divisible by 4, the PCF85363A compensates for leap

years by adding a 29th day to February.

8.2.1 Definition of BCD

The Binary-Coded Decimal (BCD) is an encoding of numbers where each digit is

represented by a separate bit field. Each bit field may only contain the values 0 to 9. In this

way, decimal numbers and counting is implemented.

Example: 59 encoded as an entire number is represented by 3Bh or 111011. In BCD the 5

is represented as 5h or 0101 and the 9 as 9h or 1001 which combines to 59h.

PCF85363A

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 9.

BCD coding

Upper-digit (ten’s place)

Value in

decimal

Digit (unit place)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00

01

02

:

0

:

0

:

0

1

:

0

1

0

:

0

:

0

:

0

1

:

0

1

0

:

09

10

:

1

0

:

0

:

0

:

1

0

:

1

0

:

0

:

0

:

1

0

:

98

99

1

0

1

0

1

8.2.2 OS: Oscillator stop

When the oscillator of the PCF85363A is stopped, the OS status bit is set. The oscillator

can be stopped, for example, by connecting one of the oscillator pins OSCI or OSCO to

ground. The oscillator is considered to be stopped during the time between power-on and

stable crystal resonance. This time can be in the range of 200 ms to 2 s depending on

crystal type, temperature, and supply voltage.

The status bit remains set until cleared by command (see Figure 8). If the bit cannot be

cleared, then the oscillator is not running. This method can be used to monitor the

oscillator and to determine if the supply voltage has reduced to the point where oscillation

fails.

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8.2.3 EMON: event monitor

The EMON can be used to monitor the status of all the flags in the Flags register, see

Section 8.14 on page 56. When one or more of the flags is set, then the EMON bit returns

a logic 1. The EMON bit cannot be cleared. EMON returns a logic 0 when all flags are

cleared.

See Figure 21 on page 40 for a pictorial representation.

PCF85363A

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Product data sheet

Rev. 3 — 18 November 2015

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

8.2.4 Definition of weekdays

Definition may be reassigned by the user.

Table 10. Weekday assignments

Day

Bit

2

1

0

1

0

1

0

1

0

1

0

1

0

Sunday

0

Monday

Tuesday

Wednesday

Thursday

Friday

0

1

Saturday

1

8.2.5 Definition of months

Table 11. Month assignments in BCD format

Month

Upper-digit

(ten’s place)

Digit (unit place)

Bit 4

0

Bit 3

0

Bit 2

Bit 1

0

Bit 0

1

January

February

March

0

1

0

1

0

1

April

0

May

0

1

June

0

1

0

July

0

1

August

September

October

November

December

0

1

0

1

0

1

0

1

0

1

0

1

0

PCF85363A

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

8.2.6 Setting and reading the time in RTC mode

Figure 9 shows the data flow and data dependencies starting from the 100 Hz clock tick.

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Fig 9. Data flow for the time function

During read operations, the time counting circuits (memory locations 00h through 07h) are

copied into an output register. The RTC continues counting in the background.

When reading or writing the time it is very important to make a read or write access in one

go, that is, setting or reading 100th seconds through to years should be made in one

single access. Failing to comply with this method could result in the time becoming

corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in a

second access the date is set, it is possible that the time increments between the two

accesses. A similar problem exists when reading. A roll-over may occur between reads

thus giving the minutes from one moment and the hours from the next.

Before setting the time, the STOP bit should be set and the prescalers should be cleared

(see Section 8.16 “Stop_enable register” on page 59).

An example of setting the time: 14 hours, 23 minutes and 19 seconds.

• I²C START condition

• I²C slave address + write (A2h)

• register address (2Eh)

• write data (set STOP, 01h)

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Product data sheet

Rev. 3 — 18 November 2015

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

• write data (clear prescaler, A4h)

• write data (100th seconds, 00h)

• write data (Hours, 14h)

• write data (Minutes, 23h)

• write data (Seconds, 19h)

• I²C START condition

• I²C slave address + write (A2h)

• register address (2Eh)

• write data (clear STOP, 00h). Time starts counting from this point

• I²C STOP condition

8.3 Stop-watch mode time registers

These registers are coded in the BCD format to simplify application use.

Stop-watch mode is enabled by setting RTCM = 1. In stop-watch mode, the PCF85363A

counts from 100th seconds to 999999 hours. There are no days, weekdays, months or

year registers.

Default state is:

Time — 000000:00:00.00

Monitor bits — OS = 1, EMON = 0 (see Section 8.2.2 on page 14 and Section 8.2.3 on

page 14)

Table 12. Time registers in stop-watch mode (RTCM = 1)

Bit positions labeled as - are not implemented and return 0 when read.

Address Register name Upper-digit (ten’s place)

Digit (unit place)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

0 to 9

-

Bit 2

Bit 1

Bit 0

00h

01h

02h

03h

04h

05h

06h

07h

100th_seconds^[1]0 to 9

Seconds

Minutes

OS

0 to 5

EMON 0 to 5

Hours_xx_xx_00 0 to 9

Hours_xx_00_xx 0 to 9

Hours_00_xx_xx 0 to 9

not used

-

[1] The 100th_seconds register is only available when the 100TH mode is enabled, see Section 8.13.1 on

page 53. When the 100TH mode is disabled, this register always returns 0.

8.3.1 Setting and reading the time in stop-watch mode

Figure 10 shows the data flow and data dependencies starting from the 100 Hz clock tick.

During read operations, the time counting circuits (memory locations 00h through 07h) are

copied into an output register. The RTC continues counting in the background.

PCF85363A

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Product data sheet

Rev. 3 — 18 November 2015

17 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

When reading or writing the time it is very important to make a read or write access in one

go, that is, setting or reading 100th_seconds through to HR_00_xx_xx should be made in

one single access. Failing to comply with this method could result in the time becoming

corrupted.

As an example, if the seconds value is set in one access and then in a following access

the minutes value is set, it is possible that the time increments between the two accesses.

A similar problem exists when reading. A roll-over may occur between reads thus giving

the seconds from one moment and the minutes from the next.

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Fig 10. Data flow for the stop-watch function

8.4 Alarms

There are two independent alarms. Each is separately configured and may be used to

generate an interrupt. In RTC mode, an alarm is configured for time and date. In

stop-watch mode when the RTC is functioning as an elapsed time counter, an alarm is

configured for time only.

8.4.1 Alarms in RTC mode

In RTC mode, Alarm 1 can be configured from seconds to months. Alarm 2 operates on

minutes, hours and weekday. Each segment of the time is independently enabled. Alarms

can be output on the INTA and INTB pins.

8.4.1.1 Alarm1 and alarm2 registers in RTC mode

Setting the time for alarm1: Only the information which is relevant for the alarm condition

must to be programmed. The unused parts are ignored.

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Product data sheet

Rev. 3 — 18 November 2015

18 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 13. Alarm1 and alarm2 registers in RTC mode coded in BCD (RTCM = 0)

Bit positions labeled as - are not implemented.

Address Register name

Upper-digit (ten’s place)

Digit (unit place)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RTC alarm1 registers

08h

09h

0Ah

Second_alarm1

Minute_alarm1

Hour_alarm1

-

0 to 5

-

0 to 9

AMPM 0 to 1 0 to 9

0 to 2

0 to 3

-

0 to 9

0Bh

0Ch

Day_alarm1

-

Month_alarm1

0 to 1 0 to 9

RTC alarm2 registers

0Dh

0Eh

Minute_alarm2

Hour_alarm2

-

0 to 5

-

0 to 9

AMPM 0 to 1 0 to 9

0 to 2

-

0 to 9

-

0Fh

Weekday_alarm2 -

-

0 to 6

8.4.1.2 Alarm1 and alarm2 control in RTC mode

Table 14. Alarm_enables- alarm enable control register (address 10h) bit description

Bit

Symbol

Value

Description

RTC alarm2

7

6

5

WDAY_A2E

weekday alarm2 enable

disabled

0^[1]

1

enabled

HR_A2E

MIN_A2E

hour alarm2 enable

disabled

0^[1]

1

enabled

minute alarm2 enable

disabled

0^[1]

1

enabled

RTC alarm1

4

3

2

1

MON_A1E

month alarm1 enable

disabled

0^[1]

1

enabled

DAY_A1E

HR_A1E

MIN_A1E

day alarm1 enable

disabled

0^[1]

1

enabled

hour alarm1 enable

disabled

0^[1]

1

enabled

minute alarm1 enable

disabled

0^[1]

1

enabled

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 14. Alarm_enables- alarm enable control register (address 10h) bit description

Bit

Symbol

Value

Description

second alarm1 enable

disabled

0

SEC_A1E

0^[1]

1

enabled

[1] Default value.

8.4.1.3 Alarm1 and alarm2 function in RTC mode

The registers at addresses 08h through 0Ch contain alarm1 information. When one or

more of these registers is loaded with second, minute, hour, day, or month, and its

corresponding alarm enable bit (SEC_A1E to MON_A1E) is set logic 1, then that

information is compared with the current second, minute, hour, day, and month.

The registers at addresses 0Dh through 0Fh contain alarm2 information. When one or

more of these registers is loaded with minute, hour or weekday, and its corresponding

alarm enable bit (MIN_A2E to WDAY_A2E) is set logic 1, then that information is

compared with the current minute, hour and weekday.

Alarm registers which have their alarm enable bit at logic 0 are ignored.

When the time increments to match the enabled alarms, the alarm flag in the Flags

register (Section 8.14 on page 56) is set. A1F for alarm1 and A2F for alarm2. The alarm

flag is cleared by command.

When the time increments to match the enabled alarms, an interrupt can be generated.

See Section 8.4.3 “Alarm interrupts”.

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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(1) Only when all enabled alarm settings are matching.

The flag is set only on increment to a matched case (and not all the time it is equal).

Fig 11. Alarm1 and alarm2 function block diagram (RTC mode)

8.4.2 Alarms in stop-watch mode

In stop-watch mode, Alarm 1 can be configured from seconds to 999999 hours. Alarm 2

operates on minutes up to 9999 hours.

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

8.4.2.1 Alarm1 and alarm2 registers in stop-watch mode

Setting the time for alarm1 and alarm2: Only the information which is relevant for the

alarm condition must to be programmed. The unused parts are ignored.

Table 15. Alarm1 and alarm2 registers in stop-watch mode coded in BCD (RTCM = 1)

Bit positions labeled as - are not implemented.

Address Register name

Upper-digit (ten’s place)

Digit (unit place)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Stop-watch alarm1 registers

08h

09h

0Bh

0Ch

Second_alm1

Minute_alm1

-

0 to 5

0 to 9

Hr_xx_xx_00_alm1 0 to 9

Hr_xx_00_xx_alm1 0 to 9

Hr_00_xx_xx_alm1 0 to 9

Stop-watch alarm2 registers

0Dh

0Eh

0Fh

Minute_alm2

-

0 to 5

0 to 9

Hr_xx_00_alm2

Hr_00_xx_alm2

0 to 9

8.4.2.2 Alarm1 and alarm2 control in stop-watch mode

Table 16. Alarm_enables- alarm enable control register (address 10h) bit description

Bit

Symbol

Value

Description

Stop-watch alarm2

7

6

5

HR_00_XX_A2E

thousands of hours alarm2 enable

0^[1]

1

disabled

enabled

HR_XX_00_A2E

MIN_A2E

tens of hours alarm2 enable

disabled

0^[1]

1

enabled

minute alarm2 enable

disabled

0^[1]

1

enabled

Stop-watch alarm1

4

3

2

HR_00_XX_XX_A1E

100 thousands of hours alarm1 enable

0^[1]

1

disabled

enabled

HR_XX_00_XX_A1E

HR_XX_XX_00_A1E

thousands of hours alarm1 enable

0^[1]

1

disabled

enabled

tens of hour alarm1 enable

disabled

0^[1]

1

enabled

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 16. Alarm_enables- alarm enable control register (address 10h) bit description

Bit

Symbol

Value

Description

minute alarm1 enable

disabled

1

MIN_A1E

0^[1]

1

enabled

0

SEC_A1E

second alarm1 enable

disabled

0^[1]

1

enabled

[1] Default value.

8.4.2.3 Alarm1 and alarm2 function in stop-watch mode

The registers at addresses 08h through 0Ch contain alarm1 information. When one or

more of these registers is loaded with second, minute, and hours, and its corresponding

alarm enable bit (SEC_A1E to HR_00_XX_XX_A1E) is set logic 1, then that information is

compared with the current second, minute, and hours.

The registers at addresses 0Dh through 0Fh contain alarm2 information. When one or

more of these registers is loaded with minute and hours, and its corresponding alarm

enable bit (MIN_A2E to HR_00_XX_A2E) is set logic 1, then that information is compared

with the current minute and hours.

Alarm registers which have their alarm enable bit at logic 0 are ignored.

When the time increments to match the enabled alarms, the alarm flag in the Flags

register (Section 8.14 on page 56) is set. A1F for alarm1 and A2F for alarm2. The alarm

flag is cleared by command.

When the time increments to match the enabled alarms, an interrupt can be generated.

See Section 8.4.3 “Alarm interrupts”.

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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(1) Only when all enabled alarm settings are matching.

The flag is set only on increment to a matched case (and not all the time it is equal).

Fig 12. Alarm1 and alarm2 function block diagram (stop-watch mode)

8.4.3 Alarm interrupts

The generation of interrupts from the alarm functions is controlled via the alarm interrupt

enable bits; A1IEA, A1IEB, A2IEA, A2IEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

The assertion of flags A1F or A2F can be used to generate an interrupt at the pins INTA

and INTB. The interrupt may be generated as a pulse signal every time the time

increments to match the alarm setting or as a permanently active signal which follows the

condition of bit A1F and/or A2F. See Section 8.9 on page 37 for interrupt control.

A1F and A2F remain set until cleared by command. Once an alarm flag has been cleared,

it will only be set again when the time increments to match the alarm condition once more.

When an interrupt pin is configured to pulse mode and if an alarm flag is not cleared and

the time increments to match the alarm condition again, then a repeated interrupt pulse

will be generated.

8.5 WatchDog

Table 17. WatchDog - WatchDog control and register (address 2Dh) bit description

Bit

Symbol

Value

Description

7

WDM

WatchDog mode

0^[1]

1

single shot

repeat mode

6 to 2 WDR[4:0]

1 to 0 WDS[1:0]

WatchDog register bits

Write: WatchDog counter load value

Read: current counter value

WatchDog step size (source clock)

4 seconds (0.25 Hz)

1 second (1 Hz)

0h^[1]to 1Fh

0h to 1Fh

00^[1]

01

10

¹⁄₄second (4 Hz)

1

11

⁄₁₆second (16 Hz)

[1] Default value.

8.5.1 WatchDog functions

The WatchDog has four selectable step sizes allowing for periods in the range from

62.5 ms to 124 seconds. For periods greater than 2 minutes, the alarm function can be

used.

WatchDog-duration = WDR  stepsize

(1)

Table 18. WatchDog durations

WDS[1:0] WatchDog step Delay

size^[1]

Minimum WatchDog duration Maximum WatchDog duration

WDR = 1

4 s

WDR = 31

00

01

10

11

4 s

1 s

¹⁄₄s

124 s

1 s

31 s

0.25 s

0.0625 s

7.75 s

1

⁄₁₆s

1.9375 s

[1] Time periods can be affected by correction pulses.

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Remark: Note that all timings are generated from the 32.768 kHz oscillator and are based

on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency results

in deviation in timings. This is not applicable to interface timing.

The WatchDog counts down from a software-loaded 5-bit binary value, WDR[4:0], in

register WatchDog. Loading the counter with 0 stops the WatchDog. Loading the counter

with a non-0 value starts the counter. Values from 1 to 31 are allowed.

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In this example, it is assumed that the WatchDog flag (WDF) is cleared before the next WatchDog

period expires and that the interrupt output is set to pulsed mode.

Fig 13. WatchDog repeat mode

If a new value of WDR[4:0] is written before the end of the current WatchDog period, then

this value takes immediate effect.

When starting the timer for the first time or when reloading WDR[4:0] before the end of the

current period, the first period has an uncertainty of maximum one count. The uncertainty

is a result of loading the WDR[4:0] from the interface clock which is asynchronous from

the WatchDog source clock. Subsequent WatchDog periods do not have such variation.

Reading the WatchDog register returns the current value of the WatchDog counter (see

Figure 13) and not the initial value WDR[4:0]. Since it is not possible to freeze the

WatchDog counter during read back, it is recommended to read the register twice and

check for consistent results.

8.5.1.1 WatchDog repeat mode

In repeat mode, at the end of every WatchDog period, the WatchDog flag (bit WDF in the

Flags register, Section 8.14 on page 56) is set and the counter automatically reloads and

starts the next WatchDog period. An example is given in Figure 13. The asserted bit WDF

can be used to generate an interrupt. Bit WDF can only be cleared by command.

8.5.1.2 WatchDog single shot mode

In single shot mode, at the end of the countdown period, the WatchDog flag (bit WDF in

the Flags register, Section 8.14 on page 56) is set and the counter stops with the value 0.

The WatchDog register must be reloaded to start another WatchDog period.

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Product data sheet

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26 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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Fig 14. WatchDog single shot mode

8.5.1.3 WatchDog interrupts

The generation of interrupts from the WatchDog functions is controlled via the WatchDog

interrupt enable bits; WDIEA and WDIEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

The assertion of the flag WDF can be used to generate an interrupt at pins INTA and

INTB. The interrupt may be generated as a pulsed signal every time the WatchDog

counter reaches the end of the countdown period. Alternatively as a permanently active

signal which follows the condition of bit WDF. WDF remains set until cleared by command.

When enabled, interrupts are triggered every time the WatchDog counter reaches the end

of the countdown period and even if the WDF is not cleared, an interrupt pulse can be

generated.

See Section 8.9 on page 37 for interrupt control.

8.6 Single RAM byte

Table 19. RAM_byte - 8-bit RAM register (address 2Ch) bit description

Bit

Symbol

Value

Description

7 to 0 B[7:0]

00000000^[1]to single RAM byte content

11111111

[1] Default value.

The PCF85363A provides a free single RAM byte, which can be used for any purpose, for

example, status bits of the system.

8.7 Timestamps

There are three timestamp registers which can be independently configured to record the

time for battery switch-over events and/or transitions on the TS pin.

Each timestamp register has an associated flag. It is also possible to generate an interrupt

signal for every timestamp register update.

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Timestamps work in both RTC and stop-watch mode. During battery operation, the

mechanical switch detector may also be used to trigger the timestamp.

The timestamp registers are read only and cannot be written. It is possible to set all three

registers to 0 with the CTS instruction in the Resets register (Section 8.15 on page 57).

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Fig 15. Timestamp

The mode for each register is controlled by the TSR_mode register.

PCF85363A

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 20. TSR_mode - timestamp mode control register (address 23h) bit description

Bit

Symbol

Value

Description

Timestamp3 (TSR3)

7 to 6 TSR3M[1:0]

timestamp register 3 mode

no timestamp

00^[1]

01

10

11

FB, record First time switch to Battery event

LB, record Last time switch to Battery event

LV, record Last time switch to V_DDevent

not used

5

-

0

Timestamp2 (TSR2)

4 to 2 TSR2M[2:0]

timestamp register 2 mode

no timestamp

000^[1]

001

FB, record First time switch to Battery event

LB, record Last time switch to Battery event

LV, record Last time switch to V_DDevent

FE, record First TS pin Event

LE, record Last TS pin Event

no timestamp

010

011

100

101

110 to 111

Timestamp1 (TSR1)

1 to 0 TSR1M[1:0]

timestamp register 1 mode

no timestamp

00^[1]

01

FE, record First TS pin Event

LE, record Last TS pin Event

no timestamp

10

11

[1] Default value.

First event means that the time is only stored on the first event and not recorded for

subsequent events. When the first event occurs, the associated timestamp flag is set.

When the flag is cleared, then a new ‘first’ event is recorded. See Figure 16 and

Figure 17.

Last event means that the time is stored on every event. When an event occurs, the

associated timestamp flag is set. It is not necessary to clear the flag before a new event is

recorded.

Interrupts can be generated in INTA pin and/or INTB pin. Interrupts are generated every

time a timestamp register is updated. Interrupt generation is not conditional on the state of

the timestamp flags. See Section 8.7.1.

PCF85363A

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Product data sheet

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29 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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(1) TS pin set to active HIGH (TSL = 0), see register Pin_IO (address 27h), Section 8.12.

Fig 17. Example TS pin driven timestamp

The recorded time is stored in the associated timestamp register. The time format

depends on the RTC mode. The timestamp registers follows the time format of the time

registers.

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PCF85363A

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 21. Timestamp registers in RTC mode (RTCM = 0)

Bit positions labeled as - are not implemented and return 0 when read.

Address Register name Upper-digit (ten’s place) Digit (unit place)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RTC timestamp1 (TSR1)

11h

12h

13h

TSR1_seconds

TSR1_minutes

TSR1_hours

-

0 to 5

-

0 to 9

AMPM 0 to 1 0 to 9

0 to 2

0 to 3

-

0 to 9

14h

15h

16h

TSR1_days

TSR1_months

TSR1_years

-

0 to 1 0 to 9

0 to 9

RTC timestamp2 (TSR2)

17h

18h

19h

TSR2_seconds

TSR2_minutes

TSR2_hours

-

0 to 5

-

0 to 9

AMPM 0 to 1 0 to 9

0 to 2

0 to 3

-

0 to 9

1Ah

1Bh

1Ch

TSR2_days

TSR2_months

TSR2_years

-

0 to 1 0 to 9

0 to 9

RTC timestamp3 (TSR3)

1Dh

1Eh

1Fh

TSR3_seconds

TSR3_minutes

TSR3_hours

-

0 to 5

-

0 to 9

AMPM 0 to 1 0 to 9

0 to 2

0 to 3

-

0 to 9

20h

21h

22h

TSR3_days

TSR3_months

TSR3_years

-

0 to 1 0 to 9

0 to 9

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Table 22. timestamp registers in stop-watch mode (RTCM = 1)

Bit positions labeled as - are not implemented and return 0 when read.

Address Register name

Upper-digit (ten’s place)

Digit (unit place)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

Stop-watch timestamp1 (TSR1)

11h

12h

13h

14h

15h

16h

TSR1_seconds

TSR1_minutes

-

0 to 5

0 to 9

-

TSR1_hr_xx_xx_00 0 to 9

TSR1_hr_xx_00_xx 0 to 9

TSR1_hr_00_xx_xx 0 to 9

not used

-

Stop-watch timestamp2 (TSR2)

17h

18h

19h

1Ah

1Bh

1Ch

TSR2_seconds

TSR2_minutes

-

0 to 5

0 to 9

-

TSR2_hr_xx_xx_00 0 to 9

TSR2_hr_xx_00_xx 0 to 9

TSR2_hr_00_xx_xx 0 to 9

not used

-

Stop-watch timestamp3 (TSR3)

1Dh

1Eh

1Fh

20h

21h

22h

TSR3_seconds

TSR3_minutes

-

0 to 5

0 to 9

-

TSR3_hr_xx_xx_00 0 to 9

TSR3_hr_xx_00_xx 0 to 9

TSR3_hr_00_xx_xx 0 to 9

not used

-

8.7.1 Timestamps interrupts

The generation of interrupts from the timestamp functions is controlled via the timestamp

interrupt enable bits; TSRIEA and TSRIEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

The loading of new information into one of the timestamp registers can be used to

generate an interrupt at pins INTA and INTB. The interrupt may be generated as a pulsed

signal every time a timestamp register updates or as a permanently active signal which

follows the condition of timestamp flags, TSR1F to TSR3F. The timestamp flags remain

set until cleared by command.

When enabled, interrupts are triggered every time a timestamp register updates and even

if the associated flag is not cleared, an interrupt pulse can be generated.

See Section 8.9 on page 37 for interrupt control.

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8.8 Offset register

The PCF85363A incorporates an offset register (address 24h) which can be used to

implement several functions, such as:

• Accuracy tuning

• Aging adjustment

• Temperature compensation

Table 23. Offset - offset register (address 24h) bit description

Bit

Symbol

Value

Description

offset value

7 to 0 OFFSET[7:0]

see Table 25

There are two modes which define the correction period, normal mode and fast mode.

The normal mode is suitable for offset trimming. The fast mode is suitable for dynamic

offset correction e.g. implementing a temperature correction. The fast mode consumes

more current. Offset mode is defined by bit OFFM in the Oscillator register (Section 8.10).

Table 24. OFFM bit - oscillator control register (address 25h)

See Section 8.10 on page 41.

Bit

Symbol

Value

Description

6

OFFM

offset mode bit

0^[1]

1

normal mode: correction is made every 4

hours; 2.170 ppm/step

fast mode: correction is made once every 8

minutes;2.0345 ppm/step

[1] Default value.

For OFFM = 0, each LSB introduces an offset of 2.170 ppm. For OFFM = 1, each LSB

introduces an offset of 2.0345 ppm. The offset value is coded in two’s complement giving

a range of +127 LSB to 128 LSB, see Table 25.

Table 25. Offset values

OFFSET[7:0]

Offset value in

decimal

Offset value in ppm

Normal mode

OFFM = 0

Fast mode

OFFM = 1

01111111

01111110

:

+127

+126

:

+275.590

+273.420

:

+258.3815

+256.3470

:

00000010

00000001

00000000^[1]

11111111

11111110

:

+2

+4.340

+2.170

0^[1]

+4.0690

+2.0345

0^[1]

+1

0

1

2.170

4.340

:

2.0345

4.0690

:

2

:

10000001

10000000

127

128

275.590

277.760

258.3815

260.416

[1] Default value.

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The correction is made by adding or subtracting clock correction pulses, thereby changing

the period of a single second but not by changing the oscillator frequency.

It is possible to monitor when correction pulses are applied. See Section 8.8.4.

8.8.1 Correction when OFFM = 0

The correction is triggered once every four hours and then correction pulses are applied

once per minute until the programmed correction values have been implemented.

Table 26. Correction pulses for OFFM = 0

Correction value

+1 or 1

Every n^thhour

Actual minute

00

4

+2 or 2

4

00 and 01

00, 01, and 02

:

+3 or 3

4

:

+59 or 59

+60 or 60

+61 or 61

4

00 to 58

00 to 59

00

4

4 + 1

4

+62 or 62

00 to 59

00 and 01

:

4 + 1

:

+123 or 123

4

00 to 59

00, 01, and 02

00 to 59

00 to 07

4 + 1

4 + 2

4

128

4 + 1

4 + 2

8.8.2 Correction when OFFM = 1

The correction is triggered once every eight minutes and then correction pulses are

applied once per second until the programmed correction values have been implemented.

Clock correction is made more frequently in OFFM = 1; however, this can result in higher

power consumption.

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Table 27. Correction pulses for OFFM = 1

Correction value

+1 or 1

Every n^thminute

Actual second

00

8

+2 or 2

8

00 and 01

00, 01, and 02

:

+3 or 3

8

:

+59 or 59

+60 or 60

+61 or 61

8

00 to 58

00 to 59

00

8

8 + 1

8

+62 or 62

00 to 59

00 and 01

:

8 + 1

:

+123 or 123

8

00 to 59

00, 01, and 02

00 to 59

00 to 07

8 + 1

8 + 2

8

128

8 + 1

8 + 2

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8.8.3 Offset calibration workflow

The calibration offset has to be calculated based on the time. Figure 18 shows the

workflow how the offset register values can be calculated:

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Fig 18. Offset calibration calculation workflow

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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With the offset calibration an accuracy of 1 ppm (0.5  offset per LSB) can be reached (see

Table 25).

1 ppm corresponds to a time deviation of 0.0864 seconds per day.

(1) 4 correction pulses in OFFM = 0 correspond to 8.680 ppm.

(2) 4 correction pulses in OFFM = 1 correspond to 8.138 ppm.

(3) Reachable accuracy zone.

Fig 19. Result of offset calibration

8.8.4 Offset interrupts

The generation of interrupts from the offset functions is controlled via the offset interrupt

enable bits; OIEA and OIEB. These bits are in registers INTA_enable (address 29h) and

INTB_enable (address 2Ah).

Every time a correction pulse is made an interrupt pulse can be generated at pins INTA

and INTB. As there are is no offset calibration flag, it is only possible to generate pulse

interrupts.

See Section 8.9 on page 37 for interrupt control.

8.9 Interrupts

There are two interrupt output pins, INTA and INTB. Both pins have the same possible

sources and a dedicated register to control what is output. The pins can be used

independently from each other.

INTA data is output on the INTA pin. INTA is an interrupt output pin with open-drain drive.

INTA pin mode is controlled by INTAPM[1:0] bits in the Pin_IO register (Section 8.12 on

page 49).

INTB data is output on TS pin with push-pull drive. The TS pin must first be configured as

INTB output by setting TSIO[1:0] bits in the Pin_IO register (Section 8.12 on page 49).

Interrupts will only be output when the pin mode is correctly defined. Interrupts are output

from the IC as active LOW signals.

The registers INTA_enable (address 29h) and INTB_enable (address 2Ah) are used to

select which interrupts should be output on which pin.

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Table 28. INTA and INTB interrupt control bits

Bit

INTA_enable - INTA pin enable control (address 29h)

Symbol ILPA PIEA OIEA A1IEA

INTB_enable - INTB pin enable control (address 2Ah)

Symbol ILPB PIEB OIEB A1IEB

7

6

5

4

3

2

1

0

A2IEA

A2IEB

TSRIEA

TSRIEB

BSIEA

BSIEB

WDIEA

WDIEB

Table 29. Definition of interrupt control bits

Bit

Symbol

INTA

Value

Description

INTB

7

ILPA

ILPB

level or pulse mode

0^[1]

1

interrupt generates a pulse

interrupt follows flags (permanent signal)

periodic interrupt enable

6

5

4

3

2

1

0

PIEA

PIEB

0^[1]

1

no periodic interrupt generated

periodic interrupt generated

OIEA

OIEB

offset correction interrupt enable

no correction interrupt generated

interrupt generated from correction

alarm1 interrupt enable

0^[1]

1

A1IEA

A2IEA

TSRIEA

BSIEA

WDIEA

A1IEB

A2IEB

TSRIEB

BSIEB

WDIEB

0^[1]

1

no alarm interrupt generated

alarm interrupt generated

alarm2 interrupt enable

0^[1]

1

no alarm interrupt generated

alarm interrupt generated

timestamp register interrupt enable

no timestamp register interrupt generated

timestamp register interrupt generated

battery switch interrupt enable

no battery switch interrupt generated

battery switch interrupt generated

WatchDog interrupt enable

0^[1]

1

0^[1]

1

0^[1]

1

no WatchDog interrupt generated

WatchDog interrupt generated

[1] Default value.

8.9.1 ILPA/ILPB: interrupt level or pulse mode

Interrupts can be configured to generate a pulse or to send a continuous level (permanent

signal) which follows the state of the flag.

In pulse mode, an interrupt pulse is generated every time that the selected source

triggers.

Triggered means

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• for periodic interrupts, every time a period has elapsed

• for offset correction, every time a correction pulse is initiated

• for alarms, every time the time increments to match the alarm time

• for timestamps, every time a register updates

• for battery switch, every time the IC switches to or from battery

• for WatchDog, every time the counter reaches the end of its count

The interrupt signal goes active coincident with the triggering event. The signal is cleared

by an internal 128 Hz clock. The internal clock is asynchronous to the triggering event and

so the pulse duration has a minimum period of one 128 Hz cycle and a maximum of two

128 Hz cycles. Interrupt pulses may be shortened by clearing the flag before the end of

the pulse period.

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Fig 20. Interrupt pulse width

In level mode, the interrupt signal follows the state of the flag. Only interrupts which are

enabled will affect the pin state. All enabled flags must be cleared for the interrupt signal

to be cleared.

The EMON is used only for monitoring all flags and can be read back in the minutes

register. See Section 8.2.3 on page 14.

8.9.2 Interrupt enable bits

The remainder of the bits in register INTA_enable (address 29h) and register

INTB_enable (address 2Ah) are used to select which interrupt data goes where. See

Figure 21 “Interrupt selection”

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8.10 Oscillator register

Table 30. Oscillator - oscillator control register (address 25h) bit description

Bit

7

6

5

4

3

2

1

0

Symbol

Section

CLKIV

OFFM

12_24

LOWJ

OSCD[1:0]

CL[1:0]

Section 8.10.6

Section 8.16

Section 8.8

Section 8.10.3

Section 8.10.4

Section 8.10.5

8.10.1 CLKIV: invert the clock output

Table 31. CLKIV bit - oscillator control register (address 25h)

Bit

Symbol

Value

Description

7

CLKIV

output clock inversion

0^[1]

1

non-inverting; LOWJ mode will affect rising

edge

inverted; LOWJ mode will affect falling edge

[1] Default value.

The clock selected with the COF[2:0] bits (register Function, address 28h) can be

inverted. This is intended for use in conjunction with the low jitter mode, LOWJ. The low

jitter mode reduces the jitter for the rising edge of the output clock. If the reduced jitter

needs to be on the falling edge, for example when using an open-drain clock output, then

the CLKIV bit can be used to implement this.

8.10.2 OFFM: offset calibration mode

See Section 8.8 “Offset register” on page 33 for a full description of offset calibration.

8.10.3 12_24: 12 hour or 24 hour clock

Table 32. 12_24 bit - oscillator control register (address 25h)

Bit

Symbol

Value

Description

5

12_24

12 hour or 24 hour mode

24 hour mode is selected

12 hour mode is selected

0^[1]

1

[1] Default value.

In RTC mode, time counting can be configured for 24 hour clock or 12 hour clock with the

AMPM flag.

This bit is ignored in stop-watch mode.

8.10.4 LOWJ: low jitter mode

Table 33. LOWJ bit - oscillator control register (address 25h)

Bit

Symbol

Value

Description

4

LOWJ

low jitter CLK output bit

normal

0^[1]

1

reduced CLK output jitter; increase I_DD

[1] Default value.

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Oscillator circuits suffer from jitter. In particular, ultra low-power oscillators like the one

used in the PCF85363A are optimized for power and not jitter. By setting the LOWJ bit,

the jitter performance can be improved at the cost of power consumption.

8.10.5 OSCD[1:0]: quartz oscillator drive control

Table 34. OSCD[1:0] bits - oscillator control register (address 25h)

Bit

Symbol

Value

Description

3 to 2 OSCD[1:0]

oscillator drive bits

00^[1]

01

normal drive; R_S(max): 100 k

low drive; R_S(max): 60 k; reduced I_DD

high drive; R_S(max): 500 k; increased I_DD

10, 11

[1] Default value.

The oscillator is designed to be used with quartz with a series resistance up to 100 k.

This covers the typical range of 32.768 kHz quartz crystals. Series resistance is also

referred to as: ESR, motional resistance, or R_S.

A low drive mode is available for low series resistance quartz. This reduces the current

consumption.

For very high series resistance quartz, there is a high drive mode. Current consumption

increases substantially in this mode.

8.10.6 CL[1:0]: quartz oscillator load capacitance

Table 35. CL[1:0] bits - oscillator control register (address 25h)

Bit

Symbol

Value

Description

1 to 0 CL[1:0]

internal oscillator capacitor selection for

quartz crystals with the corresponding load

capacitance of C_L:

00^[1]

01

7.0 pF

6.0 pF

12.5 pF

10

11

[1] Default value.

C_Lrefers to the load capacitance of the oscillator circuit and allows for a certain amount of

package and PCB parasitic capacitance. When the oscillator circuit matches the C_L

parameter of the quartz, then the frequency offset is zero.

The PCF85363A is designed to operate with quartz with C_Lvalues of 6.0 pF, 7.0 pF and

12.5 pF.

12.5 pF are generally the cheapest and most widely available, but also require the most

power to drive. The circuit also operates with 9.0 pF quartz, however the offset calibration

would be needed to compensate. If a 9.0 pF quartz is used, then it is recommended to set

C_Lto 7.0 pF.

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8.11 Battery switch register

This register configures the battery switch-over mode.

Associated with the battery switch-over is the battery switch flag (BSF) in the Flags

register (Section 8.14 on page 56). Whenever the IC switches to battery operation, the

flag is set. The flag can only be read when operating from V_DDpower, however an

interrupt pulse or static LOW signal can be generated whenever switching to battery. An

interrupt pulse can also be generated when switching back to V_DDpower. Examples are

given in Figure 23 and Figure 24.

When switched to battery, the V_DDpower domain is disabled. This means that I²C pins are

ignored, CLK output is disabled and Hi-Z, TS pin output mode is disabled and Hi-Z, TS

digital input is ignored and may be left floating. TS pin mechanical switch detector is

active. INTA output is still active for interrupt output and battery switch indication, but

disabled for clock output.

Table 36. IO pin behavior in battery mode

IO pin (mode)

V_DDoperation

active input

V_BAToperation

SCL

disabled; may be left floating

disabled; Hi-Z

SDA

active input/output

active output

active input

CLK

TS (output mode)

TS (digital input)

TS (mechanical switch input)

INTA

disabled; Hi-Z

disabled; may be left floating

active input

active output

active interrupt output

Table 37. Battery_switch - battery switch control (address 26h) bit description

Bit

7

-

6

-

5

-

4

3

2

1

0

Symbol

Section

BSOFF

BSRR

BSM[1:0]

Section 8.11.3

BSTH

-

Section 8.11.1

Section 8.11.2

Section 8.11.4

8.11.1 BSOFF: battery switch on/off control

Table 38. BSOFF bit - battery switch control (address 26h) bit description

Bit

Symbol

Value

Description

4

BSOFF

battery switch on/off

enable battery switch feature

disable battery switch feature

0^[1]

1

[1] Default value.

The battery switch circuit may be disabled when not used. This disables all the circuit and

save power consumption. When disabled connect V_BATand V_DDtogether.

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8.11.2 BSRR: battery switch internal refresh rate

Table 39. BSRR bit - battery switch control (address 26h) bit description

Bit

Symbol

Value

Description

3

BSRR

battery switch refresh rate

0^[1]

1

low

high

[1] Default value.

Non-user bit. Recommended to leave set at default.

8.11.3 BSM[1:0]: battery switch mode

Table 40. BSM[1:0] bits - battery switch control (address 26h) bit description

Bit

Symbol

Value

Description

2 to 1 BSM[1:0]

battery switch mode bits

switching at the V_thlevel

00^[1]

01

switching at the V_BATlevel

switching at the higher level of V_thor V_BAT

switching at the lower level of V_thor V_BAT

10

11

[1] Default value.

Switching is automatic and controlled by the voltages on the VBAT and VDD pins. There

are three modes:

• Compare V_DDwith an internal reference (V_th)

• Compare V_DDwith V_BAT

• Compare V_DDwith an internal reference (V_th) and V_BAT

The last mode is useful when a rechargeable battery is employed.

Table 41. Battery switch-over modes

BSM[1:0]

Condition

Internal power

V_DD

00

V_DD> V_th

V_DD< V_th

V_BAT

01

10

11

V_DD> V_BAT

V_DD

V_DD< V_BAT

V_BAT

V_DD> the higher of V_thor V_BAT

V_DD< the higher of V_thor V_BAT

V_DD> the lower of V_thor V_BAT

V_DD< the lower of V_thor V_BAT

V_DD

V_BAT

V_DD

V_BAT

Due to the nature of the power switch circuit there is a switching hysteresis (see Figure 22

and Table 68).

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

8.11.3.2 Switching at the V_BATlevel, BSM[1:0] = 01

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8.11.3.3 Switching at the higher of V_BATor V_thlevel, BSM[1:0] = 10

With this mode switching takes place when V_DDfalls below the higher of V_thor V_BAT. In

Figure 25, an example is given where the threshold is set to 1.5 V and a single cell battery

is connected to VBAT. In this example, switching to the battery voltage takes place when

V

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8.11.3.4 Switching at the lower of V_BATand V_thlevel, BSM[1:0] = 11

With this mode switching takes place when V_DDfalls below the lower of V_thor V_BAT. In

Figure 26, an example is given where the threshold is set to 1.5 V and a single cell battery

is connected to VBAT. In this example, switching to the battery voltage takes place when

V

_DDfalls below V_BAT.

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Fig 26. Switching at the lower of V_BATor V_th

8.11.4 BSTH: threshold voltage control

Table 42. BSTH - battery switch control (address 26h) bit description

Bit

Symbol

Value

Description

0

BSTH

battery switch threshold voltage, V_th

0^[1]

1

V_th= 1.5 V

V_th= 2.8 V

[1] Default value.

The threshold for battery switch-over is selectable between two voltages, 1.5 V and 2.8 V.

8.11.5 Battery switch interrupts

The generation of interrupts from the battery switch function is controlled via the battery

switch interrupt enable bits; BSIEA and BSIEB. These bits are in registers INTA_enable

(address 29h) and INTB_enable (address 2Ah).

The assertion of the flag BSF (register Flags, address 2Bh) can be used to generate an

interrupt at pins INTA and INTB. The interrupt may be generated as a pulsed signal or

alternatively as a permanently active signal which follows the condition of bit BSF. BSF

remains set until cleared by command.

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When enabled, interrupts are triggered every time the battery switch circuit switches to

either battery or to V_DDand even if the BSF is not cleared, an interrupt pulse can be

generated.

In addition, the INTA pin can be configured as a battery mode indicator

(INTAPM[1:0] = 00). See Section 8.12.6 on page 51. This mode differs from a general

interrupt signal in that it is only controlled by the current battery switch status.

See Section 8.9 on page 37 for interrupt control.

Remark: INTB pin is only active when the IC is operating from V_DD

.

8.12 Pin_IO register

Table 43. Pin_IO- pin input output control register (address 27h) bit description

Bit

7

6

5

4

3

2

1

0

Symbol

Section

CLKPM

TSPULL

TSL

TSIM

TSPM[1:0]

INTAPM[1:0]

Section 8.12.1

Section 8.12.2

Section 8.12.3

Section 8.12.5

Section 8.12.4

Section 8.12.6

This register is used to define the input and output modes of the IC.

8.12.1 CLKPM: CLK pin mode control

Table 44. CLKPM bit - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

7

CLKPM^[1]

CLK pin mode

enable CLK pin

disable CLK pin

0^[2]

1

[1] CLK pin is not available on all package types.

[2] Default value.

Setting the CLKPM bit disables the CLK output and force the pin to drive out a logic 0.

Clearing this bit enables the pad to output the selected clock frequency (see bits COF[2:0]

in the Function register, see Table 51 on page 53).

8.12.2 TSPULL: TS pin pull-up resistor value

Table 45. TSPULL bit - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

6

TSPULL

TS pin pull-up resistor value

0^[1]

1

80 k

40 k

[1] Default value.

Controls the pull-up resistor value used in the mechanical switch detector. For

applications where there is a large capacitance on the TS pin e.g. from a long connecting

cable to the mechanical switch, the pull-up resistor value can be halved to improve switch

detection.

Using the low-resistance value increases current consumption when the switch is closed

i.e. shorting to V_SS

.

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8.12.3 TSL: TS pin level sense

Table 46. TSL bit - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

5

TSL

TS pin input sense

active HIGH

0^[1]

1

active LOW

[1] Default value.

The active state of the TS pin can be defined for use as a timestamp trigger and/or as stop

control for the time counting. Active HIGH implies a transition from logic 0 to logic 1 is

active. Active LOW implies a transition from logic 1 to logic 0 is active.

8.12.4 TSPM[1:0]: TS pin I/O control

Table 47. TSPM[1:0] bits - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

3 to 2 TSPM[1:0]

TS pin IO mode

00^[1]

01

disabled; input can be left floating

INTB output; push-pull

CLK output; push-pull

input mode

10

11

[1] Default value.

These bits control the operation of the TS pin.

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TSIM is only considered when the TS pin is in input mode.

8.12.4.1 TS pin output mode; INTB

It is possible to output INTB data on the TS pin. The output is push-pull. No output is

available when on V_BAT. When on V_BATthe output is Hi-Z.

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8.12.4.2 TS pin output mode; CLK

It is possible to output a clock frequency on the TS pin. Clock frequency is selected with

the COF[2:0] bits in the Function register (Section 8.13 on page 53). The output is

push-pull. No output is available when on V_BAT. When on V_BATthe output is Hi-Z.

8.12.4.3 TS pin disabled

When disabled the pin is Hi-Z and can be left floating.

8.12.5 TSIM: TS pin input type control

Table 48. TSIM bit - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

4

TSIM

TS pin input mode

0^[1]

1

CMOS input; reference to V_DD; disabled when

on V_BAT

mechanical switch mode; active pull-up

sampled at 16 Hz; operates on V_DDand V_BAT

[1] Default value.

In CMOS input mode (TSIM = 0), input is taken directly from the TS pin. The input is

conditioned by the setting of TSL. When operating on the battery voltage (V_BAT), the input

is disabled and is allowed to float.

In mechanical switch detector mode (TSIM = 1), the TS pin is sampled at a rate of 16 Hz

for a period of 30.5 s. At the same time as the sample a pull-up resistor is activated to

detect an open pin or a pin shorted to V_SS. The input is referenced to the internal power

supply. This mode operates when on V_DDor V_BAT. The pull-up resistor value can be

controlled by TSPULL bit in the Pin_IO register (see Section 8.12 on page 49).

8.12.5.1 TS pin input mode

There are two input types which are controlled by the TSIM bit. The TS input can be used

to generate a timestamp event by configuring the timestamp mode bits; TSR2M[2:0] and

TSR1M[1:0] bits in TSR_mode register (see Table 20 on page 29).

Also it is possible to use the TS pin to control counting of time. This is typically for use with

the stop-watch mode where an elapsed time counter function can be implemented. Using

the STOPM bit in the Function register (see Table 51 on page 53) it is possible to control

the STOP bit by the TS pin.

8.12.6 INTAPM[1:0]: INTA pin mode control

Table 49. INTAPM[1:0] bits - Pin_IO control register (address 27h)

Bit

Symbol

Value

Description

1 to 0 INTAPM[1:0]

INTA pin mode

CLK output mode

battery mode indication

INTA output

00^[1]

01

10

11

Hi-Z

[1] Default value.

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The INTA pin can be used to output three different signals.

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8.12.6.1 INTAPM[1:0]: INTA

The primary function of the INTA pin is to output INTA data. INTA data is controlled by the

bits of the INTA_enable register (see Table 29 on page 38).

The output is active LOW with an open-drain output. The output is available during V_DD

and V_BAToperation.

8.12.6.2 INTAPM[1:0]: clock data

It is possible to output a clock frequency on the INTA pin. Clock frequency is selected with

the COF[2:0] bits in the Function register (Section 8.13 on page 53). The output is active

LOW with an open-drain output. The output is available only during V_DDoperation. The

output is Hi-Z when operating from V_BAT

.

Remark: Clock output is the default state. To save power, it is recommended to disable

the clock when not being used. If no clock is required, then set COF[2:0] in the Function

register (Section 8.13 on page 53) to CLK disabled. If clock output is only required on the

CLK pin, then set the INTA pin to either INTA data or battery mode.

8.12.6.3 INTAPM[1:0]: battery mode indication

It is possible to output the state of the power switch on the INTA pin. The output has an

open-drain output. The output is available during V_DDand V_BAToperation.

Table 50. INTA battery mode

Power supply

V_DD

INTA pin state

INTA = Hi-Z

V_BAT

INTA = logic 0

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8.13 Function register

Table 51. Function - chip function control register (address 28h) bit description

Bit

7

6

5

4

3

2

1

0

Symbol

Section

100TH

PI[1:0]

Section 8.13.2

RTCM

STOPM

COF[2:0]

Section 8.13.1

Section 8.13.3

Section 8.13.4

Section 8.13.5

8.13.1 100TH: 100th seconds mode

Table 52. 100TH bit - Function control register (address 28h)

Bit

Symbol

Value

Description

7

100TH

100th second mode

0^[1]

1

100th second disabled

100th second enabled

[1] Default value.

The PCF85363A can be configured to count at a resolution of 1 second or 0.01 seconds.

In 100th mode, the 100th_seconds register becomes available and the RTC counts at a

resolution of 0.01 seconds.

The 256 Hz clock signal is divided by 3 for fourteen 100 Hz periods and then by 2 for

eleven 100 Hz periods. This produces an effective division ratio of 2.56 with a maximum

jitter of 3.91 ms. Over twenty-five 100 Hz cycles the jitter is 0 ns.

8.13.2 PI[1:0]: Periodic interrupt

Table 53. PI[1:0] bits - Function control register (address 28h)

Bit

Symbol

Value

Description

6 to 5 PI[1:0]

periodic interrupt

no periodic interrupt

once per second

once per minute

once per hour

00^[1]

01

10

11

[1] Default value.

The periodic interrupt mode can be used to enable pre-defined timers for generating

pulses on the interrupt pin. Interrupts once per second, once per minute or once per hour

can be generated.

When disabled, the timers are reset. When enabled, the time to the first pulse is between

the chosen period and the chosen period minus 1 seconds.

The timers are not affected by STOP.

When the periodic interrupt triggers, the PIF (PI flag) in the Flags register (Section 8.14 on

page 56) is set.

The flag does not have to be cleared to allow another INTA or INTB pulse.

The duration of the periodic interrupt is unaffected by offset calibration.

See Section 8.9 “Interrupts” for a description of interrupt pulse control and output pins.

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8.13.3 RTCM: RTC mode

Table 54. RTCM bit - Function control register (address 28h)

Bit

Symbol

Value

Description

4

RTCM

RTC mode

0^[1]

1

real-time clock mode

stop-watch mode

[1] Default value.

The RTC mode is used to control how the time is counted. When configured as a classic

RTC, then time is counted from 100th seconds to years. In stop-watch mode, time is

counted from 100th seconds to 999999 hours.

Table 55. RTC time counting modes

RTCM Mode

Time counting

0

1

RTC

100th seconds^[1], seconds, minutes, hours, days, weekdays, months, years

stop-watch 100th seconds^[1], seconds, minutes, hours (0 hours to 999999 hours)

[1] Enabled with 100TH bit in the Function register (Section 8.13 on page 53).

8.13.4 STOPM: STOP mode control

Table 56. STOPM bit - Function control register (address 28h)

Bit

Symbol

Value

Description

3

STOPM

STOP mode

0^[1]

1

RTC stop is controlled by STOP bit only

RTC stop is controlled by STOP bit or TS pin

[1] Default value.

The STOP register bit in the Oscillator register (Section 8.10 on page 41) is used to stop

the counting of time in both RTC mode and stop-watch mode. Stopping of the oscillator

can also be controlled from the TS pin. The TS pin must first be configured as an input by

the TSPM[1:0] bits, then selected for active HIGH or active LOW by the TSL bits.

Table 57. Oscillator stop control when STOPM = 1

STOP bit^[1]

TSL

TS pin^[2]

Oscillator state

running

Description

0

1

0

1

-

TS pin active HIGH

stopped

1

-

stopped

TS pin active LOW

TS pin ignored

running

1

stopped

[1] In the Oscillator register (Section 8.10 on page 41).

[2] TSPM[1:0] = 11.

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8.13.5 COF[2:0]: Clock output frequency

Table 58. COF[2:0] bits - Function control register (address 28h)

Bit

Symbol

Value

Frequency selection (Hz)

CLK pin

32768

16384

8192

TS pin

32768

16384

8192

INTA pin

32768

16384

8192

4096

2048

1024

1

2 to 0

COF[2:0]

000^[1]

001

010

011

100

101

110

111

4096

2048

1024

1

static LOW

Hi-Z

[1] Default value.

A programmable square wave is available at pin CLK. Operation is controlled by the

COF[2:0] bits. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use

as a system clock, microcontroller clock, input to a charge pump, or for calibration of the

oscillator.

Pin CLK is a push-pull output and enabled at power-on. Pin CLK can be disabled by

setting CLKPM = 1 in the Pin_IO register (Section 8.12 on page 49). When disabled, the

CLK pin is LOW.

The selected clock frequency may also be output on the TS pin and the INTA pin. The

CLKIV bit may be used to invert the clock output. CLKIV does not invert for the setting

COF[2:0] = 111.

The duty cycle of the selected clock is not controlled. However, due to the nature of the

clock generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50.

Table 59. Clock duty cycles

COF[2:0]

000^[2]

001

Frequency (Hz)

32768

16384

8192

Typical duty cycle^[1]

60 : 40 to 40 : 60

50 : 50

-

010

011

4096

100

2048

101

1024

1^[3]

110

111

static

[1] Duty cycle definition: % HIGH-level time : % LOW-level time.

[2] Default values. The duty cycle of the CLKOUT when outputting 32,768 Hz could change from 60:40 to

40:60 depending on the detector since the 32,768 Hz is derived from the oscillator output which is not

perfect. It could change from device to device and it depends on the silicon diffusion. There is nothing that

can be done from outside the chip to influence the duty cycle.

[3] 1 Hz clock pulses are not affected by offset correction pulses.

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8.14 Flags register

Table 60. Flags - Flag status register (address 2Bh) bit description

Bit

Symbol Flag name

Value

Description

7

PIF

Periodic Interrupt Flag

Section 8.13.2 on page 53

0^[1]

read: periodic interrupt flag inactive

write: periodic interrupt flag is cleared

read: periodic interrupt flag active

write: periodic interrupt flag remains unchanged

read: alarm2 flag inactive

1

6

5

4

3

2

1

0

A2F

Alarm2 Flag

0^[1]

Section 8.4 on page 18

write: alarm2 flag is cleared

1

0^[1]

read: alarm2 flag active

write: alarm2 flag remains unchanged

read: alarm1 flag inactive

A1F

Alarm1 Flag

Section 8.4 on page 18

write: alarm1 flag is cleared

1

0^[1]

read: alarm1 flag active

write: alarm1 flag remains unchanged

read: WatchDog flag inactive

WDF

BSF

WatchDog Flag

Section 8.5 on page 25

write: WatchDog flag is cleared

1

0^[1]

read: WatchDog flag active

write: WatchDog flag remains unchanged

read: battery switch flag inactive

Battery Switch Flag

Section 8.11 on page 43

write: battery switch flag is cleared

read: battery switch flag active

1

0^[1]

write: battery switch flag remains unchanged

read: timestamp register 3 flag inactive

write: timestamp register 3 flag is cleared

read: timestamp register 3 flag active

write: timestamp register 3 flag remains unchanged

read: timestamp register 2 flag inactive

write: timestamp register 2 flag is cleared

read: timestamp register 2 flag active

write: timestamp register 2 flag remains unchanged

read: timestamp register 1 flag inactive

write: timestamp register 1 flag is cleared

read: timestamp register 1 flag active

write: timestamp register 1 flag remains unchanged

TSR3F

TSR2F

TSR1F

Timestamp Register 3

event Flag

Section 8.7 on page 27

1

0^[1]

Timestamp Register 2

event Flag

Section 8.7 on page 27

1

0^[1]

Timestamp Register 1

event Flag

Section 8.7 on page 27

1

[1] Default value.

The flags are set by their respective function. A full description can be found there. All

flags behave the same way. They are set by some function of the IC and remain set until

overwritten by command. It is possible to clear flags individually. To prevent one flag being

overwritten while clearing another, a logic AND is performed during a write access. All

flags are combined to generate an event monitoring signal called EMON. EMON is

described in Section 8.2.3 on page 14 and can be read as the MSB of minutes register.

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8.15 Reset register

Table 61. Reset - software reset control (address 2Fh) bit description

Bit

7

6

5

4

3

SR

2

1

0

Symbol

Section

CPR

0

1

0

1

0

CTS

Section 8.15.2

Section 8.15.1

Section 8.15.3

For a

• software reset (SR), 00101100 (2Ch) must be sent to register Reset (address 2Fh). A

software reset also triggers CPR and CTS

• clear prescaler (CPR), 10100100 (A4h) must be sent to register Reset (address 2Fh)

• clear timestamp (CTS),00100101 (25h) must be sent to register Reset (address 2Fh)

It is possible to combine CPR and CTS by sending 10100101 (A5h).

Remark: Any other value sent to this register is ignored.

8.15.1 SR - Software reset

A reset is automatically generated at power-on. A reset can also be initiated with the

software reset command.

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Fig 29. Software reset command

The PCF85363A resets to:

Mode — real-time clock, 100th second off

Time — 00:00:00.00

Date — 2000.01.01

Weekday — Saturday

Battery switch — on, switching on the lower threshold voltage

Oscillator — C_L= 7 pF

Pins — INTA = 32 kHz output, CLK = 32 kHz output, TS = disabled

In the reset state, all registers are set according to Table 62.

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 62. Registers reset values

Registers labeled as - remain unchanged.

Address

Register name

Bit

7

0

1

0

-

6

0

-

5

0

-

4

0

-

3

0

-

2

0

1

0

-

1

0

1

0

-

0

1

0

1

0

-

00h

01h

02h

03h

04h

05h

06h

07h

08h

100TH_seconds

Seconds

Minutes

Hours

Days

Weekdays

Months

Years

Second_alarm1

Second_alm1

Minute_alarm1

Minute_alm1

Hour_alarm1

Hr_xx_xx_00_alm1

Day_alarm1

Hr_xx_00_xx_alm1

Month_alarm1

Hr_00_xx_xx_alm1

Minute_alarm2

Minute_alm2

Hour_alarm2

Hr_xx_00_alm2

Weekday_alarm2

Hr_00_xx_alm2

Alarm enables

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

-

0

11h to 16h Timestamp 1

17h to 1Ch Timestamp 2

1Dh to 22h Timestamp 3

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

Timestamp_mode

Offset

Oscillator

Battery_switch

Pin_IO

Function

INTA_enable

INTB_enable

Flags

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 62. Registers reset values …continued

Registers labeled as - remain unchanged.

Address

Register name

Bit

7

6

0

5

0

4

0

3

0

2

0

1

0

2Ch

2Dh

2Fh

RAM_byte

WatchDog

Reset

0

8.15.2 CPR: clear prescaler

To set the time for RTC mode accurately or to clear the time in stop-watch mode, the clear

prescaler instruction is needed.

Before sending this instruction, it is recommended to first set stop either by the STOP bit

or by the TS pin (see STOPM bit).

See STOP definition for an explanation on using this instruction.

8.15.3 CTS: clear timestamp

The timestamp registers (address 11h to 22h) can be set to all 0 with this instruction.

8.16 Stop_enable register

Table 63. Stop_enable - control of STOP bit (address 2Eh)

Bit

7 to 1

0

Symbol

-

Value

Description

not used

0000000

STOP

STOP bit

0^[1]

1

RTC clock runs

RTC clock is stopped

[1] Default value.

The STOP bit stops the time from counting in both RTC mode and stop-watch mode. For

RTC mode STOP is useful to set the time accurately. For stop-watch mode it is the

start/stop control for the watch.

The counter can also be controlled from the TS pin by configuring STOPM in the Function

register (Section 8.13 on page 53). The internal stop signal is a combination of STOP and

the TS pin state.

Table 64. Counter stop signal

STOP bit

TS pin^[1][2]

stop signal

Counter

stopped

running

1

-

1

0

1

0

[1] Requires STOPM and TSPM[1:0] to be configured.

[2] TSL = 0 (active HIGH) (Pin_IO register, address 27h).

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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(1) stop is a combination of STOP register bit and the TS pin when programmed for stop control.

Fig 30. CPR and STOP bit functional diagram

The stop signal blocks the 8.192 kHz clock from generating system clocks and freezes the

time. In this state, the prescaler can be cleared with the CPR command in the Resets

register (Section 8.15 on page 57).

Remark: The output of clock frequencies is not affected.

The time circuits can then be set and do not increment until the STOP bit is released.

The stop acts on the 8.192 kHz signal. And because the I²C-bus or TS pin input is

asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is

between zero and one 8.192 kHz cycle (see Figure 31).

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Fig 31. STOP release timing

The first increment of the time circuits is between 0 s and 122 s after STOP is released.

The flow for accurately setting the time in RTC mode is:

• start an I²C access at register 2Eh

• set STOP bit

• send CPR instruction

• address counter rolls over to address 00h

• set time (100th seconds, seconds to years)

• end I²C access

• wait for external time reference to indicate that time counting should start

• start an I²C access at register 2Eh

• clear STOP bit (time starts counting from now)

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

• end I²C access

The flow for resetting time in stop-watch mode is:

• start an I²C access at register 2Eh

• set STOP bit

• send CPR instruction

• address counter will roll over to address 00h

• set time to 000000:00:00.00

• end I²C access

8.17 64 byte RAM

In addition to the single RAM byte, there is a 64 byte RAM available from address 40h to

7Fh. The RAM can be written and read when the device is powered from V_DD. The RAM

content is backed-up when the device is powered from V_BAT, but cannot be accessed as

the interface is disabled.

The address pointer is set during interface initiation and will auto increment after each

byte access. The pointer will wrap around from address 7Fh to 40h after the last byte is

accessed, (see Figure 5).

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PCF85363A

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

9. I²C-bus interface

The I²C-bus is for bidirectional, two-line communication between different ICs. The two

lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy. Both data and clock lines remain HIGH when the bus is not

busy. The PCF85363A acts as a slave receiver when being written to and as a slave

transmitter when being read from.

Remark: When on V_BATpower, the interface is not accessible.

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Fig 32. I²C read and write protocol

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Fig 33. I²C read and write signaling

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse, as changes in the data line at this time

are interpreted as STOP or START conditions.

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Product data sheet

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PCF85363A

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

9.2 START and STOP conditions

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 33).

9.3 Acknowledge

Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as

logic 0. A not-acknowledge is defined as logic 1.

When written to, the slave will generate an acknowledge after the reception of each byte.

After the acknowledge, another byte may be transmitted. It is also possible to send a

STOP or START condition.

When read from, the master receiver must generate an acknowledge after the reception

of each byte. When the master receiver no longer requires bytes to be transmitter, it must

generate a not-acknowledge. After the not-acknowledge, either a STOP or START

condition must be sent.

A detailed description of the I²C-bus specification is given in Ref. 10 “UM10204”.

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PCF85363A

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

10. Interface protocol

The PCF85363A uses the I²C interface for data transfer. Interpretation of the data is

determined by the interface protocol.

10.1 Write protocol

After the I²C slave address is transmitted, the PCF85363A requires that the register

address pointer is defined. It can take the value 00h to 2Fh. Values outside of that range

will result in the transfer being ignored, however the slave will still respond with

acknowledge pulses.

After the register address is transmitted, write data is transmitted. The minimum number

of data write bytes is 0 and the maximum number is unlimited. After each write, the

address pointer increments by one. After address 2Fh, the address pointer will roll over to

00h.

• I²C START condition

• I²C slave address + write

• register address

• write data

• :

• write data

• I²C STOP condition; an I²C RE-START condition is also possible.

10.2 Read protocol

When reading the PCF85363A, reading starts at the current position of the address

pointer. The address pointer for read data should first be defined by a write sequence.

• I²C START condition

• I²C slave address + write

• register address

• I²C STOP condition; an I²C RE-START condition is also possible.

After setting the address pointer, a read can be executed. After the I²C slave address is

transmitted, the PCF85363A will immediately output read data. After each read, the

address pointer increments by one. After address 2Fh, the address pointer will roll over to

00h.

• I²C START condition

• I²C slave address + read

• read data (master sends acknowledge bit)

• :

• read data (master sends not-acknowledge bit)

• I²C STOP condition. An I²C RE-START condition is also possible.

PCF85363A

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Product data sheet

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64 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

The master must indicate that the last byte has been read by generating a

not-acknowledge after the last read byte.

10.3 Slave addressing

10.3.1 Slave address

One I²C-bus slave address (1010001) is reserved for the PCF85363A. The entire I²C-bus

slave address byte is shown in Table 65.

Table 65. I²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

1

0

1

0

1

After a START condition, the I²C slave address has to be sent to the PCF85363A device.

Slave address can also be written in a hexadecimal format:

• A2h - Write slave address

• A3h - Read slave address

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

11. Application design-in information

In this application, stop-watch mode is used to implement an elapsed time counter. The

TS pin is used with a mechanical switch to start and stop the time. Each time the time is

stopped, timestamp2 is loaded with the current time and an interrupt is generated on the

INTA pin.

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Fig 34. Application example

The RTC must be configured correctly for this mode of operation. Outlined in Table 66 are

the settings needed for this mode.

In addition, the time must be set and any other configurations like battery switch-over,

quartz oscillator driving mode, etc., which are dependent on the application.

The sampler circuit shown in Figure 34 will hold invalid data until the mechanical switch

detector mode is enabled. It then requires a minimum of one sample period to initialize to

the current TS pin level. It is recommended to enable the mechanical detector mode on

the TS pin at least 62.5 ms before enabling the TS event mode. Failure to do so can result

in a false first event.

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 66. Application configuration

Register

Section

Bit(s)

State

11

1

Comment

Pin_IO

Function

Section 8.12

Section 8.13

TSPM[1:0]

TSIM

TS pin in input mode

select mechanical switch mode

TS pin input is active LOW

allow TS pin to control STOP

allow timestamps to create interrupts

generate interrupt pulses

last event mode for timestamp2

output interrupt on INTA

TSL

1

STOPM

TSRIEA

ILPA

1

0

TSR_mode Section 8.12

Pin_IO Section 8.12

TSR2M[2:0]

INTAPM[1:0]

101

10

Figure 35 shows the waveforms that can be expected. sample clock, vdd_int and stop are

internal nodes. vdd_int is supply which operates the IC and will be either V_DDor V_BAT

,

depending on the state of the battery switch-over.

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Fig 35. Application example timing

• At and before t1, SW1 is open (TS pin floating). The TS pin is sampled and the

internal pull-up resistor will pull the pin HIGH to vdd_int. No actions are taken by the

IC.

• At t2, SW1 is still open. No action is taken by the IC.

• At t3, SW1 closes. The TS pin is now shorted to V_SS. The TS pin has not been

sampled yet, so no action is taken by the IC.

• At t4, SW1 is closed. The internal pull-up resistor is enabled, but TS pin remains

LOW. The pin is then sampled and the LOW level detected. As the TSL bit was set for

active LOW detection, the HIGH-LOW transition of TS pin sampled triggers an event.

STOPM mode was configured to allow the TS pin to stop the time counting. As the

TSL bit was set for active LOW, time counting stops when the TS pin is LOW.

Timestamp register 2 was configured to take a copy of the time on an event of the TS

pin, hence TSR2 loads the time t4. TSR2F is also set.

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PCF85363A

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Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

INTA was configured to generate an interrupt when TSR2 loads a new time, hence an

interrupt pulse is seen on INTA.

• At t5, SW1 is opened. No action is taken by the IC.

• At t6, SW1 is open. The internal pull-up is active and the TS pin raises to vdd_int

level. The HIGH level is sampled and causes the stop signal to be released and time

starts counting again.

12. Internal circuitry

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Fig 36. Device diode protection diagram of PCF85363A

13. Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

14. Limiting values

Table 67. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

I_DD

Parameter

Conditions

Min

0.5

50

0.5

50

0.5

10

-

Max

+6.5

+50

Unit

V

supply voltage

supply current

mA

V

V_BAT

I_BAT

V_I

battery supply voltage

battery supply current

input voltage

+6.5

+50

mA

V

on pins SCL, SDA, OSCI, TS

+6.5

+10

V_O

output voltage

V

I_I

input current

at any input

mA

mW

V

I_O

output current

at any output

+10

P_tot

V_ESD

total power dissipation

300

[1]

[2]

electrostatic

discharge voltage

HBM

-

3500

CDM

PCF85363ATL

PCF85363ATT

PCF85363ATT1

-

1750

1000

2000

200

V

-

V

-

V

[3]

[4]

I_lu

latch-up current

-

mA

C

T_stg

T_amb

storage temperature

65

40

+150

+85

ambient temperature operating device

[1] Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.

[2] Pass level; Charged-Device Model (CDM), according to Ref. 7 “JESD22-C101”.

[3] Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature (T_amb(max)).

[4] According to the store and transport requirements (see Ref. 11 “UM10569”) the devices have to be stored at a temperature of +8 C to

+45 C and a humidity of 25 % to 75 %.

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Product data sheet

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69 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

15. Characteristics

Table 68. Static characteristics

V_DD= 0.9 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; f_osc= 32.768 kHz; quartz R_s= 60 k; C_L= 7 pF; all registers in

reset state; unless otherwise specified.

Symbol

Supplies

V_DD

Parameter

Conditions

Min

Typ

Max

Unit

[1]

[2]

[1]

[3]

supply voltage

interface inactive; f_SCL= 0 Hz

interface active; f_SCL= 400 kHz

0.9

1.8

0.9

-

5.5

V

V_BAT

I_DD

battery supply voltage

supply current

CLKOUT disabled;

V

_DD= 3.3 V;

interface inactive; f_SCL= 0 Hz

battery switch enabled

T_amb= 25 C

-

320

370

590

480

550

885

nA

T_amb= 50 C

T_amb= 85 C

[4]

battery switch disabled

T_amb= 25 C

-

280

330

550

10

420

500

825

-

nA

A

T_amb= 50 C

T_amb= 85 C

CLKOUT disabled;

V_DD= 3.3 V;

interface active;

f_SCL= 400 kHz

Reference voltage

V_th

threshold voltage

HIGH falling V_DD

2.4

2.5

1.3

1.37

-

2.6

2.8

2.95

1.5

1.6

-

V

HIGH rising V_DD

2.7

V

LOW falling V_DD

1.4

V

LOW rising V_DD

1.47

50

V

reference voltage hysteresis

mV

Inputs^[5]

V_I

input voltage

0.5

-

+5.5

V

V_IL

LOW-level input

voltage

+0.3V_DD

V_IH

I_LI

HIGH-level input

voltage

0.7V_DD

-

5.5

V

input leakage current V_I= V_SSor V_DD

post ESD event

-

0

-

A

pF

k

0.5

-

+0.5

7

[6]

C_i

input capacitance

-

R_PU(TS)

pull-up resistance on 80 k mode

pin TS

68

36

80

40

92

64

40 k mode

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Product data sheet

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PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 68. Static characteristics …continued

V_DD= 0.9 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; f_osc= 32.768 kHz; quartz R_s= 60 k; C_L= 7 pF; all registers in

reset state; unless otherwise specified.

Symbol

Outputs

V_OH

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level output

voltage

on pin CLK, TS

0.8V_DD

V_SS

1

-

V_DD

V

V_OL

I_OH

LOW-level output

voltage

on pins SDA, INTA, CLK, TS

-

0.2V_DD

-

V

HIGH-level output

current

output source current;

V_OH= 2.9 V;

3

mA

V

_DD= 3.3 V;

on pin CLK, TS

I_OL

LOW-level output

current

output sink current; V_OL= 0.4 V;

V_DD= 3.3 V

on pin SDA

on pin INTA

on pin CLK

on pin TS

3

2

1

8.5

6

-

mA

3

Oscillator

f_osc/f_osc

relative oscillator

frequency variation

V_DD= 200 mV; T_amb= 25 C

-

0.075

-

ppm

t_jit

jitter time

LOWJ = 0

LOWJ = 1

-

50

25

-

ns

[7]

C_L(itg)

integrated load

capacitance

on pins OSCO, OSCI;

V_DD= 3.3 V

C_L= 6 pF

C_L= 7 pF

4.8

5.6

10

-

6

7.2

8.4

15

pF

k

7

C_L= 12.5 pF

normal mode

12.5

-

R_s

series resistance

100

[1] For reliable oscillator start-up at power-on use V_DDgreater than 1.2 V. If powered up at 0.9 V the oscillator will start but it might be a bit

slow, especially if at high temperature. Normally the power supply is not 0.9 V at start-up and only comes at the end of battery

discharge. V_DDmin of 0.9 V is specified so that the customer can calculate how large a battery or capacitor they need for their

application. V_DDmin of 1.2 V or greater is needed to ensure speedy oscillator start-up time.

[2] 400 kHz I2C operation is production tested at 1.8 V. Design methodology allows I2C operation at 1.8 V  5 % (1.71 V) which has been

verified during product characterization on a limited number of devices.

[3] Measured after reset and CLK disabled, level of inputs is V_DDor V_SS

.

[4] Measured after reset, CLK disabled, battery switch disabled and level of inputs is V_DDor V_SS

[5] The I²C-bus interface of PCF85363A is 5 V tolerant.

[6] Implicit by design.

.

C_OSCI C_OSCO

-------------------------------------------

.



[7] Integrated load capacitance, C_L(itg), is a calculation of C_OSCIand C_OSCOin series: C_Litg

=

C_OSCI+ C_OSCO



PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

71 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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Fig 37. Typical I_DDwith respect to f_SCL

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(1) V_DD= 5 V.

(2) _DD= 3.3 V.

V

Fig 38. Typical I_DDas a function of temperature

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

72 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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T_amb= 25 C; f_CLKOUT= 32768 Hz.

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(2) 22 pF CLKOUT load.

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(2) C_L(itg)= 7 pF.

(3)

C_L(itg)= 6 pF.

Fig 39. Typical I_DDwith respect to V_DD

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

73 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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(1)

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(3) C_L(itg)= 7 pF.

Fig 40. Oscillator frequency variation with respect to V_DD

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

74 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

Table 69. I²C-bus characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; f_osc= 32.768 kHz; quartz R_s= 60 k; C_L= 7 pF; unless otherwise

specified. All timing values are valid within the operating supply voltage and temperature range and referenced to V_ILand V_IH

[1]

with an input voltage swing of V_SSto V_DD

.

Symbol

Parameter

Conditions

Min

Max

Unit

C_b

capacitive load for

each bus line

-

400

pF

[2]

f_SCL

SCL clock frequency

0

400

-

kHz

t_HD;STA

hold time (repeated)

START condition

0.6

s

t_SU;STA

set-up time for a

repeated START

condition

0.6

-

s

t_LOW

t_HIGH

t_r

LOW period of the

SCL clock

1.3

0.6

20

-

s

ns

s

HIGH period of the

SCL clock

-

rise time of both SDA

and SCL signals

300

[3][4]

t_f

fall time of both SDA

and SCL signals

20  (V_DD/ 5.5 V) 300

t_BUF

bus free time between

a STOP and START

condition

1.3

-

t_SU;DAT

t_HD;DAT

t_SU;STO

data set-up time

data hold time

100

0

-

ns

s

set-up time for STOP

condition

0.6

t_VD;DAT

t_VD;ACK

data valid time

0

0.9

s

data valid

acknowledge time

t_SP

pulse width of spikes

that must be

0

50

ns

suppressed by the

input filter

[1] A detailed description of the I²C-bus specification is given in Ref. 10 “UM10204”.

[2] I²C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min)of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

[4] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified t_f.

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

75 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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16. Application information

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The data sheet values were obtained using a crystal with an ESR of 60 k. If a crystal with

an ESR of 70 k is used then the power consumption would increase by a few nA and the

start-up time will increase slightly.

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

76 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

17. Test information

17.1 Quality information

UL Component Recognition

This (component or material) is Recognized by UL. Representative samples of this

component have been evaluated by UL and meet applicable UL requirements.

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

77 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

78 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

79 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

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19. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

20. Packing information

For tape and reel packing information, please see

• Ref. 12 “SOT505-1_118” on page 88

• Ref. 13 “SOT552-1_118” on page 88

• Ref. 14 “SOT1197-1_115” on page 88

21. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

21.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

21.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

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• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

21.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

21.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 46) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 70 and 71

Table 70. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 71. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

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Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 46.

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 46. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

22. Footprint information

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Fig 47. Footprint information for reflow soldering of SOT505-1 (TSSOP8), PCF85363ATT

PCF85363A

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Fig 48. Footprint information for reflow soldering of SOT1197-1 (DFN2626-10),PCF85363ATL

PCF85363A

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Fig 49. Footprint information for reflow soldering of SOT552-1 (TSSOP10), PCF85363ATT1

PCF85363A

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24. Abbreviations

Table 73. Abbreviations

Acronym

Description

BCD

CMOS

ESD

HBM

I²C

Binary Coded Decimal

Complementary Metal Oxide Semiconductor

ElectroStatic Discharge

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

LSB

MSB

MSL

PCB

POR

RTC

SCL

SDA

SMD

Least Significant Bit

Most Significant Bit

Moisture Sensitivity Level

Printed-Circuit Board

Power-On Reset

Real-Time Clock

Serial CLock line

Serial DAta line

Surface Mount Device

25. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN10366 — HVQFN application information

[3] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[5] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[7] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[8] JESD78 — IC Latch-Up Test

[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[10] UM10204 — I²C-bus specification and user manual

[11] UM10569 — Store and transport requirements

[12] SOT505-1_118 — TSSOP8; Reel pack; SMD, 13", packing information

[13] SOT552-1_118 — TSSOP10; Reel pack; SMD, 13", packing information

[14] SOT1197-1_115 — DFN2626-10; Reel pack; SMD, 7", packing information

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26. Revision history

Table 74. Revision history

Document ID

PCF85363A v.3

Modifications:

Release date

20151118

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCF85363A v.2

• Updated Table 4 “Pin description” Table note 3

• Updated Table 59 “Clock duty cycles” Table note 2

• Table 68 “Static characteristics”:

–

Corrected V_Imin from V_SSto 0.5 V

Corrected V_ILmin from V_SSto 0.5 V

Corrected V_IHmax from V_DDto 5.5 V

Corrected Table note 1

Added Table note 2

• Added text to Section 16 “Application information”

PCF85363A v.2

Modifications:

20150115

Product data sheet

-

PCF85363A v.1

• Corrected Figure 34

• Corrected V_thvalues in Table 68

PCF85363A v.1

20140710

Product data sheet

-

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27. Legal information

27.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

27.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

27.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

27.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

28. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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29. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 5. RTC mode time registers . . . . . . . . . . . . . . . . . .8

Table 6. Stop-watch mode time registers . . . . . . . . . . .10

Table 7. Control and function registers overview . . . . . .12

Table 8. Time and date registers in RTC mode

(RTCM = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 9. BCD coding . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 10. Weekday assignments . . . . . . . . . . . . . . . . . . .15

Table 11. Month assignments in BCD format. . . . . . . . . .15

Table 12. Time registers in stop-watch mode

Table 38. BSOFF bit - battery switch control

(address 26h) bit description . . . . . . . . . . . . . . 43

Table 39. BSRR bit - battery switch control

(address 26h) bit description . . . . . . . . . . . . . . 44

Table 40. BSM[1:0] bits - battery switch control

(address 26h) bit description . . . . . . . . . . . . . . 44

Table 41. Battery switch-over modes. . . . . . . . . . . . . . . . 44

Table 42. BSTH - battery switch control (address 26h)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 43. Pin_IO- pin input output control register

(address 27h) bit description . . . . . . . . . . . . . . 49

Table 44. CLKPM bit - Pin_IO control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 45. TSPULL bit - Pin_IO control register

(RTCM = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 13. Alarm1 and alarm2 registers in RTC mode

coded in BCD (RTCM = 0) . . . . . . . . . . . . . . . .19

Table 14. Alarm_enables- alarm enable control register

(address 10h) bit description . . . . . . . . . . . . . .19

Table 15. Alarm1 and alarm2 registers in stop-watch

mode coded in BCD (RTCM = 1) . . . . . . . . . . .22

Table 16. Alarm_enables- alarm enable control register

(address 10h) bit description . . . . . . . . . . . . . .22

Table 17. WatchDog - WatchDog control and register

(address 2Dh) bit description . . . . . . . . . . . . . .25

Table 18. WatchDog durations . . . . . . . . . . . . . . . . . . . . .25

Table 19. RAM_byte - 8-bit RAM register (address 2Ch)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 20. TSR_mode - timestamp mode control register

(address 23h) bit description . . . . . . . . . . . . . .29

Table 21. Timestamp registers in RTC mode (RTCM = 0)31

Table 22. timestamp registers in stop-watch mode

(RTCM = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 23. Offset - offset register (address 24h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 24. OFFM bit - oscillator control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 46. TSL bit - Pin_IO control register (address 27h) 50

Table 47. TSPM[1:0] bits - Pin_IO control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 48. TSIM bit - Pin_IO control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 49. INTAPM[1:0] bits - Pin_IO control register

(address 27h). . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 50. INTA battery mode. . . . . . . . . . . . . . . . . . . . . . 52

Table 51. Function - chip function control register

(address 28h) bit description . . . . . . . . . . . . . . 53

Table 52. 100TH bit - Function control register

(address 28h). . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 53. PI[1:0] bits - Function control register

(address 28h). . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 54. RTCM bit - Function control register

(address 28h). . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 55. RTC time counting modes . . . . . . . . . . . . . . . . 54

Table 56. STOPM bit - Function control register

(address 28h). . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 57. Oscillator stop control when STOPM = 1. . . . . 54

Table 58. COF[2:0] bits - Function control register

(address 28h). . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 59. Clock duty cycles . . . . . . . . . . . . . . . . . . . . . . . 55

Table 60. Flags - Flag status register (address 2Bh)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 61. Reset - software reset control (address 2Fh)

bit description. . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 62. Registers reset values . . . . . . . . . . . . . . . . . . 58

Table 63. Stop_enable - control of STOP bit

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 25. Offset values . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 26. Correction pulses for OFFM = 0 . . . . . . . . . . . .34

Table 27. Correction pulses for OFFM = 1 . . . . . . . . . . . .35

Table 28. INTA and INTB interrupt control bits. . . . . . . . .38

Table 29. Definition of interrupt control bits . . . . . . . . . . .38

Table 30. Oscillator - oscillator control register

(address 25h) bit description . . . . . . . . . . . . . .41

Table 31. CLKIV bit - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 32. 12_24 bit - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 33. LOWJ bit - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 34. OSCD[1:0] bits - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 35. CL[1:0] bits - oscillator control register

(address 25h) . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 36. IO pin behavior in battery mode . . . . . . . . . . . .43

Table 37. Battery_switch - battery switch control

(address 26h) bit description . . . . . . . . . . . . . .43

(address 2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 64. Counter stop signal . . . . . . . . . . . . . . . . . . . . . 59

Table 65. I²C slave address byte. . . . . . . . . . . . . . . . . . . 65

Table 66. Application configuration . . . . . . . . . . . . . . . . . 67

Table 67. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 68. Static characteristics . . . . . . . . . . . . . . . . . . . . 70

Table 69. I²C-bus characteristics. . . . . . . . . . . . . . . . . . . 75

Table 70. SnPb eutectic process (from J-STD-020D) . . . 82

Table 71. Lead-free process (from J-STD-020D) . . . . . . 82

Table 72. Selection of Real-Time Clocks . . . . . . . . . . . . 86

Table 73. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 74. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 89

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

92 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

30. Figures

Fig 1. Block diagram of PCF85363A . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration for PCF85363ATL

SOT505-1 (TSSOP8), PCF85363ATT . . . . . . . . 83

Fig 48. Footprint information for reflow soldering of

SOT1197-1 (DFN2626-10),PCF85363ATL . . . . . 84

Fig 49. Footprint information for reflow soldering of

SOT552-1 (TSSOP10), PCF85363ATT1 . . . . . . 85

(DFN2626-10) . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 3. Pin configuration for PCF85363ATT (TSSOP8). . .4

Fig 4. Pin configuration for PCF85363ATT1 (TSSOP10).4

Fig 5. Address register incrementing. . . . . . . . . . . . . . . .6

Fig 6. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Fig 7. Time mode register set selection. . . . . . . . . . . . . .7

Fig 8. OS status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 9. Data flow for the time function . . . . . . . . . . . . . . .16

Fig 10. Data flow for the stop-watch function. . . . . . . . . .18

Fig 11. Alarm1 and alarm2 function block diagram

(RTC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Fig 12. Alarm1 and alarm2 function block diagram

(stop-watch mode) . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 13. WatchDog repeat mode. . . . . . . . . . . . . . . . . . . .26

Fig 14. WatchDog single shot mode . . . . . . . . . . . . . . . .27

Fig 15. Timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 16. Example battery switch-over timestamp . . . . . . .30

Fig 17. Example TS pin driven timestamp . . . . . . . . . . . .30

Fig 18. Offset calibration calculation workflow. . . . . . . . .36

Fig 19. Result of offset calibration . . . . . . . . . . . . . . . . . .37

Fig 20. Interrupt pulse width. . . . . . . . . . . . . . . . . . . . . . .39

Fig 21. Interrupt selection . . . . . . . . . . . . . . . . . . . . . . . .40

Fig 22. Threshold voltage switching hysteresis . . . . . . . .45

Fig 23. Switching at V_th. . . . . . . . . . . . . . . . . . . . . . . . . .45

Fig 24. Switching at V_BAT. . . . . . . . . . . . . . . . . . . . . . . . .46

Fig 25. Switching at the higher of V_BATor V_th. . . . . . . . .47

Fig 26. Switching at the lower of V_BATor V_th. . . . . . . . . .48

Fig 27. TS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Fig 28. INTA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Fig 29. Software reset command. . . . . . . . . . . . . . . . . . .57

Fig 30. CPR and STOP bit functional diagram . . . . . . . .60

Fig 31. STOP release timing . . . . . . . . . . . . . . . . . . . . . .60

Fig 32. I²C read and write protocol . . . . . . . . . . . . . . . . .62

Fig 33. I²C read and write signaling. . . . . . . . . . . . . . . . .62

Fig 34. Application example. . . . . . . . . . . . . . . . . . . . . . .66

Fig 35. Application example timing . . . . . . . . . . . . . . . . .67

Fig 36. Device diode protection diagram of PCF85363A.68

Fig 37. Typical I_DDwith respect to f_SCL. . . . . . . . . . . . . .72

Fig 38. Typical I_DDas a function of temperature . . . . . . .72

Fig 39. Typical I_DDwith respect to V_DD. . . . . . . . . . . . . .73

Fig 40. Oscillator frequency variation with respect

to V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Fig 41. I²C-bus timing diagram; rise and fall times

refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . .76

Fig 42. Application diagram for PCF85363A . . . . . . . . . .77

Fig 43. Package outline SOT1197-1 (DFN2626-10),

PCF85363ATL . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Fig 44. Package outline SOT505-1 (TSSOP8),

PCF85363ATT . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Fig 45. Package outline SOT552-1 (TSSOP10),

PCF85363ATT1 . . . . . . . . . . . . . . . . . . . . . . . . . .80

Fig 46. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Fig 47. Footprint information for reflow soldering of

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

93 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

31. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

8.7.1

8.8

Timestamps interrupts . . . . . . . . . . . . . . . . . . 32

Offset register . . . . . . . . . . . . . . . . . . . . . . . . 33

Correction when OFFM = 0 . . . . . . . . . . . . . . 34

Correction when OFFM = 1 . . . . . . . . . . . . . . 34

Offset calibration workflow. . . . . . . . . . . . . . . 36

Offset interrupts . . . . . . . . . . . . . . . . . . . . . . . 37

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

ILPA/ILPB: interrupt level or pulse mode . . . . 38

Interrupt enable bits . . . . . . . . . . . . . . . . . . . . 39

Oscillator register. . . . . . . . . . . . . . . . . . . . . . 41

CLKIV: invert the clock output . . . . . . . . . . . . 41

OFFM: offset calibration mode. . . . . . . . . . . . 41

12_24: 12 hour or 24 hour clock . . . . . . . . . . 41

LOWJ: low jitter mode . . . . . . . . . . . . . . . . . . 41

OSCD[1:0]: quartz oscillator drive control . . . 42

CL[1:0]: quartz oscillator load capacitance . . 42

Battery switch register . . . . . . . . . . . . . . . . . . 43

BSOFF: battery switch on/off control . . . . . . . 43

BSRR: battery switch internal refresh rate. . . 44

BSM[1:0]: battery switch mode . . . . . . . . . . . 44

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

8.8.1

8.8.2

8.8.3

8.8.4

8.9

8.9.1

8.9.2

8.10

8.10.1

8.10.2

8.10.3

8.10.4

8.10.5

8.10.6

8.11

8.11.1

8.11.2

8.11.3

3

4

4.1

5

6

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8

8.1

Functional description . . . . . . . . . . . . . . . . . . . 6

Registers organization overview. . . . . . . . . . . . 7

Time mode registers. . . . . . . . . . . . . . . . . . . . . 7

RTC mode time registers overview (RTCM = 0) 8

Stop-watch mode time registers (RTCM = 1) . 10

Control registers overview . . . . . . . . . . . . . . . 12

RTC mode time and date registers. . . . . . . . . 13

Definition of BCD . . . . . . . . . . . . . . . . . . . . . . 13

OS: Oscillator stop . . . . . . . . . . . . . . . . . . . . . 14

EMON: event monitor . . . . . . . . . . . . . . . . . . . 14

Definition of weekdays . . . . . . . . . . . . . . . . . . 15

Definition of months . . . . . . . . . . . . . . . . . . . . 15

Setting and reading the time in RTC mode. . . 16

Stop-watch mode time registers . . . . . . . . . . . 17

Setting and reading the time in stop-watch

mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Alarms in RTC mode . . . . . . . . . . . . . . . . . . . 18

Alarm1 and alarm2 registers in RTC mode . . 18

Alarm1 and alarm2 control in RTC mode . . . . 19

Alarm1 and alarm2 function in RTC mode . . . 20

Alarms in stop-watch mode . . . . . . . . . . . . . . 21

Alarm1 and alarm2 registers in stop-watch

8.1.1

8.1.1.1

8.1.1.2

8.1.2

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.3

8.11.3.1 Switching at the V_thlevel, BSM[1:0] = 00. . . . 45

8.11.3.2 Switching at the V_BATlevel, BSM[1:0] = 01 . . 46

8.11.3.3 Switching at the higher of V_BATor V_thlevel,

BSM[1:0] = 10 . . . . . . . . . . . . . . . . . . . . . . . . 47

8.11.3.4 Switching at the lower of V_BATand V_thlevel,

BSM[1:0] = 11 . . . . . . . . . . . . . . . . . . . . . . . . 48

8.11.4

8.11.5

8.12

8.12.1

8.12.2

8.12.3

8.12.4

8.12.4.1 TS pin output mode; INTB . . . . . . . . . . . . . . . 50

8.12.4.2 TS pin output mode; CLK. . . . . . . . . . . . . . . . 51

8.12.4.3 TS pin disabled . . . . . . . . . . . . . . . . . . . . . . . 51

8.12.5

8.12.5.1 TS pin input mode . . . . . . . . . . . . . . . . . . . . . 51

8.12.6 INTAPM[1:0]: INTA pin mode control . . . . . . . 51

8.3.1

BSTH: threshold voltage control . . . . . . . . . . 48

Battery switch interrupts . . . . . . . . . . . . . . . . 48

Pin_IO register. . . . . . . . . . . . . . . . . . . . . . . . 49

CLKPM: CLK pin mode control . . . . . . . . . . . 49

TSPULL: TS pin pull-up resistor value. . . . . . 49

TSL: TS pin level sense. . . . . . . . . . . . . . . . . 50

TSPM[1:0]: TS pin I/O control . . . . . . . . . . . . 50

8.4

8.4.1

8.4.1.1

8.4.1.2

8.4.1.3

8.4.2

8.4.2.1

mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Alarm1 and alarm2 control in stop-watch

mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Alarm1 and alarm2 function in stop-watch

8.4.2.2

8.4.2.3

TSIM: TS pin input type control . . . . . . . . . . . 51

mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 24

WatchDog. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

WatchDog functions . . . . . . . . . . . . . . . . . . . . 25

WatchDog repeat mode . . . . . . . . . . . . . . . . . 26

WatchDog single shot mode. . . . . . . . . . . . . . 26

WatchDog interrupts . . . . . . . . . . . . . . . . . . . 27

Single RAM byte. . . . . . . . . . . . . . . . . . . . . . . 27

Timestamps . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.12.6.1 INTAPM[1:0]: INTA. . . . . . . . . . . . . . . . . . . . . 52

8.12.6.2 INTAPM[1:0]: clock data. . . . . . . . . . . . . . . . . 52

8.12.6.3 INTAPM[1:0]: battery mode indication . . . . . . 52

8.4.3

8.5

8.5.1

8.5.1.1

8.5.1.2

8.5.1.3

8.6

8.13

Function register . . . . . . . . . . . . . . . . . . . . . . 53

100TH: 100th seconds mode. . . . . . . . . . . . . 53

PI[1:0]: Periodic interrupt . . . . . . . . . . . . . . . . 53

RTCM: RTC mode . . . . . . . . . . . . . . . . . . . . . 54

STOPM: STOP mode control. . . . . . . . . . . . . 54

COF[2:0]: Clock output frequency . . . . . . . . . 55

8.13.1

8.13.2

8.13.3

8.13.4

8.13.5

8.7

continued >>

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 18 November 2015

94 of 95

PCF85363A

NXP Semiconductors

Tiny RTC with 64 byte RAM, alarm, battery switch-over and I²C-bus

8.14

Flags register . . . . . . . . . . . . . . . . . . . . . . . . . 56

31

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.15

Reset register . . . . . . . . . . . . . . . . . . . . . . . . . 57

SR - Software reset . . . . . . . . . . . . . . . . . . . . 57

CPR: clear prescaler . . . . . . . . . . . . . . . . . . . 59

CTS: clear timestamp . . . . . . . . . . . . . . . . . . 59

Stop_enable register. . . . . . . . . . . . . . . . . . . . 59

64 byte RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.15.1

8.15.2

8.15.3

8.16

8.17

9

I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 62

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

START and STOP conditions . . . . . . . . . . . . . 63

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 63

9.1

9.2

9.3

10

Interface protocol . . . . . . . . . . . . . . . . . . . . . . 64

Write protocol . . . . . . . . . . . . . . . . . . . . . . . . . 64

Read protocol . . . . . . . . . . . . . . . . . . . . . . . . . 64

Slave addressing . . . . . . . . . . . . . . . . . . . . . . 65

Slave address. . . . . . . . . . . . . . . . . . . . . . . . . 65

10.1

10.2

10.3

10.3.1

11

Application design-in information . . . . . . . . . 66

Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 68

Safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 69

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 70

Application information. . . . . . . . . . . . . . . . . . 77

Test information. . . . . . . . . . . . . . . . . . . . . . . . 77

Quality information . . . . . . . . . . . . . . . . . . . . . 77

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 78

Handling information. . . . . . . . . . . . . . . . . . . . 81

Packing information . . . . . . . . . . . . . . . . . . . . 81

12

13

14

15

16

17

17.1

18

19

20

21

Soldering of SMD packages . . . . . . . . . . . . . . 81

Introduction to soldering . . . . . . . . . . . . . . . . . 81

Wave and reflow soldering . . . . . . . . . . . . . . . 81

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 82

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 82

21.1

21.2

21.3

21.4

22

Footprint information . . . . . . . . . . . . . . . . . . . 83

Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Real-Time Clock selection . . . . . . . . . . . . . . . 86

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 88

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 89

23

23.1

24

25

26

27

Legal information. . . . . . . . . . . . . . . . . . . . . . . 90

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 90

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 91

27.1

27.2

27.3

27.4

28

29

30

Contact information. . . . . . . . . . . . . . . . . . . . . 91

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 November 2015

Document identifier: PCF85363A


型号：	PCF85363ATL/AX
厂家：	NXP
描述：	PCF85363A - Tiny real-time clock/calendar DFN 10-Pin PC 光电二极管外围集成电路
文件：	总95页 (文件大小：820K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCF85363ATL/AX [NXP]

相关型号：

PCF85363ATT/A

PCF85363ATT/AJ

PCF85363ATT1/A

PCF85363ATT1/AJ

PCF85363ATT1/AZ

PCF85363B

PCF8536AT

PCF8536AT/1

PCF8536AT/1,118

PCF8536AT1

PCF8536BT

PCF8536BT/1,118