PCF8566T [NXP]
Universal LCD driver for low multiplex rates; 低复用率的通用LCD驱动器
| 型号： | PCF8566T |
| 厂家： | 
NXP |
| 描述： | Universal LCD driver for low multiplex rates |
| 文件： | 总40页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCF8566
Universal LCD driver for low
multiplex rates
1998 May 04
Product specification
Supersedes data of 1997 Apr 02
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
CONTENTS
8
LIMITING VALUES
HANDLING
9
1
2
3
4
5
6
FEATURES
10
11
12
13
DC CHARACTERISTICS
AC CHARACTERISTICS
APPLICATION INFORMATION
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
CHIP DIMENSIONS AND BONDING PAD
LOCATIONS
PINNING
FUNCTIONAL DESCRIPTION
14
15
PACKAGE OUTLINES
SOLDERING
6.1
6.2
6.3
6.4
Power-on reset
LCD bias generator
LCD voltage selector
LCD drive mode waveforms
Oscillator
15.1
15.2
15.2.1
15.2.2
15.3
Introduction
DIP
Soldering by dipping or by wave
Repairing soldered joints
SO and VSO
6.5
6.6
Internal clock
6.7
External clock
15.3.1
15.3.2
15.3.3
Reflow soldering
Wave soldering
Repairing soldered joints
6.8
6.9
Timing
Display latch
Shift register
Segment outputs
Backplane outputs
Display RAM
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
16
17
18
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
Data pointer
Subaddress counter
Output bank selector
Input bank selector
Blinker
7
I2C-BUS DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Bit transfer
Start and stop conditions
System configuration
Acknowledge
PCF8566 I2C-bus controller
Input filters
I2C-bus protocol
Command decoder
Display controller
Cascaded operation
1998 May 04
2
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
1
FEATURES
• Single-chip LCD controller/driver
• Selectable backplane drive configuration: static
or 2, 3 or 4 backplane multiplexing
• Selectable display bias configuration: static, 1⁄2 or 1⁄3
• Internal LCD bias generation with voltage-follower
buffers
2
GENERAL DESCRIPTION
The PCF8566 is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) having low
multiplex rates. It generates the drive signals for any static
or multiplexed LCD containing up to four backplanes and
up to 24 segments and can easily be cascaded for larger
LCD applications. The PCF8566 is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I2C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
• 24 segment drives: up to twelve 8-segment numeric
characters; up to six 15-segment alphanumeric
characters; or any graphics of up to 96 elements
• 24 × 4-bit RAM for display data storage
• Auto-incremented display data loading across device
subaddress boundaries
• Display memory bank switching in static and duplex
drive modes
• Versatile blinking modes
• LCD and logic supplies may be separated
• 2.5 to 6 V power supply range
• Low power consumption
• Power saving mode for extremely low power
consumption in battery-operated and telephone
applications
• I2C-bus interface
• TTL/CMOS compatible
• Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers
• May be cascaded for large LCD applications
(up to 1536 segments possible)
• Cascadable with the 40 segment LCD driver PCF8576C
• Optimized pinning for single plane wiring in both single
and multiple PCF8566 applications
• Space-saving 40 lead plastic very small outline package
(VSO40; SOT158-1)
• No external components required (even in multiple
device applications)
• Manufactured in silicon gate CMOS process.
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
plastic dual in-line package; 40 leads (600 mil)
VERSION
SOT129-1
SOT158-1
PCF8566P
PCF8566T
DIP40
VSO40 plastic very small outline package; 40 leads
1998 May 04
3
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
g
BP0 BP2 BP1 BP3
13 14 15 16
S0 to S23
17 to 40
5
V
BACKPLANE
OUTPUTS
DD
DISPLAY SEGMENT OUTPUTS
R
R
R
LCD
VOLTAGE
SELECTOR
DISPLAY LATCH
LCD BIAS
GENERATOR
SHIFT REGISTER
12
V
LCD
CLK
PCF8566
4
3
DISPLAY
RAM
INPUT
BANK
OUTPUT
BANK
TIMING
BLINKER
SYNC
24 × 4 BITS
SELECTOR
SELECTOR
DISPLAY
CONTROLLER
6
OSC
OSCILLATOR
POWER-
ON
DATA
POINTER
RESET
COMMAND
DECODER
11
V
SS
2
1
SUB-
ADDRESS
COUNTER
SCL
SDA
2
INPUT
FILTERS
I C-BUS
CONTROLLER
10
7
8
9
SA0
A0 A1 A2
MGG383
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
5
PINNING
SYMBOL
PIN
DESCRIPTION
handbook, halfpage
SDA
SCL
1
2
3
I2C-bus data input/output
I2C-bus clock input/output
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SDA
SCL
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
SYNC
cascade synchronization
input/output
3
SYNC
CLK
4
CLK
VDD
OSC
A0
4
5
external clock input/output
positive supply voltage
oscillator input
V
5
DD
6
6
OSC
A0
7
7
A1
8
I2C-bus subaddress inputs
8
A1
A2
9
9
A2
SA0
VSS
VLCD
BP0
BP2
BP1
BP3
10
11
12
13
14
15
16
I2C-bus slave address bit 0 input
logic ground
10
11
12
13
14
15
16
17
18
19
20
SA0
V
PCF8566
SS
LCD supply voltage
V
LCD
BP0
BP2
BP1
BP3
S0
LCD backplane outputs
S0 to S23 17 to 40 LCD segment outputs
S8
S7
S1
S6
S2
S5
S3
S4
MGG382
Fig.2 Pin configuration.
1998 May 04
5
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
All of the display configurations given in Table 1 can be
implemented in the typical system shown in Fig.3.
The host microprocessor/microcontroller maintains the
two-line I2C-bus communication channel with the
PCF8566. The internal oscillator is selected by tying OSC
(pin 6) to VSS. The appropriate biasing voltages for the
multiplexed LCD waveforms are generated internally.
The only other connections required to complete the
system are to the power supplies (VDD, VSS and VLCD) and
to the LCD panel chosen for the application.
6
FUNCTIONAL DESCRIPTION
The PCF8566 is a versatile peripheral device designed to
interface any microprocessor to a wide variety of LCDs.
It can directly drive any static or multiplexed LCD
containing up to 4 backplanes and up to 24 segments.
The display configurations possible with the PCF8566
depend on the number of active backplane outputs
required; a selection of display configurations is given in
Table 1.
Table 1 Selection of display configurations
ACTIVE
BACKPLANE
OUTPUTS
NUMBER OF
SEGMENTS
14-SEGMENT
DOT MATRIX
7-SEGMENT NUMERIC
ALPHANUMERIC
4
3
2
1
96
12 digits + 12 indicator
symbols
6 characters + 12 indicator
symbols
96 dots (4 × 24)
72 dots (3 × 24)
48 dots (2 × 24)
24 dots
72
48
24
9 digits + 9 indicator
symbols
4 characters + 16 indicator
symbols
6 digits + 6 indicator
symbols
3 characters + 6 indicator
symbols
3 digits + 3 indicator
symbols
1 character + 10 indicator
symbols
V
DD
t
rise
R ≤
2 C
bus
V
V
DD
LCD
5
12
SDA
1
HOST
MICRO-
PROCESSOR/
MICRO-
17 to 40 24 segment drives
LCD PANEL
SCL
PCF8566
2
6
(up to 96
elements)
OSC
CONTROLLER
4 backplanes
13 to 16
7
8
9
10 11
MGG385
A0 A1 A2 SA0 V
SS
V
SS
Fig.3 Typical system configuration.
1998 May 04
6
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
6.1
Power-on reset
6.3
LCD voltage selector
At power-on the PCF8566 resets to a defined starting
condition as follows:
The LCD voltage selector coordinates the multiplexing of
the LCD according to the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of Vop = VDD − VLCD and the
resulting discrimination ratios (D), are given in Table 2.
1. All backplane outputs are set to VDD
2. All segment outputs are set to VDD
3. The drive mode ‘1 : 4 multiplex with 1⁄3bias’ is selected
4. Blinking is switched off
5. Input and output bank selectors are reset (as defined
in Table 5)
6. The I2C-bus interface is initialized
A practical value of Vop is determined by equating Voff(rms)
with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is Vop ≥ 3 Vth. Multiplex drive
ratios of 1 : 3 and 1 : 4 with 1⁄2 bias are possible but the
discrimination and hence the contrast ratios are smaller
7. The data pointer and the subaddress counter are
cleared.
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on to allow completion of the reset action.
( 3 = 1.732 for 1 : 3 multiplex or 21 ⁄ 3 = 1.528 for
1 : 4 multiplex). The advantage of these modes is a
reduction of the LCD full scale voltage Vop as follows:
6.2
The full-scale LCD voltage (Vop) is obtained from
DD − VLCD. The LCD voltage may be temperature
LCD bias generator
1 : 3 multiplex (1⁄2bias):
V
compensated externally through the VLCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an
internal voltage divider of three series resistors connected
between VDD and VLCD. The centre resistor can be
switched out of circuit to provide a 1⁄2bias voltage level for
the 1 : 2 multiplex configuration.
Vop
=
6Vop(mrs) = 2.449Voff (rms)
1 : 4 multiplex (1⁄2bias):
4
Vop
=
3 ⁄ 3Voff (rms) = 2.309Voff (rms)
These compare with Vop = 3 Voff(rms) when 1⁄3bias is used.
Table 2 Preferred LCD drive modes: summary of characteristics
Voff (rms)
V on (rms)
V on (rms)
LCD BIAS
CONFIGURATION
LCD DRIVE MODE
----------------------
Vop
D =
-----------------------
Vop
-----------------------
Voff (rms)
Static (1 BP)
static (2 levels)
0
1
∞
1 : 2 MUX (2 BP)
1⁄2 (3 levels)
10 ⁄ 4 = 0.791
2 ⁄ 4 = 0.354
1⁄3 = 0.333
5 = 2.236
5 = 2.236
1 : 2 MUX (2 BP)
1 : 3 MUX (3 BP)
1 : 4 MUX (4 BP)
1⁄3 (4 levels)
1⁄3 (4 levels)
1⁄3 (4 levels)
5 ⁄ 3 = 0.745
1⁄3 = 0.333
1⁄3 = 0.333
33 ⁄ 9 = 0.638
3 ⁄ 3 = 0.577
33 ⁄ 3 = 1.915
3 = 1.732
1998 May 04
7
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
6.4
LCD drive mode waveforms
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive
waveforms for this mode are shown in Fig.4.
When two backplanes are provided in the LCD the 1 : 2 multiplex drive mode applies. The PCF8566 allows use of
1⁄2 or 1⁄3 bias in this mode as shown in Figs 5 and 6.
The backplane and segment drive waveforms for the 1 : 3 multiplex drive mode (three LCD backplanes) and for the 1 : 4
multiplex drive mode (four LCD backplanes) are shown in Figs 7 and 8 respectively.
T
frame
LCD segments
V
DD
BP0
V
V
LCD
DD
state 1
(on)
state 2
(off)
S
n
V
V
LCD
DD
S
n + 1
V
V
LCD
(a) waveforms at driver
op
0
state 1
At any instant (t):
V
(t) = V (t) − V
(t)
BP0
state 1
S
n
V
= V
on(rms)
op
−V
op
V
op
0
V
V
(t) = V
(t) − V
(t)
BP0
state 2
S
n + 1
= 0 V
off(rms)
state 2
−V
op
(b) resultant waveforms
at LCD segment
MGG392
Fig.4 Static drive mode waveforms: Vop = VDD − VLCD
.
1998 May 04
8
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
T
frame
V
LCD segments
DD
DD
(V
V
+ V
)/2
)/2
BP0
BP1
LCD
LCD
DD
state 1
V
(V
V
state 2
+ V
DD
LCD
LCD
V
DD
S
n
V
V
LCD
DD
S
n + 1
V
LCD
op
(a) waveforms at driver
V
V
At any instant (t):
/2
op
V
V
(t) = V (t) − V
(t)
BP0
state 1
S
n
V
op
state 1
0
=
√10 = 0.791V
op
on(rms)
4
−V /2
op
−V
V
V
(t) = V (t) − V
(t)
BP1
op
state 2
S
n
V
op
=
√2 = 0.354V
op
off(rms)
V
op
4
V
/2
op
state 2
0
−V /2
op
−V
op
(b) resultant waveforms
at LCD segment
MGG394
Fig.5 Waveforms for 1 : 2 multiplex drive mode with 1⁄2 bias: Vop = VDD − VLCD
.
1998 May 04
9
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
T
frame
h
V
DD
LCD segments
V
− V /3
DD
op
BP0
BP1
V
− 2V /3
DD
op
V
V
LCD
state 1
DD
DD
DD
state 2
V
− V /3
op
V
− 2V /3
op
V
LCD
V
DD
DD
DD
V
V
V
− V /3
op
S
n
− 2V /3
op
LCD
V
DD
DD
V
V
− V /3
op
S
n + 1
− 2V /3
DD
op
V
LCD
(a) waveforms at driver
V
op
2V /3
op
/3
0
V
op
state 1
At any instant (t):
−V /3
op
V
V
(t) = V (t) − V
(t)
BP0
state 1
S
n
−2V /3
op
V
op
=
√5 = 0.745V
−V
on(rms)
op
op
3
V
op
V
V
(t) = V (t) − V
(t)
2V /3
state 2
S
n
BP1
op
V
V
/3
op
op
=
= 0.333V
op
off(rms)
state 2
0
3
−V /3
op
−2V /3
op
−V
op
(b) resultant waveforms
at LCD segment
MGG393
Fig.6 Waveforms for 1 : 2 multiplex drive mode with 1⁄3 bias: Vop = VDD − VLCD
.
1998 May 04
10
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
T
frame
V
LCD segments
DD
V
V
V
− V /3
DD
DD
op
BP0
BP1
BP2
− 2V /3
op
LCD
state 1
state 2
V
V
V
V
DD
− V /3
DD
DD
LCD
op
− 2V /3
op
V
V
V
V
DD
− V /3
DD
DD
LCD
op
− 2V /3
op
V
V
V
V
DD
− V /3
DD
DD
LCD
op
S
n
− 2V /3
op
V
DD
V
V
V
− V /3
op
DD
DD
S
n + 1
n + 2
− 2V /3
op
LCD
V
DD
V
V
V
− V /3
op
DD
DD
LCD
S
− 2V /3
op
(a) waveforms at driver
V
op
2V /3
op
/3
0
V
op
state 1
At any instant (t):
−V /3
op
V
V
(t) = V (t) − V
(t)
state 1
S
BP0
n
−2V /3
op
V
op
−V
=
√33 = 0.638V
op
op
on(rms)
9
V
op
V
V
(t) = V (t) − V
(t)
BP1
2V /3
state 2
S
n
op
V
V
/3
op
op
=
= 0.333V
op
off(rms)
state 2
0
3
−V /3
op
−2V /3
op
−V
op
(b) resultant waveforms
at LCD segment
MGG395
Fig.7 Waveforms for 1 : 3 multiplex drive mode: Vop = VDD − VLCD
.
1998 May 04
11
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
T
frame
LCD segments
V
V
V
V
DD
DD
DD
− V /3
op
BP0
− 2V /3
op
LCD
state 1
state 2
V
V
V
V
DD
− V /3
DD
DD
LCD
op
BP1
BP2
BP3
− 2V /3
op
V
V
V
V
DD
− V /3
DD
DD
LCD
op
− 2V /3
op
V
DD
V
V
V
− V /3
op
DD
DD
LCD
− 2V /3
op
V
V
V
V
DD
− V /3
DD
DD
LCD
op
S
n
− 2V /3
op
V
DD
V
V
V
− V /3
op
DD
DD
S
n + 1
− 2V /3
op
LCD
V
DD
V
V
V
− V /3
op
DD
DD
Sn + 2
− 2V /3
op
LCD
V
V
V
V
DD
− V /3
DD
DD
LCD
op
S
n + 3
− 2V /3
op
(a) waveforms at driver
V
op
2V /3
op
V
/3
op
0
state 1
At any instant (t):
−V /3
op
−2V /3
V
V
(t) = V (t) − V
(t)
BP0
op
state 1
S
n
V
−V
op
op
=
√3 = 0.577V
on(rms)
op
3
V
op
2V /3
op
V
V
(t) = V (t) − V
(t)
state 2
S
BP1
n
V
/3
op
0
V
op
=
= 0.333V
off(rms)
op
state 2
3
−V /3
op
−2V /3
op
−V
op
(b) resultant waveforms
at LCD segment
MGG396
Fig.8 Waveforms for 1 : 4 multiplex drive mode: Vop = VDD − VLCD.
1998 May 04
12
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
The lower clock frequency has the disadvantage of
6.5
Oscillator
increasing the response time when large amounts of
display data are transmitted on the I2C-bus. When a
device is unable to ‘digest’ a display data byte before the
next one arrives, it holds the SCL line LOW until the first
display data byte is stored. This slows down the
The internal logic and the LCD drive signals of the
PCF8566 or PCF8576 are timed either by the built-in
oscillator or from an external clock.
The clock frequency (fCLK) determines the LCD frame
frequency and the maximum rate for data reception from
the I2C-bus. To allow I2C-bus transmissions at their
maximum data rate of 100 kHz, fCLK should be chosen to
be above 125 kHz.
transmission rate of the I2C-bus but no data loss occurs.
6.9
Display latch
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.6
Internal clock
When the internal oscillator is used, OSC (pin 6) should be
tied to VSS. In this case, the output from CLK (pin 4)
provides the clock signal for cascaded PCF8566s and
PCF8576s in the system.
6.10 Shift register
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data are displayed.
6.7
External clock
6.11 Segment outputs
The condition for external clock is made by tying OSC
(pin 6) to VDD; CLK (pin 4) then becomes the external
clock input.
The LCD drive section includes 24 segment outputs
S0 to S23 (pins 17 to 40) which should be connected
directly to the LCD. The segment output signals are
generated in accordance with the multiplexed backplane
signals and with the data resident in the display latch.
When less than 24 segment outputs are required the
unused segment outputs should be left open-circuit.
6.8
Timing
The timing of the PCF8566 organizes the internal data flow
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal
SYNC maintains the correct timing relationship between
the PCF8566s in the system. The timing also generates
the LCD frame frequency which it derives as an integer
multiple of the clock frequency (Table 3). The frame
frequency is set by MODE SET commands when internal
clock is used, or by the frequency applied to pin 4 when
external clock is used.
6.12 Backplane outputs
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open. In the 1 : 3 multiplex drive mode BP3
carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode
BP0 and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
Table 3 LCD frame frequencies
NOMINAL
fframe (Hz)
PCF8566 MODE
fframe
Normal mode
fCLK/2880
64
64
Power saving mode
fCLK/480
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.
6.13 Display RAM
The display RAM is a static 24 × 4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the ‘on’
state of the corresponding LCD segment; similarly, a
logic 0 indicates the ‘off’ state.
1998 May 04
13
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
There is a one-to-one correspondence between the RAM
addresses and the segment outputs, and between the
individual bits of a RAM word and the backplane outputs.
The first RAM column corresponds to the 24 segments
operated with respect to backplane BP0 (see Fig.9).
In multiplexed LCD applications the segment data of the
second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.
The sequence commences with the initialization of the
data pointer by the LOAD DATA POINTER command.
Following this, an arriving data byte is stored starting at the
display RAM address indicated by the data pointer thereby
observing the filling order shown in Fig.10. The data
pointer is automatically incremented according to the LCD
configuration chosen. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1 : 2 multiplex drive mode), by
three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex
drive mode).
When display data are transmitted to the PCF8566 the
display bytes received are stored in the display RAM
according to the selected LCD drive mode. To illustrate the
filling order, an example of a 7-segment numeric display
showing all drive modes is given in Fig.10; the RAM filling
organization depicted applies equally to other LCD types.
6.15 Subaddress counter
The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to
A0, A1 and A2 (pins 7, 8, and 9). A0, A1 and A2 should
be tied to VSS or VDD. The subaddress counter value is
defined by the DEVICE SELECT command. If the contents
of the subaddress counter and the hardware subaddress
do not agree then data storage is inhibited but the data
pointer is incremented as if data storage had taken place.
The subaddress counter is also incremented when the
data pointer overflows.
With reference to Fig.10, in the static drive mode the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses. In the 1 : 2 multiplex drive mode
the eight transmitted data bits are placed in bits 0 and 1 of
four successive display RAM addresses. In the 1 : 3
multiplex drive mode these bits are placed in
bits 0, 1 and 2 of three successive addresses, with bit 2 of
the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding
adjacent data because full bytes are always transmitted.
In the 1 : 4 multiplex drive mode the eight transmitted data
bits are placed in bits 0, 1, 2 and 3 of two successive
display RAM addresses.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are being sent to the display RAM,
automatic wrap-over to the next PCF8566 occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character.
6.14 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM.
display RAM addresses (rows)/segment outputs (S)
0
1
2
3
4
19 20 21 22 23
0
1
2
3
display RAM bits
(columns) /
backplane outputs
(BP)
MGG389
Fig.9 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,
and between bits in a RAM word and backplane outputs.
1998 May 04
14
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
a
S
2
n
n
1
n
2
n
3
n
4
n
5
n
6
n 7
n
n
b
BP0
f
S
1
7
S
3
MSB
LSB
DP
n
n
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP
bit/
BP
g
4
S
S
S
n
n
x
x
x
x
x
x
c
b
a
f
g e d
static
e
S
5
6
c
n
d
DP
S
n
BP0
S
n
a
n
n
n
n
1
1
1
n
2
n 3
b
b
b
1 : 2
f
S
1
n
MSB
LSB
DP
0
1
2
3
a
b
x
x
f
e
c
x
x
d
bit/
BP
g
g
x
x
DP
x
x
a
b
f
g
e c d
BP1
S
S
e
2
3
multiplex
n
n
c
c
c
d
d
d
DP
BP0
BP1
S
1
a
n
n
n 2
S
S
2
f
1 : 3
n
n
MSB
LSB
e
0
1
2
3
b
DP
c
a
d
g
x
f
bit/
BP
g
e
x
x
BP2
b DP
c
a
d
g
f
e
multiplex
x
DP
S
n
a
n
BP2
BP3
BP0
BP1
f
1 : 4
0
1
2
3
a
c
f
bit/
BP
MSB
LSB
d
g
e
g
d
b
DP
e
multiplex
a
c
b
DP
f
e
g
S
1
DP
n
MBE534
Fig.10 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus (X = data bit
unchanged).
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
6.16 Output bank selector
6.18 Blinker
This selects one of the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence. In 1 : 4
multiplex, all RAM addresses of bit 0 are the first to be
selected, these are followed by the contents of bit 1, bit 2
and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2
are selected sequentially. In 1 : 2 multiplex, bits 0 then 1
are selected and, in the static mode, bit 0 is selected.
The display blinking capabilities of the PCF8566 are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, as shown in
Table 4.
An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and 1 : 2
LCD drive modes and can be implemented without any
communication overheads. By means of the output bank
selector, the displayed RAM banks are exchanged with
alternate RAM banks at the blinking frequency. This mode
can also be specified by the BLINK command.
The PCF8566 includes a RAM bank switching feature in
the static and 1 : 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
the contents of bit 2 to be selected for display instead of
bit 0 contents. In the 1 : 2 drive mode, the contents of
bits 2 and 3 may be selected instead of bits 0 and 1.
This gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it
is assembled.
In the 1 : 3 and 1 : 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.
If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bit E
at the required rate using the MODE SET command.
6.17 Input bank selector
The input bank selector loads display data into the display
RAM according to the selected LCD drive configuration.
Display data can be loaded in bit 2 in static drive mode or
in bits 2 and 3 in 1 : 2 drive mode by using the BANK
SELECT command. The input bank selector functions
independently of the output bank selector.
Table 4 Blinking frequencies
NORMAL OPERATING
MODE RATIO
POWER-SAVING
MODE RATIO
NOMINAL BLINKING FREQUENCY
BLINKING MODE
fblink (Hz)
Off
2 Hz
−
−
blinking off
fCLK/92160
fCLK/15360
fCLK/30720
fCLK/61440
2
1
1 Hz
f
f
CLK/184320
CLK/368640
0.5 Hz
0.5
1998 May 04
16
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
I2C-BUS DESCRIPTION
7.4
Acknowledge
7
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter whereas the master generates an extra
acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the
reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has
been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse, set up and hold times must be taken into
account. A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition.
7.1
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
7.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
7.3
System configuration
A device generating a message is a ‘transmitter’, a device
receiving a message is a ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBA607
Fig.11 Bit transfer.
1998 May 04
17
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
SDA
SDA
SCL
SCL
S
P
STOP condition
START condition
MBA608
Fig.12 Definition of START and STOP conditions.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
MBA605
Fig.13 System configuration.
clock pulse for
acknowledgement
START
condition
SCL FROM
MASTER
2
9
1
8
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
BY RECEIVER
MBA606 - 1
Fig.14 Acknowledgement on the I2C-bus.
18
1998 May 04
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
The I2C-bus protocol is shown in Fig.15. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of the two PCF8566 slave
addresses available. All PCF8566s with the corresponding
SA0 level acknowledge in parallel the slave address but all
PCF8566s with the alternative SA0 level ignore the whole
I2C-bus transfer. After acknowledgement, one or more
command bytes (m) follow which define the status of the
addressed PCF8566s. The last command byte is tagged
with a cleared most-significant bit, the continuation bit C.
The command bytes are also acknowledged by all
addressed PCF8566s on the bus.
7.5
PCF8566 I2C-bus controller
The PCF8566 acts as an I2C-bus slave receiver. It does
not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8566
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress
inputs A0, A1 and A2 are normally left open-circuit or tied
to VSS which defines the hardware subaddress 0.
In multiple device applications A0, A1 and A2 are left
open-circuit or tied to VSS or VDD according to a binary
coding scheme such that no two devices with a common
I2C-bus slave address have the same hardware
subaddress.
After the last command byte, a series of display data bytes
(n) may follow. These display data bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data are directed to the intended PCF8566 device.
The acknowledgement after each byte is made only by the
(A0, A1, A2) addressed PCF8566. After the last display
byte, the I2C-bus master issues a STOP condition (P).
In the power-saving mode it is possible that the PCF8566
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8566 forces the SCL line LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I2C-bus and
serves to slow down fast transmitters. Data loss does not
occur.
7.8
Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. All available commands carry a
continuation bit C in their most-significant bit position
(see Fig.16). When this bit is set, it indicates that the next
byte of the transfer to arrive will also represent a
command.
7.6
Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
If the bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.
7.7
I2C-bus protocol
The five commands available to the PCF8566 are defined
in Table 5.
Two I2C-bus slave addresses (0111110 and 0111111) are
reserved for PCF8566. The least-significant bit of the slave
address that a PCF8566 will respond to is defined by the
level tied at its input SA0 (pin 10). Therefore, two types of
PCF8566 can be distinguished on the same I2C-bus which
allows:
1. Up to 16 PCF8566s on the same I2C-bus for very large
LCD applications
2. The use of two types of LCD multiplex on the same
I2C-bus.
1998 May 04
19
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
acknowledge
by A0, A1 and A2
selected
acknowledge by
all addressed
PCF8566s
R / W
PCF8566 only
slave address
S
A
0
0
1
1
1
1
1
0
A C
A
DISPLAY DATA
A
P
COMMAND
S
1 byte
m ≥1 byte(s)
n ≥ 0 byte(s)
update data pointers
and if necessary,
subaddress counter
MGG390
Fig.15 I2C-bus protocol.
0 = last command
1 = commands continue
MSB
LSB
C
REST OF OPCODE
MGG388
Fig.16 General format of command byte.
1998 May 04
20
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
Table 5 Definition of PCF8566 commands
COMMAND/OPCODE
OPTIONS
DESCRIPTION
Mode set
C
1
0
LP
E
B
M1 M0
see Table 6
see Table 7
see Table 8
defines LCD drive mode
defines LCD bias configuration
defines display status; the possibility to disable
the display allows implementation of blinking
under external control
see Table 9
defines power dissipation mode
Load data pointer
P4 P3 P2 P1 P0
C
0
0
see Table 10
five bits of immediate data, bits P4 to P0, are
transferred to the data pointer to define one of
twenty-four display RAM addresses
Device select
C
1
1
0
1
0
1
A2 A1 A0
see Table 11
three bits of immediate data, bits A0 to A2, are
transferred to the subaddress counter to define
one of eight hardware subaddresses
Bank select
C
1
1
0
I
O
see Table 12
see Table 13
defines input bank selection (storage of arriving
display data)
defines output bank selection (retrieval of LCD
display data)
the BANK SELECT command has no effect in
1 : 3 and 1 : 4 multiplex drive modes
Blink
C
1
1
1
0
A
BF1 BF0
see Table 14
see Table 15
defines the blinking frequency
selects the blinking mode; normal operation
with frequency set by bits BF1 and BF0, or
blinking by alternation of display RAM banks.
Alternation blinking does not apply in 1 : 3 and
1 : 4 multiplex drive modes
Table 6 LCD drive mode
LCD DRIVE MODE
BIT M1
BIT M0
Static (1 BP)
0
1
1
0
1
0
1
0
1 : 2 MUX (2 BP)
1 : 3 MUX (3 BP)
1 : 4 MUX (4 BP)
1998 May 04
21
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
Table 7 LCD bias configuration
Table 15 Blink mode selection
LCD BIAS
BIT B
BLINK MODE
BIT A
1⁄3bias
1⁄2bias
0
1
Normal blinking
0
1
Alternation blinking
Table 8 Display status
7.9
Display controller
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8566 and coordinates their effects.
DISPLAY STATUS
Disabled (blank)
Enabled
BIT E
0
1
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
Table 9 Power dissipation mode
MODE
BIT LP
7.10 Cascaded operation
Normal mode
0
1
In large display configurations, up to 16 PCF8566s can be
distinguished on the same I2C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
Power-saving mode
programmable I2C-bus slave address (SA0). It is also
possible to cascade up to 16 PCF8566s. When cascaded,
several PCF8566s are synchronized so that they can
share the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the outputs of only one device
need to be through-plated to the backplane electrodes of
the display. The other PCF8566s of the cascade
contribute additional segment outputs but their backplane
outputs are left open-circuit (Fig.17).
Table 10 Load data pointer
BITS
P4
P3
P2
P1
P0
A2
5-bit binary value of 0 to 23
Table 11 Device select
BITS
A0
A1
3-bit binary value of 0 to 7
Table 12 Input bank selection
The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8566s.
This synchronization is guaranteed after the power-on
reset. The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when PCF8566s with differing SA0 levels
are cascaded). SYNC is organized as an input/output pin;
the output section being realized as an open-drain driver
with an internal pull-up resistor. A PCF8566 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times.
STATIC
RAM bit 0
RAM bit 2
1 : 2 MUX
BIT 1
RAM bits 0, 1
RAM bits 2, 3
0
1
Table 13 Output bank selection
STATIC
RAM bit 0
RAM bit 2
1 : 2 MUX
RAM bits 0, 1
RAM bits 2, 3
BIT 0
0
1
Should synchronization in the cascade be lost, it will be
restored by the first PCF8566 to assert SYNC. The timing
relationships between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8576
are shown in Fig.18. The waveforms are identical with the
parent device PCF8576. Cascade ability between
PCF8566s and PCF8576s is possible, giving cost effective
LCD applications.
Table 14 Blinking frequency
BLINK
FREQUENCY
BIT BF1
BIT BF0
Off
0
0
1
1
0
1
0
1
2 Hz
1 Hz
0.5 Hz
1998 May 04
22
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
V
V
LCD
DD
5
12
SDA
1
24 segment drives
SCL
17 to 40
PCF8566
2
LCD PANEL
SYNC
3
CLK
(up to 1536
elements)
4
13 to 16
OSC
6
BP0 to BP3
(open-circuit)
7
8
9
10 11
A0 A1 A2 SA0 V
SS
V
LCD
V
DD
t
rise
2 C
R ≤
V
V
LCD
bus
DD
5
12
SDA
SCL
HOST
MICRO-
1
2
3
4
6
24 segment drives
17 to 40
PCF8566
13 to 16
PROCESSOR/
MICRO-
CONTROLLER
SYNC
CLK
4 backplanes
BP0 to BP3
OSC
7
8
9
10 11
MGG384
A0 A1 A2 SA0
V
SS
V
SS
Fig.17 Cascaded PCF8566 configuration.
1998 May 04
23
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
1
T
= f
frame
frame
BP0
SYNC
(a) static drive mode.
BP1
(1/2 bias)
BP1
(1/3 bias)
SYNC
(b) 1 : 2 multiplex drive mode.
BP2
SYNC
(c) 1 : 3 multiplex drive mode.
BP3
SYNC
MBE535
(d) 1 : 4 multiplex drive mode.
Fig.18 Synchronization of the cascade for the various PCF8566 drive modes.
For single plane wiring of PCF8566s, see Chapter “Application information”.
1998 May 04
24
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
8
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
VDD
MIN.
−0.5
MAX.
UNIT
supply voltage
+7
V
V
V
V
VLCD
VI
LCD supply voltage
V
V
V
−
−
−
−
−
DD − 7
VDD
input voltage (SCL, SDA, A0 to A2, OSC, CLK, SYNC and SA0)
output voltage (S0 to S23 and BP0 to BP3)
DC input current
SS − 0.5
VDD + 0.5
VO
II
LCD − 0.5 VDD + 0.5
±20
±25
±50
400
100
mA
mA
mA
mW
mW
°C
IO
DC output current
IDD, ISS, ILCD VDD, VSS or VLCD current
Ptot
PO
Tstg
power dissipation per package
power dissipation per output
storage temperature
−65
+150
9
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
advised to take handling precautions appropriate to handling MOS devices (see “Handling MOS devices”).
1998 May 04
25
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
10 DC CHARACTERISTICS
VSS = 0 V; VDD = 2.5 to 6 V; VLCD = VDD − 2.5 to VDD − 6 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
VLCD
IDD
operating supply voltage
LCD supply voltage
2.5
−
−
6
V
VDD − 6
V
DD − 2.5 V
operating supply current
(normal mode)
fCLK = 200 kHz; note 1
−
30
90
µA
ILP
power saving mode supply current VDD = 3.5 V; VLCD = 0 V;
fCLK = 35 kHz; A0,
−
15
40
µA
A1 and A2 tied to VSS
note 1
;
Logic
VIL
LOW level input voltage
HIGH level input voltage
LOW level output voltage
HIGH level output voltage
VSS
0.7VDD
−
−
−
−
0.3VDD
VDD
0.05
−
V
VIH
V
VOL
VOH
IOL1
IO = 0 mA
V
IO = 0 mA
VDD − 0.05 −
V
LOW level output current
(CLK and SYNC)
VOL = 1 V; VDD = 5 V
1
−
−
mA
IOH
HIGH level output current (CLK)
VOH = 4 V; VDD = 5 V
−
−
−
−1
mA
mA
IOL2
LOW level output current
(SDA and SCL)
VOL = 0.4 V; VDD = 5 V
3
−
ILI
leakage current
(SA0, CLK, OSC, A0, A1, A2, SCL
and SDA)
VI = VSS or VDD
−
−
±1
µA
µA
Ipd
pull-down current
VI = 1 V; VDD = 5 V
15
50
150
(A0, A1, A2 and OSC)
RpuSYNC
Vref
pull-up resistor (SYNC)
power-on reset level
tolerable spike width on bus
input capacitance
15
−
25
1.3
−
60
2
kΩ
V
note 2
note 3
tsw
−
100
7
ns
pF
Ci
−
−
LCD outputs
VBP
DC voltage component
(BP0 to BP3)
DC voltage component (S0 to S23) CS = 5 nF
CBP = 35 nF
−
±20
−
mV
VS
−
−
−
±20
1
−
5
7
mV
kΩ
kΩ
ZBP
ZS
output impedance (BP0 to BP3)
output impedance (S0 to S23)
VLCD = VDD − 5 V; note 4
VLCD = VDD −5 V; note 4
3
Notes
1. Outputs open; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.
2. Resets all logic when VDD < Vref.
3. Periodically sampled, not 100% tested.
4. Outputs measured one at a time.
1998 May 04
26
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
11 AC CHARACTERISTICS
V
SS = 0 V; VDD = 2.5 to 6 V; VLCD = VDD − 2.5 to VDD − 6 V; Tamb = −40 to +85 °C; unless otherwise specified; note 1.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
oscillator frequency (normal mode) VDD = 5 V; note 2 125 200 315 kHz
fCLK
fCLKLP
oscillator frequency (power saving
mode)
VDD = 3.5 V
21
31
48
kHz
tCLKH
tCLKL
CLK HIGH time
1
1
−
1
−
−
−
−
−
−
−
µs
µs
ns
µs
µs
CLK LOW time
−
tPSYNC
tSYNCL
tPLCD
SYNC propagation delay
SYNC LOW time
400
−
driver delays with test loads
VLCD = VDD − 5 V
30
I2C-bus
tBUF
bus free time
4.7
4
−
−
−
−
−
−
−
−
−
−
µs
µs
µs
µs
µs
tHD; STA
tLOW
START condition hold time
SCL LOW time
4.7
4
tHIGH
SCL HIGH time
tSU; STA
START condition set-up time
(repeated start code only)
4.7
tHD; DAT
tSU; DAT
tr
data hold time
data set-up time
rise time
0
−
−
−
−
−
−
µs
ns
µs
ns
µs
250
−
−
1
tf
fall time
−
300
−
tSU; STO
STOP condition set-up time
4.7
Notes
1. All timing values referred to VIH and VIL levels with an input voltage swing of VSS to VDD
.
2. At fCLK < 125 kHz, I2C-bus maximum transmission speed is derated.
3.3 kΩ
1.5 kΩ
CLK
(pin 4)
SDA, SCL
(pins 1, 2)
0.5V
V
DD
DD
(2%)
(2%)
6.8 kΩ
SYNC
(pin 3)
V
DD
(2%)
BP0 to BP3
S0 to S23
(pins 13 to 16)
(pins 17 to 40)
I
≈ 25 µA
I
≈ 15 µA
load
load
MGG387
Fig.19 Test loads.
27
1998 May 04
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
1
f
CLK
t
t
CLKH
CLKL
0.7V
0.3V
DD
CLK
DD
0.7V
DD
SYNC
0.3V
DD
t
PSYNC
t
SYNCL
0.5 V
BP0 to BP3
S0 to S23
(V
= 5 V)
DD
0.5 V
t
MGG391
PLCD
Fig.20 Driver timing waveforms.
SDA
SCL
t
t
t
f
BUF
LOW
t
t
t
SU;DAT
t
HD;STA
r
t
HIGH
HD;DAT
SDA
t
SU;STA
MGA728
t
SU;STO
Fig.21 I2C-bus timing waveforms.
28
1998 May 04
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
MGG398
MGG397
24
40
handbook, halfpage
handbook, halfpage
I
DD
I
DD
(µA)
(µA)
−40 °C
−40 °C
30
16
+85 °C
+85 °C
20
8
10
0
0
0
0
2
4
6
8
2
4
6
8
V
(V)
V
(V)
DD
DD
a. Normal mode; VLCD = 0 V;
external clock = 200 kHz.
b. Low power mode; VLCD = 0 V;
external clock = 35 kHz.
Fig.22 Typical supply current characteristics.
MGG400
MGG399
6
12
handbook, halfpage
handbook, halfpage
R
R
S
BP
(kΩ)
(kΩ)
4
8
−40 °C
2
4
+25 °C
+85 °C
0
0
0
2
4
6
8
0
2
4
6
8
V
(V)
V
(V)
DD
DD
a. Backplane output impedance BP0 to BP3
(RBP); VDD = 5 V; Tamb = −40 to +85 °C.
b. Segment output impedance S0 to S23 (RS);
VDD = 5 V.
Fig.23 Typical characteristics of LCD outputs.
1998 May 04
29
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
SDA
SCL
SYNC
CLK
V
V
V
DD
SS
LCD
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
SDA
SCL
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
3
3
SYNC
CLK
4
4
V
5
5
DD
6
6
OSC
A0
7
7
8
8
A1
9
9
A2
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
SA0
V
SS
V
LCD
BP0
BP2
BP1
BP3
S0
BP0
BP2
BP1
BP3
S24
S25
S26
S27
PCF8566
PCF8566
open-circuit
S8
S7
S1
S6
S2
S5
S3
S4
S0
S23
S24
S47
MGG386
SEGMENTS
BACKPLANES
Fig.24 Single plane wiring of package PCF8566s.
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
13 CHIP DIMENSIONS AND BONDING PAD LOCATIONS
(1)
2.5 mm
y
25 24 23 22 21
20 19 18 17 16
15
BP1
BP2
BP0
V
26
27
28
29
30
31
32
33
34
35
S9
S10
S11
14
13
12
LCD
S12
(1)
2.91
11
10
9
x
S13
S14
S15
S16
S17
0
mm
V
0
SS
SA0
A2
PCF8566
8
A1
7
A0
6
OSC
S18
36 37 38 39 40
1
2
3
4
5
MBH783
(1) Typical value.
Pad size: 120 × 120 µm
Chip area: 7.27 mm.
The numbers given in the small squares refer to the pad numbers.
Fig.25 Bonding pad locations.
31
1998 May 04
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
Table 16 Bonding pad locations (dimensions in mm)
All x/y coordinates are referenced to centre of chip, (see Fig.25).
PAD NUMBER
SYMBOL
x
y
PIN
1
SDA
SCL
SYNC
CLK
VDD
OSC
A0
200
400
−1235
−1235
−1235
−1235
−1235
−1025
−825
−625
−425
−225
−25
1
2
2
3
605
3
4
856
4
5
1062
1080
1080
1080
1080
1080
1080
1080
1080
1080
1080
1074
874
5
6
6
7
7
8
A1
8
9
A2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SA0
VSS
VLCD
BP0
BP2
BP1
BP3
S0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
347
547
747
947
1235
1235
1235
1235
1235
1235
1235
1235
1235
1235
765
S1
674
S2
474
S3
274
S4
−274
−474
−674
−874
−1074
−1080
−1080
−1080
−1080
−1080
−1080
−1080
−1080
−1080
−1080
−1056
−830
−630
−430
−230
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
565
365
165
−35
−235
−435
−635
−835
−1035
−1235
−1235
−1235
−1235
−1235
1998 May 04
32
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
14 PACKAGE OUTLINES
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
D
M
E
A
2
A
L
A
1
c
e
w M
Z
b
1
(e )
1
b
M
H
40
21
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
1
1
E
H
max.
min.
max.
max.
1.70
1.14
0.53
0.38
0.36
0.23
52.50
51.50
14.1
13.7
3.60
3.05
15.80
15.24
17.42
15.90
4.7
0.51
4.0
2.54
0.10
15.24
0.60
0.254
0.01
2.25
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
0.56
0.54
0.14
0.12
0.62
0.60
0.69
0.63
inches
0.19
0.020
0.16
0.089
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-14
SOT129-1
051G08
MO-015AJ
1998 May 04
33
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
VSO40: plastic very small outline package; 40 leads
SOT158-1
D
E
A
X
c
y
H
v
M
A
E
Z
40
21
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
detail X
1
20
w
M
b
p
e
0
5
scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(2)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
0.3
0.1
2.45
2.25
0.42
0.30
0.22
0.14
15.6
15.2
7.6
7.5
12.3
11.8
1.7
1.5
1.15
1.05
0.6
0.3
2.70
0.11
0.25
0.762
0.03
2.25
0.089
0.2
0.1
0.1
7o
0o
0.012 0.096
0.004 0.089
0.017 0.0087 0.61
0.012 0.0055 0.60
0.30
0.29
0.48
0.46
0.067 0.045
0.059 0.041
0.024
0.012
inches
0.010
0.008 0.004 0.004
Notes
1. Plastic or metal protrusions of 0.4 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-24
SOT158-1
1998 May 04
34
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
Several techniques exist for reflowing; for example,
15 SOLDERING
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
15.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
15.3.2 WAVE SOLDERING
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Wave soldering techniques can be used for all SO and
VSO packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
15.2 DIP
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
15.2.1 SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
15.2.2 REPAIRING SOLDERED JOINTS
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
15.3.3 REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
15.3 SO and VSO
15.3.1 REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO and
VSO packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
1998 May 04
35
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
16 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 May 04
36
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
NOTES
1998 May 04
37
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
NOTES
1998 May 04
38
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
PCF8566
NOTES
1998 May 04
39
Philips Semiconductors – a worldwide company
Argentina: see South America
Middle East: see Italy
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Fax. +43 160 101 1210
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
Norway: Box 1, Manglerud 0612, OSLO,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belgium: see The Netherlands
Brazil: see South America
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Portugal: see Spain
Romania: see Italy
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Colombia: see South America
Czech Republic: see Austria
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Slovakia: see Austria
Slovenia: see Italy
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Spain: Balmes 22, 08007 BARCELONA,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA59
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/06/pp40
Date of release: 1998 May 04
Document order number: 9397 750 03725
相关型号：
©2020 ICPDF网 联系我们和版权申明