PCF8576CTT/1,118_技术文档

PCF8576C

Universal LCD driver for low multiplex rates

Rev. 09 — 9 July 2009

Product data sheet

1. General description

The PCF8576C is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)¹with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 40 segments and can easily

be cascaded for larger LCD applications. The PCF8576C is compatible with most

microprocessors or microcontrollers and communicates via a two-line bidirectional

I²C-bus. Communication overheads are minimized by a display RAM with

auto-incremented addressing, by hardware subaddressing.

2. Features

I Single-chip LCD controller and driver

I 40 segment drives:

N Up to twenty 7-segment numeric characters

N Up to ten 14-segment alphanumeric characters

N Any graphics of up to 160 elements

I Versatile blinking modes

I No external components required (even in multiple device applications)

I Selectable backplane drive conﬁguration: static or 2, 3, 4 backplane multiplexing

I Selectable display bias conﬁguration: static, ¹⁄₂or ¹⁄₃

I Internal LCD bias generation with voltage-follower buffers

I 40 × 4-bit RAM for display data storage

I Auto-incremented display data loading across device subaddress boundaries

I Display memory bank switching in static and duplex drive modes

I Wide logic LCD supply range:

N From 2 V for low-threshold LCDs

N Up to 6 V for guest-host LCDs and high-threshold twisted nematic LCDs

I Low power consumption

I May be cascaded for large LCD applications (up to 2560 segments possible)

I Cascadable with 24-segment LCD driver PCF8566

I No external components

I Compatible with chip-on-glass technology

I Separate or combined LCD and logic supplies

I Optimized pinning for plane wiring in both and multiple PCF8576C applications

I Power-saving mode for extremely low power consumption in battery-operated and

telephone applications

1. The deﬁnition of the abbreviations and acronyms used in this data sheet can be found in Section 19.

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PCF8576CH

LQFP64

plastic low proﬁle quad ﬂat package;

SOT314-2

64 leads; body 10 × 10 × 1.4 mm

PCF8576CT

VSO56

plastic very small outline package, 56 leads

SOT190-1

PCF8576CTT

HTSSOP56

plastic thermal enhanced thin shrink small outline package, 56 leads; SOT793-1

body width 6.1 mm; exposed die pad

PCF8576CU/10 PCF8576CU/10 wire bond die; 56 bonding pads; 3.0 × 2.82 × 0.38 mm^[1]

PCF8576CU PCF8576CU

wire bond die; 56 bonding pads; 3.0 × 2.82 × 0.38 mm^[2]

PCF8576CU/10

PCF8576CU

PCF8576CU/2 PCF8576CU/2 bare die; 56 bumps; 3.0 × 2.82 × 0.40 mm^[2]

PCF8576CU/2

[1] Delivery form: chip on FFC.

[2] Delivery form: chip in tray.

4. Marking

Table 2.

Marking codes

Type number

PCF8576CH

PCF8576CT

Marking code

PCF8576CH

PCF8576CT

PCF8576CTT

PC8576C-1

PC8576C-2

PCF8576CTT

PCF8576CU/10

PCF8576CU

PCF8576CU/2

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

2 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

5. Block diagram

BP0 BP2 BP1 BP3

S0 to S39

40

V

DD

BACKPLANE

OUTPUTS

DISPLAY SEGMENT OUTPUTS

DISPLAY LATCH

LCD

VOLTAGE

SELECTOR

LCD BIAS

GENERATOR

SHIFT REGISTER

V

LCD

PCF8576C

CLK

INPUT

BANK

SELECTOR

DISPLAY

RAM

40 × 4 BITS

OUTPUT

BANK

SELECTOR

TIMING

BLINKER

SYNC

DISPLAY

CONTROLLER

OSC

OSCILLATOR

POWER-

ON

RESET

DATA

POINTER

COMMAND

DECODER

V

SS

SUB-

ADDRESS

COUNTER

SCL

SDA

2

INPUT

FILTERS

I C-BUS

CONTROLLER

SA0

A0 A1 A2

013aaa094

Fig 1. Block diagram of PCF8576C

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

3 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

n.c.

S34

S35

S36

S37

S38

S39

n.c.

S17

S16

S15

S14

S13

S12

S11

S10

S9

3

4

5

6

7

8

PCF8576CH

9

n.c.

10

11

12

13

14

15

16

SDA

SCL

S8

SYNC

CLK

S7

S6

V

DD

S5

OSC

A0

S4

n.c.

001aag241

Top view. For mechanical details, see Figure 32.

Fig 2. Pin conﬁguration of PCF8576CH (LQFP64)

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

4 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

SDA

SCL

S39

S38

S37

S36

S35

S34

S33

S32

S31

S30

S29

S28

S27

S26

S25

S24

S23

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

2

3

SYNC

CLK

4

5

V

DD

6

OSC

A0

7

8

A1

9

A2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

SA0

V

SS

V

LCD

BP0

BP2

BP1

BP3

S0

PCF8576CT

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

001aag240

Top view. For mechanical details, see Figure 33.

Fig 3. Pin conﬁguration of PCF8576CT (VSO56)

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

5 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

SDA

SCL

S39

S38

S37

S36

S35

S34

S33

S32

S31

S30

S29

S28

S27

S26

S25

S24

S23

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

2

3

SYNC

CLK

4

5

V

DD

6

OSC

A0

7

8

A1

9

A2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

SA0

V

SS

V

LCD

BP0

BP2

BP1

BP3

S0

PCF8576CTT

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

013aaa095

Top view. For mechanical details, see Figure 34.

Fig 4. Pin conﬁguration of PCF8576CTT (HTSSOP56)

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

6 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

34 33 32 31 30 29 28 27 26 25 24 23 22 21

S18 35

S19 36

S20 37

S21 38

S22 39

S23 40

S24 41

S25 42

S26 43

S27 44

S28 45

S29 46

S30 47

S31 48

S32 49

S33 50

20 S3

19 S2

18 S1

17 S0

16 BP3

15 BP1

14 BP2

13 BP0

PCF8576CU

V

12

11

LCD

SS

10 SA0

9

8

A2

A1

51 52 53 54 55 56

1

2

3

4

5

6

7

013aaa096

Top view. For mechanical details, see Figure 35, Figure 36 and Figure 37.

Fig 5. Pin locations of PCF8576CU

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

7 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

6.2 Pin description

Table 3.

Symbol

Pin description

Description

PCF8576CH

PCF8576CT

PCF8576CU

PCF8576CTT

SDA

SCL

10

1

I²C-bus serial data input and output

I²C-bus serial clock input

cascade synchronization input and output

external clock input/output

supply voltage

11

2

SYNC

CLK

12

3

13

4

5^[1]

V_DD

14

5

OSC

A0 to A2

SA0

15

6

internal oscillator enable input

16 to 18

19

7 to 9

10

7 to 9

10

subaddress inputs

I²C-bus address input; bit 0

logic ground

V_SS

20

11

V_LCD

21

12

LCD supply voltage

BP0, BP2, 25 to 28

BP1, BP3

13 to 16

LCD backplane outputs

S0 to S39 2 to 7, 29 to 32,

34 to 47, 49 to 64

17 to 56

-

LCD segment outputs

not connected

n.c.

1, 8, 9, 22 to 24, 33, 48 -

[1] The substrate (rear side of the die) is wired to V_DDbut should not be electrically connected.

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

8 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

7. Functional description

The PCF8576C is a versatile peripheral device designed to interface any

microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static

or multiplexed LCD containing up to 4 backplanes and up to 40 segments.

The display conﬁgurations possible with the PCF8576C depend on the number of active

backplane outputs required. Display conﬁguration selection is shown in Table 4. All of the

display conﬁgurations given in Table 4 can be implemented in the typical system shown in

Figure 6.

Table 4.

Display conﬁgurations

7 segment numeric

Number of:

14-segment numeric

Dot matrix

Backplanes Elements

Digits

Indicator

symbols

Characters Indicator

symbols

4

3

2

1

160

120

80

20

15

10

5

20

15

10

5

10

8

20

8

160 (4 × 40)

120 (3 × 40)

80 (2 × 40)

40 (1 × 40)

5

10

12

40

2

V

DD

t

r

R≤

2C

B

V

DD

LCD

SDA

SCL

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

40 segment drives

4 backplanes

LCD PANEL

PCF8576C

(up to 160

elements)

OSC

013aaa098

A0 A1 A2 SA0 V

SS

V

SS

Fig 6. Typical system conﬁguration

The host microprocessor or microcontroller maintains the 2-line I²C-bus communication

channel with the PCF8576C.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to V_SS. The only other connections required to complete the system are the

power supplies (pins V_DD, V_SSand V_LCD) and the LCD panel selected for the application.

7.1 Power-on-reset

At power-on the PCF8576C resets to the following starting conditions:

• All backplane and segment outputs are set to V_DD

• The selected drive mode is 1:4 multiplex with ¹⁄₃bias

• Blinking is switched off

• Input and output bank selectors are reset (as deﬁned in Table 8)

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

9 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

• The I²C-bus interface is initialized

• The data pointer and the subaddress counter are cleared

Remark: Do not transfer data on the I²C-bus for at least 1 ms after a power-on to allow the

reset action to complete.

7.2 LCD bias generator

The full-scale LCD voltage (V_oper) is obtained from V_DD− V_LCD. The LCD voltage may be

temperature compensated externally through the V_LCDsupply to pin V_LCD

.

Fractional LCD biasing voltages are obtained from an internal voltage divider comprising

three series resistors connected between V_DDand V_LCD. The center resistor can be

switched out of the circuit to provide a ¹⁄₂bias voltage level for the 1:2 multiplex

conﬁguration.

7.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive conﬁguration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing conﬁgurations that apply to

the preferred modes of operation, together with the biasing characteristics as functions of

V_LCDand the resulting discrimination ratios (D), are given in Table 5.

Table 5.

Preferred LCD drive modes: summary of characteristics

LCD drive

mode

Number of:

LCD bias

conﬁguration

V _{off (RMS)}

V _on(RMS)

--------------------------

V _LCD

D = --------------------------

V _{off (RMS)}

------------------------

V _LCD

Backplanes Bias levels

static

1

2

3

4

static

0

1

∞

1

⁄

1:2 multiplex 2

1:3 multiplex 3

1:4 multiplex 4

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

2

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a deﬁned LCD

threshold voltage (V_th), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode a suitable choice is V_LCD< 3 × V_th.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 1

2

1

(n – 1)

----------------

n

1

V

V_on(RMS)

=

-- +

n

×

(1)

------------

1 + a

LCD

where V_LCDis the resultant voltage at the LCD segment and where the values for n are

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

10 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

n = 1 for static mode

n = 2 for 1:2 multiplex

n = 3 for 1:3 multiplex

n = 4 for 1:4 multiplex

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 2:

a²– 2a + n

n × (1 + a)²

V_{off (RMS)}= V

-----------------------------

(2)

(3)

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 3:

(a + 1)²+ (n – 1)

V _on(RMS)

D =

=

-------------------------------------------

------------------------

(a – 1)²+ (n – 1)

V _{off (RMS)}

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias): V _LCD

=

6 × V _{off (RMS)}= 2.449V _{off (RMS)}

(4 × 3)

• 1:4 multiplex (¹⁄₂bias): V _LCD

=

= 2.309V _{off (RMS)}

---------------------

3

These compare with V _LCD= 3V _{off (RMS)}when ¹⁄₃bias is used.

It should be noted that V_LCDis sometimes referred as the LCD operating voltage.

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

11 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4 LCD drive mode waveforms

7.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD.

Backplane and segment drive waveforms for this mode are shown in Figure 7.

T

fr

LCD segments

V

LCD

BP0

Sn

V

SS

state 1

(on)

state 2

(off)

V

LCD

V

SS

V

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

state 1

0 V

−V

LCD

V

LCD

state 2

0 V

−V

LCD

(b) Resultant waveforms

at LCD segment.

mgl745

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= V_LCD

.

V_state2(t) = V_Sn+1(t) − V_BP0(t).

V_off(RMS)= 0 V.

Fig 7. Static drive mode waveforms

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

12 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.2 1:2 Multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCF8576C allows the use of ¹⁄₂bias or ¹⁄₃bias (see Figure 8 and Figure 9).

T

fr

V

LCD

LCD segments

V

/ 2

BP0

BP1

Sn

LCD

SS

state 1

state 2

V

LCD

V

LCD

SS

V

LCD

V

SS

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

/ 2

LCD

0 V

−V

state 1

/ 2

LCD

−V

LCD

V

LCD

/ 2

LCD

0 V

state 2

−V

/ 2

LCD

−V

(b) Resultant waveforms

at LCD segment.

mgl746

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.791V_LCD

.

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.354V_LCD

Fig 8. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

13 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

T

fr

V

LCD

2V

LCD segments

/ 3

LCD

/ 3

BP0

BP1

Sn

V

LCD

SS

state 1

state 2

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+1

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 1

/ 3

LCD

−2V

/ 3

LCD

−V

LCD

V

LCD

2V

/ 3

LCD

V

LCD

0 V

−V

state 2

/ 3

LCD

−2V

/ 3

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

mgl747

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.745V_LCD

V_state2(t) = V_Sn(t) − V_BP1(t)

V_off(RMS)= 0.333V_LCD.

Fig 9. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

14 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as

shown in Figure 10.

T

fr

V

LCD

2V

LCD segments

/ 3

LCD

/ 3

BP0

BP1

BP2

Sn

V

LCD

SS

state 1

state 2

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+1

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+2

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 1

/ 3

LCD

−2V

/ 3

LCD

−V

LCD

V

LCD

2V

/ 3

LCD

V

LCD

0 V

−V

state 2

/ 3

LCD

−2V

/ 3

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

mgl748

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.638V_LCD

.

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.333V_LCD.

Fig 10. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

15 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.4 1:4 multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as

shown in Figure 11.

T

fr

V

LCD segments

LCD

2V

/ 3

LCD

/ 3

BP0

BP1

BP2

V

LCD

SS

state 1

state 2

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

BP3

Sn

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+1

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

Sn+2

Sn+3

V

LCD

SS

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/ 3

LCD

/ 3

V

LCD

0 V

−V

state 1

/ 3

LCD

−2V

/ 3

LCD

−V

LCD

V

LCD

2V

/ 3

LCD

V

LCD

0 V

−V

state 2

/ 3

LCD

−2V

/ 3

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

mgl749

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.577V_LCD

.

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.333V_LCD.

Fig 11. Waveforms for the 1:4 multiplex mode with ¹⁄₃bias

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

16 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.5 Oscillator

The internal logic and the LCD drive signals of the PCF8576C are timed by the frequency

f_clk, which equals either the built-in oscillator frequency f_oscor the external clock frequency

f_clk(ext)

.

The clock frequency (f_clk) determines the LCD frame frequency (f_fr) and the maximum rate

for data reception from the I²C-bus. To allow I²C-bus transmissions at their maximum data

rate of 100 kHz, f_clkshould be chosen to be above 125 kHz.

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to pin V_SS. In this case, the

output from pin CLK is the clock signal for any cascaded PCF8576s or PCF8566s in the

system.

Remark: The PCF8576C is backwards compatible with the PCF8576 (V_operup to 9 V).

Where resistor R_ext(on pin OSC) to V_SSis present, the internal oscillator is selected.

7.5.2 External clock

Connecting pin OSC to V_DDenables an external clock source. Pin CLK then becomes the

external clock input.

Remark: A clock signal must always be supplied to the device. Removing the clock,

freezes the LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing

The timing of the PCF8576C sequences the internal data ﬂow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. In

cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between the PCF8576Cs in the system. The timing also generates the LCD

frame frequency which is derived as an integer division of the clock frequency (see

Table 6). The frame frequency is set by the mode set commands when an internal clock is

used or by the frequency applied to the pin CLK when an external clock is used.

Table 6.

LCD frame frequencies ^[1]

PCF8576C mode

Frame frequency

Nominal frame frequency (Hz)

Normal mode

69 ^[2]

f _clk

f _fr

=

------------

2880

Power saving mode

65 ^[3]

f _clk

f _fr

---------

480

[1] The possible values for f_clksee Table 20.

[2] For f_clk= 200 kHz.

[3] For f_clk= 31 kHz.

The ratio between the clock frequency and the LCD frame frequency depends on the

mode in which the device is operating. In the power-saving mode the reduction ratio is six

times smaller; this allows the clock frequency to be reduced by a factor of six. The

reduced clock frequency results in a signiﬁcant reduction in power consumption.

PCF8576C_9

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The lower clock frequency has the disadvantage of increasing the response time when

large amounts of display data are transmitted on the I²C-bus. When a device is unable to

process a display data byte before the next one arrives, it holds the SCL line LOW until the

ﬁrst display data byte is stored. This slows down the transmission rate of the I²C-bus but

no data loss occurs.

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display register, the

LCD segment outputs and one column of the display RAM.

7.8 Shift register

The shift register transfers display information from the display RAM to the display register

while previous data is displayed.

7.9 Segment outputs

The LCD drive section includes 40 segment outputs, S0 to S39, which must be connected

directly to the LCD. The segment output signals are generated based on the multiplexed

backplane signals and with data residing in the display register. When less than

40 segment outputs are required, the unused segment outputs should be left open-circuit.

7.10 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated based on the selected LCD drive mode.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required the unused outputs can be left as an

open-circuit.

• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same

signals and can also be paired to increase the drive capabilities.

• In static drive mode: the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

7.11 Display RAM

The display RAM is a static 40 × 4-bit RAM which stores LCD data. A logic 1 in the RAM

bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0

indicates the off-state. There is a direct relationship between the RAM addresses and the

segment outputs, and between the individual bits of a RAM word and the backplane

outputs. The display RAM bit map Figure 12 shows the rows 0 to 3 which correspond with

the backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the

segment outputs S0 to S39. In multiplexed LCD applications the segment data of the ﬁrst,

second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2

and BP3 respectively.

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PCF8576C

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display RAM addresses (columns)/segment outputs (S)

0

1

2

3

4

35 36 37 38 39

0

1

2

3

display RAM bits

(rows)/

backplane outputs

(BP)

mbe525

Display RAM bit map showing direct relationship between RAM addresses and segment outputs;

also between bits in a RAM word and the backplane outputs.

Fig 12. Display RAM bit map

When display data is transmitted to the PCF8576C, the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and does not wait for an acknowledge cycle as with the commands. Depending

on the current multiplex drive mode, data is stored singularly, in pairs, triplets or

quadruplets. To illustrate the ﬁlling order, an example of a 7-segment numeric display

showing all drive modes is given in Figure 13; the RAM ﬁlling organization depicted

applies equally to other LCD types.

The following applies to Figure 13:

• In the static drive mode, the eight transmitted data bits are placed in row 0 of eight

successive 4-bit RAM words.

• In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into

row 0 and 1 of four successive 4-bit RAM words.

• In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to

three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difﬁcult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be taken to avoid overwriting adjacent data because always full bytes are

transmitted.

• In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into

row 0, 1, 2 and 3 of two successive 4-bit RAM words.

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7.12 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load data pointer command (see Table 13). After this, the data byte is

stored starting at the display RAM address indicated by the data pointer (see Figure 13).

Once each byte is stored, the data pointer is automatically incremented based on the

selected LCD conﬁguration.

The contents of the data pointer are incremented as follows:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I²C-bus data access terminates early, the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.13 Sub-address counter

The storage of display data is conditioned by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter match

with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is

deﬁned by the device select command (see Table 14). If the contents of the subaddress

counter and the hardware subaddress do not match then data storage is blocked but the

data pointer will be incremented as if data storage had taken place. The subaddress

counter is also incremented when the data pointer overﬂows.

The storage arrangements described lead to extremely efﬁcient data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCF8576C occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character (such as during the 14th

display data byte transmitted in 1:3 multiplex mode).

7.14 Bank selector

7.14.1 Output bank selector

The output bank selector (see Table 15), selects one of the four bits per display RAM

address for transfer to the display register. The actual bit selected depends on the LCD

drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially

by the contents of bit 1, bit 2 and then bit 3.

• In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially.

• In 1:2 multiplex mode: bits 0 and 1 are selected.

• In the static mode: bit 0 is selected.

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The PCF8576C includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. In the static drive mode, the bank select command may request the contents

of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 multiplex drive

mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This enables

preparation of display information in an alternative bank and the ability to switch to it once

it has been assembled.

7.14.2 Input bank selector

The input bank selector (see Table 15) loads display data into the display RAM based on

the selected LCD drive conﬁguration. Using the bank select command, display data can

be loaded in bit 2 into static drive mode or in bits 2 and 3 into 1:2 multiplex drive mode.

The input bank selector functions independently of the output bank selector.

7.15 Blinker

The display blinking capabilities of the PCF8576C are very versatile. The whole display

can be blinked at frequencies selected by the blink command. The blinking frequencies

are integer fractions of the clock frequency; the ratios between the clock and blinking

frequencies depend on the mode in which the device is operating (see Table 7).

Table 7.

Blink frequencies

Blinking mode

Normal operating

mode ratio

Power saving mode

ratio

Blink frequency

off

1

-

blinking off

2 Hz

f _clk

f _blink

=

f _blink

=

----------------

92160

----------------

15360

2

3

1 Hz

f _clk

-------------------

184320

----------------

30720

0.5 Hz

f _clk

-------------------

368640

----------------

61440

An additional feature is for an arbitrary selection of LCD segments to be blinked. This

applies to the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. Using the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blinking frequency. This mode can also be

speciﬁed by the blink command (see Table 16).

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can be blinked by selectively changing the display RAM data at ﬁxed time

intervals.

If the entire display needs to be blinked at a frequency other than the nominal blink

frequency, this can be done using the mode set command to set and reset the display

enable bit E at the required rate (see Table 9).

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8. Basic architecture

8.1 Characteristics of the I²C-bus

The I²C-bus provides bidirectional, two-line communication between different IC or

modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When

connected to the output stages of a device, both lines must be connected to a positive

supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.

8.1.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse. Changes in the data line at this time will

be interpreted as a control signal. Bit transfer is illustrated in Figure 14.

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 14. Bit transfer

8.1.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change

of the data line, while the clock is HIGH, is deﬁned as the START condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is deﬁned as the STOP

condition (P). The START and STOP conditions are illustrated in Figure 15.

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Fig 15. Deﬁnition of START and STOP conditions

8.1.2 System conﬁguration

A device generating a message is a transmitter and a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system conﬁguration is illustrated in

Figure 16.

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MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

mga807

Fig 16. System conﬁguration

8.1.3 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during

which time the master generates an extra acknowledge related clock pulse.

Acknowledgement on the I²C-bus is illustrated in Figure 17.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

• A master receiver must signal an end-of-data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

master receiver must leave the data line HIGH during the 9th pulse to not

acknowledge. The master will now generate a STOP condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from

master

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 17. Acknowledgement on the I²C-bus

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8.1.4 PCF8576C I²C-bus controller

The PCF8576C acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCF8576C are

the acknowledge signals of the selected devices. Device selection depends on the

I²C-bus slave address, the transferred command data and the hardware subaddress.

In single device application, the hardware subaddress inputs A0, A1 and A2 are normally

tied to V_SSwhich deﬁnes the hardware subaddress 0. In multiple device applications

A0, A1 and A2 are tied to V_SSor V_DDusing a binary coding scheme so that no two

devices with a common I²C-bus slave address have the same hardware subaddress.

In the power-saving mode it is possible that the PCF8576C is not able to keep up with the

highest transmission rates when large amounts of display data are transmitted. If this

situation occurs, the PCF8576C forces the SCL line LOW until its internal operations are

completed. This is known as the clock synchronization feature of the I²C-bus and serves

to slow down fast transmitters. Data loss does not occur.

8.1.5 Input ﬁlter

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

8.2 I²C-bus protocol

Two I²C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576C.

The least signiﬁcant bit of the slave address that a PCF8576C responds to is deﬁned by

the level tied at its input SA0. Therefore, two types of PCF8576C can be distinguished on

the same I²C-bus which allows:

• Up to 16 PCF8576Cs on the same I²C-bus for very large LCD applications.

• The use of two types of LCD multiplex on the same I²C-bus.

The I²C-bus protocol is shown in Figure 18. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of the two PCF8576C

slave addresses available. All PCF8576Cs with the corresponding SA0 level acknowledge

in parallel with the slave address but all PCF8576Cs with the alternative SA0 level ignore

the whole I²C-bus transfer.

After acknowledgement, one or more command bytes (m) follow which deﬁne the status of

the addressed PCF8576Cs.

The last command byte is tagged with a cleared most signiﬁcant bit, the continuation bit C.

The command bytes are also acknowledged by all addressed PCF8576Cs on the bus.

After the last command byte, a series of display data bytes (n) may follow. These display

bytes are stored in the display RAM at the address speciﬁed by the data pointer and the

subaddress counter. Both data pointer and subaddress counter are automatically updated

and the data is directed to the intended PCF8576C device. The acknowledgement after

each byte is made only by the (A0, A1 and A2) addressed PCF8576C. After the last

display byte, the I²C-bus master issues a STOP condition (P).

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acknowledge

by A0, A1 and A2

selected

acknowledge by

all addressed

PCF8576Cs

R/W

0

PCF8576C only

slave address

S

A

0

1

0

A C

A

DISPLAY DATA

A

P

COMMAND

S

n ≥ 1 byte(s)

n ≥ 0 byte(s)

1 byte

update data pointers

and if necessary,

subaddress counter

mbe538

Fig 18. I²C-bus protocol

8.3 Command decoder

The command decoder identiﬁes command bytes that arrive on the I²C-bus. All available

commands carry a continuation bit C in their most signiﬁcant bit position as shown in

Figure 19. When this bit is set, it indicates that the next byte of the transfer to arrive will

also represent a command. If this bit is reset, it indicates that the command byte is the last

in the transfer. Further bytes will be regarded as display data.

The ﬁve commands available to the PCF8576C are deﬁned in Table 8.

MSB

LSB

C

REST OF OPCODE

msa833

(1) C = 0; last command

(2) C = 1; commands continue

Fig 19. General format of byte command

Table 8.

Deﬁnition of PCF8576C commands

Command

OPCODE

Reference

Description

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

mode set

C

1

0

LP

E

B

M1

M0

Section 8.3.1 deﬁnes LCD drive mode, LCD bias

conﬁguration, display status and power

dissipation mode

load data

pointer

C

0

1

P5

1

P4

0

P3

0

P2

A2

0

P1

A1

I

P0

A0

O

Section 8.3.2 data pointer to deﬁne one of 40 display

RAM addresses

device select

Section 8.3.3 deﬁne one of eight hardware

subaddresses

bank select

1

Section 8.3.4 bit I: deﬁnes input bank selection

(storage of arriving display data);

bit O: deﬁnes output bank selection

(retrieval of LCD display data)

blink

C

1

0

A

BF1 BF0 Section 8.3.5 deﬁnes the blink frequency and blink

mode

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8.3.1 Mode set command

Table 9.

LCD drive mode command bit description

LCD drive mode

Bit

M1

0

Drive mode

Backplane

BP0

M0

1

static

1:2

BP0, BP1

1

0

1:3

BP0, BP1, BP2

BP0, BP1, BP2, BP3

1

1:4

0

Table 10. LCD bias conﬁguration command bit description

LCD bias

¹⁄₃bias

¹⁄₂bias

Bit B

0

1

Table 11. Display status command bit description^[1]

Display status

disabled (blank)

enabled

Bit E

0

1

[1] The possibility to disable the display allows implementation of blinking under external control.

Table 12. Power dissipation mode command bit description

Display status

normal mode

Bit LP

0

1

power saving mode

8.3.2 Load data pointer command

Table 13. Load data pointer command bit description

Description

Bits

6 bit binary value, 0 to 39

P5

P4

P3

A1

P2

P1

A0

P0

8.3.3 Device select command

Table 14. Device select command bit description

Description

Bits

3 bit binary value, 0 to 7

A2

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8.3.4 Bank select command

Table 15. Bank select command^[1]

Bank

Mode

Static

Bit

I

Value

1:2 multiplex drive mode

Input bank

RAM bit 0

RAM bit 2

RAM bits 0 and 1

RAM bits 2 and 3

0

1

Output bank

RAM bit 0

RAM bit 2

RAM bits 0 and 1

RAM bits 2 and 3

O

0

1

[1] The bank select command has no effect in 1:3 or 1:4 multiplex drive modes.

8.3.5 Blink command

Table 16. Blink frequency command bit description

Blink frequency

Bit

BF1

0

BF0

0

off

1

0

1

2

1

0

3

1

Table 17. Blink mode command bit description

Blink mode

Bit A

normal blinking

0

1

alternate RAM bank blinking

8.4 Display controller

The display controller executes the commands identiﬁed by the command decoder. It

contains the status registers of the PCF8576C and coordinates their effects. The

controller is also responsible for loading display data into the display RAM as required by

the ﬁlling order.

9. Internal circuitry

V

LCD

V

SS

BP0 to BP3,

S0 to S39

SDA, SCL

CLK, OSC, A0 to A2,

SA0,

SYNC

V

DD

013aaa109

Fig 20. Device protection diagram

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10. Limiting values

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

Table 18. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V

V_DD

V_LCD

V_I

supply voltage

LCD supply voltage

input voltage

−0.5

8.0

[1]

V_DD− 8.0 V_DD

V

on each of the pins SCL, SDA, −0.5

8.0

V

CLK, SYNC, SA0, OSC and

A0 to A2

[1]

V_O

output voltage

on each of the pins

−0.5

8.0

V

S0 to S39 and BP0 to BP3

I_I

input current

−20

−25

−50

-

+20

mA

mW

°C

I_O

output current

+25

I_DD

I_SS

supply current

+50

ground supply current

+50

I_DD(LCD)LCD supply current

+50

P_tot

P_o

total power dissipation

output power

400

-

100

[2]

[3]

[4]

[5]

T_stg

V_ESD

storage temperature

−65

-

+150

±4000

±200

100

electrostatic discharge

voltage

HBM

MM

V

-

V

I_lu

latch-up current

-

mA

[1] Values with respect to V_DD

.

[2] According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be

stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.

[3] Pass level; Human Body Model (HBM) according to JESD22-A114.

[4] Pass level; Machine Model (MM), according to JESD22-A115.

[5] Pass level; latch-up testing, according to JESD78.

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11. Static characteristics

Table 19. Static characteristics

V_DD= 2.0 V to 6.0 V; V_SS= 0 V; V_LCD= V_DD− 6.0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Supplies

Conditions

Min

Typ

Max

Unit

V_DD

supply voltage

2.0

-

6.0

V

[1]

[2]

V_LCD

I_DD

LCD supply voltage

supply current:

V_DD− 6.0

V_DD− 2.0 V

f_clk= 200 kHz

-

120

60

µA

I_DD(lp)

low-power mode supply

current

V_DD= 3.5 V; V_LCD= 0 V; f_clk= 35 kHz;

A0, A1 and A2 connected to V_SS

-

Logic

V_IL

LOW-level input voltage

HIGH-level input voltage

on pins CLK, SYNC, OSC,

A0 to A2 and SA0

V_SS

-

0.3V_DD

V_DD

V

V_IH

on pins CLK, SYNC, OSC,

A0 to A2 and SA0

0.7V_DD

-

V_OL

V_OH

I_OL

LOW-level output voltage

HIGH-level output voltage

LOW-level output current

I_OL= 0 mA

I_OH= 0 mA

0.05

V

V_DD− 0.05 -

-

V

V_OL= 1.0 V; V_DD= 5.0 V;

on pins CLK and SYNC

1

-

mA

I_L

leakage current

V_I= V_DDor V_SS; on pins

−1

-

+1

µA

CLK, SCL, SDA, A0 to A2 and SA0

I_L(OSC)

I_pd

leakage current on pin OSC

pull-down current

V_I= V_DD

−1

-

+1

µA

V_I= 1.0 V; V_DD= 5.0 V;

15

50

150

on pins A0 to A2 and OSC

R_{SYNC_N}SYNC resistance

20

-

50

1.0

-

150

1.6

7

kΩ

V

[3]

[4]

V_POR

C_I

power-on reset voltage

input capacitance

-

pF

I²C-bus; pins SDA and SCL

V_IL

LOW-level input voltage

HIGH-level input voltage

V_SS

-

0.3V_DD

V

V_IH

0.7V_DD

−1

6.0

-

V

I_OH(CLK)

HIGH-level output current on

pin CLK

V_OH= 4.0 V; V_DD= 5.0 V

V_OL= 0.4 V; V_DD= 5.0 V

mA

I_OL(SDA)

LOW-level output current on

pin SDA

3

-

mA

LCD outputs

V_BP

V_S

voltage on pin BP

C_bpl= 35 nF; on pins BP0 to BP3

C_sgm= 5 nF; on pins S0 to S39

−20

-

+20

5

mV

kΩ

voltage on pin S

−20

[5]

R_BP

R_S

resistance on pin BP

resistance on pin S

V_LCD= V_DD− 5 V; on pins BP0 to BP3

V_LCD= V_DD− 5 V; on pins S0 to S39

-

7.5

[1]

V

_LCD≤ V_DD− 3 V for ¹⁄₃bias.

[2] LCD outputs are open-circuit; inputs at V_SSor V_DD; external clock with 50 % duty factor; I²C-bus inactive.

[3] Resets all logic when V_DD< V_POR

.

[4] Periodically sampled, not 100 % tested.

[5] Outputs measured one at a time.

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

30 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

11.1 Typical supply current characteristics

mbe530

mbe529

50

I

−I

DD(LCD)

SS

(µA)

normal

mode

40

30

20

30

20

power-saving

mode

10

0

10

0

100

200

0

100

200

f

(Hz)

f (Hz)

fr

V_DD= 5 V; V_LCD= 0 V; T_amb= 25 °C

Fig 21. I_SSas a function of f_fr

Fig 22. −I_DD(LCD)as a function of f_fr

mbe527

mbe528

50

I

SS

−I

DD(LCD)

(µA)

40

normal mode

= 200 kHz

f

85 °C

clk

30

20

30

20

25 °C

−40 °C

power-saving mode

= 35 kHz

10

0

10

0

f

clk

0

5

10

0

5

10

V

(V)

V

DD

(V)

DD

V_LCD= 0 V; external clock; T_amb= 25 °C

Fig 23. I_SSas a function of V_DD

Fig 24. −I_DD(LCD)as a function of V_DD

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

31 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

11.2 Typical LCD output characteristics

mbe532

mbe526

2.5

10

R

S

R

O(max)

(kΩ)

R

O(max)

2.0

(kΩ)

R

S

1.5

1.0

R

BP

1

R

BP

0.5

0

−1

10

0

3

6

−40

0

40

80

120

(°C)

V

DD

(V)

T

amb

V_LCD= 0 V; T_amb= 25 °C

V_DD= 5 V; V_LCD= 0 V

Fig 25. R_O(max)as a function of V_DD

Fig 26. R_O(max)as a function of T_amb

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

32 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

12. Dynamic characteristics

Table 20. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Timing characteristics: driver timing waveforms (see Figure 27)

[1]

f_clk

clock frequency

normal mode; V_DD= 5 V 125

200

31

315

48

kHz

power saving mode;

V_DD= 3 V

21

t_clk(H)

t_clk(L)

clock HIGH time

clock LOW time

1

-

µs

ns

µs

-

t_{PD(SYNC_N)}SYNC propagation delay

400

-

t_{SYNC_NL}

SYNC LOW time

1

-

t_PD(drv)

driver propagation delay

V_LCD= V_DD− 5 V

30

[2]

Timing characteristics: I²C-bus (see Figure 28)

t_BUF

bus free time between a STOP and START

condition

4.7

-

µs

t_HD;STA

t_SU;STA

t_LOW

t_HIGH

t_r

hold time (repeated) START condition

set-up time for a repeated START condition

LOW period of the SCL clock

HIGH period of the SCL clock

rise time of both SDA and SCL signals

fall time of both SDA and SCL signals

capacitive load for each bus line

data set-up time

4.0

4.7

4.0

-

µs

pF

ns

µs

-

1

t_f

-

0.3

C_b

-

400

t_SU;DAT

t_HD;DAT

t_SU;STO

250

0

-

data hold time

set-up time for STOP condition

4.0

[1]

[2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

f

_clk< 125 kHz, I²C-bus maximum transmission speed is derated.

.

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

33 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

1/f

CLK

t

clk(L)

clk(H)

0.7V

0.3V

DD

CLK

0.7V

0.3V

DD

SYNC

t

PD(SYNC_N)

t

SYNC_NL

0.5 V

(V = 5 V)

BP0 to BP3,

and S0 to S39

DD

0.5 V

t

PD(drv)

mce424

Fig 27. Driver timing waveforms

SDA

t

f

BUF

LOW

SCL

SDA

t

HD;STA

t

SU;DAT

r

HD;DAT

t

HIGH

t

SU;STA

t

SU;STO

mga728

Fig 28. I²C-bus timing waveforms

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

34 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

In large display conﬁgurations, up to 16 PCF8576Cs can be recognized on the same

I²C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable

I²C-bus slave address (SA0).

Table 21. Addressing cascaded PCF8576C

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2

1

8

9

10

11

12

13

14

15

Cascaded PCF8576Cs are synchronized. They can share the backplane signals from one

of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCF8576Cs of the cascade contribute

additional segment outputs but their backplane outputs are left open-circuit (see

Figure 29).

The PCF8576C can also be cascaded with the PCF8566. The connections are identical to

the PCF8576C cascade.

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

35 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

V

DD

V

LCD

SDA

SCL

1

2

5

12

40 segment drives

17 to 56

LCD PANEL

SYNC

CLK

3

4

6

PCF8576CT

(up to 2560

elements)

13,15,

14,16

BP0 to BP3

(open-circuit)

OSC

A0 A1 A2 SAO V

SS

V

LCD

V

DD

t

r

R ≤

2C

V

DD

V

LCD

B

5

12

SDA

1

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

40 segment drives

17 to 56

SCL

2

PCF8576CT

SYNC

3

4

6

13,15,

14,16

4 backplanes

BP0 to BP3

CLK

OSC

mbe533

7

8

9

10 11

A0 A1 A2 SA0 V

SS

V

SS

Fig 29. Cascaded PCF8576C conﬁguration

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF8576Cs. This synchronization is guaranteed after the power-on reset. The only time

that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments; or by the deﬁning a multiplex mode when PCF8576Cs

with differing SA0 levels are cascaded).

SYNC is organized as an input/output pin; the output selection being realized as an

open-drain driver with an internal pull-up resistor. A PCF8576C asserts the SYNC line

and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is

restored by the ﬁrst PCF8576C to assert SYNC. The timing relationship between the

backplane waveforms and the SYNC signal for the various drive modes of the PCF8576C

are shown in Figure 30.

For single plane wiring of packaged PCF8576Cs and chip-on-glass cascading, see

Figure 31.

.

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

36 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

1

T

=

fr

f

fr

BP0

SYNC

(a) static drive mode.

BP0

(1/2 bias)

BP0

(1/3 bias)

SYNC

(b) 1:2 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(c) 1:3 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(d) 1:4 multiplex drive mode.

mgl755

Excessive capacitive coupling between SCL or CLK and SYNC will cause erroneous

synchronization. If this is a problem you can increase the capacitance of the SYNC line (e.g. by an

external capacitor between SYNC and V_DD.) Degradation of the positive edge of the SYNC pulse

can be countered by an external pull-up resistor.

Fig 30. Synchronization of the cascade for the various PCF8576C drive modes

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

37 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

SDA

SCL

SYNC

CLK

V

DD

V

SS

V

LCD

SDA

SCL

1

2

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

S39

S38

S37

S36

S35

S34

S33

S32

S31

S30

S29

S28

S27

S26

S25

S24

S23

S22

S21

1

2

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

S79

S78

S77

S76

S75

S74

S73

S72

S71

S70

S69

S68

S67

S66

S65

S64

S63

S62

S61

SYNC

CLK

3

4

V

5

DD

OSC

A0

6

7

A1

8

A2

9

SA0

10

11

12

13

14

15

16

17

18

19

20

10

11

12

13

14

15

16

17

18

19

20

V

SS

V

LCD

BP0

BP2

BP1

BP3

S40

S41

S42

S43

BP2

BP1

BP3

S0

open

PCF8576CT

S1

S2

S3

34

33

32

31

30

29

S17

S16

S15

34

33

32

31

30

29

S57

S56

S55

S7

S8

24

25

26

27

28

S47

S48

S49

S50

S51

24

25

26

27

28

S9

S14

S13

S12

S54

S53

S52

S10

S11

S0

S10

S11

S12

S13

S39

S40

S50

S51

S52

S53

S79

segments

backplanes

mbe537

Fig 31. Single plane wiring of packaged PCF8576CTs

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

38 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

14. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 32. Package outline SOT314-2 (LQFP64) of PCF8576CH

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

39 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

VSO56: plastic very small outline package; 56 leads

SOT190-1

D

E

A

X

c

y

H

v M

A

E

Z

56

29

Q

p

A

2

A

(A )

3

A

1

pin 1 index

θ

L

detail X

1

28

w

M

b

p

e

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

(2)

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

0.3

0.1

3.0

2.8

0.42

0.30

0.22 21.65 11.1

0.14 21.35 11.0

15.8

15.2

1.6

1.4

1.45

1.30

0.90

0.55

3.3

0.25

0.01

0.75

2.25

0.2

0.1

7^o

0^o

0.012 0.12

0.004 0.11

0.017 0.0087 0.85

0.012 0.0055 0.84

0.44

0.43

0.62

0.60

0.063 0.057

0.055 0.051

0.035

0.022

inches

0.0295

0.089

0.008 0.004 0.004

0.13

Notes

1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

97-08-11

03-02-19

SOT190-1

Fig 33. Package outline SOT190-1 (VSO56) of PCF8576CT

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

40 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

HTSSOP56: plastic thermal enhanced thin shrink small outline package; 56 leads;

body width 6.1 mm; exposed die pad

SOT793-1

D

E

A

X

c

y

exposed die pad

H

v M

A

E

D

h

Z

56

29

(A )

3

A

2

E

h

θ

A

pin 1 index

1

L

p

L

detail X

1

28

w M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

Z

UNIT

A

b

c

D

E

e

H

L

v

w

y

θ

p

1

2

3

h

E

max.

8^o

0^o

0.15 1.05

0.05 0.80

0.27 0.20 14.1

0.17 0.09 13.9

4.3

4.1

6.2

6.0

4.3

4.1

8.3

7.9

0.8

0.4

0.1

mm

1.2

0.25

0.5

1

0.2

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-03-04

SOT793-1

143E36T

MO-153

Fig 34. Package outline SOT793-1 (HTSSOP56) of PCF8576CTT

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

41 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

15. Bare die outline

Wire bond die; 56 bonding pads; 3.0 x 2.82 x 0.38 mm

PCF8576CU/10

D

A

34

21

C1

35

20

e

X

x

0

E

y

(4)

50

8

C2

51

56

1

7

F

P

3

4

P

2

1

detail X

0

0.5

1 mm

scale

Dimensions

(3)

(1)

(2)

(1)

(2)

Unit

max

A

D

E

e

P

4

1

2

3

0.610

0.096

mm nom 0.38 2.82 3.00

min

0.110 0.097 0.110 0.097

Note

1. Pad size

2. Passivation opening

3. Dimension not drawn to scale

4. Marking code: PC8576C-1

pcf8576cu_10_do

Issue date

References

JEDEC

Outline

European

projection

version

IEC

JEITA

PCF8576CU/10

09-06-02

Fig 35. Bare die outline of PCF8576CU/10

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

42 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

Wire bond die; 56 bonding pads; 3.0 x 2.82 x 0.38 mm

PCF8576CU

D

A

34

21

C1

35

20

e

X

x

0

E

y

(4)

50

8

C2

51

56

1

7

F

P

3

4

P

2

1

detail X

0

0.5

1 mm

scale

Dimensions

(3)

(1)

(2)

(1)

(2)

Unit

max

A

D

E

e

P

4

1

2

3

0.610

0.096

mm nom 0.38 2.82 3.00

min

0.110 0.097 0.110 0.097

Note

1. Pad size

2. Passivation opening

3. Dimension not drawn to scale

4. Marking code: PC8576C-1

pcf8576cu_do

References

JEDEC

Outline

version

European

projection

Issue date

IEC

JEITA

PCF8576CU

29-06-02

Fig 36. Bare die outline of PCF8576CU

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

43 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

Bare die; 56 bumps; 3.0 x 2.82 x 0.40 mm

PCF8576CU/2

D

34

21

C1

35

20

e

X

x

E

0

y

(2)

50

8

C2

51

56

1

7

F

Y

L

A

2

A

1

b

detail X

1 mm

detail Y

0

0.5

scale

Dimensions

(1)

Unit

max

A

b

D

E

e

L

1

2

0.610

0.096

mm nom 0.398 0.0175 0.380 0.094 2.82 3.00

min

0.094

Note

1. Dimension not drawn to scale

2. Marking code: PC8576C-2

pcf8576cu_2_do

Issue date

References

Outline

European

projection

version

IEC

JEDEC

JEITA

PCF8576CU/2

09-06-02

Fig 37. Bare die outline of PCF8576CU/2

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

44 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 22. Pad and bump description for PCF8576CU

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip.

Symbol

SDA

SCL

SYNC

CLK

V_DD

OSC

A0

Pad

1

X (µm)

−74

Y (µm)

−1380

−1284

−1116

−945

−751

−485

125

Description

I²C-bus serial data input/output

I²C-bus serial clock input

cascade synchronization input/output

external clock input/output

supply voltage

2

148

3

355

4

534

5

742

6

913

internal oscillator enable input

subaddress input

7

1087

1290

1074

914

A1

8

subaddress input

A2

9

subaddress input

SA0

V_SS

V_LCD

BP0

BP2

BP1

BP3

S0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

subaddress input

logic ground

LCD supply voltage

LCD backplane output

LCD segment output

285

458

618

791

S1

951

S2

1124

1284

1380

1243

1083

910

S3

S4

S5

S6

741

S7

581

S8

408

S9

248

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

75

−85

−258

−418

−591

−751

−924

−1084

−1290

750

577

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

45 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 22. Pad and bump description for PCF8576CU

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip.

Symbol

S23

S24

S25

S26

S27

S28

S29

S30

S31

S32

S33

S34

S35

S36

S37

S38

S39

Pad

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

X (µm)

−1290

−1083

−923

Y (µm)

417

Description

LCD segment output

244

84

−89

−249

−422

−582

−755

−915

−1088

−1248

−1380

−750

−590

−417

−257

Table 23. Alignment marks

Symbol

X (µm)

−1290

−1295

1305

Y (µm)

1385

C1

C2

F

−1385

−1405

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent

standards.

17. Packing information

17.1 Tray information

Tray information for the PCF8576CU and PCF8576CU/2 is shown in Figure 38, Figure 39

and Table 24.

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PCF8576C

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Universal LCD driver for low multiplex rates

G

A

C

H

D

B

F

E

001aai237

Fig 38. Tray details

001aaj619

Fig 39. Tray alignment

Table 24. Tray dimensions

Symbol

Description

Value

A

B

C

D

pocket pitch; x direction

pocket pitch; y direction

pocket width; x direction

pocket width; y direction

5.59 mm

6.35 mm

3.22 mm

3.50 mm

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

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PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

Table 24. Tray dimensions

Symbol

Description

Value

E

F

G

H

J

tray width; x direction

tray width; y direction

50.67 mm

cut corner to pocket 1,1 center

tray thickness

5.78 mm

6.29 mm

3.94 mm

1.76 mm

2.46 mm

0.89 mm

8

K

L

tray cross section

M

x

pocket depth

number of pockets; x direction

number of pockets; y direction

y

7

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

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PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

17.2 Film frame carrier information

100

m

Saw lane

200

m

detail X

Marking code

Straight edge

of the wafer

X

013aaa112

Fig 40. Layout of wafer on ﬁlm frame carrier of PCF8576CU/10

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

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PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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PCF8576C

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Universal LCD driver for low multiplex rates

18.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 41) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 25 and 26

Table 25. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 26. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 41.

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Universal LCD driver for low multiplex rates

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 41. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

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PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

19. Abbreviations

Table 27. Abbreviations

Acronym

DC

Description

Direct Current

FFC

HBM

I²C

Film Frame Carrier

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

LCD

LSB

MM

Liquid Crystal Display

Least Signiﬁcant Bit

Machine Model

MOS

MSB

MSL

PCB

POR

RC

Metal Oxide Semiconductor

Most Signiﬁcant Bit

Moisture Sensitivity Level

Printed-Circuit Board

Power-On Reset

Resistance-Capacitance

Random Access Memory

Root Mean Square

Serial Clock Line

RAM

RMS

SCL

SDA

SMD

Serial Data Line

Surface Mount Device

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Product data sheet

Rev. 09 — 9 July 2009

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PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

20. Revision history

Table 28. Revision history

Document ID

PCF8576C_9

Modiﬁcations:

Release date

20090709

Data sheet status

Change notice

Supersedes

Product data sheet

-

PCF8576C_8

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Symbols updated and checked with NXP Symbols Library

• Changed values in limiting values table (see Table 18) from relative to absolute values

• Added TT type

• Added bare die outline drawings

• Added FFC information

• Rewritten chapter 7.3 (see Section 7.3)

PCF8576C_8

PCF8576C_7

PCF8576C_6

PCF8576C_5

PCF8576C_4

PCF8576C_3

PCF8576C_2

PCF8576C_1

20041122

20011002

19980730

19971114

19970402

19970203

19961209

19950630

Product speciﬁcation

-

PCF8576C_7

PCF8576C_6

PCF8576C_5

PCF8576C_4

PCF8576C_3

PCF8576C_2

PCF8576C_1

-

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

54 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

21. Legal information

21.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Limiting values — Stress above one or more limiting values (as deﬁned in

21.2 Deﬁnitions

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

21.3 Disclaimers

Bare die — All die are tested on compliance with their related technical

speciﬁcations as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

21.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

I²C-bus — logo is a trademark of NXP B.V.

22. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

PCF8576C_9

Product data sheet

Rev. 09 — 9 July 2009

55 of 56

PCF8576C

NXP Semiconductors

Universal LCD driver for low multiplex rates

23. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

8.3.5

8.4

Blink command. . . . . . . . . . . . . . . . . . . . . . . . 28

Display controller . . . . . . . . . . . . . . . . . . . . . . 28

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

9

Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 28

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29

10

11

11.1

11.2

Static characteristics . . . . . . . . . . . . . . . . . . . 30

Typical supply current characteristics. . . . . . . 31

Typical LCD output characteristics. . . . . . . . . 32

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

12

Dynamic characteristics. . . . . . . . . . . . . . . . . 33

Application information . . . . . . . . . . . . . . . . . 35

Cascaded operation. . . . . . . . . . . . . . . . . . . . 35

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 42

Handling information . . . . . . . . . . . . . . . . . . . 46

13

13.1

14

7

7.1

7.2

7.3

Functional description . . . . . . . . . . . . . . . . . . . 9

Power-on-reset . . . . . . . . . . . . . . . . . . . . . . . . . 9

LCD bias generator. . . . . . . . . . . . . . . . . . . . . 10

LCD voltage selector . . . . . . . . . . . . . . . . . . . 10

LCD drive mode waveforms . . . . . . . . . . . . . . 12

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 12

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 13

1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 15

1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 16

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 17

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 17

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Display register. . . . . . . . . . . . . . . . . . . . . . . . 18

Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 18

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 18

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Sub-address counter . . . . . . . . . . . . . . . . . . . 21

Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 21

Output bank selector. . . . . . . . . . . . . . . . . . . . 21

Input bank selector . . . . . . . . . . . . . . . . . . . . . 22

Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

15

7.4

16

7.4.1

7.4.2

7.4.3

7.4.4

7.5

7.5.1

7.5.2

7.6

17

17.1

17.2

Packing information . . . . . . . . . . . . . . . . . . . . 46

Tray information . . . . . . . . . . . . . . . . . . . . . . . 46

Film frame carrier information . . . . . . . . . . . . 49

18

Soldering of SMD packages . . . . . . . . . . . . . . 50

Introduction to soldering. . . . . . . . . . . . . . . . . 50

Wave and reﬂow soldering . . . . . . . . . . . . . . . 50

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 50

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 51

18.1

18.2

18.3

18.4

7.7

7.8

7.9

19

20

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 53

Revision history . . . . . . . . . . . . . . . . . . . . . . . 54

7.10

7.11

7.12

7.13

7.14

7.14.1

7.14.2

7.15

21

Legal information . . . . . . . . . . . . . . . . . . . . . . 55

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 55

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 55

21.1

21.2

21.3

21.4

22

23

Contact information . . . . . . . . . . . . . . . . . . . . 55

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8

8.1

Basic architecture . . . . . . . . . . . . . . . . . . . . . . 23

Characteristics of the I²C-bus. . . . . . . . . . . . . 23

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

START and STOP conditions . . . . . . . . . . . . . 23

System conﬁguration . . . . . . . . . . . . . . . . . . . 23

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24

PCF8576C I²C-bus controller . . . . . . . . . . . . . 25

Input ﬁlter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 25

Command decoder . . . . . . . . . . . . . . . . . . . . . 26

Mode set command . . . . . . . . . . . . . . . . . . . . 27

Load data pointer command. . . . . . . . . . . . . . 27

Device select command . . . . . . . . . . . . . . . . . 27

Bank select command . . . . . . . . . . . . . . . . . . 28

8.1.1

8.1.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.2

8.3

8.3.1

8.3.2

8.3.3

8.3.4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 9 July 2009

Document identifier: PCF8576C_9


型号：	PCF8576CTT/1,118
厂家：	NXP
描述：	PCF8576C - Universal LCD driver for low multiplex rates TSSOP 56-Pin PC 驱动 CD 光电二极管接口集成电路
文件：	总56页 (文件大小：260K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCF8576CTT/1,118 [NXP]

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