PCF8890U_技术文档

INTEGRATED CIRCUITS

DATA SHEET

PCF8890

240 + 1 outputs TFT LCD gate

driver

Objective speciﬁcation

2003 Feb 25

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

CONTENTS

1

2

3

4

5

6

7

FEATURES

APPLICATION

GENERAL DESCRIPTION

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

7.1

7.2

7.3

7.4

7.5

Power-up sequence

Shift register

I/O signal voltage levels

Pulse micro timing

Waveforms

8

PROGRAMMING

9

LIMITING VALUES

10

11

12

13

14

15

16

17

18

19

HANDLING

DC CHARACTERISTICS

AC CHARACTERISTICS

APPLICATION INFORMATION

OPEN SHORT DIAGRAMS

BONDING PAD INFORMATION

TRAY INFORMATION

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

2003 Feb 25

2

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

1

FEATURES

3

GENERAL DESCRIPTION

• Low power TFT LCD gate driver and DC/DC controller

• 240 + 1 outputs

PCF8890 is a high-voltage CMOS IC designed to drive

240 + 1 gate lines of a TFT LCD with an output voltage up

to 40 V. The device includes:

• Programmable number of active outputs from

1 to 240 + 1

• A 241-bit shift register with high-voltage output stages

• A switch matrix with 5 output levels (for 4-level driving

• 4-level gate driving, 4-level HAPD (Philips) driving

scheme (1 high and 3 low levels) and additional V_SS

step for power reduction

scheme plus V_SS

)

• An automatic reset by pin FRAMESTART

• A DC/DC controller and regulator

• On-chip DC/DC controller

• High output voltage range: V_VH= +20 V (maximum

programmed indirectly via V1 settings) and V_EE= −20 V

(minimum)

• A voltage generator for all output levels of the gate driver

and for the companion source driver (PCF8880).

The device is manufactured in a high-voltage n-well

CMOS technology.

• Row inversion with pre-pulse

• Operating frequency: up to 100 kHz

• Automatic reset for shift register by frame start

The PCF8890 is completely controlled by the PCF8880.

No interface to external controller systems is required.

• Supports line and frame inversion for gate coupled

driving

The gate driver is tailored to panels which operate with a

patented gate coupled driving. On the panel, the storage

• Low power consumption optimized for battery operation capacitor must be connected to the next row. Thus, an

extra row line is required to invert the last line of the

display.

• Slim chip layout for COG, TCP and COF applications

• Compatible with PCF8880 source driver.

2

APPLICATION

The chip set PCF8890 and PCF8880 is optimized for low

power colour TFT LCDs in portable applications such as

cellular phones, PDAs and MP3 players, instrumentation,

automotive informations system, etc. The gate driver can

be used for small to medium sized panels with up to

240 lines (e.g. 1/4 VGA) and maximal 300 pF load per line.

4

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

VERSION

PCF8890U

−

chip assembly on the glass module

chip assembly on foil (tbf)

−

2003 Feb 25

3

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

5

BLOCK DIAGRAM

andbook, full pagewidth

366

367

368

369

FRAMESTART

ROWCLK0

ROWCLK1

ROWINV

PCF8890

SHIFT

REGISTER

240

2 to 241

R1 to R240

SWITCH

MATRIX

242

360

361

362

363

364

365

370

371

R241

SYSRST_N

VBG

VBGREF

IREF

337, 338

335, 336

332, 333

330, 331

359

V1

VOLTAGE

GENERATOR

AND

V2

VCTRL0

VCTRL1

V3

CONTROL

V4

V

DDA(comp)

VOK

DCDCCLK

VH

347

349

339,

340

SWCTRL0

SWCTRL1

1)

2)

3)

4)

5)

375 376 377 378 373 374 372

TP1 TP3 TP5

dummy

V

SS

BAT

V

MDB111

TP0

TP2

TP4

TP6

EE

DD(host)

(1) dummy = 1, 243, 247 to 325, 345, 346, 350, 351, 380 and 381.

(2) _EE= 246, 327 to 329 and 382.

V

(3) V_BAT= 244, 342 to 344 and 384.

(4) V_DD(host)= 356 to 358.

(5) V_SS= 245, 326, 334, 341, 348, 352 to 355, 379 and 383.

Fig.1 Block diagram.

4

2003 Feb 25

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

6

PINNING

SYMBOL

PAD

1, 243,

TYPE⁽¹⁾

DESCRIPTION

dummy

−

247 to 325,

345, 346,

350, 351,

380, 381

R1 to R240

R241

2 to 241

O

S

row output 1 to 240; 4-level high-voltage output to the TFT gate and storage

capacitor; not connected if display with less than 240 lines is used

242

row output 241; 3-level high-voltage pre-pulse output to the storage

capacitor; not connected if display with less than 241 lines is used

V_BAT

244, 342 to

344, 384

battery supply voltage; input for DC/DC converter and power supply; connect

to battery

V_SS

245, 326,

334, 341,

348,

logic ground

352 to 355,

379, 383

V_EE

246,

S

chip bulk; generated chip bulk voltage (used for external capacitor)

327 to 329,

382

V4

V3

V2

330 to 331

332 to 333

335 to 336

S

gate low pre-pulse level output; not used and not connected (only used for

testing)

gate low-level voltage output; not used and not connected (only used for

testing)

gate high pre-pulse level output; not used and not connected (only used for

testing)

V1

337 to 338

339 to 340

347

S

O

regulated high-level voltage output; (used for external capacitor)

generated high-level voltage; (used for external capacitor)

VH

SWCTRL0

switching control 0 output; controls the external switches of the DC/DC

converter

SWCTRL1

349

O

switching control 1 output; controls the external switches of the DC/DC

converter

V_DD(host)

VOK

356 to 358

359

S

logic power supply voltage; power supply for digital circuitry

O

generated voltages status output; used for start up of voltage generator;

connect to VOK input of PCF8880

SYSRST_N

360

I

system reset input; if SYSRST_N = LOW the shift register is cleared and all

analog blocks are switched off (no high-voltage available); connect to

SYSRST_N output of PCF8880

VBG

361

362

I

band gap voltage input (1.22 V); connect to VBG output of PCF8880

VBGREF

band gap reference voltage input; high-ohmic reference voltage for band gap

(0 V); connect to VBGREF output of PCF8880

IREF

363

364

I

2.2 µA current source for analog blocks input; connect to IREF output of

PCF8880

VCTRL0

voltage control 0 input; serial data link from the source driver for

programming of the output levels; connect to VCTRL0 output of PCF8880

2003 Feb 25

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Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

SYMBOL

VCTRL1

PAD

365

TYPE⁽¹⁾

DESCRIPTION

I

voltage control 1 input; serial data link from the source driver for

programming of the output levels; connect to VCTRL1 output of PCF8880

FRAMESTART 366

I

shift register for gate signals input; connect to FRAMESTART output of

PCF8880

ROWCLK0

367

shift register clock 0 input; the shift register data is shifted on the rising edge

of ROWCLK0; connect to ROWCLK0 output of PCF8880

ROWCLK1

ROWINV

368

369

I

shift register clock 1 input; connect to ROWCLK1 output of PCF8880

pre-pulse polarity control input; if ROWINV = HIGH, the pre-pulse is

positive (V2), if ROWINV = LOW, the pre-pulse is negative (V4); connect to

ROWINV output of PCF8880

V_DDA(comp)

DCDCCLK

370

371

I

V_DDAcomparator input; this signal is used for voltage generation; connect to

V_DDA(comp)output of PCF8880

DC/DC converter chopping clock input; connect to DCDCCLK output of

PCF8880

TP6

TP5

TP4

TP3

TP2

TP1

TP0

372

373

374

375

376

377

378

I

test pin 6: connect to V_SS(used for testing)

test pin 5: connect to V_SS(used for testing)

test pin 4: connect to V_SS(used for testing)

test pin 3: connect to V_SS(used for testing)

test pin 2: connect to V_SS(used for testing)

test pin 1: connect to V_SS(used for testing)

test pin 0: connect to V_SS(used for testing)

Note

1. S = supply, O = output and I = input

2003 Feb 25

6

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

7

FUNCTIONAL DESCRIPTION

Power-up sequence

7.1

When powering up the device, a certain sequence of switching-on of the different supply voltages has to be followed (tbf).

7.2 Shift register

The shift register is controlled by the shift clock ROWCLK0.

On the rising edge of ROWCLK0, the data is shifted from R1 to R241.

7.3

I/O signal voltage levels

VH

V1

handbook, full pagewidth

R1 to R240

logic inputs

V

DD(host)

V

SS

V2

V3

V4

V

EE

MDB112

Fig.2 I/O signal voltage levels.

7.4

Pulse micro timing

handbook, full pagewidth

R(n − 1)

R(n)

R(n + 1)

ROWCLK0

ROWCLK1

ROWCLK0

ROWCLK1

DCDCCLK

MDB113

Fig.3 Pulse micro timing.

7

2003 Feb 25

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

7.5

Waveforms

1

2

3

4

5

238 239 240 241 242

handbook, full pagewidth

ROWCLK0

ROWINV

FRAMESTART

R1

R2

R239

R240

R241

MDB114

Fig.4 Shift operation.

8

2003 Feb 25

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

8

PROGRAMMING

Table 1 Row driver voltage programming; V1_maxlimited by V_EEand V_BAT(V1 = V_BAT+ V_EE); V4 steps are the same

as V3 step.

V1 (V)

MAX.

V2 (V)

MAX.

V4 (V)

MIN. MAX.

V3

PROG

V3 (V)

V_EE(V)

MIN.

STEP

MIN.

STEP

11111

11110

11101

11100

11011

11010

11001

11000

10111

10110

10101

10100

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

−8.057

−7.910

−7.769

−7.633

−7.501

−7.374

−7.251

−7.132

−7.016

−6.905

−6.797

−6.692

−6.591

−6.492

−6.397

−6.304

−6.214

−6.126

−6.041

−5.958

−5.878

−5.799

−5.723

−5.648

−5.576

−5.505

−5.436

−5.369

−5.304

−5.240

−5.177

11.25

18.750

18.599

18.358

18.124

17.897

17.676

17.462

17.254

17.052

16.855

16.664

16.477

16.296

16.119

15.947

15.779

15.616

15.456

15.300

15.148

15.000

0.5

−2.510

−2.464

−2.420

−2.377

−2.336

−2.297

−2.258

−2.221

−2.185

−2.151

−2.117

−2.084

−2.053

−2.022

−1.992

−1.964

−1.935

−1.908

−1.882

−1.856

−1.831

−1.806

−1.783

−1.759

−1.737

−1.715

−1.693

−1.672

−1.652

−1.632

−1.613

−6.494

−6.375

−6.261

−6.151

−6.045

−5.943

−5.844

−5.748

−5.655

−5.565

−5.478

−5.394

−5.312

−5.232

−5.155

−5.081

−5.008

−4.937

−4.869

−4.802

−4.737

−4.674

−4.612

−4.552

−4.494

−4.437

−4.381

−4.327

−4.274

−4.223

−4.173

−0.032

−0.031

−0.030

−0.029

−0.028

−0.027

−0.026

−0.025

−0.024

−0.023

−0.022

−0.021

−0.020

13.604 −17.588 −19.142

13.356 −17.268 −18.793

13.118 −16.959 −18.457

12.887 −16.661 −18.133

12.665 −16.374 −17.820

12.450 −16.096 −17.518

12.242 −15.827 −17.225

12.041 −15.568 −16.943

11.847 −15.316 −16.669

11.659 −15.073 −16.404

11.476 −14.837 −16.148

11.300 −14.609 −15.899

11.128 −14.387 −15.658

10.962 −14.172 −15.424

10.801 −13.964 −15.197

10.644 −13.761 −14.976

10.492 −13.564 −14.762

10.344 −13.373 −14.554

10.200 −13.187 −14.352

10.060 −13.006 −14.155

9.924

9.792

9.663

9.537

9.415

9.295

9.179

9.066

8.955

8.847

8.742

−12.830 −13.964

−12.659 −13.777

−12.492 −13.596

−12.330 −13.419

−12.172 −13.247

−12.018 −13.079

−11.867 −12.916

−11.721 −12.756

−11.578 −12.600

−11.438 −12.448

−11.302 −12.300

2003 Feb 25

9

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

9

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); see notes 1 and 2; all values with respect to

V_SS= 0 V.

SYMBOL

V_BAT

PARAMETER

CONDITION

MIN.

_SS− 0.3

MAX.

V_SS+ 7.0

UNIT

battery supply voltage

interface ground voltage

V

V_SS

_EE− 0.3

_SS− 0.3

V_EE+ 10

V_SS+ 7.0

V

V_DD(host)

interface high-voltage supply

voltage

V_EE

bulk voltage

V

_VH− 45

_EE− 0.3

_SS− 0.3

_EE− 0.3

_SS− 0.3

V_VH+ 0.3

V_EE+ 45

V_DD(host)+ 0.3

V_EE+ 45

V_DD(host)+ 0.3

V_BAT+ 0.3

+85

V

V_VH

not regulated high-voltage

band gap reference voltage

drive 1 voltage

V

V_VBGREF

V_V1

V

V_V2

drive 2 voltage

V

V_V3

drive 3 voltage

V

V_V4

drive 4 voltage

V

V_I

voltage on all digital input pins

voltage on all digital output pins

voltage on all switch control pins

voltage on all row pins

operating temperature

storage temperature

V

V_O

V

V_SWCTRL

V_R(x)

T_oper

T_stg

V

−40

−55

°C

note 3

+125

Notes

1. Stresses above those listed under limiting values may cause permanent damage to the device.

2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to

V_SSunless otherwise noted.

3. The storage temperature specifies the temperature range within which the chip will not be damaged when it is not

powered.

10 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

recommended to take standard precautions appropriate for handling MOS devices (see “Handling MOS Devices”).

2003 Feb 25

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Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

11 DC CHARACTERISTICS

V_DD(host)= 1.8 V; V_BAT= 2.7 to 4.5 V; V_SS= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_BAT

battery supply voltage

2.7

1.8

−

4.5

3.6

V

V_DD(host)

interface high-voltage

supply voltage

V

V_VH

V_EE

I_BAT

not regulated high-voltage

bulk voltage

V

_BAT− V_EE

tbf

−

V_BAT+ 18 tbf

V

−18.5

tbf

V

battery supply current

V_DD(host)= 2.7 V;

f_osc= 625 kHz;

−

µA

V_V1= 15 V;

V_V2= −4 V;

V_V2= −12 V;

V_EE= 20 V

I_BAT(idle)

idle battery supply current

V_DD(host)= 2.7 V;

f_osc= 0;

−

tbf

µA

V_V1= V_V2= V_V4= 0

V_EE= 0

I_DD(host)

I_DD(idle)

interface high-voltage

supply current

V_DD(host)= 2.7 V;

f_osc= 625 kHz

−

tbf

µA

idle interface high-voltage

supply current

V_DD(host)= 2.7 V;

f_osc= 0;

Driver outputs; pins V1, V2, V3 and V4

V_V1

V_V2

V_V3

V_V4

R_V1

R_V2

R_V3

R_V4

C_o(L)

drive 1 voltage

16 steps of 0.5 V

11.25

−

18.75

−2.5

tbf

V

drive 2 voltage

128 steps of 30 mV −6

−

V

drive 3 voltage

tbf

−8

−

V

drive 4 voltage

128 steps of 30 mV −17

−13.5

1000

300

V

drive 1 resistance

drive 2 resistance

drive 3 resistance

drive 4 resistance

output load capacitance

−

tbf

150

Ω

pF

Generated voltages status; pin VOK

V_OH

V_OL

I_O

HIGH-level output voltage

LOW-level output voltage

output current

0.8V_DD(host)

−

V_DD(host)

0.2V_DD(host)

100

V

V_SS

V

−

µA

DC/DC converter switch control outputs; pins SWCTRL0 and SWCTRL1

V_OH

V_OL

I_O

HIGH-level output voltage

LOW-level output voltage

output current

tbf

−

tbf

V

µA

2003 Feb 25

11

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

All input pins

V_IH

V_IL

I_LI

HIGH-level input voltage

LOW-level input voltage

input leakage current

0.8V_DD(host)

−

V_DD(host)

V

V_SS

0.2V_DD(host)

+5

V

−5

µA

12 AC CHARACTERISTICS

_BAT= 3.6 V; V_SS= 0 V; V_DD(host)= 1.8 V; VGON = 19 V; VGOFF = −8 V; T_amb= −40 to +85 °C; see Fig.5.

V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.

Shift register clocks; pins ROWCLK0 and ROWCLK1

UNIT

T_cy(ROWCLK0)

t_ROWCLK0(H)

t_ROWCLK0(L)

T_cy(ROWCLK1)

t_ROWCLK1[H]

t_ROWCLK1[L]

row clock0 cycle time

row clock0 HIGH time

row clock0 LOW time

row clock1 cycle time

row clock1 HIGH time

row clock1 LOW time

tbf

64

−

µs

tbf

3

µs

61

64

55

9

Shift register for gate signals; pin FRAMESTART

t_su

t_h

data set-up time

data hold time

tbf

−

ns

Row outputs; pins R1 to R241

t_d

ROWCLK delay

C_L= 300 pF

−

ns

handbook, full pagewidth

t

T

ROWCLK0(L)

ROWCLK0(H)

cy(ROWCLKO)

ROWCLK0

t

su

t

h

FRAMESTART

R(x)

t

d

MDB115

Fig.5 Timing waveforms.

2003 Feb 25

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Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

13 APPLICATION INFORMATION

handbook, full pagewidth

V4

V3

V2

V1

n.c.

C1

VH

C5

D0

C4

D1

SWCTRL0

PCF8890

V

D4

L1

DDA

to

PCF8880

V

BAT

T0

D3

SWCTRL1

C7

T1

V

SS

C6

V

EE

DC/DC converter

MDB110

C1 = 50 nF.

C4 = 33 nF.

C5 and C6 = 330 nF.

C7 = 3.3 µF.

D0 to D3 = normal diode; breakthrough voltage >20 V.

D4 = Schottky diode; breakthrough voltage >6 V.

T0 = BSS84 (pMOS VT < 2 V; R_on< 10 Ω; V_ds> 50 V).

T1 = BSH103 (nMOS VT > −1 V; R_on< 5 Ω; V_ds> 30 V).

L1 = 150 µH; R < 5 Ω; rated current >180 mA (i.e. coil craft LPO1704-15).

Fig.6 Proposal for components.

13

2003 Feb 25

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

14 OPEN SHORT DIAGRAMS

V

dbook, halfpage

V1

V3

handbook, halfpage

BAT

SWCTRL0,

SWCTRL1

R1 to R241

V

SS

MDB117

MDB118

Fig.7 Row driver outputs.

Fig.8 Switching control outputs.

V

handbook, halfpage

DD(host)

VOK

input

V

MDB120

MDB119

SS

Fig.9 Voltage status output.

Fig.10 Inputs.

2003 Feb 25

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Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

Table 2 Bonding pad locations; all x and y coordinates

are referenced to the centre of the chip

(dimensions in µm; see Fig.11)

COORDINATES

BUMP

TYPE

SYMBOL

R37

PAD

x

y

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

−5442

−5378

−5314

−5250

−5186

−5122

−5058

−4994

−4930

−4866

−4802

−4738

−4674

−4610

−4546

−4482

−4418

−4354

−4290

−4226

−4162

−4098

−4034

−3970

−3906

−3842

−3778

−3714

−3586

−3522

−3458

−3394

−3330

−3266

−3202

−3138

−3074

−3010

−2946

+1153

2

COORDINATES

BUMP

SYMBOL

dummy

PAD

R38

R39

R40

R41

R42

R43

R44

R45

R46

R47

R48

R49

R50

R51

R52

R53

R54

R55

R56

R57

R58

R59

R60

R61

R62

R63

R64

R65

R66

R67

R68

R69

R70

R71

R72

R73

R74

R75

TYPE

x

y

1

−8002

−7746

−7682

−7618

−7554

−7490

−7426

−7362

−7298

−7234

−7170

−7106

−7042

−6978

−6914

−6850

−6786

−6722

−6658

−6594

−6530

−6466

−6402

−6338

−6274

−6210

−6146

−6082

−6018

−5954

−5890

−5826

−5762

−5698

−5634

−5570

−5506

+1153

1

2

R1

2

R2

3

R3

4

R4

5

R5

6

R6

7

R7

8

R8

9

R9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

R31

R32

R33

R34

R35

R36

2003 Feb 25

16

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

COORDINATES

BUMP

COORDINATES

BUMP

TYPE

SYMBOL

R76

PAD

SYMBOL

R115

PAD

TYPE

x

y

x

y

77

78

−2882

−2818

−2754

−2690

−2626

−2562

−2498

−2434

−2370

−2306

−2242

−2178

−2114

−2050

−1986

−1922

−1858

−1794

−1730

−1666

−1602

−1538

−1474

−1410

−1346

−1282

−1218

−1154

−1090

−1026

−962

+1153

2

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

−386

−322

+1153

2

R77

R116

R117

R118

R119

R120

R121

R122

R123

R124

R125

R126

R127

R128

R129

R130

R131

R132

R133

R134

R135

R136

R137

R138

R139

R140

R141

R142

R143

R144

R145

R146

R147

R148

R149

R150

R151

R152

R153

R78

79

−258

R79

80

−194

R80

81

−130

R81

82

−66

R82

83

−2

R83

84

+62

R84

85

+126

R85

86

+190

R86

87

+254

R87

88

+318

R88

89

+382

R89

90

+446

R90

91

+574

R91

92

+638

R92

93

+702

R93

94

+766

R94

95

+830

R95

96

+894

R96

97

+958

R97

98

+1022

+1086

+1150

+1214

+1278

+1342

+1406

+1470

+1534

+1598

+1662

+1726

+1790

+1854

+1918

+1982

+2046

+2110

R98

99

R99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

R100

R101

R102

R103

R104

R105

R106

R107

R108

R109

R110

R111

R112

R113

R114

−898

−834

−770

−706

−642

−578

−514

−450

2003 Feb 25

17

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

COORDINATES

BUMP

COORDINATES

BUMP

TYPE

SYMBOL

R154

PAD

SYMBOL

R193

PAD

TYPE

x

y

x

y

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

+2174

+2338

+2302

+2366

+2430

+2494

+2558

+2622

+2686

+2750

+2814

+2878

+2942

+3006

+3070

+3134

+3198

+3262

+3326

+3390

+3454

+3518

+3582

+3646

+3710

+3774

+3838

+3902

+3966

+4030

+4094

+4158

+4222

+4286

+4350

+4414

+4478

+4542

+4606

+1153

2

194

195

196

197

198

199

200

201

202+

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

+4734

+4798

+4862

+4926

+4990

+5054

+5118

+5182

+5246

+5310

+5374

+5438

+5502

+5566

+5630

+5694

+5758

+5822

+5886

+5950

+6014

+6078

+6142

+6206

+6270

+6334

+6398

+6462

+6526

+6590

+6654

+6718

+6782

+6846

+6910

+6974

+7038

+7102

+7166

+1153

2

R155

R156

R157

R158

R159

R160

R161

R162

R163

R164

R165

R166

R167

R168

R169

R170

R171

R172

R173

R174

R175

R176

R177

R178

R179

R180

R181

R182

R183

R184

R185

R186

R187

R188

R189

R190

R191

R192

R194

R195

R196

R197

R198

R199

R200

R201

R202

R203

R204

R205

R206

R207

R208

R209

R210

R211

R212

R213

R214

R215

R216

R217

R218

R219

R220

R221

R222

R223

R224

R225

R226

R227

R228

R229

R230

R231

2003 Feb 25

18

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

COORDINATES

BUMP

COORDINATES

BUMP

TYPE

SYMBOL

R232

PAD

SYMBOL

dummy

PAD

TYPE

x

y

x

y

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

+7230

+7294

+7358

+7422

+7486

+7550

+7614

+7678

+7742

+7806

+7998

+7773

+7663

+7553

+7443

+7223

+7113

+7003

+6893

+6783

+6673

+6563

+6453

+6343

+6233

+6123

+6013

+5903

+5793

+5683

+5573

+5463

+5353

+5243

+5133

+5023

+4913

+4803

+4693

+1153

−1232

2

3

4

5

6

7

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

+4583

+4473

+4363

+4253

+4143

+4033

+3923

+3813

+3703

+3593

+3483

+3373

+3263

+3153

+3043

+2933

+2823

+2713

+2603

+2493

+2383

+2273

+2163

+2053

+1943

+1833

+1723

+1613

+1503

+1393

+1283

+1173

+1063

+953

−1232

7

R233

dummy

R234

R235

R236

R237

R238

R239

R240

R241

dummy

V_BAT

V_SS

V_EE

dummy

+843

+733

+623

+513

+403

2003 Feb 25

19

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

COORDINATES

BUMP

COORDINATES

BUMP

TYPE

SYMBOL

dummy

PAD

SYMBOL

dummy

PAD

TYPE

x

y

x

y

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

+293

+183

−1232

7

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

−3997

−4107

−4217

−4327

−4437

−4547

−4657

−4667

−4877

−4987

−5097

−5207

−5317

−5427

−5537

−5647

−5757

−5867

−5977

−6087

−6197

−6307

−6417

−6527

−6637

−6747

−6857

−6967

−7077

−7187

−7297

−7407

−7517

−7627

−7737

−1232

10

15

17

6

dummy

V_SS

dummy

V_SS

+73

7

−37

7

V_SS

−147

7

V_SS

−257

7

V_SS

−367

7

V_DD(host)

VOK

−477

7

−587

7

−697

7

−807

7

SYSRST_N

VBG

6

−917

7

6

−1027

−1137

−1247

−1357

−1467

−1577

−1687

−1797

−1907

−2017

−2127

−2237

−2347

−2457

−2567

−2677

−2787

−2897

−3007

−3117

−3227

−3337

−3447

−3557

−3667

−3777

−3887

7

VBGREF

IREF

6

7

6

7

VCTRL0

VCTRL1

FRAMESTART

ROWCLK0

ROWCLK1

ROWINV

V_DDA(comp)

DCDCCLK

TP6

6

8

6

V_EE

9

6

V_EE

9

6

V_EE

9

6

V4

10

11

8

6

V4

6

V3

6

V3

6

V_SS

TP4

6

V2

12

13

14

15

10

6

TP5

6

V2

TP0

6

V1

TP1

6

V1

TP2

6

VH

TP3

6

VH

V_SS

18

6

V_SS

dummy

V_EE

V_BAT

6

V_BAT

19

20

21

V_BAT

V_SS

dummy

SWCTRL0

V_SS

V_BAT

16

6

SWCTRL1

2003 Feb 25

20

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

Table 3 Bonding pad information

Table 4 Bump dimensions

ITEM

DIMENSIONS

BUMP TYPE

h (µm)

Pad pitch

64 µm

3

333

234

273

106

180

344

113

212

245

278

179

311

410

442

166

512

272

233

383

Bump dimension

Chip size

see Fig.12

4

16300 × 2950 µm

380 µm

5

Wafer thickness (bumps

not included)

6

7

8

9

bump type 1

40 µm

bump type 2

40 µm

bump types 3-22

10

11

12

13

14

15

16

17

18

19

20

21

40 µm

4 µm

1)

100 µm

59 µm

100 µm

h

4 µm

V3

V4

4 µm

59 µm

MDB116

(1) see Table 4

Fig.12 Bump dimensions.

16 TRAY INFORMATION

handbook, halfpage

PCF8890V1

MDB122

Fig.13 Chip orientation.

2003 Feb 25

21

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

17 DATA SHEET STATUS

DATA SHEET

STATUS⁽¹⁾

PRODUCT

STATUS⁽²⁾⁽³⁾

LEVEL

DEFINITION

I

Objective data

Development This data sheet contains data from the objective speciﬁcation for product

development. Philips Semiconductors reserves the right to change the

speciﬁcation in any manner without notice.

II

Preliminary data Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the speciﬁcation without

notice, in order to improve the design and supply the best possible

product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips

Semiconductors reserves the right to make changes at any time in order

to improve the design, manufacturing and supply. Relevant changes will

be communicated via a Customer Product/Process Change Notiﬁcation

(CPCN).

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

18 DEFINITIONS

19 DISCLAIMERS

Short-form specification

The data in a short-form

Life support applications

These products are not

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -

including circuits, standard cells, and/or software -

described or contained herein in order to improve design

and/or performance. When the product is in full production

(status ‘Production’), relevant changes will be

Application information

Applications that are

communicated via a Customer Product/Process Change

Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these

products, conveys no licence or title under any patent,

copyright, or mask work right to these products, and

makes no representations or warranties that these

products are free from patent, copyright, or mask work

right infringement, unless otherwise specified.

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

no representation or warranty that such applications will be

suitable for the specified use without further testing or

modification.

2003 Feb 25

22

Philips Semiconductors

Objective speciﬁcation

240 + 1 outputs TFT LCD gate driver

PCF8890

Bare die

All die are tested and are guaranteed to

control of third party procedures in the sawing, handling,

packing or assembly of the die. Accordingly, Philips

Semiconductors assumes no liability for device

functionality or performance of the die or systems after

third party sawing, handling, packing or assembly of the

die. It is the responsibility of the customer to test and

qualify their application in which the die is used.

comply with all data sheet limits up to the point of wafer

sawing for a period of ninety (90) days from the date of

Philips' delivery. If there are data sheet limits not

guaranteed, these will be separately indicated in the data

sheet. There are no post packing tests performed on

individual die or wafer. Philips Semiconductors has no

2003 Feb 25

23

Philips Semiconductors – a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

SCA75

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

403512/01/pp24

Date of release: 2003 Feb 25

Document order number: 9397 750 10898


型号：	PCF8890U
厂家：	NXP
描述：	IC LIQUID CRYSTAL DISPLAY DRIVER, U, UUC-381, Display Driver 驱动接口集成电路
文件：	总24页 (文件大小：99K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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