PCK2010RADL-T [NXP]
IC 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56, 7.50 MM, PLASTIC, SSOP-56, Clock Generator;型号: | PCK2010RADL-T |
厂家: | NXP |
描述: | IC 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56, 7.50 MM, PLASTIC, SSOP-56, Clock Generator 时钟发生器 |
文件: | 总16页 (文件大小:117K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCK2010
CK98 (100/133MHz) Spread Spectrum
System Clock Generator
Preliminary specification
1999 Mar 01
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
FEATURES
PIN CONFIGURATION
• Mixed 2.5V and 3.3V operation
V
1
2
3
4
5
6
7
8
9
56 VDD25V
55 APIC2
54 APIC1
53 APIC0
SS
• Four CPU clocks at 2.5V
REF0
REF1
• Eight PCI clocks at 3.3V, one free-running
(synchronous with CPU clocks)
VDD3V
• Four 3.3V fixed clocks @ 66MHz
• Two 2.5V CPUDIV2 clocks @ ½ CPU clock frequency
• Three 2.5V IOAPIC clocks @ 16.67 MHz
• One 3.3V 48MHz USB clock
XTAL_IN
XTAL_OUT
52
V
SS
51 VDD25V
V
CPUDIV2_1
50
49
48
SS
PCICLK_F
PCICLK1
CPUDIV2_0
V
SS
• Two 3.3V reference clocks @ 14.318 MHz
• Reference 14.31818 MHz Xtal oscillator input
• 133 MHz or 100 MHz operation
VDD3V 10
PCICLK2 11
PCICLK3 12
47 VDD25V
CPUCLK3
46
45 CPUCLK2
V
13
44
43
42
41
40
39
38
37
V
SS
SS
• Power management control input pins
• LOW CPU clock jitter ≤ 250 ps cycle-cycle
• LOW skew outputs
PCICLK4 14
PCICLK5 15
VDD25V
CPUCLK1
CPUCLK0
VDD3V 16
PCICLK6 17
V
SS
• 0.0ns – 1.5ns CPU - 3V66 delay
PCICLK7 18
VDD3V
V
V
19
20
V
• 1.5ns – 4.0ns 3V66 - PCI delay
SS
SS
SS
PCISTOP
• 1.5ns – 4.0 ns CPU - IOAPIC delay
• Available in 56-pin SSOP package
36 CPUSTOP
35
3V66_0 21
3V66_1
22
VDD3V 23
24
PWRDWN
• ±0.5% center spread spectrum capability via select pins; –0.5%
34 SPREAD
33 SEL1
down spread spectrum capability via select pins
V
SS
3V66_2 25
3V66_3 26
32 SEL0
DESCRIPTION
31 VDD3V
The PCK2010 is a clock synthesizer/driver chip for a PentiumII and
other similar processors.
30
29
VDD3V 27
48MHz
SEL133/100 28
V
SS
The PCK2010 has four CPU clock outputs at 2.5V, two CPUDIV2
clock outputs running at ½ CPU clock frequency (66MHz or 50MHz
depending on the state of SEL133/100) and four 3V66 clocks
running at 66MHz. There are eight PCI clock outputs running at
33MHz. One of the PCI clock outputs is free-running. Additionally,
the part has three 2.5V IOAPIC clock outputs at 16.67MHz and two
3.3V reference clock outputs at 14.318MHz. All clock outputs meet
Intel’s drive strength, rise/fall time, jitter, accuracy, and skew
requirements.
SW00352
The part possesses dedicated power-down, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on-chip and ensure glitch-free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs and
3V66 clock outputs are driven LOW. When the PCISTOP input is
asserted, the PCI clock outputs are driven LOW.
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA NORTH AMERICA
PCK2010 DL PCK2010 DL
DRAWING NUMBER
56-Pin Plastic SSOP
0°C to +70°C
SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
PIN DESCRIPTION
PIN NUMBER
SYMBOL
REF [0–1]
XTAL_IN
FUNCTION
3.3V 14.318 MHz clock output
2,3
5
14.318 MHz crystal input
14.318 MHz crystal output
3.3V free running PCI clock
3.3V PCI clock outputs
6
8
XTAL_OUT
PCICLK_F
PCICLK [1–7]
3V66 [0–3]
9, 11, 12, 14, 15, 17, 18
21, 22, 25, 26
3.3V fixed 66MHz clock outputs
Select input pin for enabling 133MHz or 100MHz CPU outputs.
H = 133MHz, L = 100MHz
28
SEL133/100
30
48MHz
3.3V fixed 48MHZ clock output
Logic select pins. TTL levels.
32, 33
SEL [0–1]
3.3V LVTTL input. Enables spread spectrum mode when held
LOW.
34
SPREAD
PWRDWN
3.3V LVTTL input. Device enters powerdown mode when held
LOW.
35
36
3.3V LVTTL input. Stops all CPU clocks and 3V66 clocks when
held LOW. CPUDIV_2 output remains on all the time.
CPUSTOP
3.3V LVTTL input. Stops all PCI clocks except PCICLK_F when
held LOW.
37
PCISTOP
2.5V CPU output. 133MHz or 100MHz depending on state of input
pin SEL133/100.
41, 42, 45, 46
49, 50
CPUCLK [0–3]
CPUDIV_2 [0–1]
IOAPIC [0–2]
2.5V output running at 1/2 CPU clock frequency. 66MHz or 50MHz
depending on state of input pin SEL133/100.
2.5V clock outputs running divide synchronous with the CPU clock
frequency. Fixed 16.67 MHz limit.
53, 54, 55
4, 10, 16, 23, 27, 31, 39
V
3.3V power supply.
Ground
DD3V
1, 7, 13, 19, 20, 24, 29, 38, 40, 44,
48, 52
V
SS
43, 47, 51, 56
V
DD25V
2.5V power supply
NOTES:
1. V
, V
and V in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise
DD3V DD25V SS
on the performance of the device. In reality, the platform will be configured with the V
pins tied to a 2.5V supply, all remaining V pins
DD
DD25V
tied to a common 3.3V supply and all V pins being common.
SS
3
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
BLOCK DIAGRAM
LOGIC
PWRDWN
LOGIC
REF [0–1](14.318 MHz)
X
XTAL_IN
X
X
14.318
MHZ
OSC
XTAL_OUT
PWRDWN
LOGIC
X
X
USBPLL
SYSPLL
48MHz
STOP
STOP
CPUCLK [0–3]
3V66 [0–3] (66MHz)
X
X
LOGIC
PWRDWN
LOGIC
CPUDIV2 [0–1]
SEL0 X
SEL1 X
SPREAD X
PWRDWN
LOGIC
PCICLK_F (33MHz)
PCICLK [1–7] (33MHz)
APIC [0–2] (½ PCI)
X
X
X
X
X
X
SEL133/100
PCISTOP
CPUSTOP
STOP
PWRDWN
X
PWRDWN
LOGIC
SW00353
4
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
168-pin SDR SDRAM DIMM
BACK SIDE
FRONT SIDE
AVC
AVC
AVC
PCK2509S or PCK2510S
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00403
FUNCTION TABLE
SEL
SEL1 SEL0
133/100
CPU
CPUDIV2
3V66
PCI
48MHz
REF
IOAPIC
NOTES
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
1
0
N/A
2
3
0
100MHz
100MHz
TCLK/2
N/A
50MHz
50MHz
TCLK/4
N/A
66MHz
66MHz
TCLK/4
N/A
33MHz
33MHz
TCLK/8
N/A
HI-Z
14.318MHz
14.318MHz
TCLK
16.67MHz
16.67MHz
TCLK/16
N/A
0
48MHz
TCLK/2
N/A
4, 7, 8
5, 6
2
1
1
N/A
1
1
133MHz
133MHz
66MHz
66MHz
66MHz
66MHz
33MHz
33MHz
HI-Z
14.318MHz
14.318MHz
16.67MHz
16.67MHz
3
48MHz
4, 7, 8
NOTES:
1. Required for board level ‘‘bed-of-nails” testing.
2. Used to support Intel confidential application.
3. 48MHz PLL disabled to reduce component jitter. 48MHz outputs to be held Hi-Z instead of driven to LOW state.
4. ‘‘Normal” mode of operation.
5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133MHz CPU select logic.
6. Required for DC output impedance verification.
7. Frequency accuracy of 48MHz must be +167 PPM to match USB default.
8. Range of reference frequency allowed is MIN = 14.316MHz, NOMINAL = 14.31818MHz, MAX = 14.32MHz
CLOCK OUTPUT
TARGET FREQUENCY (MHz)
ACTUAL FREQUENCY (MHz)
PPM
7
USBCLK
48.0
48.008
167
5
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
CLOCK ENABLE CONFIGURATION
CPUSTOP
PWRDWN
PCISTOP
CPUCLK
LOW
LOW
LOW
ON
CPUDIV2
LOW
ON
APIC 3V66
PCI
LOW
LOW
ON
PCIF REF 48MHz OSC VCOs
X
0
0
1
1
0
1
1
1
1
X
0
1
0
1
LOW
ON
LOW
LOW
LOW
ON
LOW
ON
LOW
ON
OFF
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
LOW
ON
ON
ON
ON
ON
ON
ON
ON
ON
NOTES:
1. LOW means outputs held static LOW as per latency requirement below
2. ON means active.
3. PWRDWN pulled LOW, impacts all outputs including REF and 48MHz outputs.
4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW.
5. CPUDIV2, IOAPIC, REF, 48MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when
PWRDWN is LOW.
POWER MANAGEMENT REQUIREMENTS
LATENCY
SIGNAL
CPUSTOP
PCISTOP
PWRDWN
SIGNAL STATE
NO. OF RISING EDGES OF FREE RUNNING
PCICLK
0 (DISABLED)
1 (ENABLED)
1
1
1
0 (DISABLED)
1 (ENABLED)
1
1 (NORMAL OPERATION)
0 (POWER DOWN)
3ms
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to V (V = 0V)
SS
SS
LIMITS
MAX
SYMBOL
PARAMETER
CONDITION
UNIT
MIN
–0.5
–0.5
–0.5
V
DD3
DC 3.3V core supply voltage
DC 3.3V I/O supply voltage
DC 2.5V I/O supply voltage
DC input diode current
+4.6
+4.6
+3.6
–50
5.5
V
V
V
DDQ3
V
DDQ2
V
I
IK
V < 0
I
mA
V
V
I
DC input voltage
Note 2
–0.5
–0.5
–65
I
DC output diode current
DC output voltage
V
O
> V or V < 0
±50
mA
V
OK
CC
O
V
O
Note 2
V
CC
+ 0.5
I
O
DC output source or sink current
Storage temperature range
V
O
= 0 to V
CC
±50
mA
°C
T
STG
+150
Power dissipation per package
plastic medium-shrink (SSOP)
For temperature range: –40 to +125°C
above +55°C derate linearly with 11.3mW/K
P
TOT
850
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
RECOMMENDED OPERATING CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
V
DC 3.3V core supply voltage
DC 2.5V I/O supply voltage
3.135
2.375
3.465
2.625
V
V
DD3V
V
DD25V
Capacitive load on:
CPUCLK
PCICLK
1 device load, possible 2 loads
Must meet PCI 2.1 requirements
1 device load, possible 2 loads
1 device load, possible 2 loads
1 device load
10
10
10
10
10
10
10
20
30
20
30
20
20
20
CPUDIV2
3V66
48MHz clock
REF
C
pF
L
1 device load
1 device load
IOAPIC
V
DC input voltage range
DC output voltage range
0
0
V
V
V
I
DD3V
V
DD25V
V
O
V
DD3V
f
Reference frequency, oscillator nominal value
Operating ambient temperature range in free air
14.31818 14.31818
+70
MHz
REF
T
0
°C
amb
POWER MANAGEMENT
MAXIMUM 2.5V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS, V = 2.625V
MAXIMUM 3.3V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS, V = 3.465V
CK133
CONDITION
DD25V
DD25V
ALL STATIC INPUTS = V
OR V
ALL STATIC INPUTS = V OR V
DD3V SS
DD3V
SS
Power-down mode
(PWRDWN = 0)
100µA
200µA
Full active 100MHz
SEL133/100# = 0
SEL1, 0 = 1 1
75mA
90mA
160mA
160mA
CPUSTOP, PCISTOP = 1
Full active 133MHz
SEL133/100# = 1
SEL1, 0 = 1 1
CPUSTOP, PCISTOP = 1
7
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
DC CHARACTERISTICS
LIMITS
= 0°C to +70°C
TEST CONDITIONS
T
amb
UNIT
SYMBOL
PARAMETER
V
(V)
DD
OTHER
MIN
TYP
MAX
+ 0.3
V
=
DD25V
V
HIGH level input voltage
LOW level input voltage
3.135 to 3.465
2.0
V
V
V
IH
DD
2.5V ±5%
V
=
DD3V
V
3.135 to 3.465
2.375 to 2.625
V
SS
– 0.3
0.8
IL
3.3V ±5%
2.5V output HIGH voltage
CPUCLK, IOAPIC,
CPUDIV2
V
OH2
I
I
= –1mA
= 1mA
2.0
–
–
V
V
OH
2.5V output LOW voltage
CPUCLK, IOAPIC,
CPUDIV2
V
OL2
2.375 to 2.625
I
OL
0.4
3.3V output HIGH voltage
REF, 48MHz
V
OH3
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
= –1mA
= 1mA
2.0
–
–
0.4
–
V
V
V
V
OH
3.3V output LOW voltage
REF, 48MHz
V
OL3
I
OL
3.3V output HIGH voltage
PCI, 3V66
V
OH3
I
= –1mA
2.4
–
OH
3.3V output LOW voltage
PCI, 3V66
V
OL3
I
= 1mA
0.55
OL
2.375
2.625
3.135
3.465
3.135
3.465
2.375
2.625
3.135
3.465
3.135
3.465
3.465
V
= 1.0V
–27
–
–
–27
–
OUT
CPUCLK
output HIGH current
I
I
I
mA
mA
mA
mA
mA
mA
OH
V
OUT
= 2.375V
= 1.0V
V
OUT
–29
–
48MHz, REF
output HIGH current
OH
OH
V
OUT
= 3.135V
= 1.0V
–23
–
V
OUT
–33
–
PCI, 3V66
output HIGH current
V
OUT
= 3.135V
= 1.2V
–33
–
V
OUT
V
OUT
27
–
CPUCLK
output LOW current
I
I
I
OL
OL
OL
= 0.3V
30
–
V
OUT
= 1.95V
= 0.4V
29
–
48MHz, REF
output LOW current
V
OUT
27
–
V
OUT
= 1.95V
= 0.4V
30
–
PCI, 3V66
output LOW current
V
OUT
38
5
±I
Input leakage current
–
µA
µA
pF
pF
I
3-State output OFF-State
current
V
dd
=
OUT
±I
3.465
I
= 0
–
10
5
OZ
O
V
or GND
Cin
Input pin capacitance
Xtal pin capacitance, as
seen by external crystal
Cxtal
Cout
18
Output pin capacitance
Operating supply current
Powerdown supply current
Operating supply current
Powerdown supply current
6
pF
mA
mA
µA
1
1
100MHz mode
133MHz mode
Outputs loaded
Outputs loaded
160
160
200
160
160
100
I
I
3.465
2.625
dd3
All static inputs to V
or GND
DD
1
100MHz mode
133MHz mode
Output loaded
Output loaded
mA
mA
µA
1
dd2
All static inputs to V
or GND
DD
NOTE:
1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section.
8
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
AC CHARACTERISTICS
DD3V
V
= 3.3V ± 5%; VDDAPIC = V
= 2.5V ± 5%; f
= 14.31818 MHz
crystal
DD25V
CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF)
LIMITS
= 0°C to +70°C
LIMITS
= 0°C to +70°C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133MHz MODE
100MHz MODE
MIN
7.5
MAX
8.0
n/a
n/a
1.6
1.6
250
55
MIN
10.0
3.0
MAX
10.5
n/a
T
T
CPUCLK period
CPUCLK HIGH time
CPUCLK LOW time
CPUCLK rise time
ns
ns
ns
ns
ns
ps
%
2, 9
5, 10
6, 10
8
HKP
1.87
1.67
0.4
HKH
T
2.8
n/a
HKL
T
T
0.4
1.6
HRISE
HFALL
JITTER
CPUCLK fall time
0.4
0.4
1.6
8
T
CPUCLK cycle-cycle jitter
Output Duty Cycle
250
55
DUTY CYCLE
45
45
1
2
T
CPUCLK pin-pin skew
175
175
ps
HSKW
CPUDIV2 CLOCK OUTPUTS, CPUDIV2 (0–1) (LUMP CAPACITANCE TEST LOAD = 20pF)
LIMITS
= 0°C to +70°C
LIMITS
= 0°C to +70°C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133MHz MODE
100MHz MODE
MIN
15.0
5.25
5.05
0.4
MAX
16.0
n/a
MIN
20.0
7.5
MAX
21.0
n/a
T
T
CPUDIV2 CLK period
CPUDIV2 CLK HIGH time
CPUDIV2 CLK LOW time
CPUDIV2 CLK rise time
ns
ns
ns
ns
ns
ps
%
2, 9
5, 10
6, 10
8
HKP
HKH
T
n/a
7.3
n/a
HKL
T
T
1.6
0.4
1.6
HRISE
HFALL
JITTER
CPUDIV2 CLK fall time
0.4
1.6
0.4
1.6
8
T
CPUDIV2 CLK cycle-cycle jitter
CPUDIV2 CLK Duty Cycle
CPUDIV2 CLK pin-pin skew
250
55
250
55
DUTY CYCLE
45
45
1
2
T
175
175
ps
HSKW
PCI CLOCK OUTPUTS, PCI(0–7) (LUMP CAPACITANCE TEST LOAD = 30pF)
LIMITS
= 0°C to +70°C
LIMITS
= 0°C to +70°C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133MHz MODE
100MHz MODE
MIN
30.0
12.0
12.0
0.5
MAX
n/a
n/a
n/a
2.0
2.0
500
55
MIN
30.0
12.0
12.0
0.5
MAX
n/a
n/a
n/a
2.0
2.0
500
55
T
T
PCICLK period
PCICLK HIGH time
PCICLK LOW time
PCICLK rise time
ns
ns
ns
ns
ns
ps
%
2, 9
5, 10
6, 10
8
HKP
HKH
T
HKL
T
T
HRISE
HFALL
JITTER
PCICLK fall time
0.5
0.5
8
T
PCICLK cycle-cycle jitter
PCICLK Duty Cycle
PCICLK pin-pin skew
DUTY CYCLE
45
45
1
2
T
500
500
ps
HSKW
9
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
LIMITS
= 0°C to +70°C
LIMITS
= 0°C to +70°C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133MHz MODE
100MHz MODE
MIN
MAX
64.0
n/a
MIN
MAX
64.0
n/a
T
T
IOAPIC CLK period
IOAPIC CLK HIGH time
IOAPIC CLK LOW time
IOAPIC CLK rise time
60.0
25.5
25.3
0.4
60.0
25.5
25.3
0.4
ns
ns
ns
ns
ns
ps
%
2, 9
5, 10
6, 10
8
HKP
HKH
T
n/a
n/a
HKL
T
T
1.6
1.6
HRISE
HFALL
JITTER
IOAPIC CLK fall time
0.4
1.6
0.4
1.6
8
T
IOAPIC CLK cycle-cycle jitter
IOAPIC CLK Duty Cycle
IOAPIC CLK pin-pin skew
500
55
500
55
DUTY CYCLE
45
45
1
2
T
250
250
ps
HSKW
3V66 CLOCK OUTPUT, 3V66 (0–3) (LUMP CAPACITANCE TEST LOAD = 30 pF)
LIMITS
= 0°C to +70°C
LIMITS
= 0°C to +70°C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133MHz MODE
100MHz MODE
MIN
MAX
16.0
n/a
MIN
MAX
16.0
n/a
T
T
3V66 CLK period
3V66 CLK HIGH time
3V66 CLK LOW time
3V66 CLK rise time
15.0
5.25
5.05
0.4
15.0
5.25
5.05
0.4
ns
ns
ns
ns
ns
ps
%
2, 9, 4
5, 10
6, 10
8
HKP
HKH
T
n/a
n/a
HKL
T
T
1.6
1.6
HRISE
HFALL
JITTER
3V66 CLK fall time
0.4
1.6
0.4
1.6
8
T
3V66 CLK cycle-cycle jitter
3V66 CLK Duty Cycle
3V66 CLK pin-pin skew
500
55
500
55
DUTY CYCLE
45
45
1
2
T
250
250
ps
HSKW
48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
LIMITS
= 0°C to +70°C
TEST CONDITIONS
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
MIN
MAX
Determined by PLL
divider ratio
f
Frequency, Actual
48.008
+167
MHz
f
Deviation from 48MHz
Output rise edge rate
Output fall edge rate
Duty Cycle
(48.008 – 48)/48
ppm
ns
D
T
(t )
1
1
4
4
HRISE
R
T
(t )
F
ns
HFALL
DUTY CYCLE (t )
45
55
%
D
133MHz
100MHz
MAX
T
CLK cycle-cycle jitter
MIN
MAX
MIN
ps
JITTER
500
500
3
T
(f
)
Frequency stabilization from Power-up (cold start)
ms
HSTB ST
NOTES:
1. See Figure 3 for measure points.
10
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
AC CHARACTERISTICS (Continued)
LIMITS
= 0°C to +70°C
TEST CONDITIONS
T
amb
SYMBOL
PARAMETER
UNIT NOTES
Measurement loads
(lumped)
Measure points
MIN
0.0
1.5
1.5
TYP
MAX
CPUCLK to 3V66 CLK, CPU
leads
CPU@30pF,
3V66@30pF
CPU@1.25V,
3V66@1.5V
T
1.5
3.5
4.0
ns
ns
ns
ns
ns
ns
ns
1
1
1
HPOFFSET
HPOFFSET
HPOFFSET
3V66 CLK to PCICLK, 3V66
leads
3V66@30pF,
PCI@30pF
3V66@1.5V,
PCI@1.5V
T
T
CPUCLK to IOAPIC, CPU
leads
CPU@20pF,
IOAPIC@20pF
3CPU@1.25V,
IOAPIC@1.25V
PCICLK to CPUCLK, CPU
leads
PCI@30pF
CPU@30pF
PCI@1.5V
CPU@1.25V
5.8
1.6
3.7
1.7
CPUDIV2 to CPUCLK,
CPUDIV2 leads
CPUDIV2@20pF
CPU@30pF
CPUDIV2@
CPU@1.25V
IOAPICCLK to CPUCLK,
IOAPIC leads
IOAPIC@20pF
CPU@30pF
IOAPIC@20pF
CPU@1.25V
3V66 CLK to CPUCLK, 3V66
leads
3V66@30pF
CPU@30pF
3V66@1.5V
CPU@1.25V
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified V /V levels.
OL OH
2. Period, jitter, offset and skew measured on rising edge @1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. The PCICLK is the CPUCLK divided by four at CPUCLK = 133.MHz. The 3V66 CLK is internal VCO frequency divided by three at CPUCLK
= 100MHz.
4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100MHz.
5. T
6. T
is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs as shown in Figure 4.
is measured at 0.4V for all outputs as shown in Figure 4.
HKH
HKL
7. The time is specified from when V
achieves its nominal operating level (typical condition V
= 3.3V) until the frequency output is
DDQ
DDQ
stable and operating within specification.
8. T and T are measured as a transition through the threshold region V = 0.4V and V = 2.4V (1mA) JEDEC specification.
HRISE
HFALL
OL
OH
9. The average period over any 1 µs period of time must be greater than the minimum specified period.
10.Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
duty-cycle specification is met.
11. Output (see Figure 3 for measure points).
PCK2010 SPREAD SPECTRUM FUNCTION TABLE
Philips
PCK2010
SPREAD#
pin 34
SEL133/100#
pin 28
SEL1 SEL0
pin 33 pin 32
Intel CK133
Function
Intel CK133
48MHz PLL
Philips PCK2010
Function
48MHz PLL
3-State to
High Impedance
3-State to
High Impedance
0 (active)
0 (active)
0 (active)
0 (100MHz)
0 (100MHz)
0 (100MHz)
0
0
1
0
1
0
Inactive
Inactive
Active
100MHz, Center
Spread ±0.5%
(Reserved)
(Reserved)
Inactive
100MHz, Down
Spread – 0.5%
100MHz, Down
Spread – 0.5%
Inactive
100MHz, Down
Spread – 0.5%
100MHz, Down
Spread – 0.5%
0 (active)
0 (active)
0 (active)
0 (100MHz)
1 (133MHz)
1 (133MHz)
1
0
0
1
0
1
Active
Active
Active
Active
Test Mode
Active
Test Mode
133MHz, Center
Spread ±0.5%
(Reserved)
(Reserved)
133Mhz, Down
Spread – 0.5%
133MHz, Down
Spread – 0.5%
0 (active)
0 (active)
1 (133MHz)
1 (133MHz)
1
1
0
0
1
0
Inactive
Active
Inactive
Active
133Mhz, Down
Spread – 0.5%
133MHz, Down
Spread – 0.5%
3-State to
High Impedance
3-State to
High Impedance
1 (inactive) 0 (100MHz)
Inactive
Inactive
11
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
100MHz, No Center
Spread ±0.5%
1 (inactive) 0 (100MHz)
1 (inactive) 0 (100MHz)
0
1
1
0
(Reserved)
(Reserved)
Inactive
Active
100MHz, No
Spread Spectrum
100MHz, No Spread
Spectrum
Inactive
100MHz, No
Spread Spectrum
100MHz, No Down
Spread – 0.5%
1 (inactive) 0 (100MHz)
1 (inactive) 1 (133MHz)
1 (inactive) 1 (133MHz)
1
0
0
1
0
1
Active
Active
Active
Active
Test Mode
Active
Test Mode
133MHz, No Center
Spread ±0.5%
(Reserved)
(Reserved)
133MHz, No
Spread Spectrum
133MHz, No Spread
Spectrum
1 (inactive) 1 (133MHz)
1 (inactive) 1 (133MHz)
1
1
0
1
Inactive
Active
Inactive
Active
133MHz, No
Spread Spectrum
133MHz, No Down
Spread – 0.5%
AC WAVEFORMS
V
V
V
V
= 1.25V @ V
and 1.5V @ V
M
X
Y
DDQ2 DDQ3
= V + 0.3V
OL
= V –0.3V
OH
and V are the typical output voltage drop that occur with the
OL
OH
output load.
V
V
DDQ2
DDQ2
CPUCLK
@ 133MHz
1.25V
1.25V
CPUCLK
@133MHz
V
V
V
V
SS
SS
DDQ3
DDQ2
IOAPIC
@ 16.6MHz
3v66
@66MHz
1.5V
1.25V
V
V
SS
SS
CPU leads 3V66
CPUCLK leads IOAPIC
T
T
HPOFFSET
HPOFFSET
SW00354
SW00357
Figure 1. CPUCLK to 3V66 offset
Figure 3. CPU to IOAPIC offset
T
HKP
V
DDQ3
DUTY CYCLE
3V66
@ 66MHz
1.5V
T
HKH
V
V
SS
2.0
1.25
0.4
2.5V CLOCKING
INTERFACE
DDQ3
T
HKL
PCICLK
@ 33MHz
T
T
1.5V
RISE
FALL
V
T
SS
PKP
T
PKH
3V66 leads PCICLK
2.4
T
HPOFFSET
3.3V CLOCKING
INTERFACE
(TTL)
1.5
0.4
SW00356
T
PKL
Figure 2. 3V66 to PCI offset
T
T
FALL
RISE
SW00242
Figure 4. 2.5V/3.3V clock waveforms
12
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
V
I
COMPONENT
MEASUREMENT
POINTS
SEL133/100,
SEL1, SEL0
V
M
2.5VOLT MEASURE POINTS
V
DDQ2
GND
V
= 2.0V
OH
V
= 1.7V
IH
1.25V
V
= 0.7V
IL
t
t
V
= 0.4V
PLZ
PZL
OL
V
DD
V
SS
SYSTEM
MEASUREMENT
POINTS
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
M
COMPONENT
MEASUREMENT
POINTS
V
X
V
OL
3.3VOLT MEASURE POINTS
V
DDQ3
t
t
PZH
PHZ
V
= 2.4V
OH
V
= 2.0V
IH
1.5V
= 0.7V
V
OH
V
IL
V
V
= 0.4V
Y
OUTPUT
OL
V
HIGH-to-OFF
OFF-to-HIGH
M
V
SS
SYSTEM
MEASUREMENT
POINTS
V
SS
outputs
enabled
outputs
enabled
outputs
disabled
SW00243
SW00454
Figure 5. Component versus system measure points
Figure 6. 3-State enable and disable times
13
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
S
1
V
DD
2<V
DD
Open
V
SS
500Ω
500Ω
V
I
V
O
PULSE
GENERATOR
D.U.T.
R
C
T
L
TEST
/t
S
1
t
Open
PLH PHL
t
/t
2<V
PLZ PZL
DD
t
/t
V
SS
PHZ PZH
V
DD
= V
or V
, DEPENDS ON THE OUTPUT
DDQ3
DDQ2
SW00238
Figure 7. Load circuitry for switching times
PWRDWN
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
CPUCLK
(EXTERNAL)
PCICLK
(EXTERNAL)
OSC & VCO
USB (48MHz)
SW00244
Figure 8. Power Management
14
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock Generator
PCK2010
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
15
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock Generator
PCK2010
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-04955
Document order number:
Philips
Semiconductors
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