PCK2014DL [NXP]
IC 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56, 7.50 MM, PLASTIC, SSOP-56, Clock Generator;
| 型号： | PCK2014DL |
| 厂家： | 
NXP |
| 描述： | IC 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56, 7.50 MM, PLASTIC, SSOP-56, Clock Generator 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCK2014
CK98 (100/133 MHz) spread spectrum
system clock generator
Product specification
2001 Jan 19
ICL03 — PC Motherboard ICs; Logic Products Group
Philips
Semiconductors
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
FEATURES
PIN CONFIGURATION
• ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
V
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
V
25V
SS
DD
• Latch-up testing is done to JEDEC Standard JESD78
REF0
REF1
APIC2
APIC1
APIC0
which exceeds 100 mA.
• Mixed 2.5 V and 3.3 V operation
• Six CPU clocks at 2.5 V
V
3V
DD
XTAL_IN
V
V
SS
DD
XTAL_OUT
25V
• Six PCI clocks at 3.3 V, one free-running
(synchronous with CPU clocks)
V
50 CPUCLK5
SS
SS
• Two 3.3 V fixed clocks @ 66 MHz
• Three 2.5 V IOAPIC clocks @ 16.67 MHz
• One 3.3 V 48 MHz USB clock
• Two 3.3 V reference clocks @ 14.318 MHz
• Reference 14.31818 MHz Xtal oscillator input
• 133 MHz or 100 MHz operation, 133.01 MHz in 133 mode
• Power management control input pins
• CPU clock jitter ≤ 150 ps cycle-cycle
• CPU clock skew ≤ 175 ps pin-pin
• 0.0 ns – 1.5 ns CPU - 3V66 delay
• 1.5 ns – 3.5 ns 3V66 - PCI delay
• 1.5 ns – 4.0 ns CPU - IOAPIC delay
• 1.5 ns – 4.0 ns CPU - PCI delay
• Available in 56-pin SSOP package
CPUCLK4
V
49
48
47
PCI_0
V
SS
V
3V 10
V
25V
DD
DD
PCI_1 11
PCI_2 12
46 CPUCLK3
CPUCLK2
45
44
43
42
41
40
39
38
V
V
13
SS
SS
V
25V
PCI_3 14
PCI_4 15
DD
CPUCLK1
CPUCLK0
V
3V 16
3V 17
DD
V
V
SS
DD
V
V
3V
PCI_5 18
DD
SS
V
19
20
21
22
23
24
SS
37 PCISTOP
V
V
SS
CPUSTOP
PWRDWN
SPREAD
SEL1
36
35
34
33
32
31
30
29
SS
V
V
3V
DD
3V
DD
• Center spread spectrum capability via select pins
• Down spread spectrum capability via select pins
V
SS
SEL0
3V66_0 25
3V66_1
V
3V
DD
26
27
DESCRIPTION
The PCK2014 is a clock generator (frequency synthesizer) chip for a
V
3V
48MHz_USB
DD
V
SEL133/100 28
SS
Pentium III and other similar processors.
SW00764
The PCK2014 has six CPU clock outputs at 2.5 V, two 3V66 clocks
running at 66 MHz. there are six PCI clock outputs running at
33 MHz. Additionally, the part has three 2.5 V IOAPIC clock outputs
at 16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz.
All clock outputs meet Intel’s drive strength, rise/fall time, jitter,
accuracy, and skew requirements.
The part possesses dedicated power-down, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on-chip and ensure glitch-free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs and
3V66 clock outputs are driven LOW. When the PCISTOP input is
asserted, the PCI clock outputs are driven LOW.
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
56-pin plastic SSOP
0 to +70 °C
PCK2014DL
SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2
2001 Jan 19
853–2236 25451
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
PIN DESCRIPTION
PIN NUMBER
SYMBOL
REF [0–1]
XTAL_IN
FUNCTION
2, 3
3.3 V 14.318 MHz clock output
14.318 MHz crystal input
5
6
XTAL_OUT
PCI_[0–5]
3V66 [0–1]
14.318 MHz crystal output
3.3 V PCI clock outputs
9, 11, 12, 14, 15, 18
25, 26
3.3 V fixed 66 MHz clock outputs
Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
H = 133 MHz, L = 100 MHz
28
SEL133/100
30
32, 33
34
48 MHz USB
SEL [0–1]
SPREAD
3.3 V fixed 48 MHZ clock output
Logic select pins. TTL levels.
3.3 V LVTTL input. Enables spread spectrum mode when held LOW.
3.3 V LVTTL input. Device enters powerdown mode when held LOW.
35
PWRDWN
3.3 V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW.
CPUDIV_2 output remains on all the time.
36
CPUSTOP
37
PCISTOP
3.3 V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW.
41, 42, 45, 46, 49, 50
CPUCLK [0–5]
2.5 V CPU output. 133 MHz or 100 MHz depending on state of input pin SEL133/100.
2.5 V clock outputs running divide synchronous with the CPU clock frequency.
Fixed 16.67 MHz limit.
53, 54, 55
APIC [0–2]
4, 10, 16, 17,
22, 23, 27, 31, 39
V
DD3V
3.3 V power supply.
1, 7, 8, 13, 19, 20, 21, 24,
29, 38, 40, 44, 48, 52
V
SS
Ground
43, 47, 51, 56
V
DD25V
2.5 V power supply
NOTE:
1. V
, V
and V in the above table reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
SS
DD3V DD25V
the performance of the device. In reality, the platform will be configured with the V
pins tied to a 2.5 V supply, all remaining V pins
DD25V
DD
tied to a common 3.3 V supply and all V pins being common.
SS
3
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
BLOCK DIAGRAM
LOGIC
PWRDWN
LOGIC
REF [0–1](14.318 MHz)
X
XTAL_IN
X
X
14.318
MHZ
OSC
XTAL_OUT
PWRDWN
LOGIC
X
X
USBPLL
SYSPLL
48 MHz USB
STOP
LOGIC
CPUCLK [0–5]
SPREAD
X
STOP
LOGIC
3V66 [0–1] (66MHz)
PCI_[0–5] (33 MHz)
X
SEL133/100
SEL0
DECODE
LOGIC
SEL1
STOP
LOGIC
X
X
PCISTOP
CPUSTOP
PWRDWN
X
X
X
PWRDWN
LOGIC
APIC [0–2] (16.67 MHz)
SW00765
4
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
FUNCTION TABLE
SEL
133/100
SEL1
SEL0
CPU
3V66
PCI
48 MHz
REF
IOAPIC
NOTES
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
1
2
100 MHz
100 MHz
TCLK/2
N/A
66 MHz
66 MHz
TCLK/4
N/A
33 MHz
33 MHz
TCLK/8
N/A
HI-Z
14.318 MHz
14.318 MHz
TCLK
16.67 MHz
16.67 MHz
TCLK/16
N/A
3
4, 7, 8
5, 6
2
48 MHz
TCLK/2
N/A
N/A
133 MHz
133 MHz
66 MHz
66 MHz
33 MHz
33 MHz
HI-Z
14.318 MHz
14.318 MHz
16.67 MHz
16.67 MHz
3
1
48 MHz
4, 7, 8
NOTES:
1. Required for board level “bed-of-nails” testing.
2. Used to support Intel confidential application.
3. 48 MHz PLL disabled to reduce component jitter. 48 MHz outputs to be held Hi-Z instead of driven to LOW state.
4. “Normal” mode of operation.
5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133 MHz CPU select logic.
6. Required for DC output impedance verification.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
8. Range of reference frequency allowed is MIN = 14.316 MHz, NOMINAL = 14.31818 MHz, MAX = 14.32 MHz
CLOCK OUTPUT
TARGET FREQUENCY (MHz)
ACTUAL FREQUENCY (MHz)
PPM
7
USBCLK
48.0
48.008
167
CLOCK ENABLE CONFIGURATION
CPUSTOP
PWRDWN
PCISTOP
CPUCLK
LOW
LOW
LOW
ON
APIC
LOW
ON
3V66
LOW
LOW
LOW
ON
PCI
LOW
LOW
ON
REF / 48 MHz
OSC
VCOs
OFF
ON
X
0
0
1
1
0
1
1
1
1
X
0
1
0
1
LOW
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
LOW
ON
ON
ON
ON
ON
ON
ON
ON
NOTES:
1. LOW means outputs held static LOW as per latency requirement below
2. ON means active.
3. PWRDWN pulled LOW, impacts all outputs including REF and 48 MHz outputs.
4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW.
5. CPUDIV2, IOAPIC, REF, 48 MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when
PWRDWN is LOW.
POWER MANAGEMENT REQUIREMENTS
LATENCY
SIGNAL
SIGNAL STATE
NO. OF RISING EDGES OF FREE RUNNING PCICLK
0 (DISABLED)
1 (ENABLED)
1
CPUSTOP
1
1
0 (DISABLED)
PCISTOP
PWRDWN
1 (ENABLED)
1
1 (NORMAL OPERATION)
0 (POWER DOWN)
3 ms
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
5
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to V (V = 0 V).
SS
SS
LIMITS
SYMBOL
PARAMETER
CONDITION
UNIT
MIN
–0.5
–0.5
–0.5
MAX
+4.6
+4.6
+3.6
–50
V
DD3
DC 3.3 V core supply voltage
DC 3.3 V I/O supply voltage
DC 2.5 V I/O supply voltage
DC input diode current
V
V
V
DDQ3
V
DDQ2
V
I
IK
V < 0
I
mA
V
V
I
DC input voltage
Note 2
–0.5
–0.5
–65
5.5
I
DC output diode current
DC output voltage
V
O
> V or V < 0
±50
mA
V
OK
CC
O
V
O
Note 2
V
CC
+ 0.5
I
O
DC output source or sink current
Storage temperature range
V
O
= 0 to V
CC
±50
mA
°C
T
stg
+150
Power dissipation per package
plastic medium-shrink (SSOP)
For temperature range: –40 to +125 °C
above +55 °C derate linearly with 11.3 mW/K
P
TOT
850
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
MAX
3.465
2.625
V
DD3V
DC 3.3 V core supply voltage
DC 2.5 V I/O supply voltage
3.135
2.375
V
V
V
DD25V
Capacitive load on:
CPUCLK
PCI
3V66
48 MHz clock USB
REF
APIC
1 device load, possible 2 loads
Must meet PCI 2.1 requirements
1 device load, possible 2 loads
1 device load
10
10
10
10
10
10
20
30
30
20
20
20
pF
pF
pF
pF
pF
pF
C
L
1 device load
1 device load
V
I
DC input voltage range
0
V
DD3V
V
V
V
DD25V
DD3V
V
O
DC output voltage range
0
V
f
Reference frequency, oscillator nominal value
Operating ambient temperature range in free air
14.31818 14.31818
+70
MHz
REF
T
0
°C
amb
POWER MANAGEMENT
MAXIMUM 2.5V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS,
MAXIMUM 3.3V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS,
CK133
CONDITION
V
DD25V
= 2.625 V
V
DD25V
= 3.465 V
ALL STATIC INPUTS = V
OR V
ALL STATIC INPUTS = V OR V
DD3V SS
DD3V
SS
Power-down mode
(PWRDWN = 0)
100 µA
200 µA
Full active 100 MHz
SEL133/100 = 0
SEL1, 0 = 1 1
CPUSTOP, PCISTOP = 1
80 mA
90 mA
80 mA
80 mA
Full active 133 MHz
SEL133/100 = 1
SEL1, 0 = 1 1
CPUSTOP, PCISTOP = 1
6
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
DC CHARACTERISTICS
LIMITS
= 0 to +70 °C
TEST CONDITIONS
OTHER
T
UNIT
amb
SYMBOL
PARAMETER
V
(V)
DD
MIN
TYP
MAX
+ 0.3
V
=
DD25V
V
IH
HIGH level input voltage
LOW level input voltage
3.135 to 3.465
2.0
V
V
V
V
V
V
V
V
V
DD
2.5 V ±5%
V
=
DD3V
V
IL
3.135 to 3.465
2.375 to 2.625
2.375 to 2.625
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
V
SS
– 0.3
0.8
3.3 V ±5%
2.5 V output HIGH voltage
CPUCLK, APIC
V
OH2
I
I
= –1 mA
= 1 mA
2.3
–
–
0.25
–
OH
2.5 V output LOW voltage
CPUCLK, APIC
V
I
OL
OL2
OH3
3.3 V output HIGH voltage
REF, 48 MHz USB
V
= –1 mA
= 1 mA
OL
2.0
–
OH
3.3 V output LOW voltage
REF, 48 MHz USB
V
I
0.4
–
OL3
OH3
3.3 V output HIGH voltage
PCI, 3V66
V
I
= –1 mA
2.4
–
OH
3.3 V output LOW voltage
PCI, 3V66
V
OL3
I
OL
= 1 mA
0.55
2.375
2.625
3.135
3.465
3.135
3.465
2.375
2.625
3.135
3.465
3.135
3.465
3.465
V
= 1.0 V
= 2.375 V
= 1.0 V
–27
–
–
–27
–
OUT
APIC, CPUCLK
output HIGH current
I
I
I
mA
mA
mA
mA
mA
mA
OH
V
OUT
V
OUT
–29
–
48 MHz USB, REF
output HIGH current
OH
OH
V
OUT
= 3.135 V
= 1.0 V
–23
–
V
OUT
–33
–
PCI, 3V66
output HIGH current
V
OUT
= 3.135 V
= 1.2 V
–33
–
V
V
27
–
OUT
APIC, CPUCLK
output LOW current
I
I
I
OL
OL
OL
= 0.3 V
30
–
OUT
V
OUT
= 1.95 V
= 0.4 V
29
–
48 MHz USB, REF
output LOW current
V
27
–
OUT
OUT
V
= 1.95 V
= 0.4 V
30
–
PCI, 3V66
output LOW current
V
OUT
38
5
±I
Input leakage current
–
µA
µA
pF
pF
pF
I
3-State output OFF-State
current
V
dd
=
OUT
±I
3.465
I
O
= 0
–
10
5
OZ
V
or GND
Cin
Input pin capacitance
Xtal pin capacitance, as seen
by external crystal
Cxtal
Cout
18
Output pin capacitance
6
7
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
AC CHARACTERISTICS
DD3V
V
= 3.3 V ± 5%; VDDAPIC = V
= 2.5 V ± 5%; f
= 14.31818 MHz
DD25V
crystal
CPU CLOCK OUTPUTS, CPU(0–5) (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
= 0 to +70 °C
LIMITS
= 0 to +70 °C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133 MHz MODE
100 MHz MODE
MIN
7.5
MAX
7.65
n/a
MIN
10.0
9.85
3.0
MAX
10.3
n/a
T
Average CPUCLK period
Absolute minimum CPUCLK period
CPUCLK HIGH time
CPUCLK LOW time
ns
ps
ns
ns
ns
ns
ps
%
2, 9
HKP(avg)
T
7.35
1.87
1.67
0.4
HKP(abs_,om)
T
HKH
n/a
n/a
5, 10
6, 10
8
T
HKL
n/a
2.8
n/a
T
T
CPUCLK rise time
1.6
0.4
1.6
HRISE
HFALL
JITTER
CPUCLK fall time
0.4
1.6
0.4
1.6
8
T
CPUCLK cycle-cycle jitter
Output Duty Cycle
150
55
150
55
DUTY CYCLE
45
45
1
2
T
CPUCLK pin-pin skew
175
175
ps
HSKW
PCI CLOCK OUTPUTS, PCI(0–5) (LUMP CAPACITANCE TEST LOAD = 30 pF)
LIMITS
= 0 to +70 °C
LIMITS
= 0 to +70 °C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133 MHz MODE
100 MHz MODE
MIN
30.0
12.0
12.0
0.5
MAX
n/a
n/a
n/a
2.0
2.0
300
55
MIN
30.0
12.0
12.0
0.5
MAX
n/a
n/a
n/a
2.0
2.0
300
55
T
T
PCI period
ns
ns
ns
ns
ns
ps
%
2, 9
5, 10
6, 10
8
HKP
PCI HIGH time
PCI LOW time
PCI rise time
HKH
T
HKL
T
T
HRISE
HFALL
JITTER
PCI fall time
0.5
0.5
8
T
PCI cycle-cycle jitter
PCI Duty Cycle
PCI pin-pin skew
DUTY CYCLE
45
45
1
2
T
500
500
ps
HSKW
APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
= 0 to +70 °C
LIMITS
= 0 to +70 °C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133 MHz MODE
100 MHz MODE
MIN
60.0
25.5
25.3
0.4
MAX
61.2
n/a
MIN
60.0
25.5
25.3
0.4
MAX
61.2
n/a
T
T
APIC CLK period
ns
ns
ns
ns
ns
ps
%
2, 9
5, 10
6, 10
8
HKP
APIC CLK HIGH time
APIC CLK LOW time
APIC CLK rise time
HKH
T
n/a
n/a
HKL
T
T
1.6
1.6
HRISE
HFALL
JITTER
APIC CLK fall time
0.4
1.6
0.4
1.6
8
T
APIC CLK cycle-cycle jitter
APIC CLK Duty Cycle
APIC CLK pin-pin skew
500
55
500
55
DUTY CYCLE
45
45
1
2
T
250
250
ps
HSKW
8
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
3V66 CLOCK OUTPUT, 3V66 (0–1) (LUMP CAPACITANCE TEST LOAD = 30 pF)
LIMITS
= 0 to +70 °C
LIMITS
= 0 to +70 °C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133 MHz MODE
100 MHz MODE
MIN
15.0
4.95
4.55
0.5
MAX
15.3
n/a
MIN
15.0
4.95
4.55
0.5
MAX
15.3
n/a
T
T
3V66 CLK period
ns
ns
ns
ns
ns
ps
%
2, 9, 4
5, 10
6, 10
8
HKP
3V66 CLK HIGH time
3V66 CLK LOW time
3V66 CLK rise time
HKH
T
n/a
n/a
HKL
T
T
2.0
2.0
HRISE
HFALL
JITTER
3V66 CLK fall time
0.5
2.0
0.5
2.0
8
T
3V66 CLK cycle-cycle jitter
3V66 CLK Duty Cycle
3V66 CLK pin-pin skew
500
55
500
55
DUTY CYCLE
45
45
1
2
T
250
250
ps
HSKW
48MHZ CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS 133 MHz
LIMITS 100 MHz
T
amb
= 0 to +70 °C
T
amb
= 0 to +70 °C
SYMBOL
PARAMETER
UNIT
NOTES
MIN
MAX
MIN
MAX
T
T
48 MHz clock period average
48 MHz clock HIGH time
48 MHz clock LOW time
Output rise edge rate
20.83
7.57
7.17
1
20.83
n/a
n/a
4
20.83
7.57
7.17
1
20.83
n/a
n/a
4
ns
ns
ns
ns
ns
%
2
HKP
HKH
T
HKL
T
(t )
R
HRISE
T
(t )
Output fall edge rate
1
4
1
4
HFALL
F
DUTY CYCLE (t ) Duty Cycle
45
55
45
55
500
3
D
T
CLK cycle-cycle jitter
500
ps
ms
JITTER
T
(f
)
Frequency stabilization from Power-up (cold start)
HSTB ST
NOTE:
1. See Figure 5 for measure points.
2. Average period over 1 µs.
9
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
AC CHARACTERISTICS (Continued)
LIMITS
= 0 to +70 °C
TEST CONDITIONS
T
amb
SYMBOL
PARAMETER
UNIT NOTES
Measurement loads
Measure points
MIN
TYP
0.45
2.0
MAX
(lumped)
CPUCLK to 3V66 CLK,
CPU leads
CPU@20 pF,
3V66@30 pF
CPU@1.25 V,
3V66@1.5 V
T
0.0
1.5
1.5
1.5
1.5
3.5
4.0
4.0
ns
ns
ns
ns
1
1
1
HPOFFSET
HPOFFSET
HPOFFSET
HPOFFSET
3V66 CLK to PCI,
3V66 leads
3V66@30 pF,
PCI@30 pF
3V66@1.5 V,
PCI@1.5 V
T
T
T
CPUCLK to APIC,
CPU leads
CPU@20 pF,
IOAPIC@20 pF
3CPU@1.25 V,
IOAPIC@1.25 V
2.4
CPUCLK to PCI,
CPU leads
CPU@20 pF
PCI@30 pF
CPU@1.25 V
PCI@1.5 V
2.7
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified V /V levels.
OL OH
2. Period, jitter, offset and skew measured on rising edge @1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks.
3. The PCI is the CPUCLK divided by four at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100 MHz.
4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100 MHz.
5. T
6. T
is measured at 2.0 V for 2.5 V outputs, 2.4 V for 3.3 V outputs as shown in Figure 4.
is measured at 0.4 V for all outputs as shown in Figure 4.
HKH
HKL
7. The time is specified from when V
achieves its nominal operating level (typical condition V
= 3.3 V) until the frequency output is
DDQ
DDQ
stable and operating within specification.
8. T
V
and T
are measured as a transition through the threshold region V = 0.4 V and V = 2.4 V for 3 V outputs, V = 0.4 V, and
HRISE
HFALL OL OH OL
= 2.0 V for 2.5 V outputs. (1 mA) JEDEC specification.
OH
9. The average period over any 1 µs period of time must be greater than the minimum specified period.
10.Calculated at minimum edge-rate (1 V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
duty-cycle specification is met.
11. Output (see Figure 5 for measure points).
10
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
SPREAD SPECTRUM FUNCTION TABLE
SPREAD#
SEL133/100#
SEL1
SEL0
Function
pin 34
pin 28
pin 33
pin 32
0 (active)
0 (active)
0 (active)
0 (active)
0 (active)
0 (active)
0 (active)
0 (active)
1 (inactive)
1 (inactive)
1 (inactive)
1 (inactive)
1 (inactive)
1 (inactive)
1 (inactive)
1 (inactive)
0 (100 MHz)
0 (100 MHz)
0 (100 MHz)
0 (100 MHz)
1 (133 MHz)
1 (133 MHz)
1 (133 MHz)
1 (133 MHz)
0 (100 MHz)
0 (100 MHz)
0 (100 MHz)
0 (100 MHz)
1 (133 MHz)
1 (133 MHz)
1 (133 MHz)
1 (133 MHz)
0
0
3-State to High Impedance
100 MHz, Center Spread ±2.5%
100 MHz, Down Spread –3%
100 MHz, Down Spread –3%
Test Mode
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
133 MHz, Center Spread ±2.5%
133 MHz, Down Spread –3%
133 MHz, Down Spread –3%
3-State to High Impedance
100 MHz, No Center Spread
100 MHz, No Down Spread
100 MHz, No Down Spread
Test Mode
133 MHz, No Center Spread
133 MHz, No Down Spread
133 MHz, No Down Spread
11
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
AC WAVEFORMS
T
HKP
V
V
V
V
= 1.25 V @ V
and 1.5 V @ V
M
X
Y
DDQ2 DDQ3
DUTY CYCLE
= V + 0.3 V
OL
T
HKH
= V –0.3 V
OH
and V are the typical output voltage drop that occur with the
2.0
1.25
0.4
OL
OH
2.5V CLOCKING
INTERFACE
output load.
T
HKL
T
T
V
RISE
FALL
DDQ2
1.25V
CPUCLK
T
PKP
@133MHz
T
PKH
V
V
SS
2.4
1.5
0.4
3.3V CLOCKING
INTERFACE
(TTL)
DDQ3
T
PKL
3v66
@66MHz
1.5V
T
T
FALL
RISE
SW00242
V
SS
Figure 4. 2.5V/3.3V clock waveforms
CPU leads 3V66
T
HPOFFSET
COMPONENT
MEASUREMENT
POINTS
SW00354
2.5 V MEASUREMENT POINTS
V
DDQ2
Figure 1. CPUCLK to 3V66 offset
V
= 2.0 V
OH
1.25 V
V
= 0.4 V
OL
SYSTEM
MEASUREMENT
POINTS
V
SS
V
DDQ3
COMPONENT
MEASUREMENT
POINTS
3V66
@ 66MHz
1.5V
3.3 V MEASUREMENT POINTS
V
V
V
DDQ3
SS
V
= 2.4 V
OH
1.5 V
V
= 0.4 V
DDQ3
OL
SYSTEM
MEASUREMENT
POINTS
V
PCICLK
@ 33MHz
SS
1.5V
V
SS
SW00822
3V66 leads PCICLK
Figure 5. Component versus system measure points
T
HPOFFSET
SW00356
V
I
Figure 2. 3V66 to PCI offset
SEL133/100,
SEL1, SEL0
V
M
GND
V
DDQ2
CPUCLK
@ 133MHz
t
t
PZL
1.25V
PLZ
V
DD
V
V
SS
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
M
V
DDQ2
X
V
OL
IOAPIC
@ 16.6MHz
1.25V
t
t
PZH
PHZ
V
SS
V
CPUCLK leads IOAPIC
OH
V
Y
T
OUTPUT
HPOFFSET
V
HIGH-to-OFF
OFF-to-HIGH
M
SW00357
V
SS
outputs
enabled
outputs
enabled
outputs
disabled
Figure 3. CPU to IOAPIC offset
SW00454
Figure 6. 3-State enable and disable times
12
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
S
1
V
DD
2<V
DD
Open
V
SS
500Ω
500Ω
V
I
V
O
PULSE
GENERATOR
D.U.T.
R
C
T
L
TEST
/t
S
1
t
Open
PLH PHL
t
/t
2<V
PLZ PZL
DD
t
/t
V
SS
PHZ PZH
V
DD
= V
or V
, DEPENDS ON THE OUTPUT
DDQ3
DDQ2
SW00238
Figure 7. Load circuitry for switching times
PWRDWN
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
CPUCLK
(EXTERNAL)
PCICLK
(EXTERNAL)
OSC & VCO
USB (48MHz)
SW00244
Figure 8. Power Management
13
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
14
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
NOTES
15
2001 Jan 19
Philips Semiconductors
Product specification
CK98 (100/133 MHz) spread spectrum
system clock generator
PCK2014
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 2001
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 01-01
Document order number:
9397 750 07959
Philips
Semiconductors
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