PCK2010RDL [NXP]
CK98R 100/133MHz RCC spread spectrum system clock generator; CK98R 100 / 133MHz的碾压混凝土扩频系统时钟发生器
| 型号： | PCK2010RDL |
| 厂家： | 
NXP |
| 描述： | CK98R 100/133MHz RCC spread spectrum system clock generator |
| 文件： | 总18页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCK2010R
CK98R (100/133MHz) RCC spread
spectrum system clock generator
Product specification
1999 Oct 19
Philips
Semiconductors
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW.
FEATURES
• Mixed 2.5 V and 3.3 V operation
• Four CPU clocks at 2.5 V
PIN CONFIGURATION
• Eight PCI clocks at 3.3 V, one free-running
(synchronous with CPU clocks)
V
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
V
25V
SS
DD
• Four 3.3 V fixed clocks @ 66 MHz
REF0
REF1
APIC2
APIC1
APIC0
• Two 2.5 V CPUDIV2 clocks @ ½ CPU clock frequency
• Three 2.5 V IOAPIC clocks @ 16.67 MHz
• One 3.3 V 48 MHz USB clock
V
3V
DD
XTAL_IN
V
V
SS
DD
XTAL_OUT
25V
• Two 3.3 V reference clocks @ 14.318 MHz
• Reference 14.31818 MHz Xtal oscillator input
• 133 MHz or 100 MHz operation
V
50 CPUDIV2_1
CPUDIV2_0
SS
PCICLK_F
PCICLK1
49
48
47
46
45
44
43
42
41
40
39
38
V
V
SS
DD
• Power management control input pins
• CPU clock jitter ≤ 250 ps cycle-cycle
• CPU clock skew ≤ 175 ps pin-pin
V
3V 10
25V
DD
CPUCLK3
CPUCLK2
PCICLK2 11
PCICLK3 12
V
13
V
V
SS
SS
DD
• 0.0ns – 1.5 ns CPU - 3V66 delay
25V
PCICLK4 14
PCICLK5 15
• 1.5ns – 3.5 ns 3V66 - PCI delay
CPUCLK1
CPUCLK0
V
3V 16
• 1.5ns – 4.0 ns CPU - IOAPIC delay
• 1.5ns – 4.0 ns CPU - PCI delay
DD
V
PCICLK6 17
PCICLK7 18
SS
V
V
3V
DD
SS
• Available in 56-pin SSOP package
V
V
19
20
21
22
23
24
SS
SS
• ±0.5% center spread spectrum capability via select pins
• –0.5% down spread spectrum capability via select pins
37 PCISTOP
CPUSTOP
PWRDWN
SPREAD
SEL1
36
35
34
33
32
31
30
29
3V66_0
3V66_1
DESCRIPTION
The PCK2010R is a clock generator (frequency synthesizer) chip for
a Pentium II and other similar processors.
V
3V
DD
V
SS
SEL0
3V66_0 25
The PCK2010R has four CPU clock outputs at 2.5 V, two CPUDIV2
clock outputs running at ½ CPU clock frequency (66 MHz or 50 MHz
depending on the state of SEL133/100) and four 3V66 clocks
running at 66MHz. There are eight PCI clock outputs running at
33 MHz. One of the PCI clock outputs is free-running. Additionally,
the part has three 2.5 V IOAPIC clock outputs at 16.67 MHz and two
3.3 V reference clock outputs at 14.318 MHz. All clock outputs meet
Intel’s drive strength, rise/fall time, jitter, accuracy, and skew
requirements.
3V66_1
V
3V
DD
26
27
V
3V
48MHz_USB
DD
V
SEl133/100 28
SS
SW00504
The part possesses dedicated power-down, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on-chip and ensure glitch-free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs and
3V66 clock outputs are driven LOW. When the PCISTOP input is
asserted, the PCI clock outputs are driven LOW.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
56-Pin plastic SSOP
0°C to +70°C
PCK2010R DL
SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2
1999 Oct 19
853–2179 22543
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
PIN DESCRIPTION
PIN NUMBER
SYMBOL
REF [0–1]
XTAL_IN
FUNCTION
2,3
3.3 V 14.318 MHz clock output
14.318 MHz crystal input
5
6
8
XTAL_OUT
PCICLK_F
PCICLK [1–7]
3V66 [0–3]
14.318 MHz crystal output
3.3 V free running PCI clock
3.3 V PCI clock outputs
9, 11, 12, 14, 15, 17, 18
21, 22, 25, 26
3.3 V fixed 66 MHz clock outputs
Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
H = 133 MHz, L = 100 MHz
28
SEL133/100
30
32, 33
34
48 MHz USB
SEL [0–1]
SPREAD
3.3 V fixed 48 MHZ clock output
Logic select pins. TTL levels.
3.3 V LVTTL input. Enables spread spectrum mode when held LOW.
3.3 V LVTTL input. Device enters powerdown mode when held LOW.
35
PWRDWN
3.3 V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW. CPUDIV_2
output remains on all the time.
36
CPUSTOP
37
PCISTOP
3.3 V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW.
41, 42, 45, 46
CPUCLK [0–3]
2.5 V CPU output. 133 MHz or 100MHz depending on state of input pin SEL133/100.
2.5 V output running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending on
state of input pin SEL133/100.
49, 50
CPUDIV_2 [0–1]
IOAPIC [0–2]
2.5 V clock outputs running divide synchronous with the CPU clock frequency. Fixed
16.67 MHz limit.
53, 54, 55
4, 10, 16, 23, 27, 31, 39
V
DD3V
3.3 V power supply.
1, 7, 13, 19, 20, 24, 29,
38, 40, 44, 48, 52
V
SS
Ground
43, 47, 51, 56
V
DD25V
2.5 V power supply
NOTE:
1. V
, V
and V in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise
DD3V DD25V SS
on the performance of the device. In reality, the platform will be configured with the V
pins tied to a 2.5 V supply, all remaining V pins
DD
DD25V
tied to a common 3.3 V supply and all V pins being common.
SS
3
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
BLOCK DIAGRAM
LOGIC
PWRDWN
LOGIC
REF [0–1](14.318 MHz)
X
XTAL_IN
X
X
14.318
MHZ
OSC
XTAL_OUT
PWRDWN
LOGIC
X
X
USBPLL
SYSPLL
48 MHz USB
STOP
LOGIC
CPUCLK [0–3]
SPREAD
X
STOP
LOGIC
3V66 [0–3] (66MHz)
X
X
SEL133/100
SEL0
DECODE
LOGIC
SEL1
PWRDWN
LOGIC
CPUDIV2 [0–1]
PWRDWN
LOGIC
PCICLK_F (33MHz)
X
X
X
STOP
LOGIC
PCICLK [1–7] (33 MHz)
APIC [0–2] (16.67 MHz)
PCISTOP
CPUSTOP
PWRDWN
X
X
X
PWRDWN
LOGIC
SW00505
4
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
FUNCTION TABLE
SEL
133/100
SEL1 SEL0
CPU
CPUDIV2
3V66
PCI
48 MHz
REF
IOAPIC
NOTES
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
N/A
HI-Z
1
N/A
2
3
100 MHz
100 MHz
TCLK/2
N/A
50 MHz
50 MHz
TCLK/4
N/A
66 MHz
66 MHz
TCLK/4
N/A
33 MHz
33 MHz
TCLK/8
N/A
HI-Z
14.318 MHz
14.318 MHz
TCLK
16.67 MHz
16.67 MHz
TCLK/16
N/A
48 MHz
TCLK/2
N/A
4, 7, 8
5, 6
2
N/A
133 MHz
133 MHz
66 MHz
66 MHz
66 MHz
66 MHz
33 MHz
33 MHz
HI-Z
14.318 MHz
14.318 MHz
16.67 MHz
16.67 MHz
3
1
48 MHz
4, 7, 8
NOTES:
1. Required for board level “bed-of-nails” testing.
2. Used to support Intel confidential application.
3. 48 MHz PLL disabled to reduce component jitter. 48 MHz outputs to be held Hi-Z instead of driven to LOW state.
4. “Normal” mode of operation.
5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133 MHz CPU select logic.
6. Required for DC output impedance verification.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
8. Range of reference frequency allowed is MIN = 14.316 MHz, NOMINAL = 14.31818 MHz, MAX = 14.32 MHz
CLOCK OUTPUT
TARGET FREQUENCY (MHz)
ACTUAL FREQUENCY (MHz)
PPM
7
USBCLK
48.0
48.008
167
CLOCK ENABLE CONFIGURATION
CPUSTOP
PWRDWN
PCISTOP
CPUCLK
LOW
LOW
LOW
ON
CPUDIV2
LOW
ON
APIC 3V66
PCI
LOW
LOW
ON
PCI_F
LOW
ON
REF / 48 MHz
OSC VCOs
X
0
0
1
1
0
1
1
1
1
X
0
1
0
1
LOW
ON
LOW
LOW
LOW
ON
LOW
ON
OFF
ON
ON
ON
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
LOW
ON
ON
ON
ON
ON
ON
ON
ON
ON
NOTES:
1. LOW means outputs held static LOW as per latency requirement below
2. ON means active.
3. PWRDWN pulled LOW, impacts all outputs including REF and 48 MHz outputs.
4. All 3V66 clocks as well as CPU clocks should stop cleanly when CPUSTOP is pulled LOW.
5. CPUDIV2, IOAPIC, REF, 48 MHz signals are not controlled by the CPUSTOP functionality and are enabled all in all conditions except when
PWRDWN is LOW.
POWER MANAGEMENT REQUIREMENTS
LATENCY
SIGNAL
SIGNAL STATE
NO. OF RISING EDGES OF FREE RUNNING PCICLK
0 (DISABLED)
1 (ENABLED)
1
CPUSTOP
1
1
0 (DISABLED)
PCISTOP
PWRDWN
1 (ENABLED)
1
1 (NORMAL OPERATION)
0 (POWER DOWN)
3 ms
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
5
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to V (V = 0 V)
SS
SS
LIMITS
SYMBOL
PARAMETER
CONDITION
UNIT
MIN
–0.5
–0.5
–0.5
MAX
+4.6
+4.6
+3.6
–50
V
DD3
DC 3.3 V core supply voltage
DC 3.3 V I/O supply voltage
DC 2.5 V I/O supply voltage
DC input diode current
V
V
V
DDQ3
V
DDQ2
V
I
IK
V < 0
I
mA
V
V
I
DC input voltage
Note 2
–0.5
–0.5
–65
5.5
I
DC output diode current
DC output voltage
V
O
> V or V < 0
±50
mA
V
OK
CC
O
V
O
Note 2
V
CC
+ 0.5
I
O
DC output source or sink current
Storage temperature range
V
O
= 0 to V
CC
±50
mA
°C
T
STG
+150
Power dissipation per package
plastic medium-shrink (SSOP)
For temperature range: –40 to +125°C
above +55°C derate linearly with 11.3mW/K
P
TOT
850
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
MAX
3.465
2.625
V
DD3V
DC 3.3 V core supply voltage
DC 2.5 V I/O supply voltage
3.135
2.375
V
V
V
DD25V
Capacitive load on:
CPUCLK
1 device load, possible 2 loads
Must meet PCI 2.1 requirements
1 device load, possible 2 loads
1 device load, possible 2 loads
1 device load
10
10
10
10
10
10
10
20
30
20
30
20
20
20
pF
pF
pF
pF
pF
pF
pF
PCICLK
CPUDIV2
3V66
48 MHz clock USB
REF
IOAPIC
C
L
1 device load
1 device load
V
I
DC input voltage range
0
V
DD3V
V
V
V
DD25V
DD3V
V
O
DC output voltage range
0
V
f
Reference frequency, oscillator nominal value
Operating ambient temperature range in free air
14.31818 14.31818
+70
MHz
REF
T
0
°C
amb
POWER MANAGEMENT
MAXIMUM 2.5V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS,
MAXIMUM 3.3V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAP LOADS,
CK133
CONDITION
V
DD25V
= 2.625 V
V
DD25V
= 3.465 V
ALL STATIC INPUTS = V
OR V
ALL STATIC INPUTS = V OR V
DD3V SS
DD3V
SS
Power-down mode
(PWRDWN = 0)
100 µA
200 µA
Full active 100 MHz
SEL133/100# = 0
SEL1, 0 = 1 1
CPUSTOP, PCISTOP = 1
80 mA
90 mA
160 mA
160 mA
Full active 133 MHz
SEL133/100# = 1
SEL1, 0 = 1 1
CPUSTOP, PCISTOP = 1
6
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
DC CHARACTERISTICS
LIMITS
= 0°C to +70°C
TEST CONDITIONS
T
amb
UNIT
SYMBOL
PARAMETER
V
(V)
DD
OTHER
MIN
TYP
MAX
+ 0.3
V
=
DD25V
V
HIGH level input voltage
LOW level input voltage
3.135 to 3.465
2.0
V
V
V
V
V
V
V
V
V
IH
DD
2.5 V ±5%
V
=
DD3V
V
3.135 to 3.465
2.375 to 2.625
2.375 to 2.625
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
V
SS
– 0.3
0.8
IL
3.3 V ±5%
2.5 V output HIGH voltage
CPUCLK, IOAPIC, CPUDIV2
V
OH2
I
I
= –1 mA
= 1 mA
2.0
–
–
0.4
–
OH
2.5 V output LOW voltage
CPUCLK, IOAPIC, CPUDIV2
V
I
OL
OL2
OH3
3.3 V output HIGH voltage
REF, 48 MHz USB
V
= –1 mA
= 1 mA
OL
2.0
–
OH
3.3 V output LOW voltage
REF, 48 MHz USB
V
I
0.4
–
OL3
OH3
3.3 V output HIGH voltage
PCI, 3V66
V
I
= –1 mA
2.4
–
OH
3.3 V output LOW voltage
PCI, 3V66
V
OL3
I
= 1 mA
0.55
OL
2.375
2.625
3.135
3.465
3.135
3.465
2.375
2.625
3.135
3.465
3.135
3.465
3.465
V
= 1.0 V
= 2.375 V
= 1.0 V
–27
–
–
–27
–
OUT
CPUCLK
output HIGH current
I
I
I
mA
mA
mA
mA
mA
mA
OH
V
OUT
V
OUT
–29
–
48 MHz USB, REF
output HIGH current
OH
OH
V
OUT
= 3.135 V
= 1.0 V
–23
–
V
OUT
–33
–
PCI, 3V66
output HIGH current
V
OUT
= 3.135 V
= 1.2 V
–33
–
V
V
27
–
OUT
CPUCLK
output LOW current
I
I
I
OL
OL
OL
= 0.3 V
30
–
OUT
V
OUT
= 1.95 V
= 0.4 V
29
–
48 MHz USB, REF
output LOW current
V
27
–
OUT
OUT
V
= 1.95 V
= 0.4 V
30
–
PCI, 3V66
output LOW current
V
OUT
38
5
±I
Input leakage current
–
µA
µA
pF
pF
pF
I
3-State output OFF-State
current
V
dd
=
OUT
±I
3.465
I
O
= 0
–
10
5
OZ
V
or GND
Cin
Input pin capacitance
Xtal pin capacitance, as seen
by external crystal
Cxtal
Cout
18
Output pin capacitance
6
7
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
AC CHARACTERISTICS
DD3V
V
= 3.3 V ± 5%; VDDAPIC = V
= 2.5 V ± 5%; f
= 14.31818 MHz
DD25V
crystal
CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
= 0°C to +70°C
LIMITS
= 0°C to +70°C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133 MHz MODE
MIN MAX
7.5 8.0
100 MHz MODE
MIN
MAX
10.5
n/a
T
T
CPUCLK period
CPUCLK HIGH time
CPUCLK LOW time
CPUCLK rise time
10.0
3.0
2.8
0.4
0.4
ns
ns
ns
ns
ns
ps
%
2, 9
5, 10
6, 10
8
HKP
1.87
1.67
0.4
n/a
n/a
1.6
1.6
250
55
HKH
T
HKL
n/a
T
1.6
HRISE
HFALL
JITTER
T
CPUCLK fall time
0.4
1.6
8
T
CPUCLK cycle-cycle jitter
Output Duty Cycle
250
55
DUTY CYCLE
45
45
1
2
T
CPUCLK pin-pin skew
175
175
ps
HSKW
CPUDIV2 CLOCK OUTPUTS, CPUDIV2 (0–1) (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
= 0°C to +70°C
LIMITS
= 0°C to +70°C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133 MHz MODE
100 MHz MODE
MIN
MAX
16.0
n/a
MIN
MAX
21.0
n/a
T
T
CPUDIV2 CLK period
CPUDIV2 CLK HIGH time
CPUDIV2 CLK LOW time
CPUDIV2 CLK rise time
15.0
5.25
5.05
0.4
20.0
7.5
7.3
0.4
0.4
ns
ns
ns
ns
ns
ps
%
2, 9
5, 10
6, 10
8
HKP
HKH
T
n/a
n/a
HKL
T
T
1.6
1.6
HRISE
HFALL
JITTER
CPUDIV2 CLK fall time
0.4
1.6
1.6
8
T
CPUDIV2 CLK cycle-cycle jitter
CPUDIV2 CLK Duty Cycle
CPUDIV2 CLK pin-pin skew
250
55
250
55
DUTY CYCLE
45
45
1
2
T
175
175
ps
HSKW
PCI CLOCK OUTPUTS, PCI(0–7) (LUMP CAPACITANCE TEST LOAD = 30 pF)
LIMITS
= 0°C to +70°C
LIMITS
= 0°C to +70°C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133 MHz MODE
MIN MAX
30.0
100 MHz MODE
MIN MAX
30.0
T
T
PCICLK period
PCICLK HIGH time
PCICLK LOW time
PCICLK rise time
n/a
n/a
n/a
2.0
2.0
500
55
n/a
n/a
n/a
2.0
2.0
500
55
ns
ns
ns
ns
ns
ps
%
2, 9
5, 10
6, 10
8
HKP
12.0
12.0
0.5
12.0
12.0
0.5
HKH
T
HKL
T
T
HRISE
HFALL
JITTER
PCICLK fall time
0.5
0.5
8
T
PCICLK cycle-cycle jitter
PCICLK Duty Cycle
PCICLK pin-pin skew
DUTY CYCLE
45
45
1
2
T
500
500
ps
HSKW
8
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
= 0°C to +70°C
LIMITS
= 0°C to +70°C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133 MHz MODE
100 MHz MODE
MIN
MAX
64.0
n/a
MIN
MAX
64.0
n/a
T
T
IOAPIC CLK period
IOAPIC CLK HIGH time
IOAPIC CLK LOW time
IOAPIC CLK rise time
60.0
25.5
25.3
0.4
60.0
25.5
25.3
0.4
ns
ns
ns
ns
ns
ps
%
2, 9
5, 10
6, 10
8
HKP
HKH
T
n/a
n/a
HKL
T
T
1.6
1.6
HRISE
HFALL
JITTER
IOAPIC CLK fall time
0.4
1.6
0.4
1.6
8
T
IOAPIC CLK cycle-cycle jitter
IOAPIC CLK Duty Cycle
IOAPIC CLK pin-pin skew
500
55
500
55
DUTY CYCLE
45
45
1
2
T
250
250
ps
HSKW
3V66 CLOCK OUTPUT, 3V66 (0–3) (LUMP CAPACITANCE TEST LOAD = 30 pF)
LIMITS
= 0°C to +70°C
LIMITS
= 0°C to +70°C
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
133 MHz MODE
100 MHz MODE
MIN
MAX
16.0
n/a
MIN
MAX
16.0
n/a
T
T
3V66 CLK period
3V66 CLK HIGH time
3V66 CLK LOW time
3V66 CLK rise time
15.0
5.25
5.05
0.4
15.0
5.25
5.05
0.4
ns
ns
ns
ns
ns
ps
%
2, 9, 4
5, 10
6, 10
8
HKP
HKH
T
n/a
n/a
HKL
T
T
1.6
1.6
HRISE
HFALL
JITTER
3V66 CLK fall time
0.4
1.6
0.4
1.6
8
T
3V66 CLK cycle-cycle jitter
3V66 CLK Duty Cycle
3V66 CLK pin-pin skew
500
55
500
55
DUTY CYCLE
45
45
1
2
T
250
250
ps
HSKW
48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
LIMITS
= 0°C to +70°C
TEST CONDITIONS
NOTES
T
amb
SYMBOL
PARAMETER
UNIT
MIN
MAX
Determined by PLL
divider ratio
f
Frequency, Actual
48.008
+167
MHz
f
Deviation from 48 MHz
Output rise edge rate
Output fall edge rate
Duty Cycle
(48.008 – 48)/48
ppm
ns
D
T
(t )
1
1
4
4
HRISE
R
T
(t )
F
ns
HFALL
DUTY CYCLE (t )
45
55
%
D
133 MHz
100 MHz
MIN MAX
MIN
MAX
T
CLK cycle-cycle jitter
ps
JITTER
500
500
3
T
(f
)
Frequency stabilization from Power-up (cold start)
ms
HSTB ST
NOTE:
1. See Figure 5 for measure points.
9
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
AC CHARACTERISTICS (Continued)
LIMITS
= 0°C to +70°C
TEST CONDITIONS
T
amb
SYMBOL
PARAMETER
UNIT NOTES
Measurement loads
(lumped)
Measure points
MIN
0.0
1.5
1.5
1.5
0.0
TYP
0.45
2.0
MAX
CPUCLK to 3V66 CLK,
CPU leads
CPU@20 pF,
3V66@30 pF
CPU@1.25 V,
3V66@1.5 V
T
1.5
3.5
4.0
4.0
2.5
ns
ns
ns
ns
ns
1
1
1
HPOFFSET
HPOFFSET
HPOFFSET
HPOFFSET
HPOFFSET
3V66 CLK to PCICLK,
3V66 leads
3V66@30 pF,
PCI@30 pF
3V66@1.5 V,
PCI@1.5 V
T
T
T
T
CPUCLK to IOAPIC,
CPU leads
CPU@20 pF,
IOAPIC@20 pF
3CPU@1.25 V,
IOAPIC@1.25 V
2.4
CPUCLK to PCICLK ,
CPU leads
CPU@20 pF
PCI@30 pF
CPU@1.25 V
PCI@1.5 V
3.8
CPUDIV2 to CPUCLK,
CPUDIV2 leads
CPUDIV2@20 pF
CPU@20 pF
CPUDIV2@
CPU@1.25 V
1.6
NOTES:
1. Output drivers must have monotonic rise/fall times through the specified V /V levels.
OL OH
2. Period, jitter, offset and skew measured on rising edge @1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks.
3. The PCICLK is the CPUCLK divided by four at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100 MHz.
4. 3V66 CLK is internal VCO frequency divided by two at CPUCLK = 133 MHz. The 3V66 CLK is internal VCO frequency divided by three at
CPUCLK = 100 MHz.
5. T
6. T
is measured at 2.0 V for 2.5 V outputs, 2.4 V for 3.3 V outputs as shown in Figure 4.
is measured at 0.4 V for all outputs as shown in Figure 4.
HKH
HKL
7. The time is specified from when V
achieves its nominal operating level (typical condition V
= 3.3 V) until the frequency output is
DDQ
DDQ
stable and operating within specification.
8. T and T are measured as a transition through the threshold region V = 0.4 V and V = 2.4 V (1 mA) JEDEC specification.
HRISE
HFALL
OL
OH
9. The average period over any 1 µs period of time must be greater than the minimum specified period.
10.Calculated at minimum edge-rate (1V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure
duty-cycle specification is met.
11. Output (see Figure 5 for measure points).
10
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
SPREAD SPECTRUM FUNCTION TABLE
SPREAD#
SEL133/100#
SEL1
SEL0
Function
48 MHz PLL
pin 34
pin 28
pin 33
pin 32
0 (active)
0 (active)
0 (active)
0 (active)
0 (active)
0 (active)
0 (active)
0 (active)
1 (inactive)
1 (inactive)
1 (inactive)
1 (inactive)
1 (inactive)
1 (inactive)
1 (inactive)
1 (inactive)
0 (100 MHz)
0 (100 MHz)
0 (100 MHz)
0 (100 MHz)
1 (133 MHz)
1 (133 MHz)
1 (133 MHz)
1 (133 MHz)
0 (100 MHz)
0 (100 MHz)
0 (100 MHz)
0 (100 MHz)
1 (133 MHz)
1 (133 MHz)
1 (133 MHz)
1 (133 MHz)
0
0
3-State to High Impedance
Inactive
Active
Inactive
Active
Active
Active
Inactive
Active
Inactive
Active
Inactive
Active
Active
Active
Inactive
Active
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100 MHz, Center Spread ±0.5%
100 MHz, Down Spread – 0.5%
100 MHz, Down Spread – 0.5%
Test Mode
133 MHz, Center Spread ±0.5%
133 MHz, Down Spread – 0.5%
133 MHz, Down Spread – 0.5%
3-State to High Impedance
100 MHz, No Center Spread ±0.5%
100 MHz, No Down Spread – 0.5%
100 MHz, No Down Spread – 0.5%
Test Mode
133 MHz, No Center Spread ±0.5%
133 MHz, No Down Spread – 0.5%
133 MHz, No Down Spread – 0.5%
11
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
AC WAVEFORMS
V
V
V
V
= 1.25 V @ V
and 1.5 V @ V
M
X
Y
DDQ2 DDQ3
= V + 0.3 V
OL
= V –0.3 V
OH
and V are the typical output voltage drop that occur with the
OL
OH
output load.
12
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
V
DDQ2
1.25V
CPUCLK
@133MHz
V
V
SS
DDQ3
3v66
@66MHz
1.5V
V
SS
CPU leads 3V66
T
HPOFFSET
SW00354
Figure 1. CPUCLK to 3V66 offset
V
DDQ3
3V66
@ 66MHz
1.5V
V
V
SS
DDQ3
PCICLK
@ 33MHz
1.5V
V
SS
3V66 leads PCICLK
T
HPOFFSET
SW00356
Figure 2. 3V66 to PCI offset
V
DDQ2
CPUCLK
@ 133MHz
1.25V
V
V
SS
DDQ2
IOAPIC
@ 16.6MHz
1.25V
V
SS
CPUCLK leads IOAPIC
T
HPOFFSET
SW00357
Figure 3. CPU to IOAPIC offset
13
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
T
HKP
DUTY CYCLE
T
HKH
2.0
1.25
0.4
2.5V CLOCKING
INTERFACE
T
HKL
T
T
FALL
RISE
T
PKP
T
PKH
2.4
1.5
0.4
3.3V CLOCKING
INTERFACE
(TTL)
T
PKL
T
T
FALL
RISE
SW00242
Figure 4. 2.5V/3.3V clock waveforms
COMPONENT
MEASUREMENT
POINTS
2.5VOLT MEASURE POINTS
V
DDQ2
V
= 2.0V
OH
V
= 1.7V
IH
1.25V
V
= 0.7V
IL
V
= 0.4V
OL
SYSTEM
MEASUREMENT
POINTS
V
SS
COMPONENT
MEASUREMENT
POINTS
3.3VOLT MEASURE POINTS
V
DDQ3
V
= 2.4V
OH
V
= 2.0V
IH
1.5V
= 0.7V
V
IL
V
= 0.4V
OL
SYSTEM
MEASUREMENT
POINTS
V
SS
SW00243
Figure 5. Component versus system measure points
V
I
SEL133/100,
SEL1, SEL0
V
M
GND
t
t
PZL
PLZ
V
DD
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
OUTPUT
V
HIGH-to-OFF
OFF-to-HIGH
M
V
SS
outputs
enabled
outputs
enabled
outputs
disabled
SW00454
14
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
Figure 6. 3-State enable and disable times
S
1
V
DD
2<V
DD
Open
V
SS
500Ω
500Ω
V
I
V
O
PULSE
GENERATOR
D.U.T.
R
C
T
L
TEST
/t
S
1
t
Open
PLH PHL
t
/t
2<V
PLZ PZL
DD
t
/t
V
SS
PHZ PZH
V
DD
= V
or V
, DEPENDS ON THE OUTPUT
DDQ3
DDQ2
SW00238
Figure 7. Load circuitry for switching times
PWRDWN
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
CPUCLK
(EXTERNAL)
PCICLK
(EXTERNAL)
OSC & VCO
USB (48MHz)
SW00244
Figure 8. Power Management
15
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
16
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
NOTES
17
1999 Oct 19
Philips Semiconductors
Product specification
CK98R (100/133MHz) RCC spread spectrum
system clock generator
PCK2010R
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 10-99
Document order number:
9397–750–06509
Philips
Semiconductors
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