PDI1394L21BP_技术文档

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SEE ATTACHED ERRATA WHICH FOLLOWS THIS DOCUMENT FOR INFORMATION

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PDI1394L21

1394 full duplex AV link layer controller

Preliminary specification

1999 Aug 06

Supersedes data of 1999 Mar 30

Philips

Semiconductors

Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

1.0 FEATURES

2.0 DESCRIPTION

The PDI1394L21, Philips Semiconductors Full Duplex 1394

Audio/Video (AV) Link Layer Controller, is an IEEE 1394–1995

compliant link layer controller featuring 2 embedded AV layer

interfaces. The AV layers are designed to pack and un-pack

application data packets for transmission over the IEEE 1394 bus

using isochronous data transfers. Because of its full duplex

architecture, the PDI1394L21 is capable of receiving and

transmitting isochronous data during the same bus cycle. Two 8 bit

AV ports, each with its own buffer (FIFO), receive and output

isochronous data for transmission and reception of bus packets.

Each port can be configured to receive or transmit, however, the

other port always performs the opposite function. Half duplex

operation is also permitted.

• IEEE 1394–1995 Standard Link Layer Controller

• Hardware Support for the IEC61883 International Standard of

Digital Interface for Consumer Electronics

• Interface to any IEEE 1394–1995 Physical Layer Interface

• 5V Tolerant I/Os

• Single 3.3V supply voltage

• Full-duplex isochronous operation

• Operates with 400/200/100 Mbps physical layer devices

• Dual 4K Byte FIFOs for isochronous data

The application data is packetized according to the IEC 61883

International Standard of Interface for Consumer Electronic

Audio/Video Equipment. Both AV layer interfaces are byte-wide

ports capable of accommodating various MPEG–2 and DVC

codecs. An 80C51 compatible byte-wide host interface is provided

for internal register configuration as well as performing

asynchronous data transfers.

• Supports single capacitor isolation mode and IEEE 1394–1995,

Annex J. isolation

• 4-field deep SYT buffer added to enhance real-time isochronous

synchronization using the AVFSYNC pin

• Generates its own AV port clocks under software control. Select

one of three frequencies: 24.576, 12.288, or 6.144 MHz

The PDI1394L21 is powered by a single 3.3V power supply and the

inputs and outputs are 5V tolerant. It is available in the LQFP100

and TQFP100 packages.

3.0 QUICK REFERENCE DATA

GND = 0V; T

= 25°C

amb

SYMBOL

PARAMETER

Functional supply voltage range

CONDITIONS

MIN

TYP

3.3

MAX

UNIT

V

3.0

3.6

DD

I

Supply current @ V = 3.3V

Operating

75

mA

MHz

DD

SCLK

Device clock

49.147

49.152

49.157

4.0 ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

PDI1394L21BE

NORTH AMERICA

PDI1394L21BE

PDI1394L21BP

PKG. DWG. #

SOT407 AB15

SOT386 BB2

100-pin plastic LQFP100

100-pin plastic TQFP100

0°C to +70°C

PDI1394L21BP

NOTE:

This datasheet is subject to change.

Please visit out internet website www.semiconductors.philips.com/1394 for latest changes.

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1999 Aug 06

Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

5.0 PIN CONFIGURATION

100

76

75

1

TQFP

LQFP

25

51

26

50

Pin Function

1

2

3

4

5

6

7

8

9

HIF D7

HIF D6

HIF D5

HIF D4

GND

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

PHY D6*

PHY D5*

PHY D4*

GND

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

AV1 D1

AV1 D2

AV1 D3

V

DD

V

DD

GND

V

PHY D3*

PHY D2*

PHY D1*

PHY D0*

GND

DD

AV1 D4

AV1 D5

AV1 D6

AV1 D7

HIF D3

HIF D2

HIF D1

HIF D0

CLK25

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

V

DD

V

DD

GND

PHY CTL1*

PHY CTL0*

ISO_N

AV2ERR1

AV2ERR0

AV2ENDPCK

AV2SYNC

AV2CLK

V

DD

HIF A8

HIF A7

HIF A6

HIF A5

HIF A4

HIF A3

HIF A2

HIF A1

HIF A0

GND

V

DD

GND

N/C

AV1ERR1

AV1ERR0

LREQ*

SCLK

AV1ENDPCK

AV1SYNC

AV1CLK

AV1FSYNC

AV1ENKEY

AV1VALID

N/C

AV2FSYNC

AV2VALID

GND

V

DD

AV2 D0

AV2 D1

AV2 D2

AV2 D3

GND

V

DD

HIF CS_N

HIF WR_N

HIF RD_N

HIF INT_N

RESET_N

CYCLE IN

GND

V

DD

AV2D4

GND

AV2 D5

AV2 D6

AV2 D7

AV2ENKEY

V

DD

RESESRVED

RESERVED

AV1 D0

V

DD

CYCLE OUT

PHY D7*

100 N/C

*

INDICATES PIN EQUIPPED WITH INTERNAL BUS HOLD CIRCUIT

ACTIVATED BY THE STATE OF THE ISO_N PIN.

SV00877

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1999 Aug 06

Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

6.0 FUNCTIONAL DIAGRAM

HIF A[8:0]

HIF D[7:0]

PHY D[0:7]

HIF WR_N

HIF RD_N

PHY CTL[0:1]

LREQ

HIF CS_N

HIF INT_N

RESET_N

ISO_N

SCLK

CYCLEIN

VDD

GND

PDI1394L21

IEEE 1394

FULL DUPLEX

CYCLEOUT

AV LINK LAYER CONTROLLER

AV1 D[7:0]

AV1CLK

AV2D[7:0]

AV2CLK

AV1VALID

AV2VALID

AV1SYNC

AV1FSYNC

AV1ENKEY

AV1ENDPCK

AV1ERR[1:0]

AV2SYNC

AV2FSYNC

AV2ENKEY

AV2ENDPCK

AV2ERR[1:0]

SV00878

7.0 INTERNAL BLOCK DIAGRAM

AV1 D[7:0]

AV1CLK

CYCLEOUT

CYCLEIN

AV1SYNC

AV1VALID

AV1FSYNC

AV1 LAYER

PHY D[0:7]

PHY CTL[0:1]

ISOCHRONOUS

TRANSMITTER/

RECEIVER

9KB BUFFER

MEMORY

(ISOCH & ASYNC

LINK CORE

AV1ENDPCK

LREQ

ISO_N

SCLK

AV1ERR[0:1]

AV1ENKEY

PACKETS)

AV2 D[7:0]

AV2CLK

AV2SYNC

AV2VALID

AV2 LAYER

ISOCHRONOUS

TRANSMITTER/

RECEIVER

NOTE: THERE IS ONLY ONE

ISOCHRONOUS RECEIVER

AND ONE ISOCHRONOUS

TRANSMITTER—THEREFORE,

WHEN EITHER AVPORT IS SET

TO TRANSMIT, THE OTHER

AVPORT IS AUTOMATICALLY

SET TO RECEIVE.

AV2FSYNC

AV2ENDPCK

AV2ERR[0:1]

AV2ENKEY

HIF A[8:0]

HIF D[7:0]

ASYNC

TRANSMITTER

AND

RECEIVER

HIF WR_N

HIF RD_N

CONTROL

AND

STATUS

8-BIT

INTERFACE

RESET_N

SV00879

REGISTERS

HIF CS_N

HIF INT_N

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1999 Aug 06

Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

8.0 APPLICATION DIAGRAM

AV

MPEG OR DVC

DECODER

INTERFACE

PDI1394L21

AV LINK

PDI1394Pxx

PHY

PHY–LINK

INTERFACE

1394 CABLE

INTERFACE

AV

MPEG OR DVC

DECODER

INTERFACE

DATA 8/

ADDRESS 9/

INTERRUPT & CONTROL

HOST CONTROLLER

SV00880

9.0 PIN DESCRIPTION

9.1 Host Interface

PIN No.

PIN SYMBOL

I/O

NAME AND FUNCTION

1, 2, 3, 4, 7, 8,

9, 10

HIF D[7:0]

GND

I/O

Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers.

5, 12, 23, 31,

38, 44, 50, 63,

73, 79, 87, 93

Ground reference

6, 13, 24, 32,

39, 45, 49, 64,

72, 78, 88, 94

V

DD

3.3V ± 0.3V power supply

14, 15, 16, 17,

18, 19, 20, 21,

22

Host Interface Address 0 through 8. Provides the host with a byte wide interface to internal

registers. See description of Host Interface for addressing rules.

HIF A[8:0]

HIF CS_N

I

Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control and

status registers.

25

26

27

Write enable. When asserted (LOW) in conjunction with HIF CS_N, a write to the PDI1394L21

internal registers is requested. (NOTE: HIF WR_N and HIF RD_N : if these are both LOW in

conjunction with HIF CS_N, then a write cycle takes place. This can be used to connect CPUs

that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect the

R/W_N line to the HIF WR_N and tie HIF RD_N LOW.)

HIF WR_N

HIF RD_N

I

Read enable. When asserted (LOW) in conjunction with HIF CS_N, a read of the PDI1394L21

internal registers is requested.

Interrupt (active LOW). Indicates a interrupt internal to the PDI1394L21. Read the General

Interrupt Register for more information. This pin is open drain and requires a 1KW pull-up resistor.

28

29

HIF INT_N

RESET_N

O

I

Reset (active LOW). The asynchronous master reset to the PDI1394L21.

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1999 Aug 06

Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

9.2 AV Interface 1

NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register

(0X018)—default is transmit.

PIN No.

PIN SYMBOL

I/O

NAME AND FUNCTION

77, 76, 75, 74,

71, 70, 69, 68

AV1 D[7:0]

I/O

Audio/Video Data 7 (MSB) through 0. Byte-wide interface to the AV layer 1.

External application clock. Rising edge active. This pin can be programmed to output the

application clock. Depending on the configuration of AV Port 1 as transmitter or receiver, the

output enable is located in the ITXPKCTL register (address 0x020) or IRXPKCTL register

(address 0x040).

58

AV1CLK

I/O

57

59

AV1SYNC

I/O

Start of packet indicator; should only be used when AV1VALID is active.

Programmable frame sync, can be set to input. Frame sync input used for Digital Video (DV). The

signal is time stamped and transmitted in the SYT field of ITXHQ2. Frame sync output. Signal is

derived from SYT field of IRXHQ2.

AV1FSYNC

End of application packet indication from data source. Required only if input packet is not multiple

of 4 bytes. It can be tied LOW for data packets that are 4*N in size.

56

AV1ENDPCK

I

Encryption key state. Indicates state “1” or “0” of encryption key which matches present port data

during receive mode. Used to input key state during transmit mode.

60

61

53

52

AV1ENKEY

AV1VALID

AV1ERR0

AV1ERR1

I/O

O

Indicates data on AV1 D [7:0] is valid.

CRC error, indicates bus packet containing AV1 D [7:0] had a CRC error, the current AV packet is

unreliable.

O

Sequence Error. Indicates at least one source packet was lost before the current AV1 D [7:0] data.

9.3 AV Interface 2

NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register—default is

receive.

PIN No.

PIN SYMBOL

I/O

NAME AND FUNCTION

98, 97, 96, 95,

92, 91, 90, 89

AV2 D[7:0]

I/O

Audio/Video Data 7 (MSB) through 0. Byte-wide interface to the AV layer 2.

External application clock. Rising edge active. This pin can be programmed to output the

application clock. Depending on the configuration of AV Port 2 as transmitter or receiver, the

output enable is located in the ITXPKCTL register (address 0x020) or IRXPKCTL register

(address 0x040).

84

AV2CLK

I/O

83

85

AV2SYNC

I/O

Start of packet indicator; should only be used when AV2VALID is active.

Programmable frame sync, can be set to input or output. Frame sync input used for Digital Video

(DV). The signal is time stamped and transmitted in the SYT field of ITXHQ2. Frame sync output.

Signal is derived from SYT field of IRXHQ2.

AV2FSYNC

End of application packet indication from data source. Required only if input packet is not multiple

of 4 bytes. It can be tied LOW for data packets that are 4*N in size.

82

86

81

80

99

AV2ENDPCK

AV2VALID

AV2ERR0

I

I/O

O

Indicates data on AV2 D [7:0] is valid.

CRC error, indicates bus packet containing AV2 D [7:0] had a CRC error, the current AV packet is

unreliable.

AV2ERR1

O

Sequence Error. Indicates at least one source packet was lost before the current AV2 D [7:0] data.

Encryption key state. Indicates state “1” or “0” of encryption key which matches present port data

during receive mode. Used to input key state during transmit mode.

AV2ENKEY

I/O

9.4 Phy Interface

PIN No.

PIN SYMBOL

I/O

I

NAME AND FUNCTION

Data 0 (MSB) through 7 (NOTE: To preserve compatibility to the specified Link-Phy interface of

the IEEE 1394–1995 standard, Annex J, bit 0 is the most significant bit). Data is expected on

PHY D[0:1] for 100Mb/s, PHY D[0:3] for 200Mb/s, and PHY D[0:7] for 400Mb/s. See IEEE

1394–1995 standard, Annex J for more information.

43, 42, 41, 40,

37, 36, 35, 34

PHY D[0:7]

PHY CTL[0:1]

ISO_N

47, 46

48

Control Lines between Link and Phy. See 1394 Specification for more information.

Isolation mode. This pin is asserted (LOW) when an Annex J type isolation barrier is used.

See IEEE 1394–1995 Annex J. for more information. When tied HIGH, this pin enables internal

bushold circuitry on the affected PHY interface pins (see below). Active bushold circuits allow

either the direct connection to PHY pins or the use of the single capacitor isolation mode.

Link Request. Bus request to access the PHY. See IEEE 1394–1995 standard, Annex J for more

information. (Used to request arbitration or read/write PHY registers).

54

55

LREQ

SCLK

O

I

System clock. 49.152MHz input from the PHY (the PHY-LINK interface operates at this frequency).

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1999 Aug 06

Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

HIGH, the inverter will turn the upper MOS transistor on,

9.4.1 Bushold and Link/PHY single capacitor

galvanic isolation

re-enforcing the HIGH on the input pin. If the driving logic device is

then 3-Stated, the upper MOS transistor will weakly hold the input

pin HIGH.

9.4.1.1 Bushold

The PDI1394L21 uses an internal bushold circuit on each of the

indicated pins to keep these CMOS inputs from “floating” while being

driven by a 3-Stated device or input coupling capacitor.

Unterminated high impedance inputs react to ambient electrical

noise which cause internal oscillation and excess power supply

current draw.

The PHY’s outputs can be 3-Stated and single capacitor isolation

can be used with the Link; both situations will allow the Link inputs to

float. With bushold circuitry enabled, these pins are provided with dc

paths to ground, and power by means of the bushold transistors;

this arrangement keeps the inputs in known logical states.

The following pins have bushold circuitry enabled when the ISO_N

pin is in the logic “1” state:

Pin No.

47

Name

Function

PHYCTL0

PHYCTL1

LREQ

PHY control line 0

PHY control line 1

Link request line

PHY data bus bit 0

PHY data bus bit 1

PHY data bus bit 2

PHY data bus bit 3

PHY data bus bit 4

PHY data bus bit 5

PHY data bus bit 6

PHY data bus bit 7

46

54

INTERNAL

INPUT PIN

43

PHYD0

PHYD1

PHYD2

PHYD3

PHYD4

PHYD5

PHYD6

PHYD7

CIRCUITS

42

41

40

37

36

35

SV00911

34

Figure 1. Bushold circuit

Philips bushold circuitry is designed to provide a high resistance

pull-up or pull-down on the input pin. This high resistance is easily

overcome by the driving device when its state is switched. Figure 1

shows a typical bushold circuit applied to a CMOS input stage. Two

weak MOS transistors are connected to the input. An inverter is also

connected to the input pin and supplies gate drive to both

transistors. When the input is LOW, the inverter output drives the

lower MOS transistor and turns it on. This re-enforces the LOW on

the input pin. If the logic device which normally drives the input pin

were to be 3-Stated, the input pin would remain “pulled-down” by the

weak MOS transistor. If the driving logic device drives the input pin

9.4.1.2 Single capacitor isolation

The circuit example (Figure 2) shows the connections required to

implement basic single capacitor Link/PHY isolation.

NOTE: The isolation enablement pins on both devices are in their

“1” states, activating the bushold circuits on each part. The bushold

circuits provide local dc ground references to each side of the

isolating/coupling capacitors. Also note that ground

isolation/signal-coupling must be provided in the form of a parallel

combination of resistance and capacitance as indicated in

IEEE 1394–1995.

APPLICATION

+3.3V

ISOLATED

+3.3V

6, 13, 24, 32, etc.

48

ISO_N

ISO–

D0

D1

43

Cc

PHY D0

PHY D1

42

Cc

LINK

PDI1394L21

PHY

41

40

47

46

54

55

Cc

PDI1394Pxx

D2

PHY D2

PHY D3

PHYCTL0

PHYCTL1

LREQ

Cc

D3

PHYCTL0

PHYCTL1

LREQ

Cc

SCLK

SYSCLK

1MEG Ω

APPLICATION GROUND

ISOLATED PHY GROUND

SV00912

Cr

Cc = 0.001µF; Cr = 0.1µF

Figure 2. Single capacitor Link/PHY isolation

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1999 Aug 06

Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

9.5 Other Pins

PIN No.

65, 66, 67

51, 62, 100

30

PIN SYMBOL

RESERVED

N/C

I/O

NA

I

NAME AND FUNCTION

These pins are reserved for factory testing. For normal operation they should be connected to

ground.

These pins should not be connected or terminated.

Provides the capability to supply an external cycle timer signal for the beginning of 1394 bus

cycles.

CYCLEIN

33

11

CYCLEOUT

CLK25

O

Reproduces the 8kHz cycle clock of the cycle master.

Auxiliary clock, value is SCLK/2 (usually 24.576 MHz)

10.0 RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

CONDITIONS

UNIT

MIN.

3.0

0

MAX.

3.6

5

V

CC

DC supply voltage

Input voltage

V

I

V

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Input transition rise or fall time

Operating ambient temperature range

System clock

2.0

V

IH

V

0.8

8

V

IL

I

mA

ns/V

°C

OH

I

OL

–8

dT/dV

0

20

T

amb

0

49.147

0

+70

49.157

24

SCLK

MHz

ns

AVCLK

AV interface clock

t

Input rise time

10

r

t

f

input fall time

10

ns

1, 2

11.0 ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).

LIMITS

SYMBOL

PARAMETER

CONDITIONS

UNIT

MIN

–0.5

–

MAX

+4.6

–50

V

I

DC supply voltage

V

mA

V

DD

DC input diode current

DC input voltage

IK

V

I

–0.5

–

+5.5

±50

I

DC output diode current

DC output voltage

mA

V

OK

V

O

–0.5

–

V

+0.5

DD

I

O

DC output source or sink current

±50

mA

°C

W

I

, I

DC V or GND current

–

±150

150

70

GND CC

CC

T

stg

Storage temperature range

Operating ambient temperature

Power dissipation per package

–60

0

T

amb

P

tot

0.6

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

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1999 Aug 06

Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

11.1 Buffer Memory Sizes

SIZE

(Quadlets)

BUFFER MEMORY

Asynchronous Receive Response FIFO

Asynchronous Receive Request FIFO

Asynchronous Transmit Response FIFO

Asynchronous Transmit Request FIFO

Isochronous (AV) Transmit Buffer

64

128

64

1024

Isochronous (AV) Receive Buffer

12.0 FUNCTIONAL DESCRIPTION

12.1 Overview

The PDI1394L21 is an IEEE 1394–1995 compliant link layer controller. It provides a direct interface between a 1394 bus and various MPEG–2

and DVC codecs. Via this interface, the AV Link maps and unmaps these AV datastreams from these codecs onto 1394 isochronous bus

packets. The AV Link also provides an 8051 compatible microcontroller interface for an attached host controller. Through the host interface port,

the host controller can configure the AV layer for transmission or reception of AV datastreams. The host interface port also allows the host

controller to transmit and receive 1394 asynchronous data packets.

12.2 AV interface and AV layer

The AV interface and AV layer allow AV packets to be transmitted from one node to another. The AV transmitter and receiver within the AV layer

perform all the functions required to pack and unpack AV packet data for transfer over a 1394 network. Once the AV layer is properly configured

for operation, no further host controller service should be required. The operation of the AV layer is full-duplex, i.e., the AV layer can receive and

transmit AV packets at the same time.

12.2.1 The AV Interface

The AV Link provides an 8 bit data path to the AV layer. The 8 bit data path is designed with associated clock and control signals to be

compatible with various MPEG–2 and DVC codecs.

The AV interface port buffer, if so programmed, can time stamp incoming AV packets. The AV packet data is stored in the embedded memory

buffer, along with its time stamp information. After the AV packet has been written into the AV layer, the AV layer creates an isochronous bus

packet with the appropriate CIP header. The bus packet along with the CIP header is transferred over the appropriate isochronous

channel/packet. The size and configuration of isochronous data packet payload transmitted is determined by the AV layer’s configuration

registers accessible through the host interface.

The AV interface port waits for the assertion for AVxVALID and AVxSYNC. Note: Do not assert AVxSYNC without AVxVALID. AVxSYNC is

aligned with the rising edge of AVxCLK and the first byte of data on AVxDATA[7:0]. The duration of AVxSYNC is one AVxCLK cycle. AVxSYNC

signals the AV layer that the transfer of an AV packet has begun. At the time the AVxSYNC is asserted, the AV layer creates a new time stamp

in the buffer memory. (This only happens if so configured. The DVC format does not use these time stamps). The time stamp is then transmitted

as part of the source packet header. This allows the AV receiver to provide the AV packet for output at the appropriate time. Only one AVSYNC

pulse is allowed per application packet; if additional sync pulses are presented before the full packet is inputted, a new packet will be started

and the previously inputted packet data will be discarded (and not transmitted) in conjunction with the input error interrupt bit (INPERR, bit 3 of

register 0x02C) being set to flag the error.

When the DV video is enabled (via the format code of the CIP header), the frame synchronization signal AVxFSYNC is time stamped and

placed in the SYT field. The default timestamp value is 3 cycle times (duration of 125ms each) in the future and is transmitted in the SYT field of

the current CIP header; this value is programmable from 2 to 4 cycle times (see section 13.2.1). On the receiver side, when the SYT stamp

matches the cycle timer register, a pulse is generated on the AVxFSYNC output. The timing for AVxFSYNC is independent of AVxCLK.

12.2.2 IEC 61883 International Standard

The PDI1394L21 is specifically designed to support the IEC61883 International Standard of Digital Interface for Consumer Electronic

Audio/Video Equipment. The IEC specification defines a scheme for mapping various types of AV datastreams onto 1394 isochronous data

packets. The standard also defines a software protocol for managing isochronous connections in a 1394 bus called Connection Management

Protocol (CMP). It also provides a framework for transfer of functional commands, called Function Control Protocol (FCP).

12.2.3 CIP Headers

A feature of the IEC61883 International Standard is the definition of Common Isochronous Packet (CIP) headers. These CIP headers contain

information about the source and type of datastream mapped onto the isochronous packets.

The AV Layer supports the use of CIP headers. CIP headers are added to transmitted isochronous data packets at the AV data source. When

receiving isochronous data packets, the AV layer automatically analyzes their CIP headers. The analysis of the CIP headers determines the

method the AV layer uses to unpack the AV data from the isochronous data packets.

The information contained in the CIP headers is accessible via registers in the host interface.

(See IEC61883 International Standard of Digital Interface for Consumer Electronic Audio/Video Equipment for more details on CIP headers).

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12.3 The host interface

The host interface allows an 8 bit CPU to access all registers and the asynchronous packet queues. It is specifically designed for an 8051

microcontroller but can also be used with other CPUs. There are 64 register addresses (for quadlet wide registers). To access bytes rather than

quadlets the address spaces is 256 bytes, requiring 8 address lines.

The use of an 8 bit interface introduces an inherent problem that must be solved: register fields can be more than 8 bits wide and be used

(control) or changed (status) at every internal clock tick. If such a field is accessed through an 8 bit interface it requires more than one read or

write cycle, and the value should not change in between to maintain consistency. To overcome this problem accesses to the chip’s internal

register space are always 32 bits, and the host interface must act as a converter between the internal 32 bit accesses and external 8 bit

accesses. This is where the shadow registers are used.

12.3.1 Read accesses

To read an internal register the host interface can make a snapshot (copy) of that specific register which is then made available to the CPU 8

bits at a time. The register that holds the snapshot copy of the real register value inside the host interface is called the read shadow register.

During a read cycle address lines HIF A0 and HIF A1 are used to select which of the 4 bytes currently stored in the read shadow register is

output onto the CPU data bus. This selection is done by combinatorial logic only, enabling external hardware to toggle these lines through

values 0 to 3 while keeping the chip in a read access mode to get all 4 bytes out very fast (in a single extended read cycle), for example into an

external quadlet register.

This solution requires a control line to direct the host interface to make a snapshot of an internal register when needed, as well as the internal

address of the target register. The register address is connected to input address lines HIF A2..HIF A7, and the update control line to input

address line HIF A8. To let the host interface take a new snapshot the target address must be presented on HIF A2..HIF A7 and HIF A8 must be

raised while executing a read access. The new value will be stored in the read shadow register and the selected byte (HIF A0, HIF A1)

appears on the output.

TR

MUX

Q

8

32

CPU

REGISTERS

32

HIF A0..1

HIF A2..7

HIF A8

UPDATE/COPY CONTROL

SV00803

NOTES:

1. It is not required to read all 4 bytes of a register before reading another register. For example, if only byte 2 of register 0x54 is required a

read of byte address 0x100 + (0×54) + 2 = 0x156 is sufficient.

2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by

other means, for example a combinatorial circuit that activates the update control line whenever a read access is done for byte 0. This

makes the internal updating automatic for quadlet reading.

3. Reading the bytes of the read shadow register can be done in any order and as often as needed.

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12.3.2 Write accesses

To write to an internal register the host interface must collect the 4 byte values into a 32 bit value and then write the result to the target register

in a single clock tick. This requires a register to hold the 32 bit value being compiled until it is ready to be written to the actual target register.

This temporary register inside the host interface is called the write shadow register. During all write cycles address lines HIF A0 and HIF A1

are used to select which of the 4 bytes of the write shadow register is to be written with the value on the CPU data bus. Only one byte can be

written in a single write access cycle.

TR

MUX

Q

MUX

8

32

CPU

REGISTERS

32

HIF A0..1

HIF A2..7

HIF A8

UPDATE/COPY CONTROL

SV00804

NOTES:

1. It is not required to write all 4 bytes of a register: those bytes that are either reserved (undefined) or don’t care do not have to be written in

which case they will be assigned the value that was left in the corresponding byte of the write shadow register from a previous write

access. For example, to acknowledge an interrupt for the isochronous receiver (external address 0x04C), a single byte write to location

0x100+(0x4C)+3 = 0x14F is sufficient. The value 256 represents setting HIF A8=1. The host interface cannot directly access the FIFOs, but

instead reads from/writes into a transfer register (shown as TR in the Figures above). Data is moved between FIFO and TR by internal logic

as soon as possible without CPU intervention.

2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by

other means, for example a combinatorial circuit that activates the update control line whenever a write access is done for byte 3. This

makes the internal updating automatic for quadlet writing.

3. Writing the bytes of the read shadow register can be done in any order and as often as needed (new writes simply overwrite the old value).

12.3.3 Byte order

The bytes in each quadlet are numbered 0..3 from left (most significant) to right (least significant) as shown in Figure 3. To access a register at

internal address N the CPU should use addresses E:

E = N

; to access the upper 8 bits of the register.

; to access the upper middle 8 bits of the register.

; to access the lower middle 8 bits of the register.

; to access the lower 8 bits of the register.

E = N + 1

E = N + 2

E = N + 3

3130 29 28 27 2625 24 23 22 212019 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

BYTE 0

BYTE 1

BYTE 2

BYTE 3

SV00656

Figure 3. Byte order in quadlets as implemented in the host interface

12.3.4 Accessing the packet queues

Although entire incoming packets are stored in the receiver buffer memory they are not randomly accessible. These buffers act like FIFOs and

only the frontmost (oldest) data quadlet entry is accessible for reading. Therefore only one location (register address) is allocated to each of the

two receiver queues. Reading this location returns the head entry of the queue, and at the same time removes it from the queue, making the

next stored data quadlet accessible.

With the current host interface such a read is in fact a move operation of the data quadlet from the queue to the read shadow register. Once the

data is copied into the read shadow register it is no longer available in the queue itself so the CPU should always read all 4 bytes before

attempting any other read access (be careful with interrupt handlers for the PDI1394L21!).

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12.3.5 The CPU bus interface signals

The CPU interface is directly compatible with an 8051 microcontroller. It uses a separate HIF RD_N and HIF WR_N inputs and a HIF CS_N chip

select line, all of which are active LOW. There are 9 address inputs (HIF A0..HIF A8) and 8 data in/out lines HIF D0..HIF D7. An open drain

HIF INT_N output is used to signal interrupts to the CPU.

The CPU is not required to run at a clock that is synchronous to the 1394 base clock. The control signals will be resampled by the host interface

before being used internally.

An access through the host interface starts when HIF CS_N = 0 and either HIF WR_N = 0 or HIF RD_N = 0. Typically the chip select signal is

derived from the upper address lines of the CPU (address decode stage), but it could also be connected to a port pin of the CPU to avoid the

need for an external address decoder in very simple CPU systems. When both HIF CS_N = 0 and HIF RD_N = 0 the host interface will start a

read access cycle, so the cycle is triggered at the falling edge of either HIF CS_N or HIF RD_N, whichever is later.

HIF CS_N

T

AS

HIF RD_N

T

AS

HIF WR_N

HIF A8

HIF A0..HIF A7

T

ACC

HIF D0..HIF D7

RSR

n

O

n

SV00686

Figure 4. Read cycle signal timing (2 independent read cycles)

HIF CS_N

HIF RD_N

T

AS

HIF WR_N

T

AS

HIF A0..HIF A8

HIF D0..HIF D7

SV00687

Figure 5. Write cycle signal timing (2 independent write cycles)

12.4 The Asynchronous Packet Interface

The PDI1394L21 provides an interface to asynchronous data packets through the registers in the host interface. The format of the

asynchronous packets is specified in the following sections.

12.4.1 Reading an Asynchronous Packet

Upon reception of a packet, the packet data is stored in the appropriate receive FIFO, either the Request or Response FIFO. The location of the

packet is indicated by either the RREQQQAV or RRSPQAV status bit being set in the Asynchronous Interrupt Acknowledge (ASYINTACK)

register. The packet is transferred out of the FIFO by successive reads of the Asynchronous Receive Request (RREQ) or Asynchronous

Receive Response (RRSP) register. The end of the packet (the last quadlet) is indicated by either the RREQQLASTQ or RRSPQLASTQ bit set

in ASYINTACK. Attempting to read the FIFO when either RREQQQAV bit or RRSPQQAV bit is set to 0 (in the Asynchronous RX/TX interrupt

acknowledge (ASYINTACK) register) will result in a queue read error.

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12.5 Link Packet Data Formats

The data formats for transmission and reception of data are shown below. The transmit format describes the expected organization for data

presented to the link at the asynchronous transmit, physical response, or isochronous transmit FIFO interfaces.

12.5.1 Asynchronous Transmit Packet Formats

These sections describe the formats in which packets need to be delivered to the queues (FIFOs) for transmission. There are four basic formats

as follows:

TRANSACTION CODE

ITEM

FORMAT

No-packet data

USAGE

Quadlet read requests

(tCode)

4

2

0

6

5

1

7

9

1

Quadlet/block write responses

Quadlet write requests

Quadlet read responses

Block read requests

2

Quadlet packet

Block write requests

Block read responses

Lock requests

3

4

Block Packet

Lock responses

B

hex

E

hex

Unformatted transmit

Concatenated self-ID / PHY packets

Each packet format uses several fields (see names and descriptions below). More information about these fields (not the format) can be found

in the 1394 specification. Grey fields are reserved and should be set to zero values.

12.5.1.1 No-data Transmit

The no-data transmit formats are shown in Figures 6 and 7. The first quadlet contains packet control information. The second and third quadlets

contain 16-bit destination ID and either the 48-bit, quadlet aligned destination offset (for requests) or the response code (for responses).

31 30 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

0000

destinationID

destinationOffsetHigh

destinationOffsetLow

SV00250

Figure 6. Quadlet Read Request Transmit Format

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

0000

destinationID

rCode

SV00249

Figure 7. Quadlet/Block Write Response Packet Transmit Format

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Table 1. No-Data Transmit Format

Field Name

Description

spd

This field indicates the speed at which this packet is to be sent. 00=100 Mbs, 01=200 Mbs, and 10=400 Mbs.

11 = undefined

tLabel

This field is the transaction label, which is used to pair up a response packet with its corresponding request packet.

The retry code for this packet. Supported values are: 00=retry1, and 01=retryX.

The transaction code for this packet.

rt

tCode

DestinationID

Contains a node ID value.

DestinationOffsetHigh

DestinationOffsetLow

The concatenation of these two field addresses a quadlet in the destination node’s address space.

Response code for write response packet.

rCode

Meaning

0

1–3

4

Node successfully completed requested operation.

Reserved

Resource conflict detected by responding agent. Request may be retried.

5

6

7

Hardware error. Data not available.

Field within request packet header contains unsupported or invalid value.

Address location within specified node not accessible.

Reserved

8–Fh

12.5.1.2 Quadlet Transmit

Three quadlet transmit formats are shown below. In these figures: The first quadlet contains packet control information. The second and third

quadlets contain 16-bit destination ID and either the 48-bit quadlet-aligned destination offset (for requests) or the response code (for responses).

The fourth quadlet contains the quadlet data for read response and write quadlet request formats, or the upper 16 bits contain the data length

for the block read request format.

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

0000

destinationID

destinationOffsetHigh

destinationOffsetLow

quadlet data

SV00251

Figure 8. Quadlet Write Request Transmit Format

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31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

0000

destinationID

rCode

quadlet data

SV00252

Figure 9. Quadlet Read Response Transmit Format

31 30 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

0000

destinationID

destinationOffsetHigh

destinationOffsetLow

data length

SV00253

Figure 10. Block Read Request Transmit Format

Table 2. Quadlet Transmit Fields

Field Name

Description

spd, tLabel, rt, tCode, destinationID,

destinationOffsetHigh, destinationOffsetLow, rCode

See Table 1.

Quadlet data

Data length

For quadlet write requests and quadlet read responses, this field holds the data to

be transferred.

The number of bytes requested in a block read request.

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12.5.1.3 Block Transmit

The block transmit format is shown below, this is the generic format for reads and writes. The first quadlet contains packet control information.

The second and third quadlets contain the 16-bit destination node ID and either the 48-bit destination offset (for requests) or the response code

and reserved data (for responses). The fourth quadlet contains the length of the data field and the extended transaction code (all zeros except

for lock transaction). The block data, if any, follows the extended transaction code.

31 30 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

0000

destinationID

dataLength

destinationOffsetHigh

extendedTcode

destinationOffsetLow

Block data

padding (if needed)

SV00254

Figure 11. Block Packet Transmit Format

31 30 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0

spd

tLabel

rt

tCode

0000

destinationID

rCode

dataLength

extendedTcode

Block data

padding (if needed)

SV00255

Figure 12. Block Read or Lock Response Transmit Format

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Table 3. Block Transmit Field

Field Name

Description

spd, tLabel, rt, tCode, destinationID,

See Table 2.

destinationOffsetHigh, destinationOffsetLow, rCode

dataLength

The number of bytes of data to be transmitted in this packet

extendedTcode

The tCode indicates a lock transaction, this specifies the actual lock action to be

performed with the data in this packet.

block data

padding

The data to be sent. If dataLength=0, no data should be written into the FIFO for

this field. Regardless of the destination or source alignment of the data, the first

byte of the block must appear in the high order byte of the first quadlet.

If the dataLength mod 4 is not zero, then zero-value bytes are added onto the end

of the packet to guarantee that a whole number of quadlets is sent.

12.5.1.4 Unformatted Transmit

The unformatted transmit format is shown in Figure 13. The first quadlet contains packet control information. The remaining quadlets contain

data that is transmitted without any formatting on the bus. No CRC is appended on the packet, nor is any data in the first quadlet sent. This is

used to send PHY configuration and Link-on packets. Note that the bit-inverted check quadlet must be included in the FIFO since the AV Link

core will not generate it.

31 3029 28 27 2625 24 23 22 212019 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

spd

tLabel

1110

0000

unformatted packet data

SV00256

Figure 13. Unformatted Transmit Format

12.5.2 Asynchronous Receive Packet Formats

This section describes the asynchronous receive packet formats. Four basic asynchronous data packet formats and one confirmation format exist:

Table 4. Asynchronous Data Packet Formats

ITEM

FORMAT

USAGE

Quadlet read requests

TRANSACTION CODE

4

2

0

6

5

1

7

9

1

No-packet data

Quadlet/block write responses

Qaudlet write requests

Quadlet read responses

Block read requests

2

Quadlet packet

Block Packet

Block write requests

3

Block read responses

Lock requests

Lock responses

B

E

hex

4

5

Self-ID / PHY packet

Confirmation packet

Concatenated self-ID / PHY packets

Confirmation of packet transmission

hex

8

Each packet format uses several fields. More information about most of these fields can be found in the 1394 specification.

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Table 5. Asynchronous Receive Fields

Field Name

Description

destinationID

This field is the concatenation of busNumbers (or all ones for “local bus”) and nodeNumbers (or all ones for

broadcast) for this node.

tLabel

rt

This field is the transaction label, which is used to pair up a response packet with its corresponding request packet.

The retry code for this packet. 00=retry1, 01=retryX, 10=retryA, 11=retryB.

The transaction code for this packet.

tCode

priority

sourceID

The priority level for this packet (0000 for cable environment).

This is the node ID of the sender of this packet.

destinationOffsetHigh, The concatenation of these two field addresses a quadlet in this node’s address space.

destinationOffsetLow

rCode

Response code for response packets.

quadlet data

dataLength

extendedTcode

For quadlet write requests and quadlet read responses, this field holds the data received.

The number of bytes of data to be received in a block packet.

If the tCode indicates a lock transaction, this specifies the actual lock action to be performed with the data in this

packet.

block data

padding

The data received. If dataLength=0, no data will be written into the FIFO for this field. Regardless of the destination

or source alignment of the data, the first byte of the block will appear in the high order byte of the first quadlet.

If the dataLength mod 4 is not zero, then zero-value bytes are added onto the end of the packet to guarantee that a

whole number of quadlets is sent.

u

Unsolicited response tag bit. This bit is set to one (1) if the received response was unsolicited.

ackSent

This field contains the acknowledge code that the link layer returned to the sender of the received packet. For

packets that do not need to be acknowledged (such as broadcasts) the field contains the acknowledge value that

would have been sent if an acknowledge had been required. The values for this field are listed in Table 6 (they also

can be found in the IEEE 1394 standard).

Table 6. Acknowledge codes

Code

Name

Description

0001

ack_complete

The node has successfully accepted the packet. If the packet was a request subaction, the

destination node has successfully completed the transaction and no response subaction shall follow.

0010

0100

0101

0110

1101

ack_pending

ack_busy_X

ack_busy_A

ack_busy_B

ack_data_error

The node has successfully accepted the packet. If the packet was a request subaction, a response

subaction will follow at a later time. This code shall not be returned for a response subaction.

The packet could not be accepted. The destination transaction layer may accept the packet on a

retry of the subaction.

The packet could not be accepted. The destination transaction layer will accept the packet when the

node is not busy during the next occurrence of retry phase A.

The packet could not be accepted. The destination transaction layer will accept the packet when the

node is not busy during the next occurrence of retry phase B.

The node could not accept the block packet because the data field failed the CRC check, or because

the length of the data block payload did not match the length contained in the dataLength field. This

code shall not be returned for any packet that does not have a data block payload.

1110

ack_type_error

reserved

A field in the request packet header was set to an unsupported or incorrect value, or an invalid

transaction was attempted (e.g., a write to a read-only address).

0000, 0011,

0111 – 1100,

and 1111

This revision of the AV Link will not generate other acknowledge codes, but may receive them from

newer (1394 A) links. In that case, these new values will show up here.

NOTE:

1. Upon receipt of a broadcast packet, if any ACK code other than ACK_DATA_ERROR is produced, asume packet receipt was OK.

ACK_DATA ERROR indicates the packet was received with an error, appropriate steps should be taken to ignore the packet and inform the

sending node of the error.

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12.5.2.1 No-Data Receive

The no-data receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second

and third quadlet contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for

responses). The last quadlet contains packet reception status.

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

destinationOffsetHigh

destinationOffsetLow

spd

ackSent

SV00257

Figure 14. Quadlet Read Request Receive Format

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

rCode

spd

u

ackSent

SV00258

Figure 15. Write Response Receive Format

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12.5.2.2 Quadlet Receive

The quadlet receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second

and third quadlets contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for

responses). The fourth quadlet is the quadlet data for read responses and write quadlet requests, and is the data length and reserved for block

read requests. The last quadlet contains packet reception status.

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

destinationOffsetHigh

destinationOffsetLow

quadlet data

spd

ackSent

SV00259

Figure 16. Quadlet Write Request Receive Format

31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

rCode

quadlet data

spd

u

ackSent

SV00260

Figure 17. Quadlet Read Response Receive Format

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313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

destinationOffsetHigh

destinationOffsetLow

data length

spd

ackSent

SV00261

Figure 18. Block Read Request Receive Format

12.5.2.3 Block receive

The block receive format is shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and

third quadlets contain 16-bit sourceID and either the 48-bit destination offset (for requests) or the response code and reserved data (for

responses). The fourth quadlet contains the length of the data field and the extended transaction code (all zeros except for lock transactions).

The block data, if any, follows the extended code. The last quadlet contains packet reception status.

31 30 29 28 2726 25 24 23 22 21 2019 18 17 16 15 1413 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

destinationOffsetHigh

destinationOffsetLow

dataLength

extendedTcode

Block data

padding (if needed)

spd

ackSent

SV00262

Figure 19. Block Write or Lock Request Receive Format

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313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

destinationID

tLabel

rt

tCode

priority

sourceID

rCode

dataLength

extendedTcode

Block data

padding (if needed)

spd

u

ackSent

SV00263

Figure 20. Block Read or Lock Response Receive Format

12.5.2.4 Self-ID and PHY packets receive

The self-ID and PHY packet receive formats are shown below. The first quadlet contains a synthesized packet header with a tCode of 0xE

(hex). For self-ID information, the remaining quadlets contain data that is received from the time a bus reset ends to the first subaction gap. This

is the concatenation of all the self-ID packets received. Note that the bit-inverted check quadlet is included in the Read Request FIFO and the

application must check it.

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

1110

0000

2

self ID packet data

00

ackSent

SV00264

Figure 21. Self-ID Receive Format

The “ackSent” field will either be “ACK_DATA_ERROR” if a non-quadlet-aligned packet is received or there was a data overrun, or

“ACK_COMPLETE” if the entire string of self-ID packets was received.

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31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

1110

0000

2

PHY packet first quadlet

SV00265

Figure 22. PHY Packet Receive Format

For PHY packets, there is a single following quadlet which is the first quadlet of the PHY packet. The check quadlet has already been verified

and is not included.

12.5.2.5 Transaction data confirmation formats

After a packet from one of the queues has been transmitted, the asynchronous transmitter assembles a confirmation (see Figure 23) which is

used to confirm the result of the transmission to the higher layers. Separate confirmations are assembled for request and response

transmissions. Request confirmations are written into the receiver request queue and response confirmations are written into the receiver

response queue.

313029 28 27 2625 24 23 22 21 2019 18 17 16 15 14 13 12 11 10

9

8

2

7 6 5 4 3 2 1 0

destinationID

tLabel

00

1000

conf

2

SV00821

Figure 23. Request and response confirmation format

Table 7. Confirmation codes

1

CODE

DESCRIPTION

0

1

Non-broadcast packet transmitted; addressed node returned no acknowledge (transaction complete).

Broadcast packet transmitted or non-broadcast packet transmitted; addressed node returned an acknowledge complete

(transaction complete).

2

4

Non-broadcast packet transmitted; addressed node returned an acknowledge pending.

Retry limit exceeded; destination node hasn’t accepted the non-broadcast packet within the maximum number of retries

(transaction complete).

D

E

Acknowledge data error received (transaction complete).

Acknowledge type error received (transaction complete).

16

NOTE:

1. All other codes are reserved.

For every packet written in a transmitter queue by the CPU, there will be one confirmation written in the corresponding receiver queue by the AV

layer logic.

23

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Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

12.5.3 Interrupts

The PDI1394L21 provides a single interrupt line (HIF INT_N) for connection to a host controller. Status indications from four major areas of the

device are collected and ORed together to activate HIF INT_N. Status from four major areas of the device are collected in four status registers;

LNKPHYINTACK, ITXINTACK, IRXINTACK, and ASYINTACK. At this level, each individual status can be enabled to generate a chip-level

interrupt by activating HIF INT_N. To aid in determining the source of a chip-level interrupt, the major area of the device generating an interrupt

is indicated in the lower 4 bits of the GLOBCSR register. These bits are non-latching Read-Only status bits and do not need to be

acknowledged. To acknowledge and clear a standing interrupt, the bit in LNKPHYINTACK, ITXINTACK, IRXINTACK, or ASYINTACK causing

the interrupt status has to be written to a logic ‘1’; Note: Writing a value of ‘0’ to the bit has no effect.

12.5.3.1 Determining and Clearing Interrupts

When responding to an interrupt event generated by the PDI1394L21, or operating in polled mode, the first register examined is the GLOBCSR

register. The least significant nibble contains interrupt status bits from general sections of the device; the link layer controller, the AV transmitter,

the AV receiver, and the asynchronous transceiver. The bits in GLOBCSR[3:0] are self clearing status bits. They represent the logical OR of all

the enabled interrupt status bits in their section of the AV Link Layer Controller.

Once an interrupt, or status is detected in GLOBCSR, the appropriate interrupt status register needs to be read, see the Interrupt Hierarchy

diagram for more detail. After all the interrupt indications are dealt with in the appropriate interrupt status register, the interrupt status indication

will automatically clear in the GLOBCSR.

All interrupt status bits in the various interrupt status registers are latching unless otherwise noted.

12.5.3.2 Interrupt Hierarchy

HIF INT_N

3

2 1 0

GLOBCSR (0x018)

18 1716 15 14 13 12 11 10

9

1

0

8 7 6 5 4 3 2 1 0

LNKPHYINTACK (0x008)

10

9

8

7

6

5

4

3

2

0

IRXINTACK (0x04C)

6

7

5 4 3 2 1

9

ITXINTACK (0x02C)

16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

ASYINTACK (0x0A0)

SV01076

Figure 24. Interrupt Hierarchy

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Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

13.0 REGISTER MAP

Registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. This means that it is not possible to write just the

lower 8 bits, and leave the other bits unaffected (see Section 12.3.2 for more information). The values written to undefined fields/bits are ignored

and thus DON’T CARE.

A full bitmap of all registers is listed in Table 8. The meaning of shading and bit cell values is as follows:

A bit/field with no name written in it and dark shading is reserved and not used.

A bit/field with a name in it and light shading is a READ ONLY (status) bit/field.

A one bit value (0 or 1) written at the bottom of a writeable (control) bit is the default value after power-on-reset.

Table 8. Full Bitmap of all Registers (consists of three tables shown on the following pages)

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Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

31

24 23

16 15

8

7

0

REGISTER

ADDRESS

IDREG

PART CODE

VERSION CODE

BUS ID

NODE ID

0x000

1

LNKCTL

0x004

BSYCTRL

ATACK

0

1

0

1

0

LNKPHYINTACK

0x008

0

LNKPHYINTE

0x00C

0

CYCLE_SECONDS

CYCLE_NUMBER

CYCTM

0x010

CYCLE_OFFSET

0

PHYACS

0x014

PHYRGAD

PHYRGDATA

PHYRXAD

PHYRXDATA

0

1

GLOBCSR

0x018

0

0x01C

ITXPKCTL

0x020

TRDEL

MAXBL

PM

0

1

0

ITXHQ1

0x024

DBS

FN

QPC

0

ITXHQ2

0x028

FMT

FDF

SYT

0

ITXINTACK

0x02C

0

ITXINTE

0x030

0

SV00883

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Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

31

24 23

16 15

8

7

0

REGISTER

ADDRESS

ITXCTL

0x034

SPD

TAG

CHANNEL

0

ITXMEM

0x038

0x03C

IRXPKCTL

0x040

BPAD

0

1

0

1

0

IRXHQ1

0x044

SID

DBS

FDF

FN

QPC

IRXHQ2

0x048

FMT

SYT

IRXINTACK

0x04C

0

IRXINTE

0x050

0

IRXCTL

0x054

SPD TAG

CHANNEL

ERR

0

IRXMEM

0x058

0x05C

.

0x07C

SV00884

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Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

31

24 23

16 15

8

7

0

REGISTER

ADDRESS

ASYCTL

MAXRC

TOS

0

TOF

0

0x080

0

1

0

1

0

1

0

ASYMEM

0x084

FIRST/MIDDLE QUADLET OF PACKET FOR TRANSMITTER REQUEST QUEUE

(WRITE ONLY)

TX_RQ_NEXT

0x088

LAST QUADLET OF PACKET FOR TRANSMITTER REQUEST QUEUE

(WRITE ONLY)

TX_RQ_LAST

0x08C

FIRST/MIDDLE QUADLET OF PACKET FOR TRANSMITTER RESPONSE QUEUE

(WRITE ONLY)

TX_RP_NEXT

0x090

LAST QUADLET OF PACKET FOR TRANSMITTER RESPONSE QUEUE

(WRITE ONLY)

TX_RP_LAST

0x094

RREQ

0x098

QUADLET OF PACKET FROM RECEIVER REQUEST QUEUE (TRANSFER REGISTER)

RRSP

0x09C

QUADLET OF PACKET FROM RECEIVER RESPONSE QUEUE (TRANSFER REGISTER)

ASYINTACK

0x0A0

0

ASYINTE

0x0A4

0

0x0A8

.

0x0F8

SV00914

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Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

13.1 Link Control Registers

13.1.1 ID Register (IDREG) – Base Address: 0x000

The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset.

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

BUS ID

NODE ID

PART CODE

VERSION CODE

SV00915

Reset Value 0xFFFF0101

Bit 31..22:

R/W

BUS ID: The 10-bit bus number that is used with the Node ID in the source address for outgoing packets and used to

accept or reject incoming packets. This field reverts to all ‘1’s (0x3FF) upon bus reset.

Bit 21..16:

R/W

NODE ID: Used in conjunction with Bus ID in the source address for outgoing packets and used to accept or reject

incoming packets. This register auto-updates with the node ID assigned after the 1394 bus Tree-ID sequence.

Bit 15..8:

Bit 7..0:

R

PART CODE: “01” designates PDI1394L21.

VERSION CODE: “02” shows this is revision level 2 of this part.

13.1.2 General Link Control (LNKCTL) – Base Address: 0x004

The General Link control register is used to program the Link Layer isochronous transceiver, as well as the overall link transceiver. It also

provides general link status.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

BSYCTRL

ATACK

SV00892

Reset Value 0x46000002

Bit 31:

R/W

IDValid (IDVALID): When equal to one, the PDI1394L21 accepts the packets addressed to this node. This bit is

automatically set after selfID complete and node ID is updated.

Bit 30:

R/W

Receive Self ID (RCVSELFID): When asserted, the self-identification packets, generated by each PHY device on the

bus, during bus initialization are received and placed into the asynchronous request queue as a single packet. Bit 30

also enables the reception of PHY configuration packets in the asynchronous request queue.

Bit 29..27:

R/W

Busy Control (BSYCTRL): These bits control what busy status the chip returns to incoming packets. The field is

defined below:

000 = use protocol requested by received packet (either dual phase or single phase)

001 = send busy A when it is necessary to send a busy acknowledge (testing/diagnostics)

010 = send a busy B when it is necessary to send a busy acknowledge (testing/diagnostics)

011 = use single phase retry protocol

100 = use protocol requested in packet, always send a busy ack (for all packets)

101 = busy A all incoming packets

110 = busy B all incoming packets are ‘1’

111 = use single phase retry protocol, always send a busy ack

Bit 26:

Bit 25:

Bit 21:

Bit 20:

Bit 12:

R/W

Transmitter Enable (TxENABLE): When this bit is set, the link layer transmitter will arbitrate and send packets.

Receiver Enable (RxENABLE): When this bit is set, the link layer receiver will receive and respond to bus packets.

Reset Transmitter (RSTTx): When set to one, this synchronously resets the transmitter within the link layer.

Reset Receiver (RSTRx): When set to one, this synchronously resets the receiver within the link layer.

Strict Isochronous (STRICTISOCH): Used to accept or reject isochronous packets sent outside of specified

isochronous cycles (between a Cycle Start and subaction gap). A ‘1’ rejects packets sent outside the specified

cycles, a “0” accepts isochronous packets sent outside the specified cycle.

Bit 11:

R/W

Cycle Master (CYMASTER): When asserted and the PDI1394L21 is attached to the root PHY (ROOT bit = 1), and

the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master

function will be disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle

Master function in such a case, first reset CYMASTER, then set it again.

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Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

Bit 10:

R/W

Cycle Source (CYSOURCE): When asserted, the cycle_count field increments and the cycle_offset field resets for

each positive transition of CYCLEIN. When deasserted, the cycle count field increments when the cycle_offset field

rolls over.

Bit 9:

Bit 6:

Bit 5:

Bit 4:

R/W

R

Cycle Timer Enable (CYTIMREN): When asserted, the cycle offset field increments.

Transmitter Ready (TxRDY): The transmitter is idle and ready.

R

Root (ROOT): Indicates this device is the root on the bus. This automatically updates after the self_ID phase.

R

Busy Flag (BUSYFLAG): The type of busy acknowledge which will be sent next time an acknowledge is required.

0 = Busy A, 1 = Busy B (only meaningful during a dual-phase busy/retry operation).

Bit 3..0:

R

AT acknowledge received (ATACK): The last acknowledge received by the transmitter in response to a packet sent

from the transmit-FIFO interface while the ATF is selected (diagnostic purposes).

13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008

The Link/Phy Interrupt Acknowledge register indicates various status and error conditions in the Link and Phy which can be programmed to

generate an interrupt. The interrupt enable register (LNKPHYINTE) is a mirror of this register. Acknowledgment of an interrupt is accomplished

by writing a ‘1’ to a bit in this register that is set. This action reset the bit indication to a ‘0’. Writing a ‘1’ to a bit that is already “0” will have no

effect on the register.

31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

SV00893

Reset Value 0x00000000

Bit 18:

Bit 17:

R/W

Command Reset Received (CMDRST): A write request to RESET-START has been received.

Fair Gap (FAIRGAP): The serial bus has been idle for a fair-gap time (called subaction gap in the IEEE 1394

specification).

Bit 16:

Bit 15:

R/W

Arbitration Reset Gap (ARBGAP): The serial bus has been idle for an arbitration reset gap.

Phy Chip Int (PHYINT): The Phy chip has signaled an interrupt through the Phy interface. This bit becomes active for

any of the following reasons (1) PHY has detected a loop on the bus, (2) cable power has fallen below the minimum

voltage, (3) the PHY arbitration state machine has timed-out usually indicative of a bus loop, (4) a bus cable has

been disconnected. Typically, recognition and notification of any of the above events by the PHY requires between

166 and 500 microseconds; therefore, this bit is not instantaneously set.

Bit 14:

Bit 13:

R/W

Phy Register Information Received (PHYRRX): A register has been transferred by the Physical Layer device into the

Link.

Phy Reset Started (PHYRST): A Phy-layer reconfiguration has started. This interrupt clears the ID valid bit. (Called

Bus Reset in the IEEE 1394 specification).

Bit 11:

Bit 10:

R/W

Receiver has data (RxDATA): The receiver has confirmed data to the receiver response/request FIFO.

Isochronous Transmitter is Stuck (ITBADFMT): The transmitter has detected invalid data at the transmit-FIFO

interface when the ITF is selected.

Bit 9:

Bit 8:

Bit 7:

Bit 6:

Bit 5:

Bit 4:

R/W

Asynchronous Transmitter is Stuck (ATBADFMT): The transmitter expected start of new async packet in queue, but

found other data (out of sync with user). Reset to clear.

Busy Acknowledge Sent by Receiver (SNT_REJ): The receiver was forced to send a busy acknowledge to a packet

addressed to this node because the receiver response/request FIFO overflowed.

Header Error (HDRERR): The receiver detected a header CRC error on an incoming packet that may have been

addressed to this node.

Transaction Code Error (TCERR): The transmitter detected an invalid transaction code in the data at the transmit

FIFO interface.

Cycle Timed Out (CYTMOUT): ISOCH cycle lasted more than 125µs from Cycle-Start to Fair Gap: Disables cycle

master function

Cycle Second incremented (CYSEC): The cycle second field in the cycle-timer register incremented. This occurs

approximately every second when the cycle timer is enabled.

Bit 3:

Bit 2:

R/W

Cycle Started (CYSTART): The transmitter has sent or the receiver has received a cycle start packet.

Cycle Done (CYDONE): A fair gap has been detected on the bus after the transmission or reception of a cycle start

packet. This indicates that the isochronous cycle is over; Note: Writing a value of ‘0’ to the bit has no effect.

Bit 1:

Bit 0:

R/W

Cycle Pending (CYPEND): Cycle pending is asserted when cycle timer offset is set to zero (rolled over or reset) and

stays asserted until the isochronous cycle has ended.

Cycle Lost (CYLOST): The cycle timer has rolled over twice without the reception of a cycle start packet. This only

occurs when cycle master is not asserted.

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Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C

This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’

to the bit corresponding to the interrupt desired.

This register enables the interrupts described in the Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. A one in any of the

bits enables that function to create an interrupt. A zero disables the interrupt, however the status is readable in the Link /Phy Interrupt

Acknowledge register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

SV00894

Reset Value 0x00000000

Bits 18..0 are interrupt enable bits for the Link/Phy Interrupt Acknowledge (LNKPHYINTACK).

13.1.5 Cycle Timer Register (CYCTM) – Base Address: 0x010

Cycle Timer Register operation is controlled by the Cycle Timer Enable (CYTMREN) bit in the Link Control Register (LNKCTL, 0x004).

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

CYCLE_SECONDS

CYCLE_NUMBER

CYCLE_OFFSET

SV00276

Reset Value 0x00000000

Bit 31..25:

Bit 24..12:

Bit 11..0:

R/W

Seconds count: 1-Hz cycle timer counter.

Cycle Number: 8kHz cycle timer counter.

Cycle Offset: 24.576MHz cycle timer counter.

13.1.6 Phy Register Access (PHYACS) – Base Address: 0x014

This register provides access to the internal registers on the Phy. There are special considerations when reading or writing to this register. When

reading a PHY register, the address of the register is written to the PHYRGAD field with the RDPHY bit set. The PHY data will be valid when the

PHYRRX bit (LNKPHYINTACK register bit 14) is set. Once this happens the register data is available in the PHYRXDATA, the address of the

register just read is also available in the PHYRXAD fields. When writing a Phy register, the address of the register to be written is set in the

PHYRGAD field and the data to be written to the register is set in PHYRGDATA, along with the WRPHY bit being set. Once the write is

complete, the WRPHY bit will be cleared. Do not write a new Read/Write command until the previous one has been completed. After the Self-ID

phase, PHY register 0 will be read automatically.

31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

PHYRGAD

PHYRGDATA

PHYRXAD

PHYRXDATA

SV00277

Reset Value 0x00000000

Bit 31:

R/W

Read Phy Chip Register (RDPHY): When asserted, the PDI1394L21 sends a read register request with address

equal to Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent.

Bit 30:

R/W

Write Phy Chip Register (WRPHY): When asserted, the PDI1394L21 sends a write register request with address

equal to Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent.

Bit 27..24:

Bit 23..16:

Bit 11..8:

Bit 7..0:

R/W

R

Phy Chip Register Address (PHYRGAD): This is the address of the Phy-chip register that is to be accessed.

Phy Chip Register Data (PHYRGDATA): This is the data to be written to the Phy-chip register indicated in Phy Rg Ad.

Phy Chip Register Received Address (PHYRXAD): Address of register from which Phy Rx Data came.

Phy Chip Register Received Data (PHYRXDATA): Data from register addressed by Phy Rx Ad.

R

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Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

13.1.7 Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018

This register is the top level interrupt status register. If the external interrupt line is set, this register will indicate which major portion of the AV

Link generated the interrupt. There is no interrupt acknowledge required at this level. These bits auto clear when the interrupts in the

appropriate section of the device are cleared or disabled. Control of the AV transceiver is also provided by this register.

Bits 0 to 3 are used to identify which internal modules are currently generating an interrupt. After identifying the module, the appropriate register

in that module must be read to determine the exact cause of the interrupt.

NOTES

1. There can be more than one interrupt source active at the same time.

2. The HIF INT_N signal (pin 28) remains active as long as there is at least one more enabled active interrupt status bit.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

SV00857

Reset Value 0x00010000

Bit 18:

Bit 17:

Bit 16:

R/W

Enable output AVPORT2: A ‘1’ enables AVPORT2 as an output. A ‘0’ sets the 3-State condition on the port. In

3-State condition the port may be used as an input or unused output according to the state of DIRAV1 (bit 16).

Enable output AVPORT1: A ‘1’ enables AVPORT1 as an output. A ‘0’ sets the 3-State condition on the port. In

3-State condition the port may be used as an input or unused output according to the state of DIRAV1 (bit 16).

Direction of AVPORT1 (DIRAV1): A ‘1’ enables AVPORT1 as a transmitter, thus AVPORT1 pins are inputs. A ‘0’

configures AVPORT1 as a receiver, AVPORT1 pins are outputs in this configuration. The configuration of AVPORT2

pins is opposite of AVPORT1 pins. When AVPORT1 is set to transmit, AVPORT2 receives and vice versa.

Bit 11:

Bit 10:

Bit 9:

Bit 8:

Bit 3:

R/W

R

Enables generation of external interrupt by asynchronous transmitter and receiver module (ASYTX/RX, bit 3) when

set (1). Disables such interrupts when clear (0) (regardless of ASYINTE contents).

Enables generation of external interrupt by the isochronous transmitter module (ITXINT, bit 2) when set (1).

Disables such interrupts when clear (0) (regardless of ITXINTE contents).

Enables generation of external interrupt by the isochronous receiver module (IRXINT, bit 1) when set (1).

Disables such interrupts when clear (0) (regardless of IRXINTE contents).

Enables generation of external interrupt by general link/phy module (LKPHYINT, bit 0) when set (1). Disables such

interrupts when clear (0) (regardless of LNKPHYINTE contents).

Asynchronous Transmitter/Receiver Interrupt (ASYITX/RX): Interrupt source is in the Asynchronous Transmitter/

Receiver Interrupt Acknowledge/Source register.

Bit 2:

Bit 1:

Bit 0:

R

AV Transmitter Interrupt (ITXINT): Interrupt source is in the AV Transmitter Interrupt Acknowledge/Source register.

AV Receiver Interrupt (IRXINT): Interrupt source is in the AV Receiver Interrupt Acknowledge/Source register.

Link-Phy Interrupt (LNKPHYINT): Interrupt source is in the Link Phy Interrupt Acknowledge register.

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Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

13.2 AV (Isochronous) Transmitter and Receiver Registers

13.2.1 Isochronous Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020

This register allows the user to set up the appropriate AV packets from data entered into the AV interface. The packing and control parameters

(TRDEL, MAXBL, DBS, FN, QPC, and SPH) should never be changed while the transmitter is operating. The only exception to this is the

MAXBL parameter when in MPEG-2 packing mode.

NOTE: When reset of isochronous transmitter is necessary, first disable the transmitter (place bit 4, EN_ITX, LOW), wait for FIFO to empty, then

reset the transmitter (place RST_ITX, bit 0, HIGH). This procedure will ensure that data in the FIFO is transmitted before reset.

3130 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

TRDEL

MAXBL

PM

SV00886

Reset Value 0x00000001

Bit 29..28: R/W

TXAP_CLK: Application Clock, default mode, ‘00’ the AVxCLK pin is an input. This pin can become an application

clock for the isochronous Transmitter (and output) by programming it to ‘01’, ‘10’, or ‘11’.

The programming values are:

00

01

10

11

Input

24.576MHz

12.288MHz

6.144MHz

Note that when enabled as ‘01’, ‘10’, or ‘11’, the AV port that is configured as transmitter and enabled will output this

clock signal on its AVxCLK pin.

Bit 27..16:

R/W

TRDEL: Transport delay. Value added to cycle timer to produce time stamps. Lower 4 bits add to upper 4 bits of

cycle_offset, (Cycle Timer Register, CYCTM). Remainder adds to cycle_count field.

Bit 15..8:

Bit 7:

R/W

MAXBL: The (maximum) number of data blocks to be put in a payload.

ENXTMSTP: Enable External time stamp control. Allows an external time stamp (generated by the application) to be

inserted in place of the link-generated time stamp. Defaults to link generated time stamp. The application must

present the first byte of a quadlet-wide time stamp accompanied by the AVSYNC pulse (and AVVALID) to the

AVPORT. The external time stamp quadlet is inputted first, followed by the application data packet. The transmitted

packet size is now one quadlet larger than the original isochronous data packet—Set up the isochronous

transmitter accordingly with SPH = 1. CAUTION: Unless valid IEC 61883 time stamp format (based on the link cycle

timer) is used, the receiving node link chip must be equipped with a time stamp check disabling function similar to

the DIS_TSC bit (register 0X040, Bit 7). Please see section 13.2.8 for details.

Bit 6..5:

R/W

SYT_DELAY: Programmable delay of AV1FSYNC and AV2FSYNC. Each cycle is 1 bus cycle, 125 ms.

Reset value is “00”, a 3 cycle delay.

01 = 2 cycles

00 = 3 cycles

10 = 4 cycles

11 = Reserved

Bit 4:

R/W

EN_ITX: Enable receipt of new application packets and generation of isochronous bus packets in every cycle. This

bit also enables the Link Layer to arbitrate for the transmitter in each subsequent bus cycle. When this bit is disabled

(0), the current packet will be transmitted and then the transmitter will shut down.

Bit 3..2:

PM: packing mode:

00 = variable sized bus packets, most generic mode.

01 = fixed size bus packets.

10 = MPEG–2 packing mode.

11 = No data, just CIP headers are transmitted.

Bit 1:

Bit 0:

R/W

EN_FS:enable generation/insertion of SYT stamps (Time Stamps) in CIP header.

Reset Isochronous Transmitter (RST_ITX): causes transmitter to be reset when ‘1’. In order for synchronous reset of

ITX to work properly, an AVxCLK (from either the internal or external source) must be present and ensure that the

reset bit is kept (programmed) HIGH for at least the duration of one AVxCLK period. Failure to do so may cause

the application interface of this module to be improperly reset (or not reset at all). When reset is enabled, all bytes

will be flushed from the FIFO and transmission will cease immediately.

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Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024

The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. This information is

included in Common Isochronous Packet (CIP) header quadlet 1.

31 3029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

DBS

FN

QPC

SV01747

Reset Value 0x00000000

Bit 16..23:

Bit 14..15:

R/W

DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.

FN: (Fraction Number) The encoding for the number of data blocks into which each source packet shall be divided

(00 = 1, 01 = 2, 10 = 4, 11 = 8).

Bit 11..13:

Bit 10:

R/W

QPC: Number of dummy quadlets to append to each source packet before it is divided into data blocks of the

FN

specified size. The value QPC must be less than DBS and less than 2

.

SPH: Indicates that a 25-bit CYCTM based time stamp has to be inserted before each application packet.

13.2.3 Common Isochronous Transmit Packet Header Quadlet 2 (ITXHQ2) – Base Address: 0x028

The contents of this register are copied to the second quadlet of the CIP header and transmitted with each isochronous packet.

313029 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

FMT

FDF

SYT

SV00281

Reset Value 0x00000000

Bit 29..24:

Bit 23..0:

R/W

FMT: Value to be inserted in the FMT field in the AV header.

FDF/SYT: Value to be inserted in the FDF field. When the EN_FS bit in the Transmit Control and Status Register

(ITXPKCTL) is set (=1), the lower 16 bits of this register are replaced by an SYT stamp if a rising edge on

AVFSYNCIN has been detected or all ‘1’s if no such edge was detected since the previous packet. The upper 8 bits

of the register are sent as they appear in the FDF register. When the EN_FS bit in the Transmit Control and Status

Register is unset (=0), the full 24 bits can be set to any application specified value.

34

1999 Aug 06

Philips Semiconductors

Preliminary specification

1394 full duplex AV link layer controller

PDI1394L21

13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C

The AV Transmitter Interrupt Control and Status register is the interrupt register for the AV transmitter.

Bits 2, 3, and 4 ”auto repair” themselves, i.e. AVLINK will detect the situation and attempt to recover on its own. The host controller still needs to

clear these interrupts to be alerted the next time.

31 30 29 28 27 2625 24 23 22 2120 19 18 1716 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

SV00882

Reset Value 0x00000000

Bits 9 .. 0 are interrupt acknowledge bits; and are defined as:

Bit 9:

Bit 8:

Bit 7:

Bit 6:

Bit 5:

Bit 4:

Bit 3:

Bit 2:

Bit 1:

R/W

IT100LFT: Interrupt when transmitter queue reaches 100 quadlets from full. (924 of 1024 quadlets in queue)

IT256LFT: Interrupt when transmitter queue reaches 256 quadlets from full. (768 of 1024 quadlets in queue)

IT512LFT: Interrupt when transmitter queue reaches 50% of full. (512 of 1024 quadlets in queue)

TRMSYT: Interrupt on transmission of a SYT in CIP header quadlet 2

TRMBP: Interrupt on payload transmission/discard complete.

DBCERR: Acknowledge interrupt on Data Block Count (DBC) synchronization loss.

INPERR: Acknowledge interrupt on input error (input data discarded).

DISCARD: Interrupt on lost cycle (payload discarded).

ITXFULL: Interrupt on isochronous memory bank full. This is a fatal error, the recommended action is to reset and

re-initialize the transmitter.

Bit 0:

R/W

ITXEMPTY: Interrupt on isochronous memory bank empty.


型号：	PDI1394L21BP
厂家：	NXP
描述：	1394 full duplex AV link layer controller 1394全双工的AV链路层控制器微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输时钟
文件：	总52页 (文件大小：346K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PDI1394L21BP [NXP]

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