PHB45N03LT/T3 [NXP]
TRANSISTOR 45 A, 25 V, 0.024 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3, FET General Purpose Power;型号: | PHB45N03LT/T3 |
厂家: | NXP |
描述: | TRANSISTOR 45 A, 25 V, 0.024 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3, FET General Purpose Power 开关 脉冲 晶体管 |
文件: | 总6页 (文件大小:45K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT, PHB45N03LT, PHD45N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
VDSS = 30 V
ID = 45 A
R
DS(ON) ≤ 24 mΩ (VGS = 5 V)
g
RDS(ON) ≤ 21 mΩ (VGS = 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHP45N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB45N03LT is supplied in the SOT404 surface mounting package.
The PHD45N03LT is supplied in the SOT428 surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404
SOT428
PIN
1
DESCRIPTION
tab
tab
tab
gate
2
drain1
source
3
2
2
tab drain
1
3
1
3
1 2 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
-
-
-
-
-
-
-
30
30
± 15
45
33
180
86
V
V
V
A
A
A
W
˚C
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tmb = 25 ˚C
- 55
175
1 It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
January 1998
1
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT, PHB45N03LT, PHD45N03LT
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-mb
Thermal resistance junction
to mounting base
-
-
1.75 K/W
Rth j-a
Thermal resistance junction SOT78 package, in free air
-
-
60
50
-
-
K/W
K/W
to ambient
SOT404 and SOT428 packages, pcb
mounted, minimum footprint
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
V(BR)DSS
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
30
27
1
0.5
-
-
-
-
8
-
-
-
-
-
-
-
2
V
V
V
V
V
mΩ
mΩ
mΩ
S
µA
µA
nA
Tj = -55˚C
VDS = VGS; ID = 1 mA
1.5
-
-
20
16
-
27
0.05
-
Tj = 175˚C
Tj = -55˚C
-
2.3
24
21
45
-
10
500
100
RDS(ON)
Drain-source on-state
resistance
VGS = 5 V; ID = 25 A
VGS = 10 V; ID = 25 A
VGS = 5 V; ID = 25 A; Tj = 175˚C
gfs
IDSS
Forward transconductance
Zero gate voltage drain
current
VDS = 25 V; ID = 25 A
VDS = 30 V; VGS = 0 V;
Tj = 175˚C
IGSS
Gate source leakage current VGS = ±5 V; VDS = 0 V
10
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 40 A; VDD = 24 V; VGS = 5 V
-
-
-
23
7
10
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; ID = 25 A;
VGS = 5 V; RG = 5 Ω
Resistive load
-
-
-
-
12
80
35
31
20
130
60
ns
ns
ns
ns
45
Ld
Ld
Internal drain inductance
Internal drain inductance
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
-
-
3.5
4.5
-
-
nH
nH
Ls
Internal source inductance
Measured from source lead to source
bond pad
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
1050
270
140
-
-
-
pF
pF
pF
January 1998
2
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT, PHB45N03LT, PHD45N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
-
-
-
-
45
A
A
V
ISM
VSD
180
IF = 25 A; VGS = 0 V
IF = 40 A; VGS = 0 V
-
-
0.95
1.0
1.2
-
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 40 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 25 V
-
-
52
0.08
-
-
ns
µC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
60
UNIT
WDSS
Drain-source non-repetitive
ID = 25 A; VDD ≤ 15 V;
-
mJ
unclamped inductive turn-off VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
Normalised Power Derating
PD%
Normalised Current Derating
ID%
120
120
110
100
90
80
70
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
Tmb /
100 120 140 160 180
C
0
20
40
60
80
100 120 140 160 180
Tmb /
C
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
January 1998
3
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT, PHB45N03LT, PHD45N03LT
Drain-Source on resistance, RDS(on) (Ohms)
0.06
ID, Drain current (Amps)
1000
4.5 V
3.5 V
4 V
3 V
0.05
0.04
0.03
0.02
0.01
0
tp = 10us
100 us
100
RDS(ON) = VDS/ID
5 V
1 ms
10
10 V
DC
10 ms
100 ms
VGS = 15 V
Tj = 25 C
10
Tmb = 25 C
1
0
20
30
40
50
60
70
80
1
10
100
ID, Drain current (Amps)
VDS, Drain-source voltage (Volts)
Fig.3. Safe operating area
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance
RDS(ON) = f(ID); parameter VGS
Zth j-mb / (K/W)
Drain current, ID (A)
VDS = 25 V
50
40
30
20
10
0
10
D =
1
0.1
0.5
0.2
0.1
p
t
0.05
p
t
P
D
D =
T
0.02
0
Tj = 25 C
3
175 C
t
T
0.01
1E-07
1E-05
1E-03
t / s
1E-01
1E+01
0
1
2
4
5
6
Gate-source voltage, VGS (V)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Fig.7. Typical transfer characteristics.
ID = f(VGS)
ID, Drain current (Amps)
15 V
5 V
10 V
Transconductance, gfs (S)
VDS = 25 V
30
25
20
15
10
5
80
Tj = 25 C
Tj = 25 C
4.5 V
70
60
50
40
30
20
10
0
4 V
175 C
3.5 V
3 V
VGS = 2.5 V
0
0
2
4
6
8
10
0
10
20
30
40
50
VDS, Drain-Source voltage (Volts)
Drain current, ID (A)
Fig.5. Typical output characteristics
ID = f(VDS); parameter VGS
Fig.8. Typical transconductance
gfs = f(ID)
January 1998
4
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT, PHB45N03LT, PHD45N03LT
a
2
C / pF
Ciss
10000
1000
100
1.5
1
0.5
Coss
Crss
0
-100
0
100
200
-50
50
Tj / C
150
0.1
1
10
100
VDS / V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); VGS = 0 V; f = 1 MHz
VGS(TO) / V
max.
VGS, Gate-Source voltage (Volts)
2.5
2
15
10
5
VDS = 24 V
ID = 40 A
Tj = 25 C
typ.
1.5
1
min.
0.5
0
0
0
10
20
30
40
50
-100
-50
0
50
Tj / C
100
150
200
Qg, Gate charge (nC)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Sub-Threshold Conduction
IF / A
1E-01
60
50
40
30
20
10
0
1E-02
1E-03
1E-04
1E-05
1E-05
Tj / C = 175
25
2%
typ
98%
0
0.5
1
1.5
2
VSDS / V
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
ID = f(VGS); VDS = VGS
Fig.14. Typical reverse diode current.
IF = f(VSDS
)
January 1998
5
Rev 1.300
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHP45N03LT, PHB45N03LT, PHD45N03LT
WDSS%
120
VDD
110
100
90
80
70
60
50
40
30
20
10
0
+
L
VDS
-
VGS
-ID/100
T.U.T.
0
R 01
RGS
shunt
20
40
60
80
100
120
140
160
180
Tmb /
C
Fig.16. Avalanche energy test circuit.
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); ID = 25 A
WDSS = 0.5 LID2 BVDSS/(BVDSS − VDD
)
January 1998
6
Rev 1.300
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