PHK18NQ03LT [NXP]
N-channel TrenchMOS logic level FET; N沟道的TrenchMOS逻辑电平FET
| 型号： | PHK18NQ03LT |
| 厂家： | 
NXP |
| 描述： | N-channel TrenchMOS logic level FET |
| 文件： | 总12页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHK18NQ03LT
N-channel TrenchMOS logic level FET
Rev. 01 — 18 December 2006
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
I Optimized for use in DC-to-DC
I Very low switching and conduction
converters
losses
I Logic level compatible
1.3 Applications
I DC-to-DC converters
I Voltage regulators
I Switched-mode power supplies
I Notebook computers
1.4 Quick reference data
I VDS ≤ 30 V
I ID ≤ 20.3 A
I RDSon ≤ 8.9 mΩ
I QGD = 2.5 nC (typ)
2. Pinning information
Table 1.
Pin
Pinning
Description
source (S)
gate (G)
Simplified outline
Symbol
1, 2, 3
4
D
S
8
5
4
5, 6, 7, 8
drain (D)
G
mbb076
1
SOT96-1 (SO8)
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2.
Ordering information
Type number
Package
Name
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
PHK18NQ03LT
SOT96-1
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
VDGR
VGS
ID
drain-source voltage
25 °C ≤ Tj ≤ 150 °C
-
30
V
drain-gate voltage (DC)
gate-source voltage
drain current
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
-
30
V
-
±20
20.3
12.1
80
V
Tsp = 25 °C; VGS = 10 V; see Figure 2 and 3
Tsp = 100 °C; VGS = 10 V; see Figure 2
Tsp = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
Tsp = 25 °C; see Figure 1
-
A
-
A
IDM
Ptot
Tstg
Tj
peak drain current
-
A
total power dissipation
storage temperature
junction temperature
-
6.25
+150
+150
W
°C
°C
−55
−55
Source-drain diode
IS
source current
peak source current
Tsp = 25 °C
-
-
5.2
A
A
ISM
Tsp = 25 °C; pulsed; tp ≤ 10 µs
20.8
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 31.5 A;
tp = 0.07 ms; VDS ≤ 25 V; RGS = 50 Ω;
-
50
mJ
VGS = 10 V; starting at Tj = 25 °C
PHK18NQ03LT_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 18 December 2006
2 of 12
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa17
03aa25
120
120
Ider
(%)
Pder
(%)
80
40
0
80
40
0
0
50
100
150
200
0
50
100
150
200
Tsp ( C)
Tsp ( C)
°
°
Ptot
ID
Pder
=
× 100 %
Ider
=
× 100 %
-----------------------
-------------------
Ptot(25°C)
ID(25°C)
Fig 1. Normalized total power dissipation as a
function of solder point temperature
Fig 2. Normalized continuous drain current as a
function of solder point temperature
003aaa680
103
ID
(A)
Limit RDSon = VDS / ID
102
t =
p
10 µs
100 µs
10
1
1 ms
DC
10 ms
100 ms
10-1
10-1
1
10
102
VDS (V)
Tsp = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHK18NQ03LT_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 18 December 2006
3 of 12
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4.
Thermal characteristics
Symbol Parameter
Conditions
Min
Typ
Max Unit
20 K/W
Rth(j-sp) thermal resistance from junction to solder point
see Figure 4
-
-
003aaa681
102
Zth(j-sp)
(K/W)
δ =0.5
10
0.2
0.1
tp
δ =
0.05
P
1
T
0.02
single pulse
t
tp
T
10-1
10-5
10-4
10-3
10-2
10-1
1
10
tp (s)
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
PHK18NQ03LT_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 18 December 2006
4 of 12
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5.
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max Unit
Static characteristics
V(BR)DSS drain-source breakdown
voltage
ID = 250 µA; VGS = 0 V
Tj = 25 °C
30
27
-
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain leakage current
ID = 1 mA; VDS = VGS; see Figure 9 and 10
Tj = 25 °C
1.3
0.8
-
1.7
2.15
-
V
V
V
Tj = 150 °C
-
-
Tj = −55 °C
2.6
IDSS
VDS = 30 V; VGS = 0 V
Tj = 25 °C
-
-
-
-
-
1
µA
µA
nA
Ω
Tj = 150 °C
-
100
100
-
IGSS
RG
gate leakage current
gate resistance
VGS = ±16 V; VDS = 0 V
f = 1 MHz; VGSS(AC) = 150 mV
VGS = 10 V; ID = 25 A; see Figure 6 and 8
Tj = 25 °C
-
1.6
RDSon
drain-source on-state
resistance
-
-
-
7.1
8.9
mΩ
Tj = 150 °C
12.1 15.1 mΩ
10.1 12.5 mΩ
VGS = 4.5 V; ID = 25 A; see Figure 6 and 8
Dynamic characteristics
QG(tot)
QGS
QGS1
QGS2
QGD
VGS(pl)
Ciss
total gate charge
ID = 15 A; VDS = 12 V; VGS = 4.5 V;
see Figure 11 and 12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10.6
4.85
2.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
V
gate-source charge
pre-VGS(th) gate-source charge
post-VGS(th) gate-source charge
gate-drain charge
2.45
2.5
gate-source plateau voltage
input capacitance
3
VGS = 0 V; VDS = 12 V; f = 1 MHz;
see Figure 14
1380
290
135
1590
19
pF
pF
pF
pF
ns
ns
ns
ns
Coss
Crss
Ciss
output capacitance
reverse transfer capacitance
input capacitance
VGS = 0 V; VDS = 0 V; f = 1 MHz
td(on)
tr
td(off)
tf
turn-on delay time
VDS = 12 V; RL = 0.8 Ω; VGS = 4.5 V;
RG = 5.6 Ω
rise time
22
turn-off delay time
19
fall time
11
Source-drain diode
VSD
trr
source-drain voltage
IS = 20 A; VGS = 0 V; see Figure 13
-
-
-
0.95 1.2
V
reverse recovery time
recovered charge
IS = 15 A; dIS/dt = −100 A/µs; VGS = 0 V
34
14
-
-
ns
nC
Qr
PHK18NQ03LT_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 18 December 2006
5 of 12
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aaa682
003aaa684
20
50
RDSon
(mΩ)
10 4.5 3.4
3.2
3
VGS (V) = 2.8
ID
(A)
40
3
15
10
5
30
20
10
0
3.2
3.4
2.8
2.6
4.5
10
VGS (V) =
2.4
0.8
0
0
0.2
0.4
0.6
0
5
10
15
20
ID (A)
V
DS (V)
Tj = 25 °C
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
003aaa683
003aab467
40
2
ID
a
(A)
1.6
30
20
10
1.2
0.8
0.4
0
Tj = 150 °C
25 °C
0
0
1
2
3
4
-60
0
60
120
180
VGS (V)
Tj (°C)
Tj = 25 °C and 150 °C; VDS > ID × RDSon
RDSon
a =
-----------------------------
RDSon(25°C)
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
PHK18NQ03LT_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 18 December 2006
6 of 12
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aab272
003aab271
3
10-3
VGS(th)
(V)
2.5
ID
(A)
max
2
10-4
min
typ
max
typ
1.5
min
1
0.5
0
10-5
10-6
-60
0
60
120
180
0
0.5
1
1.5
2
2.5
V
GS (V)
Tj (°C)
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
003aaa685
10
ID = 15 A
VGS
(V)
Tj = 25 °C
8
6
4
2
0
V
DS
I
D
VDS = 19 V
12 V
V
GS(pl)
V
GS(th)
GS
V
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
0
5
10
15
20
QG (nC)
25
003aaa508
ID = 15 A; VDS = 12 V and 19 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Gate charge waveform definitions
PHK18NQ03LT_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 18 December 2006
7 of 12
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
003aaa686
003aaa687
40
104
IS
(A)
C
(pF)
30
20
10
Ciss
103
150 °C
Tj = 25 °C
Coss
Crss
0
102
10-1
0
0.4
0.8
1.2
1
10
102
V
SD (V)
VDS (V)
Tj = 25 °C and 150 °C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain
voltage; typical values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aaa688
104
C
(pF)
Ciss
Crss
103
102
10-1
1
10
V
GS (V)
VGS = 0 V; f = 1 MHz
Fig 15. Input and reverse transfer capacitances as a function of gate-source voltage; typical values
PHK18NQ03LT_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 18 December 2006
8 of 12
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT96-1
076E03
MS-012
Fig 16. Package outline SOT96-1 (SO8)
PHK18NQ03LT_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 18 December 2006
9 of 12
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 6.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PHK18NQ03LT_1
20061218
Product data sheet
-
-
PHK18NQ03LT_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 18 December 2006
10 of 12
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
PHK18NQ03LT_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 18 December 2006
11 of 12
PHK18NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.1
9.2
9.3
9.4
10
11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2006.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 December 2006
Document identifier: PHK18NQ03LT_1
相关型号：
©2020 ICPDF网 联系我们和版权申明