PHKD3NQ10T [NXP]
Dual N-channel TrenchMOS transistor; 双N沟道晶体管的TrenchMOS
| 型号： | PHKD3NQ10T |
| 厂家： | 
NXP |
| 描述： | Dual N-channel TrenchMOS transistor |
| 文件： | 总7页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
FEATURES
SYMBOL
QUICK REFERENCE DATA
• Dual device
• Low on-state resistance
• Fast switching
• Low profile surface mount
package
d1
d2
s2
VDS = 100 V
ID = 3 A
g1
g2
R
DS(ON) ≤ 90 mΩ (VGS = 10 V)
s1
GENERAL DESCRIPTION
PINNING
SOT96-1
8
7
6
5
Dual N-channel enhancement
mode field-effect transistor in a
plastic envelope using ’trench’
technology.
PIN
DESCRIPTION
source 1
gate 1
1
2
Applications:-
• Motor and relay drivers
• d.c. to d.c. converters
3
source 2
gate 2
pin 1 index
4
1
2
3
4
The PHKD3NQ10T is supplied in
the SOT96-1 (SO8) surface
mounting package.
5,6
7,8
drain 2
drain 1
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
Continuous drain-source voltage
Drain-gate voltage
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C;
RGS = 20 kΩ
-
-
100
100
V
V
VGS
ID
Gate-source voltage
Drain current per MOSFET
-
-
-
-
-
-
± 20
3
2.4
2.2
1.7
12
V
A
A
A
A
A
Ta = 25 ˚C, t ≤ 10 s
Ta = 70 ˚C, t ≤ 10 s
Ta = 25 ˚C, t ≤ 10 s
Ta = 70 ˚C, t ≤ 10 s
ID
Drain current per MOSFET (both
MOSFETs conducting)
Drain current (pulse peak value per Ta = 25 ˚C
MOSFET)
IDM
Ptot
Total power dissipation
Ta = 25 ˚C, t ≤ 10 s
Ta = 70 ˚C, t ≤ 10 s
-
-
2
1.3
150
W
W
˚C
Tstg, Tj
Storage & operating temperature
- 65
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-a
Thermal resistance junction Surface mounted on FR4 board, t ≤ 10
to ambient sec; either or both MOSFETs conducting
Thermal resistance junction Surface mounted on FR4 board; either or
to ambient both MOSFETs conducting
-
62.5
K/W
Rth j-a
150
-
K/W
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
ELECTRICAL CHARACTERISTICS
Tj= 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS Drain-source breakdown
CONDITIONS
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 250 µA;
100
-
-
-
-
V
V
voltage
Tj = -55˚C
89
VGS(TO)
Gate threshold voltage
VDS = VGS; ID = 1 mA
2
1.1
3
-
4
-
6
90
216
100
10
100
V
V
V
mΩ
mΩ
nA
µA
µA
Tj = 150˚C
Tj = -55˚C
-
-
-
-
-
-
RDS(ON)
Drain-source on-state
resistance
Gate source leakage current VGS = ±20 V; VDS = 0 V
Zero gate voltage drain
current
VGS = 10 V; ID = 1.5 A
70
-
10
0.05
-
Tj = 150˚C
Tj = 150˚C
IGSS
IDSS
VDS = 100 V; VGS = 0 V;
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 3 A; VDD = 80 V; VGS = 10 V
-
-
-
21
2.5
8
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 50 V; RD = 15 Ω;
VGS = 10 V; RG = 5.6 Ω
Resistive load
-
-
-
-
6
-
-
-
-
ns
ns
ns
ns
12
20
10
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from drain lead to centre of die
Measured from source lead to source
bond pad
-
-
2.5
5
-
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
-
-
-
633
103
61
-
-
-
pF
pF
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source diode
current
Ta = 25 ˚C, t ≤ 10 s
-
-
2
A
ISM
VSD
Pulsed source diode current
Diode forward voltage
-
-
-
12
1.2
A
V
IF = 2 A; VGS = 0 V
0.8
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 2 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
-
-
55
135
-
-
ns
nC
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
Transient thermal impedance, Zth j-a (K/W)
Normalised Power Derating, PD (%)
100
100
10
D = 0.5
90
80
70
60
50
40
30
20
10
0
0.2
0.1
0.05
0.02
1
single pulse
P
D = tp/T
D
tp
0.1
T
0.01
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
0
25
50
75
100
125
150
Ambient temperature, Ta (C)
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Ta)
Fig.4. Transient thermal impedance.
Zth j-a = f(t); parameter D = tp/T
Drain Current, ID (A)
6
5
4
3
2
1
0
Normalised Current Derating, ID (%)
VGS = 10V
8 V
5.4 V
100
90
80
70
60
50
40
30
20
10
0
5.2 V
Tj = 25 C
5 V
6 V
4.8 V
4.6 V
4.4 V
0
25
50
75
100
125
150
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Ambient temperature, Ta (C)
Drain-Source Voltage, VDS (V)
Fig.2. Normalised continuous drain current.
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
ID% = 100 ID/ID 25 ˚C = f(Ta); VGS ≥ 10 V
Peak Pulsed Drain Current, IDM (A)
100
10
Drain-Source On Resistance, RDS(on) (Ohms)
0.2
4.6V
4.8V
5 V
0.18
0.16
0.14
0.12
0.1
RDS(on) = VDS/ ID
tp = 10 us
100 us
1 ms
5.2 V
5.4 V
6V
1
10 ms
0.08
0.06
0.04
0.02
0
8 V
D.C.
100 ms
0.1
0.01
VGS = 10V
Tj = 25 C
1
0.1
1
10
100
1000
0
2
3
4
5
6
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
Fig.3. Safe operating area
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
Threshold Voltage, VGS(TO) (V)
Drain current, ID (A)
4.5
4
6
VDS > ID X RDS(ON)
maximum
5
4
3
3.5
3
typical
2.5
2
minimum
150 C
1.5
1
2
Tj = 25 C
1
0
0.5
0
0
1
2
3
4
5
6
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.10. Gate threshold voltage.
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
V
Transconductance, gfs (S)
VDS > ID X RDS(ON)
Drain current, ID (A)
15
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
14
13
12
11
10
9
8
7
6
5
Tj = 25 C
minimum
150 C
typical
maximum
4
3
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
6
Gate-source voltage, VGS (V)
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised On-state Resistance
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
Capacitances, Ciss, Coss, Crss (pF)
10000
Ciss
1000
100
10
Coss
Crss
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
0.1
1
10
100
Junction temperature, Tj (C)
Drain-Source Voltage, VDS (V)
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
Source-Drain Diode Current, IF (A)
VGS = 0 V
6
5
4
3
2
1
0
Gate-source voltage, VGS (V)
15
ID = 3A
14
13
12
11
10
9
Tj = 25 C
VDD = 20 V
150 C
8
7
6
5
4
3
2
1
VDD = 80 V
Tj = 25 C
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Gate charge, QG (nC)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Source-Drain Voltage, VSDS (V)
1
1.1 1.2
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
MECHANICAL DATA
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
v
c
y
H
M
A
E
Z
5
8
Q
A
2
A
(A
)
3
A
1
pin 1 index
θ
L
p
L
1
4
e
w
M
detail X
b
p
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(2)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.050
1.05
0.041
0.25
0.01
0.25
0.1
1.75
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches 0.069
0.01 0.004
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-05-22
SOT96-1
076E03S
MS-012AA
Fig.15. SOT96 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Integrated Circuit Packages, Data Handbook IC26.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999
7
Rev 1.000
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