PHX14NQ20T,127 [NXP]
PHX14NQ20T;
| 型号： | PHX14NQ20T,127 |
| 厂家： | 
NXP |
| 描述： | PHX14NQ20T 局域网 开关 脉冲 晶体管 |
| 文件： | 总9页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Low on-state resistance
• Fast switching
VDSS = 200 V
ID = 7.6 A
g
RDS(ON) ≤ 230 mΩ
s
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic full pack envelope using ’trench’ technology.
The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching
applications.
The PHX14NQ20T is supplied in the SOT186A (FPAK) conventional leaded package.
PINNING
SOT186A (FPAK)
SOT186 (FPAK)
PIN
DESCRIPTION
case
case
1
2
3
gate
drain
source
case isolated
1
2 3
1
2 3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 kΩ
-
-
-
-
-
-
-
200
200
± 20
7.6
4.8
30
V
V
V
A
A
A
W
˚C
Ths = 25 ˚C; VGS = 10 V
Ths = 100 ˚C; VGS = 10 V
Ths = 25 ˚C
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Ths = 25 ˚C
30
150
- 55
November 2000
1
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS Non-repetitive avalanche
CONDITIONS
MIN.
MAX.
UNIT
Unclamped inductive load, IAS = 14 A;
tp = 38 µs; Tj prior to avalanche = 25˚C;
-
70
mJ
energy
VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer
to fig 15
IAS
Peak non-repetitive
avalanche current
-
14
A
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-hs
Thermal resistance junction
to mounting base
-
-
4.17 K/W
Rth j-a
Thermal resistance junction SOT186A package, in free air
to ambient
-
55
-
K/W
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS Drain-source breakdown
CONDITIONS
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 0.25 mA;
200
-
-
-
-
V
V
voltage
Tj = -55˚C
178
VGS(TO)
Gate threshold voltage
VDS = VGS; ID = 1 mA
2
1
-
3
-
-
4
-
6
V
V
V
Tj = 150˚C
Tj = -55˚C
RDS(ON)
Drain-source on-state
resistance
Forward transconductance
Gate source leakage current VGS = ± 10 V; VDS = 0 V
Zero gate voltage drain
current
VGS = 10 V; ID = 7 A
VGS = 10 V; ID = 7 A; Tj = 150˚C
VDS = 25 V; ID = 7 A
-
-
6
-
-
150
-
12.1
10
0.05
-
230
540
-
100
10
500
mΩ
mΩ
S
nA
µA
µA
gfs
IGSS
IDSS
VDS = 200 V; VGS = 0 V
Tj = 150˚C
-
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 14 A; VDD = 160 V; VGS = 10 V
-
-
-
38
4
13.3
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 100 V; RD = 10 Ω;
VGS = 10 V; RG = 5.6 Ω
Resistive load
-
-
-
-
25
40
83
31
-
-
-
-
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from drain lead to centre of die
Measured from source lead to source
bond pad
-
-
4.5
7.5
-
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
1500
128
60
-
-
-
pF
pF
pF
November 2000
2
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
-
-
-
-
-
14
56
A
A
V
ISM
VSD
IF = 14 A; VGS = 0 V
1.0
1.5
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 14 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
-
135
690
-
-
ns
nC
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Visol
Visol
Cisol
R.M.S. isolation voltage from all SOT186A package; f = 50-60 Hz;
-
-
-
2500
1500
-
V
three terminals to external
heatsink
sinusoidal waveform; R.H. ≤ 65%;
clean and dustfree
Repetitive peak voltage from all SOT186 package; R.H. ≤ 65%;
V
three terminals to external
heatsink
clean and dustfree
f = 1 MHz
Capacitance from pin 2 to
external heatsink
10
pF
November 2000
3
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
Transient thermal impedance, Zth j-a (K/W)
Normalised Power Derating
PD%
120
10
1
with heatsink compound
110
D = 0.5
0.2
100
90
80
70
60
50
40
30
20
10
0
0.1
0.05
0.02
0.1
single pulse
0.01
0
20
40
60
80
Ths /
100
120
140
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
C
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Drain Current, ID (A)
Normalised Current Derating
ID%
30
25
20
15
10
5
120
10V
15V
with heatsink compound
110
100
90
80
70
60
50
40
30
20
10
0
6.5V
6 V
5.5
5 V
VGS=4.5
0
0
1
2
3
4
5
6
7
8
9
10
0
20
40
60
80
Ths /
100
120
140
Drain-Source Voltage, VDS (V)
C
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Drain-Source On Resistance, RDS(on) (Ohms)
0.8
Peak Pulsed Drain Current, IDM (A)
1000
4.5V
0.7
5V
100
0.6
RDS(on) = VDS/ ID
5.5V
0.5
0.4
tp = 10 us
10V
10
6.5V
6V
100us
0.3
0.2
0.1
0
1 ms
D.C.
1
VGS =20 V
10 ms
100 ms
0.1
0
10
20
1
10
100
1000
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
November 2000
4
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
Drain current, ID (A)
28
VGS(TO) / V
5
4.5
4
max
typ
24
20
16
3.5
3
min
2.5
2
150 C
12
8
Tj = 25 C
1.5
1
4
0
0.5
0
0
2
4
6
8
10
-100
-50
0
50
100
150
Tj / C
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Fig.10. Gate threshold voltage.
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
V
Transconductance, gfs (S)
Sub-Threshold Conduction
20
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
15
10
5
2%
typ
98%
0
0
4
8
12
16
ID / (A)
20
24
28
0
1
2
3
4
5
Fig.8. Typical transconductance, Tj = 25 ˚C.
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
gfs = f(ID); conditions: VDS = 25 V
Capacitances, Ciss, Coss, Crss (pF)
a
Rds(on) normalised to 25 deg C
10000
2.5
2
Ciss
1000
100
10
Coss
Crss
1.5
1
0.5
0
10
20
30
40
-70
-20
30
80
130
Drain-Source Voltage, VDS (V)
Ths / deg C
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 7 A; VGS = 10 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
November 2000
5
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
Gate-source voltage, VGS (V)
14
Maximum Avalanche Current, IAS (A)
100
10
1
12
VDD = 40 V
10
25 C
8
6
VDD = 160 V
Tj prior to avalanche = 150 C
4
2
0
0.1
0
10
20
30
40
0.001
0.01
0.1
1
10
Gate charge, QG (nC)
Avalanche time, tAV (ms)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 14 A; parameter VDS
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
Source-Drain Diode Current, IF (A)
30
VGS = 0 V
20
150 C
Tj = 25 C
10
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Source-Drain Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
November 2000
6
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Plastic single-ended package; isolated heatsink mounted; 1 mounting hole; 3 lead TO-220
SOT186A
E
P
A
A
1
q
D
1
T
D
j
L
L
2
1
K
Q
b
b
1
L
2
1
2
3
b
w
M
c
e
e
1
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
(1)
(2)
L
A
A
b
b
b
c
D
D
E
e
e
j
K
L
L
1
P
Q
q
T
w
UNIT
mm
2
1
1
2
1
1
max.
1.1
0.9
1.4
1.2
2.7
2.3
0.6 14.4 3.30
0.4 13.5 2.79
2.6
2.3
4.6 2.9
4.0 2.5
0.9
0.7
3.0
2.6
0.7 15.8 6.5 10.3
0.4 15.2 6.3 9.7
3.2
3.0
3
5.08
2.54
2.5
0.4
Notes
1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned.
2. Both recesses are 2.5 × 0.8 max. depth
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-06-11
SOT186A
TO-220
Fig.16. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
November 2000
7
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
Plastic single-ended package; isolated heatsink mounted;
1 mounting hole; 3 lead TO-220 exposed tabs
SOT186
E
E
1
A
P
m
A
1
q
D
1
D
L
1
Q
b
1
L
L
2
1
2
3
b
w
M
c
e
e
1
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
b
b
c
D
D
1
E
E
e
e
L
L
1
m
P
Q
q
w
UNIT
mm
L
2
1
1
1
1
1.5
1.3
14.3
13.5
4.8
4.0
1.4
1.2
4.4
4.0
2.9
2.5
0.9
0.7
4.4
4.0
0.55 17.0
0.38 16.4
7.9 10.2
7.5 9.6
5.7
5.3
0.9
0.5
3.2
3.0
5.08
2.54
10
0.4
Note
1. Terminal dimensions within this zone are uncontrolled. Terminals in this zone are not tinned.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-06-11
SOT186
TO-220
Fig.17. SOT186; The seating plane is electrically isolated from all terminals.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for F-pack envelopes.
3. Epoxy meets UL94 V0 at 1/8".
November 2000
8
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
PHX14NQ20T , PHF14NQ20T
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
November 2000
9
Rev 1.100
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