PSMN050-80BS,118 [NXP]
PSMN050-80BS - N-channel 80 V 46 mΩ standard level MOSFET in D2PAK D2PAK 3-Pin;型号: | PSMN050-80BS,118 |
厂家: | NXP |
描述: | PSMN050-80BS - N-channel 80 V 46 mΩ standard level MOSFET in D2PAK D2PAK 3-Pin |
文件: | 总14页 (文件大小:208K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSMN050-80BS
AK
D2P
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
Rev. 1 — 2 March 2012
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel MOSFET in D2PAK package qualified to 175 °C. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
High efficiency due to low switching
Suitable for standard level gate drive
and conduction losses
sources
1.3 Applications
DC-to-DC converters
Load switching
Motor control
Server power supplies
1.4 Quick reference data
Table 1.
Symbol
VDS
Quick reference data
Parameter
Conditions
Min
Typ
Max
80
Unit
V
drain-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tmb = 25 °C; VGS = 10 V; see Figure 1
-
-
-
-
-
ID
-
22
A
Ptot
total power dissipation Tmb = 25 °C; see Figure 2
junction temperature
-
56
W
Tj
-55
175
°C
Static characteristics
RDSon drain-source on-state
resistance
Dynamic characteristics
VGS = 10 V; ID = 10 A; Tj = 25 °C
-
37
46
mΩ
QGD
gate-drain charge
total gate charge
VGS = 10 V; ID = 25 A; VDS = 40 V;
see Figure 14; see Figure 15
-
-
2.3
11
-
-
nC
nC
QG(tot)
Avalanche ruggedness
EDS(AL)S non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 22 A;
-
-
18
mJ
drain-source
Vsup ≤ 80 V; RGS = 50 Ω; unclamped
avalanche energy
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
2. Pinning information
Table 2.
Pinning information
Symbol Description
Pin
1
Simplified outline
Graphic symbol
G
D
S
D
gate
drain[1]
mb
D
S
2
3
source
G
mb
mounting base;
connected to drain
mbb076
2
1
3
SOT404 (D2PAK)
[1] It is not possible to make connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN050-80BS
D2PAK
plastic single-ended surface-mounted package (D2PAK);
3 leads (one lead cropped)
SOT404
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
80
Unit
V
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
VDGR
VGS
-
80
V
-20
20
V
ID
VGS = 10 V; Tmb = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1
-
-
-
16
A
22
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C;
88
A
see Figure 3
Ptot
Tstg
Tj
total power dissipation
storage temperature
Tmb = 25 °C;see Figure 2
-
56
W
-55
-55
-
175
175
260
°C
°C
°C
junction temperature
Tsld(M)
peak soldering temperature
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
22
88
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 22 A;
Vsup ≤ 80 V; RGS = 50 Ω; unclamped
-
18
mJ
PSMN050-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
2 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
003aad056
03aa16
120
30
ID
P
(%)
der
(A)
80
20
10
0
40
0
0
50
100
150
200
0
50
100
150
200
Tmb (°C)
T
(°C)
mb
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aad301
103
ID
(A)
102
10 μs
Limit RDSon = VDS / ID
10
100 μs
1
DC
1 ms
10 ms
100 ms
10-1
10-2
1
10
102
103
VDS (V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN050-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
3 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from junction to see Figure 4
mounting base
-
2.2
2.7
K/W
Rth(j-a)
thermal resistance from junction to Minimum footprint; mounted on a
-
50
-
K/W
ambient
printed circuit board
003aad055
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
0.05
0.02
10-1
10-2
10-3
10-4
tp
δ =
P
T
single shot
t
tp
T
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN050-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
4 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
6. Characteristics
Table 6.
Characteristics
Tested to JEDEC standards where applicable.
Symbol
Static characteristics
V(BR)DSS drain-source
breakdown voltage
Parameter
Conditions
Min
Typ
Max
Unit
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
73
80
1
-
-
-
-
-
-
V
V
V
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 175 °C;
voltage
see Figure 11; see Figure 12
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 11; see Figure 12
-
-
4.6
4
V
V
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11; see Figure 12
2
3
IDSS
drain leakage current
gate leakage current
VDS = 80 V; VGS = 0 V; Tj = 25 °C
VDS = 80 V; VGS = 0 V; Tj = 125 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
-
-
-
-
-
1
µA
µA
nA
nA
mΩ
15
IGSS
100
100
74
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 10 A; Tj = 100 °C;
see Figure 13
VGS = 10 V; ID = 10 A; Tj = 25 °C
-
-
37
2
46
-
mΩ
RG
internal gate resistance f = 1 MHz
(AC)
Ω
Dynamic characteristics
QG(tot)
total gate charge
ID = 0 A; VDS = 0 V; VGS = 10 V
-
-
-
-
9
-
-
-
-
nC
nC
nC
nC
ID = 25 A; VDS = 40 V; VGS = 10 V;
see Figure 14; see Figure 15
11
3.8
1.9
QGS
gate-source charge
QGS(th)
pre-threshold
gate-source charge
ID = 25 A; VDS = 40 V; VGS = 10 V;
see Figure 14
QGS(th-pl)
QGD
post-threshold
gate-source charge
-
-
-
1.9
2.3
5.2
-
-
-
nC
nC
V
gate-drain charge
ID = 25 A; VDS = 40 V; VGS = 10 V;
see Figure 14; see Figure 15
VGS(pl)
gate-source plateau
voltage
VDS = 40 V
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 17
-
-
-
633
100
50
-
-
-
pF
pF
pF
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 12 V; RL = 0.5 Ω; VGS = 10 V;
RG(ext) = 4.7 Ω
-
-
-
-
9.2
1
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
16
2.4
PSMN050-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
5 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
Table 6.
Characteristics …continued
Tested to JEDEC standards where applicable.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Source-drain diode
VSD
source-drain voltage
IS = 15 A; VGS = 0 V; Tj = 25 °C;
see Figure 16
-
0.86
1.2
V
trr
reverse recovery time IS = 50 A; dIS/dt = 100 A/µs; VGS = 0 V;
-
-
32
28
-
-
ns
VDS = 40 V
Qr
recovered charge
nC
003aad046
003aad047
40
ID
(A)
100
VGS (V) =
5
5.5
10
20
8
RDSon
5.5
(mΩ)
6
6
30
80
60
40
20
8
5
10
20
10
0
20
VGS (V) =
4.5
0
10
20
30
40
0
2
4
6
8
10
ID (A)
V
DS (V)
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
003aad052
003aad053
1000
35
gfs
C
Ciss
(pF)
(S)
30
800
25
20
15
10
5
600
Crss
400
200
0
0
0
10
20
30
40
50
2
4
6
8
10
ID (A)
V
GS (V)
Fig 7. Input and reverse transfer capacitances as a
function of gate-source voltage; typical values
Fig 8. Forward transconductance as a function of
drain current; typical values
PSMN050-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
6 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
003aad054
003aad048
40
100
RDSon
ID
(mΩ)
(A)
30
20
10
80
60
40
20
Tj = 175 °C
25 °C
0
0
5
10
15
20
GS (V)
0
2
4
6
8
V
VGS (V)
Fig 9. Drain-source on-state resistance as a function
of gate-source voltage; typical values
Fig 10. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
03aa35
003aad280
−1
10
5
I
V
D
GS(th)
(V)
(A)
min
typ
max
−2
−3
−4
−5
−6
10
10
10
10
10
4
max
3
typ
2
min
1
0
0
2
4
6
−60
0
60
120
180
V
GS
(V)
T (°C)
j
Fig 11. Sub-threshold drain current as a function of
gate-source voltage
Fig 12. Gate-source threshold voltage as a function of
junction temperature
PSMN050-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
7 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
003aad045
2.5
a
V
2.0
DS
I
D
1.5
1.0
0.5
0.0
V
GS(pl)
V
GS(th)
GS
V
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
-60 -30
0
30
60
90 120 150 180
003aaa508
Tj (°C)
Fig 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig 14. Gate charge waveform definitions
003aad050
003aad049
10
100
IS
VGS
(A)
80
(V)
8
VDS = 40 V
6
4
2
0
60
40
20
0
175 °C
Tj = 25 °C
Q
G (nC)
0
5
10
15
0
0.5
1
1.5
V
SD (V)
Fig 15. Gate-source voltage as a function of gate
charge; typical values
Fig 16. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values
PSMN050-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
8 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
003aad051
103
C
iss
C
(pF)
102
C
oss
C
rss
10
10-1
1
10
102
V
(V)
DS
Fig 17. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PSMN050-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
9 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
7. Package outline
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-02-11
06-03-16
SOT404
Fig 18. Package outline SOT404 (D2PAK)
PSMN050-80BS
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
10 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PSMN050-80BS v.1
20120302
Product data sheet
-
-
PSMN050-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
11 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
9. Legal information
9.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URLhttp://www.nxp.com.
Right to make changes— NXP Semiconductors reserves the right to make
9.2 Definitions
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preview— The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Suitability for use— NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft— The document is a draft version only. The content is still under
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modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
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information. For detailed and full information see the relevant full data sheet,
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In case of any inconsistency or conflict with the short data sheet, the full data
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product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications— Applications that are described herein for any of these
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specified use without further testing or modification.
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shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
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Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
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products planned, as well as for the planned application and use of
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Limited warranty and liability— Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
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damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
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testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
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punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Limiting values— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with theTerms and conditions of commercial saleof NXP Semiconductors.
PSMN050-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
12 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
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sale, as published athttp://www.nxp.com/profile/terms, unless otherwise
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Notice: All referenced brands, product names, service names and trademarks
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the product is not suitable for automotive use. It is neither qualified nor tested
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reenChip,HiPerSmart,HITAG,I²C-buslogo,ICODE,I-CODE,ITEC,Labelution
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10. Contact information
For more information, please visit:http://www.nxp.com
For sales office addresses, please send an email to:salesaddresses@nxp.com
PSMN050-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 March 2012
13 of 14
PSMN050-80BS
NXP Semiconductors
N-channel 80 V 46 mΩ standard level MOSFET in D2PAK
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11
2
3
4
5
6
7
8
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
9.1
9.2
9.3
9.4
10
Contact information. . . . . . . . . . . . . . . . . . . . . .13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 March 2012
Document identifier: PSMN050-80BS
相关型号:
PSMN057-200B/T3
TRANSISTOR 39 A, 200 V, 0.057 ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3, FET General Purpose Power
NXP
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