PSMN130-200D [NXP]
N-channel TrenchMOS transistor; N沟道晶体管的TrenchMOS
| 型号： | PSMN130-200D |
| 厂家： | 
NXP |
| 描述： | N-channel TrenchMOS transistor |
| 文件： | 总12页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DISCRETE SEMICONDUCTORS
DATA SHEET
PSMN130-200D
N-channel TrenchMOS(TM)
transistor
Product specification
August 1999
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
VDSS = 200 V
ID = 20 A
• Low thermal resistance
g
RDS(ON) ≤ 130 mΩ
s
GENERAL DESCRIPTION
PINNING
SOT428 (DPAK)
SiliconMAXproductsusethelatest
Philips Trench technology to
achieve the lowest possible
on-state resistance in each
package at each voltage rating.
PIN
DESCRIPTION
tab
1
2
gate
drain1
source
drain
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
3
2
tab
1
3
The PSMN130-200D is supplied in
the SOT428 (Dpak) surface
mounting package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
-
-
-
-
-
-
-
200
200
± 20
20
14
80
V
V
V
A
A
A
W
˚C
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tmb = 25 ˚C
150
175
- 55
1 It is not possible to make connection to pin 2 of the SOT428 package.
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS Non-repetitive avalanche
CONDITIONS
MIN.
MAX.
UNIT
Unclamped inductive load, IAS = 19 A;
tp = 100 µs; Tj prior to avalanche = 25˚C;
-
252
mJ
energy
VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer
to fig;15
IAS
Non-repetitive avalanche
current
-
20
A
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-mb
Thermal resistance junction
to mounting base
-
-
1
K/W
Rth j-a
Thermal resistance junction SOT428 package, pcb mounted, minimum
to ambient footprint
-
50
-
K/W
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS Drain-source breakdown
CONDITIONS
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 0.25 mA;
200
-
-
-
-
V
V
voltage
Tj = -55˚C
178
VGS(TO)
Gate threshold voltage
VDS = VGS; ID = 1 mA
2
1
-
-
-
-
-
-
3
-
-
120
-
0.02 100
0.05
-
4
-
6
130
377
V
V
V
mΩ
mΩ
nA
µA
µA
Tj = 175˚C
Tj = -55˚C
RDS(ON)
Drain-source on-state
resistance
Gate source leakage current VGS = ±10 V; VDS = 0 V
Zero gate voltage drain
current
VGS = 10 V; ID = 25 A
Tj = 175˚C
IGSS
IDSS
VDS = 150 V; VGS = 0 V;
10
500
Tj = 175˚C
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 20 A; VDD = 160 V; VGS = 10 V
-
-
-
65
10
22
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 100 V; RD = 4.7 Ω;
VGS = 10 V; RG = 5.6 Ω
Resistive load
-
-
-
-
15
46
50
38
-
-
-
-
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured tab to centre of die
Measured from source lead to source
bond pad
-
-
3.5
7.5
-
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
2470
207
90
-
-
-
pF
pF
pF
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
-
-
-
-
20
A
A
V
ISM
-
80
VSD
IF = 25 A; VGS = 0 V
0.95
1.2
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 20 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 25 V
-
-
124
0.74
-
-
ns
µC
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
Transient thermal impedance, Zth j-mb (K/W)
Normalised Power Derating, PD (%)
100
10
1
90
80
70
60
50
40
30
20
10
0
D = 0.5
0.2
0.1
0.1
0.05
P
D = tp/T
0.02
D
tp
0.01
single pulse
T
0.001
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
0
25
50
75
100
125
150
175
Pulse width, tp (s)
Mounting Base temperature, Tmb (C)
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
th j-mb = f(t); parameter D = tp/T
Z
Drain Current, ID (A)
Tj = 25 C
20
18
16
14
12
10
8
Normalised Current Derating, ID (%)
6 V
VGS = 10V
100
90
80
70
60
50
40
30
20
10
0
5.4 V
5.2 V
5 V
8 V
4.8 V
4.6 V
6
4
2
4.4 V
1.8
0
0
25
50
75
100
125
150
175
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
2
Mounting Base temperature, Tmb (C)
Drain-Source Voltage, VDS (V)
Fig.2. Normalised continuous drain current.
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS)
ID% = 100 ID/ID 25 ˚C = f(Tmb); VGS ≥ 10 V
Peak Pulsed Drain Current, IDM (A)
100
Drain-Source On Resistance, RDS(on) (Ohms)
0.3
RDS(on) = VDS/ ID
4.6 V
4.4 V
4.8 V
Tj = 25 C
tp = 10 us
100 us
1 ms
5 V
0.25
0.2
0.15
0.1
0.05
0
10
1
5.2 V
D.C.
5.4 V
10 ms
6V
100 ms
VGS = 10V
8 V
14
0.1
1
10
100
1000
0
2
4
6
8
10
12
16
18
20
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
Fig.3. Safe operating area
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID)
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
Threshold Voltage, VGS(TO) (V)
Drain current, ID (A)
20
4.5
4
VDS > ID X RDS(ON)
18
maximum
typical
16
14
3.5
3
12
2.5
2
175 C
10
minimum
8
Tj = 25 C
1.5
1
6
4
2
0
0.5
0
0
1
2
3
4
5
6
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Transconductance, gfs (S)
VDS > ID X RDS(ON)
Drain current, ID (A)
30
25
20
15
10
5
1.0E-01
Tj = 25 C
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
175 C
minimum
typical
maximum
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
2
4
6
8
10
12
14
16
18
20
Gate-source voltage, VGS (V)
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C
Normalised On-state Resistance
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
Capacitances, Ciss, Coss, Crss (pF)
10000
1000
100
Ciss
Coss
Crss
10
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
0.1
1
10
100
Junction temperature, Tj (C)
Drain-Source Voltage, VDS (V)
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
Maximum Avalanche Current, IAS (A)
100
10
1
Gate-source voltage, VGS (V)
15
ID = 20A
14
13
12
11
10
9
Tj = 25 C
25 C
VDD = 40 V
8
7
6
5
Tj prior to avalanche = 150 C
VDD = 160 V
4
3
2
1
0
0.1
0
5
10 15 20 25 30 35 40 45 50 55 60
Gate charge, QG (nC)
0.001
0.01
0.1
1
10
Avalanche time, tAV (ms)
Fig.13. Typical turn-on gate-charge characteristics.
GS = f(QG)
Fig.15. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
V
Source-Drain Diode Current, IF (A)
VGS = 0 V
30
28
26
24
22
20
18
16
14
12
10
8
175 C
Tj = 25 C
6
4
2
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Source-Drain Voltage, VSDS (V)
1
1.1 1.2
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
7
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
A
y
A
2
E
A
A
1
b
D
1
2
mounting
base
E
1
D
H
E
L
2
2
L
1
L
1
3
b
1
b
w
M
A
c
e
e
1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
b
E
H
E
max.
D
L
1
min.
A
max.
D
max.
E
max.
y
1
1
(1)
1
A
b
2
A
UNIT
b
c
e
e
1
L
L
w
2
1
2
max.
max.
min.
max.
0.65 0.89
0.45 0.71
0.7
0.5
2.38
2.22
0.89 1.1
0.71 0.9
5.36
5.26
0.4 6.22
0.2 5.98
6.73
6.47
10.4 2.95
9.6
2.55
4.81
4.45
mm
4.57
0.2
0.2
4.0 2.285
0.5
Note
1. Measured from heatsink back to lead.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SOT428
98-04-07
Fig.16. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
August 1999
8
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
2.5
1.5
4.57
Fig.17. SOT428 : soldering pattern for surface mounting.
August 1999
9
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
August 1999
10
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN130-200D
NOTES
August 1999
11
Rev 1.000
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69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
603502/300/03/pp12
Date of release: August 1999
Document order number: 9397 750 09675
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NEXPERIA
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