PSMN7R6-100BSE [NXP]
75A, 100V, 0.0076ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3/2;型号: | PSMN7R6-100BSE |
厂家: | NXP |
描述: | 75A, 100V, 0.0076ohm, N-CHANNEL, Si, POWER, MOSFET, PLASTIC, D2PAK-3/2 开关 脉冲 晶体管 |
文件: | 总13页 (文件大小:279K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
18 December 2012
Product data sheet
1. General description
Standard level N-channel MOSFET in a D2PAK package qualified to 175 °C. Part of
NXP's "NextPower Live" portfolio, the PSMN7R6-100BSE complements the latest "hot-
swap" controllers - robust enough to withstand substantial inrush currents during turn on,
whilst offering a low RDS(on) characteristic to keep temperatures down and efficiency up in
continued use. Ideal for telecommunication systems based on a 48 V backplane / supply
rail.
2. Features and benefits
Enhanced forward biased safe operating area for superior linear mode operation
Very low RDS(on) for low conduction losses
•
•
3. Applications
Electronic fuse
Hot swap
Load switch
Soft start
•
•
•
•
4. Quick reference data
Table 1.
Symbol
Quick reference data
Parameter
Conditions
Min
Typ
Max
100
75
Unit
V
VDS
ID
drain-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tmb = 100 °C; VGS = 10 V; Fig. 1
-
-
-
-
-
-
[1]
A
Ptot
total power dissipation Tmb = 25 °C; Fig. 2
296
W
Static characteristics
RDSon drain-source on-state
resistance
Dynamic characteristics
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 12
-
6.5
7.6
mΩ
QGD
gate-drain charge
total gate charge
VGS = 10 V; ID = 25 A; VDS = 50 V;
Fig. 14; Fig. 15
-
-
41
-
-
nC
nC
QG(tot)
128
Scan or click this QR code to view the latest information for this product
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
Symbol
Avalanche Ruggedness
EDS(AL)S non-repetitive drain-
Parameter
Conditions
Min
Typ
Max
Unit
VGS = 10 V; Tj(init) = 25 °C; ID = 75 A;
Vsup ≤ 100 V; RGS = 50 Ω; unclamped;
Fig. 3
-
-
426
mJ
source avalanche
energy
[1] Continuous current limited by package
5. Pinning information
Table 2.
Pin
Pinning information
Symbol Description
Simplified outline
Graphic symbol
mb
D
S
1
G
D
S
D
gate
2
drain[1]
source
G
3
mbb076
mb
mounting base; connected to
drain
2
1
3
D2PAK (SOT404)
[1] It is not possible to make connection to pin 2
6. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN7R6-100BSE
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
7. Marking
Table 4.
Marking codes
Type number
Marking code
PSMN7R6-100BSE
PSMN7R6100BSE
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
100
100
Unit
V
VDS
drain-source voltage
drain-gate voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
VDGR
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
All information provided in this document is subject to legal disclaimers.
18 December 2012
V
PSMN7R6-100BSE
© NXP B.V. 2012. All rights reserved
Product data sheet
2 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
Symbol
VGS
Parameter
Conditions
Min
Max
20
Unit
V
gate-source voltage
drain current
-20
ID
VGS = 10 V; Tj = 25 °C; Fig. 1
VGS = 10 V; Tmb = 100 °C; Fig. 1
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4
Tmb = 25 °C; Fig. 2
[1]
[1]
-
75
A
-
75
A
IDM
peak drain current
-
481
296
175
175
260
A
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
peak soldering temperature
-
W
°C
°C
°C
-55
-55
-
Tsld(M)
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
[1]
-
-
75
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
481
Avalanche Ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 75 A;
Vsup ≤ 100 V; RGS = 50 Ω; unclamped;
Fig. 3
-
426
mJ
[1] Continuous current limited by package
003aak744
03aa16
150
125
100
75
120
I
D
(A)
P
der
(%)
80
(1)
(1)
50
40
25
0
0
0
30
60
90
120
150
T (°C)
180
0
50
100
150
200
j
T
(°C)
mb
(1) Capped at 75A due to package
Fig. 2. Normalized total power dissipation as a
function of mounting base temperature
Fig. 1. Continuous drain current as a function of
mounting base temperature
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
3 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
003aak745
2
10
I
AL
(A)
(1)
(2)
10
1
-3
10
-2
-1
10
10
1
AL
10
t
(ms)
Fig. 3. Single pulse avalanche rating; avalanche current as a function of avalanche time
003aak746
3
10
I
D
(A)
Limit R
= V / I
DS
DSon
D
t
= 10 us
p
2
10
100 us
10
DC
1 ms
10 ms
100 ms
1
-1
10
2
3
1
10
10
10
V
(V)
DS
Fig. 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
Fig. 5
-
0.42
0.51
K/W
Rth(j-a)
thermal resistance
from junction to
ambient
Minimum footprint; mounted on a
printed circuit board
-
50
-
K/W
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
4 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
003aak747
1
Z
th(j-mb)
(K/W)
δ = 0.5
-1
-2
-3
0.2
10
0.1
0.05
t
p
0.02
P
10
10
δ =
T
single shot
t
t
p
T
-6
-5
-4
-3
-2
-1
10
10
10
10
10
10
1
t
p
(s)
Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
100
90
2
-
-
V
V
V
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C;
voltage
3
4
Fig. 10; Fig. 11
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 175 °C;
VGSth
1
-
-
-
-
V
V
voltage
Fig. 11
ID = 1 mA; VDS = VGS; Tj = -55 °C;
Fig. 11
4.6
IDSS
drain leakage current
gate leakage current
VDS = 100 V; VGS = 0 V; Tj = 25 °C
VDS = 100 V; VGS = 0 V; Tj = 175 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
0.1
-
2
µA
µA
nA
nA
mΩ
500
100
100
7.6
IGSS
10
10
6.5
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 12
VGS = 10 V; ID = 25 A; Tj = 100 °C;
Fig. 12; Fig. 13
-
-
13.7
20.5
1.66
mΩ
mΩ
Ω
VGS = 10 V; ID = 25 A; Tj = 175 °C;
Fig. 12; Fig. 13
-
-
RG
gate resistance
f = 1 MHz
0.42
0.83
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
5 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 50 V; VGS = 10 V;
Fig. 14; Fig. 15
-
128
-
nC
ID = 0 A; VDS = 0 V; VGS = 10 V
-
-
-
-
110
33
-
-
-
-
nC
nC
nC
V
QGS
gate-source charge
gate-drain charge
ID = 25 A; VDS = 50 V; VGS = 10 V;
Fig. 14; Fig. 15
QGD
41
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 50 V; Fig. 14; Fig. 15
5.3
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 50 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 16
-
-
-
7110
450
310
-
-
-
pF
pF
pF
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 50 V; RL = 2 Ω; VGS = 10 V;
RG(ext) = 5 Ω
-
-
-
-
31
48
82
47
-
-
-
-
ns
ns
ns
ns
turn-off delay time
fall time
Source-drain diode
VSD source-drain voltage
trr
IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17
-
-
-
0.8
69
1.2
V
reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
-
ns
nC
VDS = 50 V
Qr
recovered charge
210
003aak748
003aak749
120
96
72
48
24
0
20
R
DSon
6.5 V
I
7 V
8 V
6 V
D
(A)
10 V
16
5.5 V
12
8
5 V
4
4.5 V
4 V
0
0
0.5
1
1.5
DS
2
0
4
8
12
16
V (V)
GS
20
V
(V)
Fig. 6. Output characteristics; drain current as a
function of drain-source voltage; typical values
Fig. 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
6 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
003aak751
003aak750
200
80
I
g
fs
D
(A)
(S)
160
60
120
80
40
20
0
40
175°C
T = 25°C
j
0
0
1
2
3
4
5
6
GS
7
(V)
8
0
16
32
48
64
(A)
80
V
I
D
Fig. 9. Transfer characteristics; drain current as a
function of gate-source voltage; typical values
Fig. 8. Forward transconductance as a function of
drain current; typical values
03aa35
003aad280
- 1
10
5
I
V
D
GS(th)
(A)
(V)
min
typ
max
- 2
- 3
- 4
- 5
- 6
10
10
10
10
10
4
max
3
typ
2
min
1
0
0
2
4
6
- 60
0
60
120
180
V
(V)
T (°C)
j
GS
Fig. 10. Sub-threshold drain current as a function of
gate-source voltage
Fig. 11. Gate-source threshold voltage as a function of
junction temperature
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
7 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
003aak752
003aak756
20
3
R
DSon
a
5 V
5.5 V
6 V
2.4
16
1.8
1.2
0.6
0
12
8
6.5 V
7 V 8 V 10 V
4
0
20
40
60
80
100
(A)
120
-60 -30
0
30
60
90 120 150 180
T (°C)
I
D
j
Fig. 12. Drain-source on-state resistance as a function Fig. 13. Normalized drain-source on-state resistance
of drain current; typical values
factor as a function of junction temperature
003aak753
10
V
V
GS
(V)
DS
V
GS
= 20 V
I
D
8
6
4
2
0
V
GS(pl)
80 V
V
GS(th)
GS
50 V
V
Q
Q
GS1
GS2
Q
Q
GD
GS
Q
G(tot)
003aaa508
Fig. 14. Gate charge waveform definitions
0
25
50
75
100
125
(nC)
150
Q
G
Fig. 15. Gate-source voltage as a function of gate
charge; typical values
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
8 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
003aak755
003aak754
4
120
10
I
C
S
(A)
(pF)
C
iss
100
80
60
40
3
10
C
C
oss
T = 175°C
j
T = 25°C
j
rss
20
0
2
10
-1
2
0
0.2
0.4
0.6
0.8
1
(V)
1.2
10
1
10
10
V
V
(V)
SD
DS
Fig. 17. Source current as a function of source-drain
voltage; typical values
Fig. 16. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
9 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
11. Package outline
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-02-11
06-03-16
SOT404
Fig. 18. Package outline D2PAK (SOT404)
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
10 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
12. Legal information
12.1 Data sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Document
Product
Definition
status [1][2] status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preliminary
[short] data
sheet
Qualification This document contains data from the
preliminary specification.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
Product
[short] data
sheet
Production
This document contains the product
specification.
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the Internet at URL http://www.nxp.com.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
12.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
12.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
11 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
12.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
12 / 13
NXP Semiconductors
PSMN7R6-100BSE
N-channel 100 V 7.6 mΩ standard level MOSFET in D2PAK
13. Contents
1
General description ............................................... 1
2
Features and benefits ............................................1
Applications ........................................................... 1
Quick reference data ............................................. 1
Pinning information ...............................................2
Ordering information .............................................2
Marking ...................................................................2
Limiting values .......................................................2
Thermal characteristics .........................................4
Characteristics .......................................................5
Package outline ................................................... 10
3
4
5
6
7
8
9
10
11
12
Legal information .................................................11
Data sheet status ............................................... 11
Definitions ...........................................................11
Disclaimers .........................................................11
Trademarks ........................................................ 12
12.1
12.2
12.3
12.4
© NXP B.V. 2012. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 December 2012
PSMN7R6-100BSE
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
18 December 2012
13 / 13
相关型号:
PSMN7R6-60BS,118
PSMN7R6-60BS - N-channel 60 V 7.8 mΩ standard level MOSFET in D2PAK D2PAK 3-Pin
NXP
PSMN7R8-100PSE
N-channel 100 V 7.8 mΩ standard level MOSFET with improved SOA in TO220 packageProduction
NEXPERIA
PSMN7R8-120PSQ
PSMN7R8-120PS MIKEB - N-channel 120V 7.9mΩ standard level MOSFET in TO220 TO-220 3-Pin
NXP
©2020 ICPDF网 联系我们和版权申明