PTN3365BSMP_技术文档

PTN3365

Enhanced performance HDMI/DVI level shifter with active DDC

buffer, supporting 3 Gbit/s operation

Rev. 1.1 — 28 July 2015

Product data sheet

1. General description

PTN3365 is a high-speed level shifter device which converts four lanes of low-swing

AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain

current-steering differential output signals, up to 3.0 Gbit/s per lane to support 36-bit

deep color mode, 4K  2K video format or 3D video data transport. Each of these lanes

provides a level-shifting differential buffer to translate from low-swing AC-coupled

differential signaling on the source side, to TMDS-type DC-coupled differential

current-mode signaling terminated into 50  to 3.3 V on the sink side. Additionally,

PTN3365 provides a single-ended active buffer for voltage translation of the HPD signal

from 5 V on the sink side to 3.3 V on the source side and provides a channel with active

buffering and level shifting of the DDC channel (consisting of a clock and a data line)

between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using

active I²C-bus buffer technology providing capacitive isolation, redriving and level shifting

as well as disablement (isolation between source and sink) of the clock and data lines.

The low-swing AC-coupled differential input signals to PTN3365 typically come from a

display source with multi-mode I/O, which supports multiple display standards, for

example, DisplayPort, HDMI and DVI. While the input differential signals are configured to

carry DVI or HDMI coded data, they do not comply with the electrical requirements of the

DVI v1.0 or HDMI v1.4b specification. By using PTN3365, chip set vendors are able to

implement such reconfigurable I/Os on multi-mode display source devices, allowing the

support of multiple display standards while keeping the number of chip set I/O pins low.

See Figure 1.

PTN3365 features low-swing self-biasing differential inputs which are compliant to the

electrical specifications of DisplayPort Standard v1.2 and/or PCI Express Standard v1.1,

and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.4b

electrical specifications. The I²C-bus channel actively buffers as well as level-translates

the DDC signals for optimal capacitive isolation. PTN3365 also supports power-saving

modes in order to minimize current consumption when no display is active or connected.

PTN3365 is a full-featured HDMI and DVI level shifter.

PTN3365 is powered from a single 3.3 V power supply consuming a small amount of

power (230 mW typical) and is offered in a 32-terminal HVQFN32 package.

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

MULTI-MODE DISPLAY SOURCE

OE_N

reconfigurable I/Os

PCIe PHY ELECTRICAL

AC-coupled

differential pair

TMDS data

OUT_D4+

OUT_D4-

PCIe

output buffer

TMDS

coded

data

TX

FF

IN_D4+

IN_D4-

DATA LANE

TX

AC-coupled

differential pair

TMDS data

OUT_D3+

OUT_D3-

PCIe

output buffer

TMDS

coded

data

TX

FF

IN_D3+

IN_D3-

DATA LANE

TX

AC-coupled

differential pair

TMDS data

OUT_D2+

OUT_D2-

PCIe

output buffer

TMDS

coded

data

TX

FF

IN_D2+

IN_D2-

DATA LANE

DVI/HDMI

CONNECTOR

TX

PTN3365

OUT_D1+

OUT_D1-

AC-coupled

differential pair

clock

PCIe

output buffer

TMDS

clock

pattern

TX

FF

IN_D1+

IN_D1-

CLOCK LANE

TX

0 V to 3.3 V

quinary input

0 V to 5 V

HPD_SOURCE

EQ5

HPD_SINK

DDC_EN

(0 V to 3.3 V)

3.3 V

5 V

SCL_SOURCE

SDA_SOURCE

SCL_SINK

SDA_SINK

3.3 V

DDC I/O

2

(I C-bus)

CONFIGURATION

aaa-013693

Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].

Fig 1. Typical application system diagram

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

2 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

2. Features and benefits

2.1 High-speed TMDS level shifting

 Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and

HDMI v1.4b compliant open-drain current-steering differential output signals

 TMDS level shifting operation up to 3.0 Gbit/s per lane supporting 4K  2K and 3D

video formats

 Programmable equalizer

 Integrated 50  termination resistors for self-biasing differential inputs

 Back-current safe outputs to disallow current when device power is off and monitor is

on

 Disable feature to turn off TMDS inputs and outputs and to enter low-power state

2.2 DDC level shifting

 Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)

 Rise time accelerator on sink-side DDC ports

 0 Hz to 400 kHz I²C-bus clock frequency

 Back-power safe sink-side terminals to disallow backdrive current when power is off or

when DDC is not enabled

2.3 HPD level shifting

 HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or

from 5 V on the sink side to 3.3 V on the source side

 Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ when

no display is plugged in

 Back-power safe design on HPD_SINK to disallow backdrive current when power is off

2.4 General

 Power supply 3.0 V to 3.6 V

 ESD resilience to 6 kV HBM, 1 kV CDM

 Power-saving modes (using output enable)

 Back-current-safe design on all sink-side main link, DDC and HPD terminals

 Transparent operation: no re-timing or software configuration required

 32-terminal HVQFN32 package

3. Applications

 PC motherboard/graphics card

 Docking station

 DisplayPort to HDMI adapters supporting 4K  2K and 3D video formats

 DisplayPort to DVI adapters required to drive long cables

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

3 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

4. Ordering information

Table 1.

Ordering information

Type number

Topside mark Package

Name

Description

plastic thermal enhanced very thin quad flat package; no

leads; 32 terminals; body 5 x 5 x 0.85 mm

Version

PTN3365BS

P3365

HVQFN32

SOT617-3

4.1 Ordering options

Table 2.

Ordering options

Type number

Orderable

part number

Package

Packing method

Minimum

order

Temperature range

quantity

PTN3365BS

PTN3365BSMP

HVQFN32 Reel 13” Q2/T3

*standard mark SMD dry pack

6000

T_amb= 40 C to +85 C

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

4 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

5. Functional diagram

OE_N

input bias

PTN3365

enable

OUT_D4+

OUT_D4-

50 W

IN_D4+

IN_D4-

EQ

enable

input bias

enable

OUT_D3+

OUT_D3-

50 W

IN_D3+

IN_D3-

EQ

input bias

enable

OUT_D2+

OUT_D2-

50 W

IN_D2+

IN_D2-

EQ

input bias

enable

OUT_D1+

OUT_D1-

50 W

IN_D1+

IN_D1-

EQ

EQ5

HPD level shifter

HPD_SOURCE

(0 V to 3.3 V)

HPD_SINK

(0 V to 5 V)

200 kW

DDC_EN (0 V to 3.3 V)

SCL_SOURCE

SCL_SINK

SDA_SINK

DDC BUFFER

AND

LEVEL SHIFTER

SDA_SOURCE

aaa-013694

Fig 2. Functional diagram of PTN3365

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

5 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

6. Pinning information

6.1 Pinning

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

V

DD

EQ5

TEST

DDC_EN

GND

REXT

HPD_SINK

SDA_SINK

SCL_SINK

PTN3365

HPD_SOURCE

SDA_SOURCE

SCL_SOURCE

V

DD

V

OE_N

DD

aaa-013695

Transparent top view

HVQFN32 package supply ground is connected to both GND pins and exposed center pad.

GND pins and the exposed center pad must be connected to supply ground for proper device

operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs

to be soldered to the board using a corresponding thermal pad on the board and for proper heat

conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad

region.

Fig 3. Pin configuration for HVQFN32

6.2 Pin description

Table 3.

Symbol

OE_N, IN_Dx and OUT_Dx signals

Pin description

Pin Type

Description

OE_N

17

3.3 V low-voltage

Output Enable and power saving function for

CMOS single-ended high-speed differential level shifter path.

input

When OE_N = HIGH:

IN_Dx termination = high-impedance

OUT_Dx outputs = high-impedance; zero

output current

When OE_N = LOW:

IN_Dx termination = 50 

OUT_Dx outputs = active

IN_D4+

32

Self-biasing

differential input

Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D4+ makes a differential pair with IN_D4.

The input to this pin must be AC coupled

externally.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

6 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

Table 3.

Pin description …continued

Symbol

Type

Description

IN_D4

31

Self-biasing

differential input

Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D4 makes a differential pair with IN_D4+.

The input to this pin must be AC coupled

externally.

IN_D3+

IN_D3

IN_D2+

IN_D2

IN_D1+

IN_D1

30

29

28

27

26

25

Self-biasing

differential input

Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D3+ makes a differential pair with IN_D3.

The input to this pin must be AC coupled

externally.

Self-biasing

differential input

Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D3 makes a differential pair with IN_D3+.

The input to this pin must be AC coupled

externally.

Self-biasing

differential input

Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D2+ makes a differential pair with IN_D2.

The input to this pin must be AC coupled

externally.

Self-biasing

differential input

Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D2 makes a differential pair with IN_D2+.

The input to this pin must be AC coupled

externally.

Self-biasing

differential input

Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D1+ makes a differential pair with IN_D1.

The input to this pin must be AC coupled

externally.

Self-biasing

differential input

Low-swing differential input from display source

with PCI Express electrical signaling.

IN_D1 makes a differential pair with IN_D1+.

The input to this pin must be AC coupled

externally.

OUT_D4+

OUT_D4

OUT_D3+

OUT_D3

OUT_D2+

9

TMDS differential

output

HDMI compliant TMDS output. OUT_D4+ makes

a differential pair with OUT_D4. OUT_D4+ is in

phase with IN_D4+.

10

11

12

13

TMDS differential

output

HDMI compliant TMDS output. OUT_D4 makes

a differential pair with OUT_D4+. OUT_D4 is in

phase with IN_D4.

TMDS differential

output

HDMI compliant TMDS output. OUT_D3+ makes

a differential pair with OUT_D3. OUT_D3+ is in

phase with IN_D3+.

TMDS differential

output

HDMI compliant TMDS output. OUT_D3 makes

a differential pair with OUT_D3+. OUT_D3 is in

phase with IN_D3.

TMDS differential

output

HDMI compliant TMDS output. OUT_D2+ makes

a differential pair with OUT_D2. OUT_D2+ is in

phase with IN_D2+.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

7 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

Table 3.

Pin description …continued

Symbol

Type

Description

OUT_D2

14

TMDS differential

output

HDMI compliant TMDS output. OUT_D2 makes

a differential pair with OUT_D2+. OUT_D2 is in

phase with IN_D2.

OUT_D1+

15

16

TMDS differential

output

HDMI compliant TMDS output. OUT_D1+ makes

a differential pair with OUT_D1. OUT_D1+ is in

phase with IN_D1+.

OUT_D1

TMDS differential

output

HDMI compliant TMDS output. OUT_D1 makes

a differential pair with OUT_D1+. OUT_D1 is in

phase with IN_D1.

HPD and DDC signals

HPD_SINK 21

5 V CMOS

single-ended input

0 V to 5 V (nominal) input signal. This signal

comes from the DVI or HDMI sink. A HIGH value

indicates that the sink is connected; a LOW value

indicates that the sink is disconnected.

HPD_SINK is pulled down by an integrated

200 k pull-down resistor.

HPD_SOURCE 5

SCL_SOURCE

SDA_SOURCE 6

3.3 V CMOS

0 V to 3.3 V (nominal) output signal. This is

single-ended output level-shifted version of the HPD_SINK signal.

7

single-ended 3.3 V 3.3 V source-side DDC clock I/O. Pulled up by

open-drain DDC I/O external termination to 3.3 V. 5 V tolerant I/O.

single-ended 3.3 V 3.3 V source-side DDC data I/O. Pulled up by

open-drain DDC I/O external termination to 3.3 V. 5 V tolerant I/O.

SCL_SINK

SDA_SINK

DDC_EN

19

single-ended 5 V

open-drain DDC I/O external termination to 5 V. Provides rise time

acceleration for LOW-to-HIGH transitions.

5 V sink-side DDC clock I/O. Pulled up by

20

23

single-ended 5 V

open-drain DDC I/O external termination to 5 V. Provides rise time

acceleration for LOW-to-HIGH transitions.

5 V sink-side DDC data I/O. Pulled up by

3.3 V CMOS input

Enables the DDC buffer and level shifter.

When DDC_EN = LOW, buffer/level shifter is

disabled.

When DDC_EN = HIGH, buffer and level shifter

are enabled.

TEST

3

3.3 V CMOS input

This is a test pin and it shall always be connected

to GND in the system applications.

Supply and ground

V_DD

1, 8,

18, 24

3.3 V DC supply

ground

Supply voltage; 3.3 V  10 %.

GND^[1]

22

Supply ground. All GND pins must be connected

to ground for proper operation.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

8 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

Table 3.

Symbol

Feature control signals

Pin description …continued

Type

Description

REXT

4

analog I/O

Current sense port used to provide an accurate

current reference for the differential outputs

OUT_Dx. For best output voltage swing

accuracy, use of a 10 k resistor (1 % tolerance)

from this terminal to GND is recommended. May

also be tied to either V_DDor GND directly (0 ).

See Section 7.2 for details.

EQ5

2

3.3 V low-voltage

Equalizer setting input pin. This pin can be

CMOS quinary input board-strapped to one of five decode values:

short to GND, resistor to GND, open-circuit,

resistor to V_DD, short to V_DD. See Table 5 for

truth table.

[1] HVQFN32 package supply ground is connected to both GND pins and exposed center pad. GND pins and

the exposed center pad must be connected to supply ground for proper device operation. For enhanced

thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using

a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

9 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

7. Functional description

Refer to Figure 2 “Functional diagram of PTN3365”.

PTN3365 level shifts four lanes of low-swing AC-coupled differential input signals to DVI

and HDMI compliant open-drain current-steering differential output signals, up to

3.0 Gbit/s per lane to support 36-bit deep color mode. It has integrated 50  termination

resistors for AC-coupled differential input signals. An enable signal OE_N can be used to

turn off the TMDS inputs and outputs, thereby minimizing power consumption. The TMDS

outputs are back-power safe to disallow current flow from a powered sink while PTN3365

is unpowered.

PTN3365's DDC channel provides active level shifting and buffering, allowing 3.3 V

source-side termination and 5 V sink-side termination. The sink-side DDC ports are

equipped with a rise time accelerator enabling drive of long cables or high bus

capacitance. This enables the system designer to isolate bus capacitance to meet/exceed

HDMI DDC specification. PTN3365 offers back-power safe sink-side I/Os to disallow

backdrive current from the DDC clock and data lines when power is off or when DDC is

not enabled. An enable signal DCC_EN enables the DDC level shifter block.

PTN3365 also provides voltage translation for the Hot Plug Detect (HPD) signal from 0 V

to 5 V on the sink side to 0 V to 3.3 V on the source side.

PTN3365 does not re-time any data. It contains no state machines. No inputs or outputs of

the device are latched or clocked. Because PTN3365 acts as a transparent level shifter,

no reset is required.

7.1 Enable and disable features

PTN3365 offers different ways to enable or disable functionality, using the Output Enable

(OE_N), and DDC Enable (DDC_EN) inputs. Whenever PTN3365 is disabled, the device

will be in Standby mode and power consumption will be minimal; otherwise PTN3365 will

be in active mode and power consumption will be nominal. These two inputs each affect

the operation of PTN3365 differently: OE_N controls the TMDS channels, DDC_EN

affects only the DDC channel, and HPD_SINK does not affect either of the channels. The

following sections and truth table describe their detailed operation.

7.1.1 Hot plug detect

The HPD channel of PTN3365 functions as a level-shifting buffer to pass the HPD logic

signal from the display sink device (via input HPD_SINK) on to the display source device

(via output HPD_SOURCE).

The output logic state of HPD_SOURCE output always follows the logic state of input

HPD_SINK, regardless of whether the device is in Active mode or Standby mode.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

10 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

7.1.2 Output Enable function (OE_N)

When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully

functional. Input termination resistors are enabled and the internal bias circuits are turned

on.

When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a

high-impedance state and drive zero output current. The IN_Dx input buffers are disabled

and IN_Dx termination is disabled. Power consumption is minimized.

Remark: Note that OE_N signal level has no influence on the HPD_SINK input,

HPD_SOURCE output, or the SCL and SDA level shifters. A transition from HIGH to LOW

at OE_N may disable the DDC channel for up to 20 s.

7.1.3 DDC channel enable function (DDC_EN)

The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When

DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never

change state during an I²C-bus operation. Note that disabling DDC_EN during a bus

operation may hang the bus, while enabling DDC_EN during bus traffic would corrupt the

I²C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. (See

I²C-bus specification).

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

11 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

7.1.4 Enable/disable truth table

Table 4.

Inputs

HPD_SINK, OE_N and DDC_EN enabling truth table

Channels

Mode

HPD_SINK OE_N DDC_EN IN_Dx

OUT_Dx^[3]

DDC^[4]

HPD_SOURCE^[5]

[1]

[2]

LOW

50  termination enabled

to V_RX(bias)

high-impedance LOW

Active;DDC

disabled

LOW

HIGH

50  termination enabled

to V_RX(bias)

SDA_SINK

LOW

Active;DDC

enabled

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

LOW

HIGH LOW

HIGH HIGH

high-impedance high-impedance;

zero output current

high-impedance LOW

Standby

high-impedance high-impedance;

SDA_SINK LOW

Standby;

DDC

enabled

zero output current connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

HIGH

LOW

HIGH

50  termination enabled

to V_RX(bias)

high-impedance HIGH

Active;DDC

disabled

50  termination enabled

to V_RX(bias)

SDA_SINK

HIGH

Active;DDC

enabled

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

HIGH

HIGH LOW

HIGH HIGH

high-impedance high-impedance;

zero output current

high-impedance HIGH

Standby

high-impedance high-impedance;

SDA_SINK HIGH

Standby;

DDC

enabled

zero output current connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

[1] A HIGH level on input OE_N disables only the TMDS channels. A transition from HIGH to LOW at OE_N may disable the DDC channel

for up to 20 s.

[2] A LOW level on input DDC_EN disables only the DDC channel.

[3] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.

[4] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.

[5] The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

12 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

7.2 Analog current reference

The REXT pin (pin 6) is an analog current sense port used to provide an accurate current

reference for the differential outputs OUT_Dx. For best output voltage swing accuracy,

use of a 10 k resistor (1 % tolerance) connected between this terminal and GND is

recommended.

If an external 10 k  1 % resistor is not used, this pin can be connected to GND or V_DD

directly (0 ). In any of these cases, the output will function normally but at reduced

accuracy over voltage and temperature of the following parameters: output levels (V_OL),

differential output voltage swing, and rise and fall time accuracy.

7.3 Equalizer

PTN3365 supports 5 level equalization setting by the quinary input pin EQ5.

Table 5.

Inputs

EQ5

Equalizer settings

Quinary notation

Equalizer mode

short to GND

0₅

0 dB

2 dB

3.5 dB

9 dB

7 dB

10 k resistor to GND

open-circuit

1₅

2₅

3₅

4₅

10 k resistor to V_DD

short to V_DD

7.4 Backdrive current protection

PTN3365 is designed for backdrive prevention on all sink-side TMDS outputs, sink-side

DDC I/Os and the HPD_SINK input. This supports user scenarios where the display is

connected and powered, but PTN3365 is unpowered. In these cases, PTN3365 will sink

no more than a negligible amount of leakage current, and will block the display (sink)

termination network from driving the power supply of PTN3365 or that of the inactive DVI

or HDMI source.

7.5 Active DDC buffer with rise time accelerator

PTN3365 DDC channel, besides providing 3.3 V to 5 V level shifting, includes active

buffering and rise time acceleration which allows up to 18 meters bus extension for

reliable DDC applications. While retaining all the operating modes and features of the

I²C-bus system during the level shifts, it permits extension of the I²C-bus by providing

bidirectional buffering for both the data (SDA) and the clock (SCL) line as well as the

rise time accelerator on the sink-side port (SCL_SINK and SDA_SINK) enabling the bus

to drive a load up to 1400 pF or distance of 18 m on the sink-side port, and 400 pF on the

source-side port (SCL_SOURCE and SCA_SOURCE). Using PTN3365 for DVI or HDMI

level shifting enables the system designer to isolate bus capacitance to meet/exceed

HDMI DDC specification. The SDA and SCL pins are overvoltage tolerant and are

high-impedance when PTN3365 is unpowered or when DDC_EN is LOW.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

13 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

PTN3365 has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK)

only. During positive bus transitions on the sink-side port, a current source is switched on

to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus V_IL

threshold level of around 1.5 V is exceeded, and turns off as the 5 V DDC bus V_IH

threshold voltage of approximately 3.5 V is approached.

8. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

0.3

65

-

Max

Unit

V

V_DD

V_I

supply voltage

input voltage

+4.6

3.3 V CMOS inputs

5.0 V CMOS inputs

V_DD+ 0.5

6.0

V

T_stg

storage temperature

+150

6000

1000

C

V

[1]

[2]

V_ESD

electrostatic discharge

voltage

HBM

CDM

-

V

[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -

Component level; Electrostatic Discharge Association, Rome, NY, USA.

[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device

Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.

9. Recommended operating conditions

Table 7.

Symbol

Recommended operating conditions

Parameter

Conditions

Min

3.0

0

Typ

Max Unit

V_DD

V_I

supply voltage

input voltage

3.3

3.6

5.5

-

V

3.3 V CMOS inputs

5.0 V CMOS inputs

IN_Dn+, IN_Dn inputs

-

0

-

[1]

[2]

V_I(AV)

R_ref(ext)

T_amb

average input

voltage

-

0

external reference

resistance

connected between pin

REXT (pin 6) and GND

-

10  1 %

-

k

C

ambient temperature operating in free air

40

-

+85

[1] Input signals to these pins must be AC-coupled.

[2] Operation without external reference resistor is possible but will result in reduced output voltage swing

accuracy. For details, see Section 7.2.

9.1 Current consumption

Table 8.

Symbol Parameter

I_DDsupply current

Current consumption

Conditions

Min

Typ

70

-

Max

100

5

Unit

mA

OE_N = 0; Active mode

-

OE_N = 1 and DDC_EN = 0;

Standby mode

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

14 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

10. Characteristics

10.1 Differential inputs

Table 9.

Symbol

UI

Differential input characteristics for IN_Dx signals

Parameter

Conditions

Min

333

0.175

0.8

Typ

Max

4000

1.200

-

Unit

ps

unit interval^[1]

-

[2]

[3]

V_{RX_DIFFp-p}differential input peak-to-peak voltage

V

t_{RX_EYE}

receiver eye time

minimum eye width at

IN_Dx input pair

UI

[4]

V_i(cm)M(AC)

peak common-mode input voltage (AC)

includes all frequencies

above 30 kHz

-

100

mV

Z_{RX_DC}

V_RX(bias)

Z_I(se)

DC input impedance

40

50

1.2

-

60

1.4

-



bias receiver voltage

1.0

100

V

[5]

single-ended input impedance

inputs in

k

high-impedance state

[1] UI (unit interval) = t_bit(bit time).

[2] UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 3.0 Gbit/s per lane.

[3] _{RX_DIFFp-p}= 2  V_{RX_D+} V_{RX_D}. Applies to IN_Dx signals.

[4] V_i(cm)M(AC)= V_{RX_D+}+ V_{RX_D} / 2  V_RX(cm)

V

.

V_RX(cm)= DC (avg) of V_{RX_D+}+ V_{RX_D} / 2.

[5] Differential inputs will switch to a high-impedance state when OE_N is HIGH.

10.2 Differential outputs

The level shifter’s differential outputs are designed to meet HDMI version 1.4a and

DVI version 1.0 specifications.

Table 10. Differential output characteristics for OUT_Dx signals

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

[2]

[3]

V_OH(se)

single-ended HIGH-level

output voltage

V_TT 0.01 V_TT

V_TT+ 0.01

V

V_OL(se)

single-ended LOW-level

output voltage

V_TT 0.60 V_TT 0.50 V_TT 0.40

V

V_O(se)

single-ended output

voltage variation

logic 1 and logic 0 state applied

respectively to differential inputs

IN_Dn; R_ref(ext)connected;

see Table 7

400

500

600

mV

I_OZ

t_r

OFF-state output current single-ended

-

10

A

ps

rise time

fall time

20 % to 80 %

80 % to 20 %

intra-pair

75

-

240

10

t_f

-

[4]

[5]

[6]

t_sk

skew time

-

inter-pair

-

250

-

t_jit(add)

added jitter time

jitter contribution

-

10

[1] V_TTis the DC termination voltage in the HDMI or DVI sink. V_TTis nominally 3.3 V.

[2] The open-drain output pulls down from V_TT

[3] Swing down from TMDS termination voltage (3.3 V  10 %).

.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

15 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

[4] This differential skew budget is in addition to the skew presented between IN_D+ and IN_D paired input pins.

[5] This lane-to-lane skew budget is in addition to skew between differential input pairs.

[6] Jitter budget for differential signals as they pass through the level shifter.

10.3 HPD_SINK input, HPD_SOURCE output

Table 11. HPD characteristics

Symbol

V_IH

Parameter

Conditions

HPD_SINK

Min

2.0

0

Typ

Max

5.3

0.8

15

Unit

V

[1]

HIGH-level input voltage

LOW-level input voltage

input leakage current

HIGH-level output voltage

LOW-level output voltage

propagation delay

5.0

V_IL

HPD_SINK

-

V

I_LI

HPD_SINK

-

A

V

V_OH

V_OL

t_PD

HPD_SOURCE

2.5

0

V_DD

0.2

200

V

[2]

from HPD_SINK to HPD_SOURCE;

50 % to 50 %

-

ns

[3]

[4]

t_t

transition time

HPD_SOURCE rise/fall; 10 % to 90 %

HPD_SINK input pull-down resistor

1

-

20

ns

R_pd

pull-down resistance

100

200

300

k

[1] Low-speed input changes state on cable plug/unplug.

[2] Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time.

[3] Time required to transition from V_OHto V_OLor from V_OLto V_OH

.

[4] Guarantees HPD_SINK is LOW when no display is plugged in.

10.4 OE_N, DDC_EN and test inputs

Table 12. OE_N, DDC_EN input characteristics

Symbol

V_IH

Parameter

Conditions

Min

Typ

Max

Unit

V

HIGH-level input voltage

LOW-level input voltage

input leakage current

2.0

-

V_IL

0.8

10

V

[1]

I_LI

OE_N pin

-

A

[1] Measured with input at V_IHmaximum and V_ILminimum.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

16 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

10.5 DDC characteristics

Table 13. DDC characteristics

Symbol Parameter

Input and output SCL_SOURCE and SDA_SOURCE, V_CC1= 3.0 V to 3.6 V^[1]

Conditions

Min

Typ

Max

Unit

V_IH

HIGH-level input voltage

contention LOW-level input voltage

input leakage current

0.7V_CC1

-

3.6

0.4

10

V

V_ILc

I_LI

guaranteed by design

V_I= 3.6 V

0.5

V

-

A

V

I_IL

LOW-level input current

LOW-level output voltage

V_I= 0.2 V

-

10

[2]

V_OL

V_OLV_ILc

I_OL= 6 mA

0.47

-

0.52 0.6

difference between LOW-level output guaranteed by design

and LOW-level input voltage

-

70

mV

contention

C_io

input/output capacitance

V_I= 3 V or 0 V; V_DD= 3.3 V

V_I= 3 V or 0 V; V_DD= 0 V

-

6

7

pF

Input and output SDA_SINK and SCL_SINK, V_CC2= 4.5 V to 5.5 V^[3]

V_IH

V_IL

I_LI

HIGH-level input voltage

LOW-level input voltage

input leakage current

0.7V_CC2

-

5.5

+1.2

10

0.2

7

V

0.5

-

V

V_I= 5.5 V

-

A

V

I_IL

LOW-level input current

LOW-level output voltage

input/output capacitance

V_I= 0.2 V

-

V_OL

C_io

I_OL= 6 mA

0.1

-

V_I= 3 V or 0 V; V_DD= 3.3 V

V_I= 3 V or 0 V; V_DD= 0 V

pF

mA

6

7

I_trt(pu)

transient boosted pull-up current

V_CC2= 4.5 V;

-

slew rate = 1.25 V/s

[1] V_CC1is the pull-up voltage for DDC source.

[2] I_OLbetween 100 A and 6 mA guaranteed by design (3 mA typical application)

[3] V_CC2is the pull-up voltage for DDC sink.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

17 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

11. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-3

D

B

A

terminal 1

index area

A

1

E

detail X

C

e

1

y

v

C

A

B

C

1

e

1/2 e

b

w

9

16

L

17

8

e

E

h

2

1/2 e

24

1

terminal 1

index area

32

25

X

D

h

0

2.5

scale

5 mm

Dimensions

(1)

Unit

A

1

b

c

D

h

E

e

2

L

v

w

y

1

h

1

max

0.05 0.30

5.1 3.75 5.1 3.75

0.5

mm nom 0.85

min

0.2

0.5 3.5 3.5

0.1 0.05 0.05 0.1

0.00 0.18

4.9 3.45 4.9 3.45

0.3

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

sot617-3_po

References

Outline

version

European

projection

Issue date

IEC

JEDEC

JEITA

11-06-14

11-06-21

SOT617-3

MO-220

Fig 4. Package outline SOT617-3 (HVQFN32)

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

18 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

19 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

12.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 5) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 14 and 15

Table 14. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 15. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 5.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

20 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 5. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

13. Abbreviations

Table 16. Abbreviations

Acronym

CDM

CEC

Description

Charged-Device Model

Consumer Electronics Control

Data Display Channel

DDC

DVI

Digital Visual Interface

EMI

ElectroMagnetic Interference

ElectroStatic Discharge

ESD

HBM

HDMI

HPD

Human Body Model

High-Definition Multimedia Interface

Hot Plug Detect

I²C-bus

Inter-IC bus

I/O

Input/Output

NMOS

TMDS

VESA

Negative-channel Metal-Oxide Semiconductor

Transition Minimized Differential Signaling

Video Electronic Standards Association

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

21 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

14. Revision history

Table 17. Revision history

Document ID

PTN3365 v.1.1

Modifications:

PTN3365 v.1

Release date

Data sheet status

Change notice

Supersedes

20150728

Product data sheet

-

PTN3365 v.1

• Changed document status to Company Public.

20141203 Product data sheet

-

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

22 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

15.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

23 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

15.4 Licenses

Purchase of NXP ICs with HDMI technology

non-automotive qualified products in automotive equipment or applications.

Use of an NXP IC with HDMI technology in equipment that complies with

the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.

Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:

admin@hdmi.org.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

15.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PTN3365

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 28 July 2015

24 of 25

PTN3365

NXP Semiconductors

HDMI/DVI level shifter supporting 3 Gbit/s operation

17. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

15.5

16

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Contact information . . . . . . . . . . . . . . . . . . . . 24

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 3

High-speed TMDS level shifting . . . . . . . . . . . . 3

DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1

2.2

2.3

2.4

17

3

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

7.1

7.1.1

7.1.2

7.1.3

7.1.4

7.2

7.3

7.4

7.5

Functional description . . . . . . . . . . . . . . . . . . 10

Enable and disable features. . . . . . . . . . . . . . 10

Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . 10

Output Enable function (OE_N) . . . . . . . . . . . 11

DDC channel enable function (DDC_EN). . . . 11

Enable/disable truth table . . . . . . . . . . . . . . . . 12

Analog current reference . . . . . . . . . . . . . . . . 13

Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Backdrive current protection. . . . . . . . . . . . . . 13

Active DDC buffer with rise time accelerator . 13

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14

Recommended operating conditions. . . . . . . 14

Current consumption . . . . . . . . . . . . . . . . . . . 14

9

9.1

10

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15

Differential inputs . . . . . . . . . . . . . . . . . . . . . . 15

Differential outputs . . . . . . . . . . . . . . . . . . . . . 15

HPD_SINK input, HPD_SOURCE output. . . . 16

OE_N, DDC_EN and test inputs. . . . . . . . . . . 16

DDC characteristics . . . . . . . . . . . . . . . . . . . . 17

10.1

10.2

10.3

10.4

10.5

11

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18

12

Soldering of SMD packages . . . . . . . . . . . . . . 19

Introduction to soldering . . . . . . . . . . . . . . . . . 19

Wave and reflow soldering . . . . . . . . . . . . . . . 19

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 19

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 20

12.1

12.2

12.3

12.4

13

14

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 23

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

15.1

15.2

15.3

15.4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 28 July 2015

Document identifier: PTN3365


型号：	PTN3365BSMP
厂家：	NXP
描述：	PTN3365 - Enhanced performance HDMI/DVI level shifter with active DDC buffer, supporting 3 Gbit/s operation QFN 32-Pin
文件：	总25页 (文件大小：409K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PTN3365BSMP [NXP]

相关型号：

PTN3366BSMP

PTN3380BBS

PTN3380BBS,518

PTN3381BBS,518

PTN3381DBS

PTN3392BS

PTN3392BS,518

PTN3392BS/F1,518

PTN3392BS/F2,518

PTN3392BS/F3,518

PTN3392BS/F4Y

PTN3392BS/FXY