PTN3381DBS_技术文档

PTN3381D

Enhanced performance HDMI/DVI level shifter with voltage

regulator, dongle detection and supporting 3 Gbit/s operation

Rev. 2 — 26 July 2012

Product data sheet

1. General description

The PTN3381D is a high-speed level shifter device which converts four lanes of low-swing

AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain

current-steering differential output signals, up to 3 Gbit/s to support 36-bit deep color, 3D

and 3 Gbit/s modes. Each of these channels provides a level-shifting differential buffer to

translate from low-swing AC-coupled differential signaling on the source side, to

TMDS-type DC-coupled differential current-mode signaling terminated into 50  to 3.3 V

on the sink side. Additionally, the PTN3381D provides a single-ended active buffer for

voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side

and provides a channel with active buffering and level shifting of the DDC channel

(consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The

DDC channel is implemented using active I²C-bus buffer technology providing capacitive

isolation, redriving and level shifting as well as disablement (isolation between source and

sink) of the clock and data lines.

To provide the highest level of integration in external adapter (or: dongle) applications,

PTN3381D includes an on-board 5 V DC regulator. Its output is designed to provide the

required 5 V power supply to the DVI or HDMI connector, thereby eliminating the need for

a separate external regulator. The on-board regulator needs only two external capacitors

to operate, and its output is active whenever a valid 3.3 V is applied to the PTN3381D V_DD

pins.

The low-swing AC-coupled differential input signals to the PTN3381D typically come from

a display source with multi-mode I/O, which supports multiple display standards, for

example, DisplayPort, HDMI and DVI. While the input differential signals are configured to

carry DVI or HDMI coded data, they do not comply with the electrical requirements of the

DVI v1.0 or HDMI v1.3a specification. By using PTN3381D, chip set vendors are able to

implement such reconfigurable I/Os on multi-mode display source devices, allowing the

support of multiple display standards while keeping the number of chip set I/O pins low.

See Figure 1.

The PTN3381D main high-speed differential lanes feature low-swing self-biasing

differential inputs which are compliant to the electrical specifications of DisplayPort

Standard v1.2 and/or PCI Express Standard v1.1, and open-drain current-steering

differential outputs compliant to DVI v1.0 and HDMI v1.4b electrical specifications. The

I²C-bus channel actively buffers as well as level-translates the DDC signals for optimal

capacitive isolation. Its I²C-bus control block also provides for optional software HDMI

dongle detect by issuing a predetermined code sequence upon a read command to an

I²C-bus specified address. The PTN3381D also supports power-saving modes in order to

minimize current consumption when no display is active or connected.

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

The PTN3381D is a fully featured HDMI as well as DVI level shifter. It is functionally

equivalent to PTN3361D but provides an onboard 5 V regulator. The PTN3381D

supersedes PTN3381B, and provides a better high speed performance with a

programmable equalizer.

PTN3381D is powered from a single 3.3 V power supply consuming a small amount of

power (230 mW typical with no load at 5 V regulator) and is offered in a 48-terminal

HVQFN48 package.

MULTI-MODE DISPLAY SOURCE

OE_N

PTN3381D

reconfigurable I/Os

PHY ELECTRICAL

AC-coupled

differential pair

TMDS data

OUT_D4+

OUT_D4−

TMDS

coded

data

output buffer

TX

FF

IN_D4+

IN_D4−

DATA LANE

AC-coupled

differential pair

TMDS data

OUT_D3+

OUT_D3−

TMDS

coded

data

output buffer

TX

FF

IN_D3+

IN_D3−

DATA LANE

AC-coupled

differential pair

TMDS data

OUT_D2+

OUT_D2−

TMDS

coded

data

output buffer

TX

FF

IN_D2+

IN_D2−

DATA LANE

OUT_D1+

OUT_D1−

AC-coupled

differential pair

clock

TMDS

clock

pattern

output buffer

TX

FF

IN_D1+

IN_D1−

CLOCK LANE

0 V to 3.3 V

quinary input

0 V to 5 V

HPD_SOURCE

EQ5

HPD_SINK

DDC_EN

(0 V to 3.3 V)

3.3 V

5 V

3.3 V

DDET

SCL_SOURCE

SCL_SINK

3.3 V

DDC I/O

2

(I C-bus)

SDA_SINK

V5OUT

CONFIGURATION

SDA_SOURCE

5 V

out

DC

002aaf310

Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].

Fig 1. Typical application system diagram

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

2 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

2. Features and benefits

2.1 High-speed TMDS level shifting

 Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and

HDMI v1.4b compliant open-drain current-steering differential output signals

 TMDS level shifting operation up to 3 Gbit/s per lane (300 MHz character clock)

supporting 36-bit deep color, 3D and 3 Gbit/s modes

 Programmable equalizer

 Integrated 50  termination resistors for self-biasing differential inputs

 Back-current safe outputs to disallow current when device power is off and monitor is

on

 Disable feature to turn off TMDS inputs and outputs and to enter low-power state

2.2 DDC level shifting

 Integrated DDC buffering and level shifting (3.3 V source to 5 V sink side)

 Rise time accelerator on sink-side DDC ports

 100 kHz I²C-bus clock frequency

 Back-power safe sink-side terminals to disallow backdrive current when power is off or

when DDC is not enabled

2.3 HDMI dongle detect support

 Incorporates I²C slave ROM

 Responds to DDC read to address 81h with predetermined byte sequence

 Feature enabled by pin DDET (must be enabled for correct operation in accordance

with DisplayPort interoperability guideline)

2.4 HPD level shifting

 HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or

from 5 V on the sink side to 3.3 V on the source side

 Integrated 200 k pull-down resistor on HPD sink input guarantees ‘input LOW’ when

no display is plugged in

 Back-power safe design on HPD_SINK to disallow backdrive current when power is off

2.5 5 V DC voltage regulator

 Generates 5 V for the DVI/HDMI connector from the 3.3 V DP_PWR pin supplied by

the DisplayPort connector

 Supports up to 75 mA of load current with an accuracy of 300 mV

 Only two external capacitors required

 Eliminates need for an external 5 V regulator in dongle applications

 Back drive protection on 5 V output

 Short-circuit protection

 Overcurrent protection

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

3 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

2.6 General

 Power supply 2.85 V to 3.6 V

 ESD resilience to 6 kV HBM, 1 kV CDM

 Power-saving modes (using output enable)

 Back-current-safe design on all sink-side main link, DDC and HPD terminals

 Transparent operation: no re-timing or software configuration required

3. Applications

 DisplayPort to HDMI adapters supporting 36-bit deep color, 3D and 3 Gbit/s modes

 DisplayPort to DVI adapters required to drive long cables

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

PTN3381DBS

HVQFN48

plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; SOT619-1

body 7  7  0.85 mm

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

4 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

5. Functional diagram

OE_N

PTN3381D

input bias

enable

OUT_D4+

OUT_D4−

50 Ω

IN_D4+

IN_D4−

EQ

enable

input bias

enable

OUT_D3+

OUT_D3−

50 Ω

IN_D3+

IN_D3−

EQ

input bias

enable

OUT_D2+

OUT_D2−

50 Ω

IN_D2+

IN_D2−

EQ

input bias

enable

OUT_D1+

OUT_D1−

50 Ω

IN_D1+

IN_D1−

EQ

EQ5

HPD level shifter

HPD_SOURCE

(0 V to 3.3 V)

HPD_SINK

(0 V to 5 V)

200 kΩ

DDC_EN (0 V to 3.3 V)

SCL_SOURCE

2

SCL_SINK

SDA_SINK

I C-BUS

SLAVE

ROM

DDC BUFFER

AND

LEVEL SHIFTER

SDA_SOURCE

DDET

CP

V5OUT

C

DC REGULATOR

reg(ext)

C

o(reg)

CN

002aaf311

Fig 2. Functional diagram of PTN3381D

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

5 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

6. Pinning information

6.1 Pinning

terminal 1

index area

1

2

36

35

34

33

32

31

30

29

28

27

26

25

GND

CP

V

CN

DD

3

EQ5

DDET

V5OUT

4

V

DD

5

GND

DDC_EN

GND

6

REXT

PTN3381DBS

7

HPD_SOURCE

SDA_SOURCE

SCL_SOURCE

GND

HPD_SINK

SDA_SINK

SCL_SINK

GND

8

9

10

11

12

V

DD

V

DD

GND

OE_N

002aaf312

Transparent top view

HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND

pins and the exposed center pad must be connected to supply ground for proper device operation.

For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat

conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad

region.

Fig 3. Pin configuration for HVQFN48

6.2 Pin description

Table 2.

Symbol

Pin description

Type

Description

OE_N, IN_Dx and OUT_Dx signals

OE_N

25

3.3 V low-voltage

Output Enable and power saving function for high-speed differential

CMOS single-ended level shifter path.

input

When OE_N = HIGH:

IN_Dx termination = high-impedance

OUT_Dx outputs = high-impedance; zero output current

When OE_N = LOW:

IN_Dx termination = 50 

OUT_Dx outputs = active

IN_D4+

48

Self-biasing

differential input

Low-swing differential input from source. IN_D4+ makes a

differential pair with IN_D4. The input to this pin must be AC

coupled externally.

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

6 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

Table 2.

Symbol

IN_D4

Pin description …continued

Type

Description

47

Self-biasing

Low-swing differential input from source. IN_D4 makes a

differential pair with IN_D4+. The input to this pin must be AC

coupled externally.

differential input

IN_D3+

IN_D3

IN_D2+

IN_D2

IN_D1+

IN_D1

45

44

42

41

39

38

Self-biasing

differential input

Low-swing differential input from source. IN_D3+ makes a

differential pair with IN_D3. The input to this pin must be AC

coupled externally.

Self-biasing

differential input

Low-swing differential input from source. IN_D3 makes a

differential pair with IN_D3+. The input to this pin must be AC

coupled externally.

Self-biasing

differential input

Low-swing differential input from source. IN_D2+ makes a

differential pair with IN_D2. The input to this pin must be AC

coupled externally.

Self-biasing

differential input

Low-swing differential input from source. IN_D2 makes a

differential pair with IN_D2+. The input to this pin must be AC

coupled externally.

Self-biasing

differential input

Low-swing differential input from source. IN_D1+ makes a

differential pair with IN_D1. The input to this pin must be AC

coupled externally.

Self-biasing

differential input

Low-swing differential input from source. IN_D1 makes a

differential pair with IN_D1+. The input to this pin must be AC

coupled externally.

OUT_D4+

OUT_D4

OUT_D3+

OUT_D3

OUT_D2+

OUT_D2

OUT_D1+

OUT_D1

13

14

16

17

19

20

22

23

TMDS differential

output

HDMI compliant TMDS output. OUT_D4+ makes a differential pair

with OUT_D4. OUT_D4+ is in phase with IN_D4+.

TMDS differential

output

HDMI compliant TMDS output. OUT_D4 makes a differential pair

with OUT_D4+. OUT_D4 is in phase with IN_D4.

TMDS differential

output

HDMI compliant TMDS output. OUT_D3+ makes a differential pair

with OUT_D3. OUT_D3+ is in phase with IN_D3+.

TMDS differential

output

HDMI compliant TMDS output. OUT_D3 makes a differential pair

with OUT_D3+. OUT_D3 is in phase with IN_D3.

TMDS differential

output

HDMI compliant TMDS output. OUT_D2+ makes a differential pair

with OUT_D2. OUT_D2+ is in phase with IN_D2+.

TMDS differential

output

HDMI compliant TMDS output. OUT_D2 makes a differential pair

with OUT_D2+. OUT_D2 is in phase with IN_D2.

TMDS differential

output

HDMI compliant TMDS output. OUT_D1+ makes a differential pair

with OUT_D1. OUT_D1+ is in phase with IN_D1+.

TMDS differential

output

HDMI compliant TMDS output. OUT_D1 makes a differential pair

with OUT_D1+. OUT_D1 is in phase with IN_D1.

HPD and DDC signals

HPD_SINK

30

5 V CMOS

single-ended input

0 V to 5 V (nominal) input signal. This signal comes from the DVI or

HDMI sink. A HIGH value indicates that the sink is connected; a

LOW value indicates that the sink is disconnected. HPD_SINK is

pulled down by an integrated 200 k pull-down resistor.

HPD_SOURCE

SCL_SOURCE

SDA_SOURCE

7

9

8

3.3 V CMOS

single-ended output the HPD_SINK signal.

0 V to 3.3 V (nominal) output signal. This is level-shifted version of

single-ended 3.3 V

open-drain DDC I/O to 3.3 V. 5 V tolerant I/O.

3.3 V source-side DDC clock I/O. Pulled up by external termination

single-ended 3.3 V

3.3 V source-side DDC data I/O. Pulled up by external termination

open-drain DDC I/O to 3.3 V. 5 V tolerant I/O.

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

7 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

Table 2.

Pin description …continued

Symbol

Type

single-ended 5 V

open-drain DDC I/O 5 V. Provides rise time acceleration for LOW-to-HIGH transitions.

single-ended 5 V 5 V sink-side DDC data I/O. Pulled up by external termination to

open-drain DDC I/O 5 V. Provides rise time acceleration for LOW-to-HIGH transitions.

Description

SCL_SINK

28

5 V sink-side DDC clock I/O. Pulled up by external termination to

SDA_SINK

DDC_EN

29

32

3.3 V CMOS input

Enables the DDC buffer and level shifter.

When DDC_EN = LOW, buffer/level shifter is disabled.

When DDC_EN = HIGH, buffer and level shifter are enabled.

Supply and ground

V_DD

2, 11, 15,

DC supply

Supply voltage (2.85 V to 3.6 V).

21, 26, 33,

40, 46

GND^[1]

1, 5, 10, 12, ground

18, 24, 27,

Supply ground. All GND pins must be connected to ground for

proper operation.

31, 37, 43

Feature control signals

REXT

6

analog I/O

3.3 V input

Current sense port used to provide an accurate current reference

for the differential outputs OUT_Dx. For best output voltage swing

accuracy, use of a 10 k resistor (1 % tolerance) from this terminal

to GND is recommended. May also be tied to either V_DDor GND

directly (0 ). See Section 7.2 for details.

DDET

4

Dongle detect enable input. When HIGH, the dongle detect function

via I²C is active. When LOW, the dongle detect function will not

respond to an I²C-bus command. Must be tied to GND or V_DDeither

directly or via a resistor. Note that this pin may not be left

open-circuit. When used in an HDMI dongle, this pin must be tied

HIGH for correct operation in accordance with DisplayPort

interoperability guidelines. When used in a DVI dongle, this pin

must be tied LOW.

EQ5

3

3.3 V low-voltage

Equalizer setting input pin. This pin can be board-strapped to one of

CMOS quinary input five decode values: short to GND, resistor to GND, open-circuit,

resistor to V_DD, short to V_DD. See Table 4 for truth table.

Voltage regulator terminals

CP

36

35

34

analog high-voltage Positive terminal for the voltage regulator external capacitor.^[2]

analog high-voltage Negative terminal for the voltage regulator external capacitor.^[2]

CN

V5OUT

power output

5 V regulated output from the integrated voltage regulator.^[2]

[1] HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed

pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the

board, thermal vias need to be incorporated in the PCB in the thermal pad region.

[2] A ceramic capacitor with ESR < 100 m is recommended and should be placed close to the pin(s).

PTN3381D

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 26 July 2012

8 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

7. Functional description

Refer to Figure 2 “Functional diagram of PTN3381D”.

The PTN3381D level shifts four lanes of low-swing AC-coupled differential input signals to

DVI and HDMI compliant open-drain current-steering differential output signals, up to

3 Gbit/s per lane to support 36-bit deep color, 3D and 3 Gbit/s modes. It has integrated

50  termination resistors for AC-coupled differential input signals. An enable signal

OE_N can be used to turn off the TMDS inputs and outputs, thereby minimizing power

consumption. The TMDS outputs are back-power safe to disallow current flow from a

powered sink while the PTN3381D is unpowered.

The PTN3381D’s DDC channel provides active level shifting and buffering, allowing 3.3 V

source-side termination and 5 V sink-side termination. The sink-side DDC ports are

equipped with a rise time accelerator enabling drive of long cables or high bus

capacitance. This enables the system designer to isolate bus capacitance to meet HDMI

DDC specification. Furthermore, the DDC channel is augmented with an I²C-bus slave

ROM device that provides optional HDMI dongle detect response, which can be enabled

by dongle detect signal DDET. The PTN3381D offers back-power safe sink-side I/Os to

disallow backdrive current from the DDC clock and data lines when power is off or when

DDC is not enabled. An enable signal DCC_EN enables the DDC level shifter block.

Remark: When used in an HDMI dongle, the DDET function must be enabled for correct

operation in accordance with DisplayPort interoperability guidelines. When used in a DVI

dongle, the DDET function must be disabled.

The PTN3381D also provides voltage translation for the Hot Plug Detect (HPD) signal

from 0 V to 5 V on the sink side to 0 V to 3.3 V on the source side.

PTN3381D includes an onboard 5 V_DCregulator, designed to provide the required 5 V

power supply to the DVI or HDMI connector, thereby eliminating the need for a separate

external regulator. The onboard regulator needs only two external capacitors to operate,

and its output is active whenever a valid 3.3 V is applied to the PTN3381D V_DDpins. The

back drive protection on 5 V output prevents back-drive current from 5 V output to the

input supply. The short-circuit protection limits current flowing through the supply, and the

overcurrent protection prevents overload conditions at the charge pump output.

The PTN3381D does not re-time any data. It contains no state machines except for the

DDC/I²C-bus block. No inputs or outputs of the device are latched or clocked. Because

the PTN3381D acts as a transparent level shifter, no reset is required.

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

9 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

7.1 Enable and disable features

PTN3381D offers different ways to enable or disable functionality, using the Output

Enable (OE_N), and DDC Enable (DDC_EN) inputs. Whenever the PTN3381D is

disabled, the device will be in standby mode and power consumption will be minimal;

otherwise the PTN3381D will be in active mode and power consumption will be nominal.

These two inputs each affect the operation of PTN3381D differently: OE_N controls the

TMDS channels, DDC_EN affects only the DDC channel, and HPD_SINK does not affect

either of the channels. The following sections and truth table describe their detailed

operation.

7.1.1 Hot plug detect

The HPD channel of PTN3381D functions as a level-shifting buffer to pass the HPD logic

signal from the display sink device (via input HPD_SINK) on to the display source device

(via output HPD_SOURCE).

The output logic state of HPD_SOURCE output always follows the logic state of input

HPD_SINK, regardless of whether the device is in active or standby mode.

7.1.2 Output Enable function (OE_N)

When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully

functional. Input termination resistors are enabled and the internal bias circuits are turned

on.

When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a

high-impedance state and drive zero output current. The IN_Dx input buffers are disabled

and IN_Dx termination is disabled. Power consumption is minimized.

Remark: Note that OE_N signal level has no influence on the HPD_SINK input,

HPD_SOURCE output, or the SCL and SDA level shifters. A transition from HIGH to LOW

at OE_N may disable the DDC channel for up to 20 s.

7.1.3 DDC channel enable function (DDC_EN)

The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When

DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never

change state during an I²C-bus operation. Note that disabling DDC_EN during a bus

operation may hang the bus, while enabling DDC_EN during bus traffic would corrupt the

I²C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. (See

I²C-bus specification).

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

10 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

7.1.4 Enable/disable truth table

Table 3.

Inputs

HPD_SINK, OE_N and DDC_EN enabling truth table

Channels

Mode

HPD_SINK OE_N DDC_EN IN_Dx

OUT_Dx^[3]

DDC^[4]

HPD_SOURCE^[5]

[1]

[2]

LOW

50  termination enabled

to V_RX(bias)

high-impedance LOW

Active;DDC

disabled

LOW

HIGH

50  termination enabled

to V_RX(bias)

SDA_SINK

LOW

Active;DDC

enabled

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

LOW

HIGH LOW

HIGH HIGH

high-impedance high-impedance;

zero output current

high-impedance LOW

Standby

high-impedance high-impedance;

SDA_SINK LOW

Standby;

DDC

enabled

zero output current connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

HIGH

LOW

HIGH

50  termination enabled

to V_RX(bias)

high-impedance HIGH

Active;DDC

disabled

50  termination enabled

to V_RX(bias)

SDA_SINK

HIGH

Active;DDC

enabled

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

HIGH

HIGH LOW

HIGH HIGH

high-impedance high-impedance;

zero output current

high-impedance HIGH

Standby

high-impedance high-impedance;

SDA_SINK HIGH

Standby;

DDC

enabled

zero output current connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

[1] A HIGH level on input OE_N disables only the TMDS channels.

[2] A LOW level on input DDC_EN disables only the DDC channel.

[3] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.

[4] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.

[5] The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

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PTN3381D

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7.2 Analog current reference

The REXT pin (pin 6) is an analog current sense port used to provide an accurate current

reference for the differential outputs OUT_Dx. For best output voltage swing accuracy,

use of a 10 k resistor (1 % tolerance) connected between this terminal and GND is

recommended.

If an external 10 k  1 % resistor is not used, this pin can be connected to GND or V_DD

directly (0 ) to use the internal resistor. In any of these cases, the output will function

normally but at reduced accuracy over voltage and temperature of the following

parameters: output levels (V_OL), differential output voltage swing, and rise and fall time

accuracy.

7.3 Equalizer

The PTN3381D supports 5 level equalization setting by the quinary input pin EQ5.

Table 4.

Inputs

EQ5

Equalizer settings

Quinary notation

Equalizer mode

short to GND

0₅

0 dB

2 dB

3.5 dB

9 dB

7 dB

10 k resistor to GND

open-circuit

1₅

2₅

3₅

4₅

10 k resistor to V_DD

short to V_DD

7.4 Backdrive current protection

The PTN3381D is designed for backdrive prevention on all sink-side TMDS outputs,

sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the

display is connected and powered, but the PTN3381D is unpowered. In these cases, the

PTN3381D will sink no more than a negligible amount of leakage current, and will block

the display (sink) termination network from driving the power supply of the PTN3381D or

that of the inactive DVI or HDMI source.

7.5 Active DDC buffer with rise time accelerator

The PTN3381D DDC channel, besides providing 3.3 V to 5 V level shifting, includes

active buffering and rise time acceleration which allows up to 18 meters bus extension for

reliable DDC applications. While retaining all the operating modes and features of the

I²C-bus system during the level shifts, it permits extension of the I²C-bus by providing

bidirectional buffering for both the data (SDA) and the clock (SCL) line as well as the

rise time accelerator on the sink-side port (SCL_SINK and SDA_SINK) enabling the bus

to drive a load up to 1400 pF or distance of 18 m on the sink-side port, and 400 pF on the

source-side port (SCL_SOURCE and SCA_SOURCE). Using the PTN3381D for DVI or

HDMI level shifting enables the system designer to isolate bus capacitance to meet HDMI

DDC specification. The SDA and SCL pins are overvoltage tolerant and are

high-impedance when the PTN3381D is unpowered or when DDC_EN is LOW.

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PTN3381D has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK)

only. During positive bus transitions on the sink-side port, a current source is switched on

to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus V_IL

threshold level of around 1.5 V is exceeded, and turns off as the 5 V DDC bus V_IH

threshold voltage of approximately 3.5 V is approached.

7.6 I²C-bus based HDMI dongle detection

The PTN3381D includes an on-board I²C-bus slave ROM which provides a means to

detect the presence of an HDMI dongle by the system through the DDC channel,

accessible via ports SDA_SOURCE and SCL_SOURCE. This allows system vendors to

detect HDMI dongle presence through the already available DDC/I²C-bus port using a

predetermined bus sequence. Please see Section 8 for more information.

For the I²C-bus HDMI Dongle Detect function to be active, input pin DDET (dongle detect)

should be tied HIGH. When DDET is LOW, the PTN3381D will not respond to an I²C-bus

command. When used in an HDMI dongle, the DDET function must be enabled for

correct operation in accordance with DisplayPort interoperability guidelines. When used in

a DVI dongle, the DDET function must be disabled.

The HDMI dongle detection is accomplished by accessing the PTN3381D on-board

I²C-bus slave ROM using a simple sequential I²C-bus Read operation as described

below.

7.6.1 Slave address

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

1

0

R/W

slave address

002aad340

R = 1; W = 0

Fig 4. PTN3381D slave address

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7.6.2 Read operation

The slave device address of PTN3381D is 80h. PTN3381D will respond to a Read

command to slave address 81h (PTN3381D will respond with an ACK to a Write

command to address 80h). Following the Read command, the PTN3381D will respond

with the contents of its internal ROM, as a sequence of 16 bytes, for as long as the master

continues to issue clock edges with an acknowledge after each byte. The 16-byte

sequence represents the ‘DP-HDMI ADAPTOR<EOT>’ symbol converted to ASCII and is

documented in Table 5.

The PTN3381D auto-increments its internal ROM address pointer (0h through Fh) as long

as it continues to receive clock edges from the master with an acknowledge after each

byte. If the master continues to issue clock edges past the 16^thbyte, the PTN3381D will

respond with a data byte of FFh. If the master does not acknowledge a received byte, the

PTN3381D internal address pointer will be reset to 0 and a new Read sequence should

be started by the master. Access to the 16-byte is by sequential read only as described

above; there is no random-access possible to any specific byte in the ROM.

Table 5.

DisplayPort - HDMI Adaptor Detection ROM content

Internal pointer

offset (hex)

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Data (hex)

44

50

2D

48

44

4D

49

20

41

44

41

50

54

4F

52

04

Table 6.

HDMI dongle detect transaction sequence outline

Phase I²C transaction

Transmitting

Bit

Status

7

6

5

4

3

2

1

R/W

Master

Slave

1

START

master

slave

optional

-

2

Write command

Acknowledge

1

0

optional

-

3

-

mandatory

4

Word address offset master

word address offset data byte

optional

-

5

Acknowledge

STOP

slave

master

slave

master

slave

:

-

mandatory

6

optional

-

7

START

mandatory

-

8

Read command

Acknowledge

Read data

Acknowledge

Read data

:

1

0

1

mandatory

-

9

-

mandatory

10

11

12

13

:

data byte at offset 0

data byte at offset 1

-

mandatory

-

mandatory

-

:

-

40

41

42

Read data

Not Acknowledge

STOP

slave

master

data byte at offset 15

-

mandatory

-

Remark: If the slave does not acknowledge the above transaction sequence, the entire

sequence should be retried by the source.

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7.7 Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.7.1 Bit transfer

One data bit is transferred during each clock phase. The data on the SDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at this

time will be interpreted as control signals (see Figure 5).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 5. Bit transfer

7.7.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P). See Figure 6.

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 6. Definition of START and STOP conditions.

7.7.3 System configuration

An I²C-bus device generating a message is a ‘transmitter’, a device receiving is the

‘receiver’. The device that controls the message is the ‘master’ and the devices which are

controlled by the master are the ‘slaves’. See Figure 7.

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SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

002aaa381

Fig 7. System configuration

7.7.4 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also, a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating as

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 8. Acknowledgement on the I²C-bus

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8. Application design-in information

8.1 Dongle or cable adaptor detect discovery mechanism

The PTN3381D supports the source-side dongle detect discovery mechanism described

in VESA DisplayPort Interoperability Guideline Version 1.1a.

When a source-side cable adaptor is plugged into a multi-mode source device that

supports multiple standards such as DisplayPort, DVI and HDMI, a discovery mechanism

is needed for the multi-mode source to configure itself for outputting DisplayPort, DVI or

HDMI compliant signals through the dongle or cable adaptor. The discovery mechanism

ensures that a multi-mode source device only sends either DVI or HDMI signals when a

valid DVI or HDMI cable adaptor is present.

The VESA Interoperability Guideline recommends that a multi-mode source to power up

with both DDC and AUX CH disabled. After initialization, the source device can use a

variety of mechanisms to decide whether a dongle or cable adaptor is present by

detecting pin 13 on the DisplayPort connector. Depending on the voltage level detected at

pin 13, the source configures itself either:

• as a DVI or HDMI source (see below paragraph for detection between DVI and

HDMI), and enables DDC, while keeping AUX CH disabled, or

• as a DisplayPort source and enables AUX CH, while keeping DDC disabled.

The monitoring of the voltage level on pin 13 by a multi-mode source device is optional. A

multi-mode source may also, for example, attempt an AUX CH read transaction and, if the

transaction fails, a DDC transaction to discover the presence/absence of a cable adaptor.

Furthermore, a source that supports both DVI and HDMI can discover whether a DVI or

HDMI dongle or cable adaptor is present by using a variety of discovery procedures. One

possible method is to check the voltage level of pin 14 of the DisplayPort connector.

Pin 14 also carries CEC signal used for HDMI. Please note that other HDMI devices on

the CEC line may be momentarily pulling down pin 14 as a part of CEC protocol.

The VESA Interoperability Guideline recommends that a multi-mode source should

distinguish a source-side HDMI cable adaptor from a DVI cable adaptor by checking the

DDC buffer ID as described in Section 7.6 “I²C-bus based HDMI dongle detection”. While

it is optional for a multi-mode source to use the I²C-bus based HDMI dongle detection

mechanism, it is mandatory for HDMI dongle or cable adaptor to respond to the I²C-bus

read command described in Section 7.7. The PTN3381D provides an integrated I²C-bus

slave ROM to support this mandatory HDMI dongle detect mechanism for HDMI dongles.

For a DisplayPort-to-HDMI source-side dongle or cable adaptor, DDET must be tied HIGH

to enable the I²C-based HDMI dongle detection response function of PTN3381D. For a

DisplayPort-to-DVI sink-side dongle or cable adaptor, DDET must be tied LOW to disable

the function.

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9. Limiting values

Table 7.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

0.3

66

Max

+4.6

V_DD+ 0.5

6.0

Unit

V

V_DD

V_I

supply voltage

input voltage

3.3 V CMOS inputs

5.0 V CMOS inputs

5 V regulator output

V

R_L

load resistance

-



T_stg

V_ESD

storage temperature

65

-

+150

6000

1000

C

V

[1]

[2]

electrostatic discharge

voltage

HBM

CDM

-

V

[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -

Component level; Electrostatic Discharge Association, Rome, NY, USA.

[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device

Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.

10. Recommended operating conditions

Table 8.

Symbol

Recommended operating conditions

Parameter

Conditions

Min

Typ

Max Unit

V_DD

V_I

supply voltage

input voltage

2.85

3.3

3.6

5.5

-

V

3.3 V CMOS inputs

5.0 V CMOS inputs

IN_Dn+, IN_Dn inputs

0

-

[1]

[2]

[3]

V_I(AV)

average input

voltage

0

R_ref(ext)

C_o(reg)

C_reg(ext)

T_amb

external reference

resistance

connected between pin

REXT (pin 6) and GND

-

10 ± 1 %

-

k

F

nF

C

regulator output

capacitance

external capacitor on

pin V5OUT

-

1

-

external regulator

capacitance

from pin CP to pin CN

-

330

-

ambient temperature operating in free air

40

+85

[1] Input signals to these pins must be AC-coupled.

[2] Operation without external reference resistor is possible but will result in reduced output voltage swing

accuracy. For details, see Section 7.2.

[3] A ceramic capacitor with ESR < 100 m is recommended and should be placed close to the pin(s).

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10.1 Current consumption

Table 9.

Current consumption

Symbol Parameter

Conditions

Min

Typ

Max

Unit

I_DD

supply current

OE_N = 0; Active mode

no load

-

70

200

-

100

300

7

mA

with 75 mA load

OE_N = 1 and DDC_EN = 0;

Standby mode; no load

11. Characteristics

11.1 Differential inputs

Table 10. Differential input characteristics for IN_Dx signals

Symbol

Parameter

unit interval^[1]

Conditions

Min

Typ

Max

Unit

ps

[2]

[3]

UI

333

-

4000

1.200

-

V_{RX_DIFFp-p}differential input peak-to-peak voltage

0.175

0.8

V

t_{RX_EYE}

receiver eye time

minimum eye width at

IN_Dx input pair

UI

[4]

[5]

V_i(cm)M(AC)

peak common-mode input voltage (AC)

includes all frequencies

above 30 kHz

-

100

mV

Z_{RX_DC}

V_RX(bias)

Z_I(se)

DC input impedance

40

50

1.2

-

60

1.4

-



bias receiver voltage

1.0

100

V

single-ended input impedance

inputs in

k

high-impedance state

[1] UI (unit interval) = t_bit(bit time).

[2] UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 2.5 Gbit/s per lane. Nominal UI at 2.5 Gbit/s = 400 ps.

360 ps = 400 ps  10 %.

[3] V_{RX_DIFFp-p}= 2  V_{RX_D+} V_{RX_D}. Applies to IN_Dx signals.

[4]

V

_i(cm)M(AC)= V_{RX_D+}+ V_{RX_D} / 2  V_RX(cm)

V_RX(cm)= DC (avg) of V_{RX_D+}+ V_{RX_D} / 2.

[5] Differential inputs will switch to a high-impedance state when OE_N is HIGH.

.

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11.2 Differential outputs

The level shifter’s differential outputs are designed to meet HDMI version 1.4b and

DVI version 1.0 specifications.

Table 11. Differential output characteristics for OUT_Dx signals

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

[2]

[3]

V_OH(se)

single-ended HIGH-level

output voltage

V_TT 0.01 V_TT

V_TT+ 0.01

V

V_OL(se)

single-ended LOW-level

output voltage

V_TT 0.60 V_TT 0.50 V_TT 0.40

V

V_O(se)

single-ended output

voltage variation

logic 1 and logic 0 state applied

respectively to differential inputs

IN_Dn; R_ref(ext)connected;

see Table 8

400

500

600

mV

I_OZ

t_r

OFF-state output current single-ended

-

10

A

ps

rise time

fall time

20 % to 80 %

80 % to 20 %

intra-pair

75

-

240

10

t_f

-

[4]

[5]

[6]

t_sk

skew time

-

inter-pair

-

250

-

t_jit(add)

added jitter time

jitter contribution by IC,

PRBS7 pattern

-

10

[1] V_TTis the DC termination voltage in the HDMI or DVI sink. V_TTis nominally 3.3 V.

[2] The open-drain output pulls down from V_TT

[3] Swing down from TMDS termination voltage (3.3 V  10 %).

.

[4] This differential skew budget is in addition to the skew presented between IN_Dn+ and IN_Dn paired input pins.

[5] This lane-to-lane skew budget is in addition to skew between differential input pairs.

[6] Jitter budget for differential signals as they pass through the level shifter.

11.3 HPD_SINK input, HPD_SOURCE output

Table 12. HPD characteristics

Symbol

V_IH

Parameter

Conditions

HPD_SINK

Min

2.0

0

Typ

Max

Unit

V

[1]

HIGH-level input voltage

LOW-level input voltage

input leakage current

HIGH-level output voltage

LOW-level output voltage

propagation delay

5.0

5.3

0.8

15

V_IL

HPD_SINK

-

V

I_LI

HPD_SINK

-

A

V

V_OH

V_OL

t_PD

HPD_SOURCE

2.5

0

V_DD

0.2

200

V

[2]

from HPD_SINK to HPD_SOURCE;

50 % to 50 %

-

ns

[3]

[4]

t_t

transition time

HPD_SOURCE rise/fall; 10 % to 90 %

HPD_SINK input pull-down resistor

1

-

20

ns

R_pd

pull-down resistance

100

200

300

k

[1] Low-speed input changes state on cable plug/unplug.

[2] Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time.

[3] Time required to transition from V_OHto V_OLor from V_OLto V_OH

[4] Guarantees HPD_SINK is LOW when no display is plugged in.

.

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11.4 OE_N, DDC_EN and DDET inputs

Table 13. OE_N, DDC_EN and DDET input characteristics

Symbol

V_IH

Parameter

Conditions

Min

Typ

Max

Unit

V

HIGH-level input voltage

LOW-level input voltage

input leakage current

2.0

-

V_IL

0.8

10

V

[1]

I_LI

OE_N pin

-

A

[1] Measured with input at V_IHmaximum and V_ILminimum.

11.5 DDC characteristics

Table 14. DDC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input and output SCL_SOURCE and SDA_SOURCE, V_CC1= 2.85 V to 3.6 V^[1]

V_IH

HIGH-level input voltage

LOW-level input voltage

input leakage current

0.7V_CC1

-

3.6

+0.4

10

V

V_IL

0.5

V

I_LI

V_I= 3.6 V

-

A

V

I_IL

LOW-level input current

LOW-level output voltage

V_I= 0.2 V

-

10

V_OL

V_OLV_IL

I_OL= 100 A or 6 mA

0.47

-

0.52 0.6

difference between LOW-level output guaranteed by design to

70

-

mV

and LOW-level input voltage

prevent contention

C_io

input/output capacitance

V_I= 3 V or 0 V; V_DD= 3.3 V

-

6

7

pF

V_I= 3 V or 0 V; V_DD= 0 V

Input and output SDA_SINK and SCL_SINK, V_CC2= 4.5 V to 5.5 V^[2]

V_IH

V_IL

I_LI

HIGH-level input voltage

LOW-level input voltage

input leakage current

0.7V_CC2

-

5.5

+1

10

0.2

7

V

0.5

-

V

V_I= 5.5 V

-

A

V

I_IL

LOW-level input current

LOW-level output voltage

input/output capacitance

V_I= 0.2 V

-

V_OL

C_io

I_OL= 6 mA

0.1

-

V_I= 3 V or 0 V; V_DD= 3.3 V

V_I= 3 V or 0 V; V_DD= 0 V

pF

mA

6

4

7

I_trt(pu)

transient boosted pull-up current

V_CC2= 4.5 V;

-

slew rate = 1.25 V/s

[1] V_CC1is the pull-up voltage for DDC source.

[2] V_CC2is the pull-up voltage for DDC sink.

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11.6 5 V DC regulator characteristics

Table 15. 5 V DC regulator characteristics

Symbol

V_O

Parameter

Conditions

Min

Typ

Max

Unit

output voltage

load current

5 V regulator output

V_DD= 3.0 V to 3.6 V

V_DD= 2.85 V

4.7

5

5.3

V

I_load

-

75

mA

A

mV

%

-

60

I_O(sc)

short-circuit output current

backdrive current

100

150

-

200

10

I_bckdrv

5 V regulator output

C_o(reg)= 1 F

-

[1]

V_{o(ripple)(p-p)}peak-to-peak ripple output voltage

efficiency

-

250

75

400

80



I_load> 10 mA

70

[1] Recommend low ESR ceramic output capacitor of 2 F to reduce the output ripple.

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12. Package outline

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 7 x 7 x 0.85 mm

SOT619-1

D

B

A

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

1/2 e

e

v

M

b

C

A B

1

w

13

24

L

25

12

e

E

2

h

1/2 e

1

36

terminal 1

index area

48

37

D

h

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

1

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

7.1

6.9

5.25

4.95

7.1

6.9

5.25

4.95

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

5.5

0.1 0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT619-1

- - -

MO-220

- - -

Fig 9. Package outline SOT619-1 (HVQFN48)

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

23 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

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Product data sheet

Rev. 2 — 26 July 2012

24 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

13.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 10) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 16 and 17

Table 16. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 17. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 10.

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Product data sheet

Rev. 2 — 26 July 2012

25 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 10. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Abbreviations

Table 18. Abbreviations

Acronym

ASCII

CDM

CEC

Description

American Standard Code for Information Interchange

Charged-Device Model

Consumer Electronics Control

Complementary Metal-Oxide Semiconductor

Data Display Channel

CMOS

DDC

DVI

Digital Visual Interface

ESD

ElectroStatic Discharge

ESR

Equivalent Series Resistance

Human Body Model

HBM

HDMI

HPD

High-Definition Multimedia Interface

Hot Plug Detect

I²C-bus

Inter-IC bus

I/O

Input/Output

PCB

Printed-Circuit Board

ROM

TMDS

VESA

Read Only Memory

Transition Minimized Differential Signaling

Video Electronic Standards Association

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Product data sheet

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15. Revision history

Table 19. Revision history

Document ID

PTN3381D v.2

Modifications:

Release date

Data sheet status

Change notice

Supersedes

20120726

Product data sheet

-

PTN3381D v.1

• Descriptive title of this data sheet modified from “supporting deep color mode” to “supporting

3 Gbit/s operation”

• Section 1 “General description”:

–

first paragraph, first sentence: changed from “HDMI v1.3a” to “HDMI v1.4b”

–

first paragraph, first sentence: changed from “up to 2.5 Gbit/s per lane to support 36-bit deep

color mode” to “up to 3 Gbit/s to support 36-bit deep color, 3D and 3 Gbit/s modes”

–

first paragraph, second sentence: changed from “Each of these lanes” to “Each of these

channels”

fourth paragraph, first sentence: changed from “DisplayPort Standard v1.1” to “DisplayPort

Standard v1.2”

fourth paragraph, first sentence: changed from “HDMI v1.3a” to “HDMI v1.4b”

• Figure 1 “Typical application system diagram” updated (deleted “PCIe” in five places)

• Section 2.1 “High-speed TMDS level shifting”:

–

first bullet: changed from “HDMI v1.3a” to “HDMI v1.4b”

second bullet: changed from “up to 2.5 Gbit/s” to “up to 3 Gbit/s”

second bullet: changed from “250 MHz character clock” to “300 MHz character clock”

second bullet: changed from “36-bit deep color mode” to “36-bit deep color, 3D and 3 Gbit/s

modes”

• Section 3 “Applications”: first bullet changed from “36-bit deep color mode” to “36-bit deep color,

3D and 3 Gbit/s modes”

• Table 2 “Pin description”: Description of pins IN_Dn+, IN_Dn changed from “Low-swing

differential input from display source with PCI Express electrical signalling” to “Low-swing

differential input from source”

• Section 7 “Functional description”:

–

second paragraph, first sentence changed from “up to 2.5 Gbit/s per lane to support 36-bit

deep color mode” to “up to 3 Gbit/s per lane to support 36-bit deep color, 3D and 3 Gbit/s

modes”

–

third paragraph, third sentence changed from “HDMI DDC version 1.3a distance specification”

to “HDMI DDC specification”

Section 7.5 “Active DDC buffer with rise time accelerator”, first paragraph, third sentence

changed from “HDMI DDC version 1.3a distance specification” to “HDMI DDC specification”

• Section 8.1 “Dongle or cable adaptor detect discovery mechanism”, first paragraph: changed from

“Version 1.1” to “Version 1.1a”

• Table 10 “Differential input characteristics for IN_Dx signals”: UI Min value changed from “360 ps”

to “333 ps”

• Section 11.2 “Differential outputs”, first paragraph changed from “HDMI version 1.3” to “HDMI

version 1.4b”

PTN3381D v.1

20120323

Product data sheet

-

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

27 of 30

PTN3381D

NXP Semiconductors

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16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

16.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

28 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

16.4 Licenses

Purchase of NXP ICs with HDMI technology

non-automotive qualified products in automotive equipment or applications.

Use of an NXP IC with HDMI technology in equipment that complies with

the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.

Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:

admin@hdmi.org.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

16.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PTN3381D

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Product data sheet

Rev. 2 — 26 July 2012

29 of 30

PTN3381D

NXP Semiconductors

Fully integrated HDMI/DVI level shifter supporting 3 Gbit/s operation

18. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

12

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 23

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 3

High-speed TMDS level shifting . . . . . . . . . . . . 3

DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

HDMI dongle detect support. . . . . . . . . . . . . . . 3

HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

5 V DC voltage regulator . . . . . . . . . . . . . . . . . 3

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

13

Soldering of SMD packages. . . . . . . . . . . . . . 24

Introduction to soldering. . . . . . . . . . . . . . . . . 24

Wave and reflow soldering. . . . . . . . . . . . . . . 24

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 24

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 25

2.1

2.2

2.3

2.4

2.5

2.6

13.1

13.2

13.3

13.4

14

15

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 26

Revision history . . . . . . . . . . . . . . . . . . . . . . . 27

3

4

5

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Ordering information. . . . . . . . . . . . . . . . . . . . . 4

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

16

Legal information . . . . . . . . . . . . . . . . . . . . . . 28

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 29

16.1

16.2

16.3

16.4

16.5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

17

18

Contact information . . . . . . . . . . . . . . . . . . . . 29

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7

7.1

7.1.1

7.1.2

7.1.3

7.1.4

7.2

7.3

7.4

7.5

7.6

7.6.1

7.6.2

7.7

7.7.1

7.7.2

7.7.3

7.7.4

Functional description . . . . . . . . . . . . . . . . . . . 9

Enable and disable features. . . . . . . . . . . . . . 10

Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . 10

Output Enable function (OE_N) . . . . . . . . . . . 10

DDC channel enable function (DDC_EN). . . . 10

Enable/disable truth table . . . . . . . . . . . . . . . . 11

Analog current reference . . . . . . . . . . . . . . . . 12

Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Backdrive current protection. . . . . . . . . . . . . . 12

Active DDC buffer with rise time accelerator . 12

I²C-bus based HDMI dongle detection . . . . . . 13

Slave address. . . . . . . . . . . . . . . . . . . . . . . . . 13

Read operation. . . . . . . . . . . . . . . . . . . . . . . . 14

Characteristics of the I²C-bus. . . . . . . . . . . . . 15

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

START and STOP conditions . . . . . . . . . . . . . 15

System configuration . . . . . . . . . . . . . . . . . . . 15

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 16

8

8.1

Application design-in information . . . . . . . . . 17

Dongle or cable adaptor detect discovery

mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18

Recommended operating conditions. . . . . . . 18

Current consumption . . . . . . . . . . . . . . . . . . . 19

10

10.1

11

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 19

Differential inputs . . . . . . . . . . . . . . . . . . . . . . 19

Differential outputs . . . . . . . . . . . . . . . . . . . . . 20

HPD_SINK input, HPD_SOURCE output. . . . 20

OE_N, DDC_EN and DDET inputs. . . . . . . . . 21

DDC characteristics . . . . . . . . . . . . . . . . . . . . 21

5 V DC regulator characteristics. . . . . . . . . . . 22

11.1

11.2

11.3

11.4

11.5

11.6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 July 2012

Document identifier: PTN3381D


型号：	PTN3381DBS
厂家：	NXP
描述：	SPECIALTY CONSUMER CIRCUIT
文件：	总30页 (文件大小：258K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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